A three-stage capacitor array for a successive approximation analog-to-digital converter

Abstract

This invention discloses a three-segment capacitor array for a successive approximation analog-to-digital converter (ADC), comprising a P-terminal capacitor array and an N-terminal capacitor array. Both the P-terminal and N-terminal capacitor arrays include a low-position capacitor region, a middle-position capacitor region, and a high-position capacitor region. Adjacent capacitor regions are connected by bridging capacitors to form the three-segment capacitor array. The geometric center points of the P-terminal and N-terminal capacitor arrays coincide, and multiple capacitor cells within each capacitor region are arranged symmetrically about the geometric center point of their respective regions. Based on this, the matching between the P-terminal and N-terminal capacitor arrays can be improved, mismatch errors caused by process gradients between capacitor cells can be reduced, and the layout and wiring requirements of the capacitor array can be considered, thereby improving the conversion accuracy of the successive approximation ADC.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a three-segment capacitor array for a successive approximation analog-to-digital converter. Background Technology

[0002] Existing successive approximation analog-to-digital converters (ADCs) typically employ capacitor arrays for analog-to-digital conversion. To reduce the area of ​​the capacitor array, current technologies generally use bridging capacitors to implement segmented capacitor arrays. However, in some segmented capacitor arrays, the complex layout and capacitor connections make layout implementation difficult, hindering the reduction of mismatch errors caused by process gradients. Simultaneously, as the size of the capacitor array continues to increase, layout design must also consider factors such as capacitor matching, wiring resources, and chip area. Existing layout methods struggle to meet these requirements simultaneously, thus leaving room for further optimization.

[0003] Therefore, there is a need to provide a three-segment capacitor array with optimized layout to balance capacitor matching performance, layout routing resources, and chip area. Summary of the Invention

[0004] The purpose of this invention is to provide a three-segment capacitor array for successive approximation analog-to-digital converters, which can improve the matching between the P-end capacitor array and the N-end capacitor array, reduce the mismatch error caused by the process gradient between capacitor units, and at the same time take into account the layout and wiring requirements of the capacitor array, thereby improving the conversion accuracy of the successive approximation analog-to-digital converter.

[0005] To address the aforementioned technical problems, this invention provides a three-segment capacitor array for a successive approximation analog-to-digital converter, comprising a P-terminal capacitor array and an N-terminal capacitor array. Both the P-terminal and N-terminal capacitor arrays include a low-position capacitor region, a middle-position capacitor region, and a high-position capacitor region arranged sequentially. The low-position capacitor region and the middle-position capacitor region are connected by a low-to-middle-position bridging capacitor, and the middle-position capacitor region and the high-position capacitor region are connected by a middle-to-high-position bridging capacitor, thereby forming the three-segment capacitor array. The geometric center point of the P-terminal capacitor array coincides with the geometric center point of the N-terminal capacitor array. The multiple capacitor units in the low-position capacitor region, the middle-position capacitor region, and the high-position capacitor region of the P-end capacitor array and the N-end capacitor array are arranged in a centrally symmetrical manner about the geometric center point of their respective capacitor regions.

[0006] Preferably, the system further includes a switch array, which comprises multiple switch units, each of which is connected to a corresponding capacitor unit to control the connection state between the corresponding capacitor unit and different potential nodes.

[0007] Preferably, the low-position capacitor region includes multiple low-position capacitor units and low-position redundant capacitor units. The median capacitor region includes multiple median capacitor units and median redundant capacitor units; The high-level capacitor region includes multiple high-level capacitor units.

[0008] Preferably, the low-position capacitor region includes a low-position redundant bit capacitor unit for forming two low-position redundant bits, and the middle-position capacitor region includes a middle-position redundant bit capacitor unit for forming one middle-position redundant bit.

[0009] Preferably, the capacitor units in the low-position capacitor region, the middle-position capacitor region, and the high-position capacitor region, as well as the low-to-middle-position bridging capacitor and the middle-to-high-position bridging capacitor, are all composed of a unit capacitor or an integer multiple of a unit capacitor. Each capacitor unit in the low-position capacitor region, the middle-position capacitor region, and the high-position capacitor region, as well as the low-to-middle-position bridging capacitor and the middle-to-high-position bridging capacitor, are connected to the reference voltage, the input signal, or the ground potential through corresponding switching units.

[0010] Preferably, the three-segment capacitor array is divided into multiple capacitor groups, each capacitor group includes multiple capacitor units arranged longitudinally, and the switch array is respectively disposed on both sides of each capacitor group, and each switch unit in the switch array is respectively connected to the capacitor unit in the corresponding capacitor group. Alternatively, the three-segment capacitor array can be arranged continuously to form an overall capacitor array, and the switch array can be disposed around the overall capacitor array.

[0011] Preferably, each of the capacitor groups is provided with a virtual capacitor unit on its periphery, and / or, the three-segment capacitor array is provided with a virtual capacitor unit on its periphery.

[0012] Preferably, it further includes a low-position ground supplementary capacitor and a middle-position ground supplementary capacitor. One end of the low-position ground supplementary capacitor is connected to the connection node between the low-position capacitor area and the low-to-middle-position bridging capacitor, and the other end is grounded. One end of the middle-position ground supplementary capacitor is connected to the connection node between the middle-position capacitor area and the middle-to-high-position bridging capacitor, and the other end is grounded.

[0013] Preferably, the low-position ground supplement capacitor, the low-to-middle-position bridging capacitor, and the middle-position ground supplement capacitor together constitute a scaling capacitor.

[0014] Preferably, the capacitor unit is formed using a metal-insulator-metal capacitor, and each capacitor unit is surrounded by a protective ring located on the same metal layer as the metal-insulator-metal capacitor, and the protective ring is grounded.

[0015] This application provides a three-segment capacitor array for a successive approximation analog-to-digital converter (ADC), comprising a P-terminal capacitor array and an N-terminal capacitor array. Both the P-terminal and N-terminal capacitor arrays include a low-position capacitor region, a middle-position capacitor region, and a high-position capacitor region. Adjacent capacitor regions are connected by bridging capacitors to form the three-segment capacitor array. The geometric center points of the P-terminal and N-terminal capacitor arrays coincide, and multiple capacitor cells within each capacitor region are arranged centrally symmetrically about the geometric center point of their respective regions. Based on this, the matching between the P-terminal and N-terminal capacitor arrays can be improved, reducing mismatch errors caused by process gradients between capacitor cells. Simultaneously, the layout and wiring requirements of the capacitor array are considered, thereby improving the conversion accuracy of the successive approximation ADC. Attached Figure Description

[0016] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of a three-segment capacitor array for a successive approximation analog-to-digital converter provided in this application; Figure 2 A detailed schematic diagram of a three-segment capacitor array for a successive approximation analog-to-digital converter provided in this application; Figure 3 This application provides a schematic diagram of a three-segment capacitor array for a successive approximation analog-to-digital converter. Detailed Implementation

[0018] The core of this invention is to provide a three-segment capacitor array for successive approximation analog-to-digital converters, which can improve the matching between the P-end capacitor array and the N-end capacitor array, reduce the mismatch error caused by the process gradient between capacitor units, and at the same time take into account the layout and wiring requirements of the capacitor array, thereby improving the conversion accuracy of the successive approximation analog-to-digital converter.

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Please refer to Figure 1 , Figure 1This application provides a schematic diagram of a three-segment capacitor array for a successive approximation analog-to-digital converter. In this array, CP1 is a low-level capacitor cell in the low-level capacitor region of the P-terminal capacitor array, CN1 is a low-level capacitor cell in the low-level capacitor region of the N-terminal capacitor array, CP1_ground is a low-level ground supplementary capacitor in the low-level capacitor region of the P-terminal capacitor array, CN1_ground is a low-level ground supplementary capacitor in the low-level capacitor region of the N-terminal capacitor array, CP1-m is a low-to-middle bridging capacitor in the P-terminal capacitor array, CN1-m is a low-to-middle bridging capacitor in the N-terminal capacitor array, and CPm is a P-terminal capacitor... The middle capacitor unit in the middle capacitor region of the capacitor array, CNm is the middle capacitor unit in the middle capacitor region of the N-terminal capacitor array, CPm is the middle-to-ground supplementary capacitor in the middle capacitor region of the P-terminal capacitor array, CNm is the middle-to-ground supplementary capacitor in the middle capacitor region of the N-terminal capacitor array, CPm-h is the middle-to-high-level bridging capacitor in the P-terminal capacitor array, CNm-h is the middle-to-high-level bridging capacitor in the N-terminal capacitor array, CPh is the high-level capacitor unit in the high-level capacitor region of the P-terminal capacitor array, CNh is the high-level capacitor unit in the high-level capacitor region of the N-terminal capacitor array.

[0021] The three-segment capacitor array used for successive approximation analog-to-digital converter includes a P-terminal capacitor array and an N-terminal capacitor array. Both the P-terminal capacitor array and the N-terminal capacitor array include a low-position capacitor region, a middle-position capacitor region and a high-position capacitor region arranged in sequence. The low-position capacitor region and the middle-position capacitor region are connected by a low-to-middle-position bridging capacitor, and the middle-position capacitor region and the high-position capacitor region are connected by a middle-to-high-position bridging capacitor to form a three-segment capacitor array. The geometric center point of the P-terminal capacitor array coincides with the geometric center point of the N-terminal capacitor array. In the P-terminal capacitor array and the N-terminal capacitor array, multiple capacitor units in the low-position capacitor region, middle-position capacitor region and high-position capacitor region are arranged in a centrally symmetrical manner about the geometric center point of their respective capacitor regions.

[0022] The three-segment capacitor array for a successive approximation analog-to-digital converter (ADC) in this embodiment includes a P-terminal capacitor array and an N-terminal capacitor array. Successive approximation ADCs typically employ a differential structure for signal sampling and digital-to-analog conversion. The P-terminal and N-terminal capacitor arrays correspond to the two input terminals of the differential input signal, respectively, and both participate in the sampling, charge redistribution, and successive approximation conversion processes. By setting the P-terminal and N-terminal capacitor arrays, common-mode interference can be suppressed while maintaining the differential input method, and the successive approximation conversion can be completed through the cooperation between the two capacitor arrays. It should be noted that this application does not limit the number of capacitors, their capacitance values, or the specific connection method in the P-terminal and N-terminal capacitor arrays, as long as a differential capacitor array can be formed.

[0023] Furthermore, both the P-terminal capacitor array and the N-terminal capacitor array include a low-position capacitor region, a middle-position capacitor region, and a high-position capacitor region arranged sequentially. The arrangement direction of the low-position capacitor region, the middle-position capacitor region, and the high-position capacitor region can be determined according to the actual layout direction of the chip layout. For example, it can be a horizontal arrangement direction in the layout, a vertical arrangement direction, or other arrangement directions determined according to actual wiring requirements. This application does not limit this. The reason for dividing the entire capacitor array into low-position capacitor region, middle-position capacitor region, and high-position capacitor region is that the capacitance values ​​corresponding to different position weights are different. If all capacitor units are concentrated in the same area, capacitors with different capacitance values ​​are prone to interleaving, making the layout wiring more complex. Moreover, capacitors with different position weights are also affected differently by the layout environment. Therefore, concentrating capacitor units with similar position weights in the same area facilitates subsequent layout and wiring processing. At the same time, it allows for separate layout planning for different position weight regions to take into account capacitor matching and wiring space. When the low-level capacitor region, the middle-level capacitor region, and the high-level capacitor region are arranged in sequence, the positional relationship between each region is fixed, and the wiring length between different regions is easy to control uniformly, thereby reducing the parasitic parameter changes caused by wiring differences.

[0024] Furthermore, the low-weight capacitor region and the middle-weight capacitor region are connected by a low-to-middle-weight bridging capacitor, and the middle-weight capacitor region and the high-weight capacitor region are connected by a middle-to-high-weight bridging capacitor, forming a three-segment capacitor array. A bridging capacitor is a connecting capacitor that connects two adjacent capacitor regions. Its function is to enable regions with different bit weights to participate in the successive approximation conversion process and establish the capacitance ratio between each capacitor region. After connecting different capacitor regions using bridging capacitors, the entire capacitor array can be divided into multiple bit-weight regions, with each bit-weight region undertaking the capacitance conversion function for its corresponding number of bits. Simultaneously, the connection between different bit-weight regions is established through the bridging capacitors, thus forming a complete three-segment capacitor array. It should be noted that this application does not limit the specific capacitance value, specific implementation form, or bridging position of the bridging capacitors. These can be adjusted according to different resolution successive approximation analog-to-digital converters and different capacitor array sizes, as long as the connection between adjacent capacitor regions can be achieved.

[0025] The three-segment division is only one suitable implementation method. In other embodiments, the number of capacitor units in each capacitor region can be adjusted according to the resolution of the successive approximation analog-to-digital converter, the number of capacitors, or the bit weighting method. The specific division positions of the low-position capacitor region, the middle-position capacitor region, and the high-position capacitor region can also be determined according to actual needs. This application does not limit the number of capacitor units in each capacitor region to be the same, nor does it limit the layout area occupied by each capacitor region to be the same, as long as multiple bit weighting regions can be formed and connected by bridging capacitors to form a corresponding capacitor array.

[0026] Furthermore, the geometric center point of the P-terminal capacitor array coincides with the geometric center point of the N-terminal capacitor array. The geometric center point refers to the geometric center position of the corresponding outer contour or overall arrangement area of ​​the capacitor array. It can be calculated based on the overall outline of the capacitor array or determined based on the overall distribution area of ​​all capacitor cells. The P-terminal and N-terminal capacitor arrays are arranged around the same geometric center, ensuring a corresponding relationship between the two arrays relative to this common center. When there are influencing factors such as process gradients, stress distribution, or temperature distribution during chip manufacturing, the positional relationship between the P-terminal and N-terminal capacitor arrays is basically consistent, and the influence on the two arrays is more similar. Therefore, the mismatch between the two arrays can be controlled, thus ensuring good matching performance of the differential capacitor array.

[0027] In this application, the geometric center point is used as the reference for layout because the geometric center can reflect the overall distribution of capacitor cells within the entire area. When the P-terminal capacitor array and the N-terminal capacitor array are arranged around the same geometric center, the capacitor cells at corresponding positions on both sides can maintain a basically consistent layout environment. This ensures that the capacitor arrays on both sides have high consistency when affected by factors such as process gradients, temperature gradients, and stress changes, thereby reducing the possibility of mismatch between the capacitor arrays on both sides.

[0028] It should be noted that the geometric center point mentioned in this application is only used as a reference position for layout arrangement. It does not limit the setting of a physical center point or positioning mark, nor does it limit the geometric center point to be located at the geometric center of the chip. As long as the P-terminal capacitor array and the N-terminal capacitor array are arranged around the same reference center.

[0029] Furthermore, in the P-terminal and N-terminal capacitor arrays, the multiple capacitor cells in the low-position, middle-position, and high-position capacitor regions are arranged centrally symmetrically about the geometric center point of their respective capacitor regions. A capacitor cell refers to the smallest capacitor unit constituting the corresponding capacitor region; it can be a single unit capacitor or multiple unit capacitors forming a single capacitor cell, and this application does not limit this. Each capacitor region has a corresponding geometric center point, and each capacitor cell is arranged centrally symmetrically around the geometric center point of its respective capacitor region. This ensures that capacitor cells located at symmetrical positions within the same capacitor region have the same or similar layout environment, such as wiring length, surrounding metal distribution, process conditions, and parasitic parameters, all of which remain essentially consistent. When the process gradient changes along any direction, the capacitor cells located at the centrally symmetrical positions are situated on either side of the gradient, and their effects correspond to each other. Therefore, the matching relationship between different capacitor cells within the entire capacitor region is more stable.

[0030] In this application, each capacitor region is arranged symmetrically around its own geometric center point, rather than the entire capacitor array being arranged symmetrically around the overall geometric center. This is because the low-position capacitor region, the middle-position capacitor region, and the high-position capacitor region correspond to different position weights, and the number of capacitor cells, capacitance values, and layout dimensions within each region may differ. If only the entire capacitor array is considered as the object of symmetry, the capacitor cells within some regions may still be affected by differences in the local layout environment, causing a certain degree of mismatch between different capacitor cells within the same region.

[0031] Therefore, this application uses the low-position capacitor region, the middle-position capacitor region, and the high-position capacitor region as independent layout units, so that the capacitor units in each capacitor region are arranged symmetrically around the geometric center point of the corresponding capacitor region, so that the capacitor units in the same capacitor region maintain a basically consistent layout environment. At the same time, the capacitor regions are arranged as a whole around the common geometric center of the P-end capacitor array and the N-end capacitor array, thereby taking into account the matching relationship within each capacitor region and the matching relationship between the entire differential capacitor array.

[0032] It should be noted that the specific implementation of the centrally symmetrical arrangement within each capacitor region can be adjusted according to the number of capacitor cells, bit weights, and layout space. For example, different centroid arrangement forms or other arrangements that can form a centrally symmetrical relationship can be adopted. This application does not limit these aspects.

[0033] Furthermore, it should be noted that the aforementioned centrally symmetrical arrangement can be implemented in various ways. For example, each capacitor cell can be arranged with 180° rotational symmetry about the geometric center of its corresponding capacitor region, or it can be arranged with a common centroid, as long as the capacitor cells at corresponding positions form a centrally symmetrical relationship around the geometric center. This application does not limit the specific arrangement of the centrally symmetrical arrangement, nor does it limit each capacitor region to adopt the exact same arrangement. Different capacitor regions can choose a suitable centrally symmetrical arrangement method according to their corresponding bit weights, the number of capacitors, and the layout space.

[0034] It should be further clarified that the overall centrosymmetric arrangement of the P-terminal capacitor array and the N-terminal capacitor array in this application, as well as the centrosymmetric arrangement of the low-position capacitor region, the middle-position capacitor region, and the high-position capacitor region about their respective geometric centers, are not independently set, but rather work together to affect the entire capacitor array layout. Specifically, the P-terminal capacitor array and the N-terminal capacitor array form an overall correspondence, while each capacitor region has a local correspondence, giving the entire capacitor array both overall and local symmetry layout features. When there are process gradients, temperature gradients, or stress changes during chip manufacturing, the overall correspondence can reduce the mismatch between the P-terminal capacitor array and the N-terminal capacitor array, while the local correspondence can reduce the mismatch between different capacitor units within the same capacitor region, thus taking into account the matching relationship within the entire differential capacitor array and each weighted capacitor region.

[0035] Capacitor mismatch is a significant factor affecting the conversion accuracy of successive approximation analog-to-digital converters (ADCs). When there is a capacitance deviation among the capacitor cells in the capacitor array, the capacitor weights of the ADC will change, resulting in nonlinear errors. Therefore, in this embodiment, the capacitor cells are arranged in a centrally symmetrical manner to maintain a symmetrical distribution of the corresponding capacitor cells in the layout.

[0036] For capacitor cells formed using a metal-insulator-metal capacitor architecture, mismatch can be analyzed using the Pelgrom mismatch model. The Pelgrom mismatch model primarily establishes a statistical model based on the final mismatch result of the device, without separately analyzing the various physical factors leading to the mismatch. For two capacitor cells with the same layout size, their dimensional parameter mismatch can be represented by corresponding statistical parameters, and the mismatch variance can be divided into random mismatch and systematic mismatch components. Random mismatch mainly corresponds to short-distance random process deviations, while systematic mismatch mainly corresponds to the influence of long-distance process gradients in the chip layout.

[0037] In this embodiment, multiple capacitor cells within each capacitor region are arranged symmetrically about the geometric center of their respective regions. Therefore, the effects of long-distance process gradients in the layout on the corresponding capacitor cells can cancel each other out. From the statistical model described above, when the symmetrical arrangement condition is met, the random mismatch portion can be primarily considered, while the impact of the systematic mismatch portion is relatively small. Therefore, the capacitor cells in the entire capacitor array maintain relatively consistent mismatch characteristics.

[0038] It should be noted that the Pelgrom mismatch model described above is only used to explain the reason for using a centrally symmetrical arrangement in this embodiment, and does not limit this application to using a specific statistical model for analysis. Under different manufacturing processes or different layout design conditions, other mismatch analysis methods can also be used to design the capacitor array, as long as the aforementioned centrally symmetrical arrangement can be achieved. This application does not impose any limitations on this.

[0039] In summary, by dividing the entire capacitor array into low-position capacitor region, middle-position capacitor region, and high-position capacitor region, and connecting them with bridging capacitors to form a three-segment capacitor array, and arranging the P-end capacitor array and N-end capacitor array around a common geometric center, and ensuring that the multiple capacitor units in each capacitor region are arranged symmetrically around their respective geometric center points, the matching relationship of the capacitor array and the layout routing requirements can be taken into account. While ensuring the normal operation of the three-segment capacitor array, the impact of process gradient on capacitor matching is reduced, and the differential capacitor array maintains good matching performance.

[0040] Based on the above embodiments: Please refer to Figure 2 , Figure 2 This application provides a schematic diagram of a three-segment capacitor array for a successive approximation analog-to-digital converter. In this diagram, Cdm is a virtual capacitor unit, CPl is a low-order redundant capacitor unit in the P-terminal capacitor array, CNl is a low-order redundant capacitor unit in the N-terminal capacitor array, CPm is a middle-order redundant capacitor unit in the P-terminal capacitor array, CNm is a middle-order redundant capacitor unit in the N-terminal capacitor array, CP_half is the equivalent half-capacitance in the P-terminal capacitor array, and CN_half is the equivalent half-capacitance in the N-terminal capacitor array.

[0041] Please refer to Figure 3 , Figure 3 This application provides a schematic diagram of a three-segment capacitor array for a successive approximation analog-to-digital converter.

[0042] In a preferred embodiment, the system further includes a switch array comprising multiple switch units, each switch unit being connected to a corresponding capacitor unit to control the connection state between the corresponding capacitor unit and different potential nodes.

[0043] The three-segment capacitor array in this embodiment also includes a switch array. The switch array is used to establish switchable connections between each capacitor unit and different potential nodes. Specifically, the switch array establishes conduction connections between the capacitor units and different potential nodes, thereby cooperating with the successive approximation analog-to-digital converter to complete the charge distribution process during the sampling and successive approximation conversion stages. A switch unit refers to a switching device capable of changing its conduction state according to a control signal. It can be a MOS (Metal-Oxide-Semiconductor) switch, a transmission gate switch, or other switching structures capable of turning the circuit on and off; this application does not limit this. Each switch unit is connected to its corresponding capacitor unit, enabling each capacitor unit to be independently controlled for conduction. This allows for switching of the corresponding capacitor unit based on the control results corresponding to different bit weights during the successive approximation conversion process.

[0044] The corresponding capacitor unit refers to the correspondence between each switching unit and one or a group of capacitor units, enabling the switching unit to control the connection state of the corresponding capacitor unit. In one implementation, one switching unit can correspond to one capacitor unit; in another, one switching unit can correspond to multiple capacitor units, as long as the switching control of the corresponding capacitor units can be achieved. This application does not limit the unique correspondence between switching units and capacitor units; the specific correspondence method can be determined based on the capacitor array size, position weighting method, and control logic.

[0045] Furthermore, different potential nodes refer to different voltage nodes that may be connected to the capacitor unit during the operation of the successive approximation analog-to-digital converter. For example, these can be input signal nodes, reference voltage nodes, common potential nodes, ground nodes, or other operating potential nodes. The specific number and voltage values ​​of different potential nodes can be determined based on the circuit structure of the successive approximation analog-to-digital converter, and this application does not impose any limitations on this. Each switching unit selects the corresponding potential node according to the control signal, enabling the capacitor unit to be connected to different potentials at different operating stages, thereby completing processes such as sampling, charge retention, and charge redistribution.

[0046] The connection state includes both on and off states, and may also include switching states between multiple different potential nodes. During the sampling phase, each switching unit can control the corresponding capacitor unit to connect to the input signal node to complete input signal sampling. During the successive approximation conversion process, each switching unit, based on the successive approximation control result, sequentially switches the corresponding capacitor unit to the corresponding potential node, enabling the entire capacitor array to redistribute charge and form the corresponding comparison voltage. It is easy to understand that capacitor units corresponding to different bit weights can be switched in different orders, or controlled according to different control strategies; this application does not limit either approach.

[0047] Furthermore, since each switching unit controls its corresponding capacitor unit, the switching array can be arranged accordingly with the layout of the capacitor array. With the switching and capacitor arrays respectively configured, the connection paths between each capacitor unit and its corresponding switching unit can remain relatively short, and the connection relationships are clearer, thereby reducing the possibility of large differences in parasitic parameters between different connection paths. Simultaneously, each switching unit controls its corresponding capacitor unit, and capacitor units with different bit weights can switch according to the successive approximation conversion process. Therefore, the entire capacitor array can complete the sampling and successive approximation conversion process required by the successive approximation analog-to-digital converter.

[0048] It should be noted that this application does not limit the specific arrangement of the switch array. The switch array can be placed on one side, both sides, or other locations of the capacitor array, or it can be placed near different capacitor regions according to the layout space. The switch units can be arranged in a centralized manner or in a distributed manner, as long as the connection state between the corresponding capacitor unit and different potential nodes can be controlled separately. Similarly, this application does not limit the control method of the switch array. The switch array can switch in response to the control signal output by the successive approximation control logic, or it can use other methods that can realize capacitor switching control.

[0049] Furthermore, the switch array in this application is not merely for controlling the conduction of capacitor cells, but rather to establish a correspondence between the switch cells and capacitor cells, ensuring that the circuit connections of the capacitor array are consistent with the layout. In a successive approximation analog-to-digital converter, each capacitor cell needs to be connected to different potential nodes through a corresponding switch cell; therefore, a correspondence exists between the switch array and the capacitor array. When each switch cell controls its respective capacitor cell, capacitor cells with different bit weights can switch according to the successive approximation conversion process. Simultaneously, the connection relationship between each capacitor cell and its corresponding switch cell is relatively clear, facilitating the connection of the entire capacitor array.

[0050] Since both the P-terminal and N-terminal capacitor arrays include multiple capacitor units, they can each be equipped with corresponding switch arrays. Each switch unit controls the connection between its corresponding capacitor unit and different potential nodes. In this way, the P-terminal and N-terminal capacitor arrays can respectively complete the charge control of their respective differential branches. The two capacitor arrays complete the sampling and successive approximation conversion process according to the same or corresponding control methods, keeping the entire differential capacitor array in its corresponding operating state.

[0051] It should be noted that the correspondence between the switch array and the capacitor array described in this application is not limited to one implementation. For example, each switch unit can be directly connected to the corresponding capacitor unit, or an electrical connection can be established with the corresponding capacitor unit through wires, vias, or other interconnection structures; the connection between each switch unit and the corresponding capacitor unit can also adopt different relationships such as one-to-one, one-to-many, or many-to-one, as long as the connection control between the corresponding capacitor unit and different potential nodes can be realized, and this application does not limit this.

[0052] Furthermore, in this application, after the switch array and capacitor array are configured together, the layout of the capacitor array and the circuit connection relationship can remain consistent, and different capacitor units can participate in the sampling and successive approximation conversion process through their corresponding switch units. Simultaneously, during the layout process, the switch array can be arranged accordingly based on the arrangement of the capacitor array, ensuring that each capacitor unit and its corresponding switch unit maintain a short or balanced connection path, thereby reducing the impact of parasitic parameter differences between different connection paths on the operation of the capacitor array.

[0053] In this application, each switching unit is connected to a corresponding capacitor unit, rather than directly corresponding to the entire low-position capacitor region, middle-position capacitor region, or high-position capacitor region. This is because during the operation of a successive approximation analog-to-digital converter (ADC), capacitor units corresponding to different bit weights need to participate in sampling and charge redistribution separately, and each capacitor unit typically has independent control requirements. Therefore, by using the capacitor unit as the control object, each switching unit controls the connection state of its corresponding capacitor unit, which can meet the switching requirements of capacitor units with different bit weights at different operating stages. Furthermore, when the size of the capacitor array changes or the number of capacitor units in each capacitor region is adjusted, only the corresponding switching units need to be added or removed accordingly, without affecting the correspondence between the entire switching array and the capacitor array. Therefore, this correspondence method is applicable to successive approximation ADCs of different sizes and bit weights.

[0054] In one implementation, each switching unit can be formed using a MOSFET. Depending on the switching requirements of the corresponding capacitor unit in different operating stages, the switching unit can employ a single-pole double-throw switch, a single-pole triple-throw switch, or other switching structures capable of achieving the corresponding switching function. This application does not limit each capacitor unit to corresponding to the same type of switch; different capacitor units can adopt different forms of switching units according to actual switching requirements. For example, some capacitor units can correspond to single-pole double-throw switches, and some capacitor units can correspond to single-pole triple-throw switches, as long as the switching between the corresponding potential nodes in the sampling stage and the successive approximation stage can be completed. This application does not impose any limitations on this.

[0055] In a preferred embodiment, the low-position capacitor region includes multiple low-position capacitor units and low-position redundant capacitor units. The center capacitor region includes multiple center capacitor units and center redundant capacitor units; The high-level capacitor region includes multiple high-level capacitor units.

[0056] In this embodiment, the low-position capacitor region includes multiple low-position capacitor units and low-position redundant capacitor units. The low-position, middle-position, and high-position capacitor units correspond to capacitor units with different bit weights in the successive approximation analog-to-digital converter. Depending on the bit weight allocation method of the capacitor array, the capacitor units in the low-position capacitor region are mainly used to form capacitor arrays corresponding to lower bit weights, the capacitor units in the middle-position capacitor region are mainly used to form capacitor arrays corresponding to middle bit weights, and the capacitor units in the high-position capacitor region are mainly used to form capacitor arrays corresponding to higher bit weights. By setting capacitor units corresponding to different bit weights in different capacitor regions, capacitor units with different bit weights can be centrally arranged according to bit weight order, facilitating the formation of a regular layout and establishing corresponding connection relationships between each bit weight.

[0057] A capacitor cell refers to the basic unit that constitutes a capacitor with a corresponding position weight. It can be a single physical capacitor or a combination of multiple physical capacitors to form an equivalent capacitor; this application does not limit this. The number of capacitor cells in different capacitor regions can be determined based on the resolution of the successive approximation analog-to-digital converter, the size of the capacitor array, and the position weight division method. The number of capacitor cells in each capacitor region can be the same or different, as long as a capacitor array with the corresponding position weight can be formed. Therefore, this application does not limit the specific number and arrangement of capacitor cells in the low-position capacitor region, the middle-position capacitor region, and the high-position capacitor region.

[0058] Furthermore, the low-position capacitor region also includes low-position redundant capacitor units, and the middle-position capacitor region also includes middle-position redundant capacitor units. The redundant capacitor units mentioned here refer to capacitor units additionally disposed in the corresponding capacitor region besides forming normal bit weights. They can participate in the charge redistribution process of the successive approximation analog-to-digital converter and jointly complete the successive approximation conversion with other capacitor units in the corresponding capacitor region. In this application, disposing of redundant capacitor units in the low-position and middle-position capacitor regions is a suitable implementation method. Their specific number, corresponding bit weights, and participation in the conversion can be adjusted according to different successive approximation analog-to-digital converter control methods, and this application does not limit them in any way.

[0059] Furthermore, the low-order redundant bit capacitor units are shared with the low-order capacitor units in the low-order capacitor region, and the middle-order redundant bit capacitor units are shared with the middle-order capacitor units in the middle-order capacitor region, ensuring that the redundant bit capacitor units and their corresponding weighted capacitor units maintain a similar layout environment. For example, the low-order redundant bit capacitor units can be arranged around the low-order capacitor region together with the low-order capacitor units, and the middle-order redundant bit capacitor units can be arranged around the middle-order capacitor region together with the middle-order capacitor units, maintaining essentially consistent layout conditions between the redundant bit capacitor units and their corresponding weighted capacitor units, thereby reducing the impact of layout position differences. Simultaneously, since the redundant bit capacitor units are located within their corresponding weighted regions, they do not require separate independent regions, and the entire capacitor array can still maintain a regular regional division.

[0060] It should be noted that in this application, the high-weight capacitor region includes multiple high-weight capacitor units, but there is no requirement that the high-weight capacitor region must have redundant capacitor units. This is because the configuration of redundant bits may differ for successive approximation analog-to-digital converters with different resolutions and conversion accuracy requirements. In some embodiments, redundant capacitor units may be set only in the low-weight capacitor region and the middle-weight capacitor region; in other embodiments, corresponding capacitor units may be set in other weighted regions as needed, as long as it does not affect the operation of the entire three-segment capacitor array. This application does not impose any limitations on this.

[0061] Furthermore, this application places ordinary capacitor units and redundant capacitor units in corresponding capacitor regions, so that different types of capacitor units can be uniformly arranged according to their corresponding bit weights and establish a corresponding relationship with the corresponding switching units. In this way, during successive approximation conversion, each capacitor unit can participate in charge redistribution according to the control sequence, while the redundant capacitor units can also participate in the corresponding conversion process, so that the entire capacitor array maintains a uniform layout and connection relationship.

[0062] It should be noted that the arrangement of the low-position capacitor units, middle-position capacitor units, high-position capacitor units, and redundant capacitor units described in this application is not limited. For example, they can be arranged continuously, staggered, centrally symmetrically, or in other ways that meet the layout requirements; different types of capacitor units can be arranged adjacently or spaced apart, as long as they can form a capacitor array with corresponding position weights. Therefore, this application does not limit the specific arrangement of various types of capacitor units in the corresponding capacitor area.

[0063] Furthermore, in this application, ordinary capacitor cells are used to form the basic capacitor array corresponding to the bit weight, and redundant bit capacitor cells are used to form redundant capacitors corresponding to the bit weight. Ordinary capacitor cells and redundant bit capacitor cells together constitute the corresponding capacitor region, so that the corresponding capacitor region includes both capacitors forming normal bit weights and capacitors forming redundant bit weights. Therefore, the entire capacitor region can still be laid out as a complete bit weight region without needing to separately divide a new capacitor region for redundant bits. This maintains the overall structure of the three-segment capacitor array while ensuring that the redundant bit capacitors maintain a consistent layout environment with the corresponding bit weight capacitors.

[0064] In a preferred embodiment, the low-position capacitor region includes a low-position redundant bit capacitor unit for forming two low-position redundant bits, and the middle-position capacitor region includes a middle-position redundant bit capacitor unit for forming one middle-position redundant bit.

[0065] In this embodiment, a low-level redundant capacitor unit for forming two low-level redundant bits is set in the low-level capacitor region, and a middle-level redundant capacitor unit for forming one middle-level redundant bit is set in the middle-level capacitor region. The two low-level redundant bits and one middle-level redundant bit are determined according to the bit weight allocation method of the successive approximation analog-to-digital converter corresponding to this embodiment. Since the low-level capacitor region corresponds to lower bit weights, its number of capacitors is relatively large, and its bit weight division is more detailed, therefore two redundant bits are set in the low-level capacitor region. The middle-level capacitor region corresponds to middle bit weights, and its bit weight variation range is between that of the low-level and high-level capacitor regions; therefore, setting one redundant bit is sufficient to meet the bit weight configuration requirements of the capacitor array corresponding to this embodiment. Through the above configuration method, both the low-level and middle-level capacitor regions contain corresponding redundant capacitors, ensuring the bit weight division of the three-segment capacitor array while forming a capacitor composition method corresponding to this embodiment.

[0066] For forming two low-order redundant bits, it means that the low-order redundant bit capacitor unit participates in forming the capacitor corresponding to two low-order redundant bits; for forming one middle-order redundant bit, it means that the middle-order redundant bit capacitor unit participates in forming the capacitor corresponding to one middle-order redundant bit. It should be noted that the two and one bits in this application correspond to the number of redundant bits, and are not limited to a specific type of capacitor, nor are they limited to a single physical capacitor completing the corresponding bit weight formation. For example, a redundant bit can be formed by one capacitor unit, or multiple capacitor units can jointly form the corresponding bit weight, as long as the corresponding number of redundant bits can be formed, this application does not impose any limitations on this.

[0067] From a layout perspective, low-position redundant capacitor cells remain in the low-position capacitor region, and middle-position redundant capacitor cells remain in the middle-position capacitor region. Therefore, redundant capacitor cells can be arranged in the layout together with their corresponding position-weighted capacitor cells, maintaining a layout environment that is essentially consistent with their counterparts. When the entire capacitor region is arranged centrally symmetrically in the aforementioned manner, the corresponding redundant capacitor cells can also participate in the arrangement, ensuring that the redundant capacitors and ordinary position-weighted capacitors maintain similar layout conditions. This guarantees that the entire capacitor region maintains a uniform arrangement without requiring the allocation of new layout areas for redundant bits.

[0068] Meanwhile, after the low-position capacitor region and the middle-position capacitor region each form the corresponding number of redundant bits, the ordinary bit-weighted capacitors and the redundant bit capacitors still together constitute the corresponding bit-weighted regions. The connections between each capacitor region are still established through bridging capacitors. Therefore, the composition of the entire three-segment capacitor array remains unchanged, with only the capacitor units required to form redundant bits added within the corresponding capacitor regions. In this way, the entire capacitor array can still be wired and connected in a unified manner without changing the connection relationships between each capacitor region, nor is it necessary to change the overall correspondence between the P-end capacitor array and the N-end capacitor array.

[0069] It should be noted that the use of two low-level redundant bits and one middle-level redundant bit in the low-level capacitor region and the use of one middle-level redundant bit in the middle-level capacitor region in this embodiment is merely a specific implementation method given in conjunction with the bit weight allocation method of the capacitor array in this embodiment. In other embodiments, the composition method of the capacitor units used to form the corresponding redundant bits can be adjusted according to different bit successive approximation analog-to-digital converters or different bit weight division methods, as long as it can form the two low-level redundant bits and one middle-level redundant bit as described in this embodiment. This application does not further limit this.

[0070] It is easy to understand that the number of capacitors in the low-position capacitor area is usually greater than that in the middle-position capacitor area, and the corresponding bit weighting is also more detailed. Therefore, two redundant bits are set in the low-position capacitor area, and one redundant bit is set in the middle-position capacitor area, so that the redundant bits are distributed between different bit weighting areas. The entire capacitor array still maintains the three-segment division method, and the capacitor composition within each capacitor area remains continuous. There is no need to add new capacitor areas or change the connection relationship between the original capacitor areas.

[0071] In a preferred embodiment, the capacitor units in the low-position capacitor region, the middle-position capacitor region, and the high-position capacitor region, as well as the low-to-middle-position bridging capacitor and the middle-to-high-position bridging capacitor, are all composed of a unit capacitor or an integer multiple of a unit capacitor. Each capacitor unit in the low-level capacitor region, the middle-level capacitor region, and the high-level capacitor region, as well as the low-to-middle-level bridging capacitor and the middle-to-high-level bridging capacitor, are connected to the reference voltage, the input signal, or the ground potential through their respective switching units.

[0072] In this embodiment, the unit capacitor is the basic capacitor unit used to determine the capacitance ratio in the entire capacitor array. Its capacitance value can be determined based on the resolution, input range, and scale of the successive approximation analog-to-digital converter. In this application, other capacitor units and bridging capacitors are configured with the unit capacitor as the reference. When a larger capacitance value is required, multiple unit capacitors can be combined to form the corresponding capacitor. Therefore, the capacitance relationship in the entire capacitor array can be represented by the unit capacitor. The unit capacitor mentioned here can be a single physical capacitor or a combination of multiple physical capacitors of the same size, as long as it can serve as the capacitance value reference for the entire capacitor array. This application does not limit this.

[0073] Here, "integer multiples of unit capacitance" means that the corresponding capacitor unit or bridging capacitor can be composed of a single unit capacitor or multiple unit capacitors connected in parallel or other ways. The overall capacitance value formed by multiple unit capacitors is an integer multiple of the unit capacitance value. For example, the corresponding capacitor can be formed by combining two, three, four, or more unit capacitors. The use of integer multiples in this application is to ensure that all different capacitors in the entire capacitor array can be obtained by combining unit capacitors of uniform specifications, without using independent capacitor structures with non-integer multiple capacitance values.

[0074] In this embodiment, the capacitor units in the low-position capacitor region, middle-position capacitor region, and high-position capacitor region are all composed of a single unit capacitor or an integer multiple of a single unit capacitor, allowing capacitors corresponding to different position weights to be combined using unit capacitors of the same specification. Since each capacitor unit uses a basic capacitor of the same specification, capacitors with different position weights are distinguished only by the number of unit capacitors. During layout, each capacitor unit can be arranged using a uniform size or uniform unit, maintaining a consistent layout for the entire capacitor array. When the capacitance value needs to be adjusted for different position weights, the corresponding capacitance value can be achieved by increasing or decreasing the number of unit capacitors without needing to redesign capacitors of different sizes or structures.

[0075] In addition to the capacitor units in each capacitor region, the low-to-middle and middle-to-high bridging capacitors in this embodiment are also constructed using unit capacitance or integer multiples of unit capacitance. The bridging capacitors are used to establish connections between adjacent capacitor regions, and their capacitance values ​​directly affect the capacitance ratio between different capacitor regions. When the bridging capacitors are also constructed using unit capacitance or integer multiples of unit capacitance, the bridging capacitors maintain a consistent capacitance value configuration with the capacitor units in each capacitor region. Therefore, the entire three-segment capacitor array can be formed by combining unit capacitors of the same specification, maintaining consistency between different types of capacitors.

[0076] From a layout perspective, since each capacitor cell and bridging capacitor is composed of a single unit capacitor or an integer multiple of a single unit capacitor, the only difference between different capacitance values ​​is the number of unit capacitors, without needing to create capacitors of different sizes or structures for different capacitance values. Therefore, during layout, a uniformly sized single unit capacitor can be used as the basic layout unit, and then capacitor cells and bridging capacitors can be formed according to their corresponding capacitance values, maintaining a regular arrangement of the entire capacitor array. Furthermore, since different capacitance values ​​are all derived from combinations of single units capacitors, the manufacturing conditions of each capacitor are similar, making it easier to maintain consistency between capacitors of different capacitance values ​​even when there are process fluctuations during chip manufacturing.

[0077] It should be noted that the integer multiples in this application are not limited to a specific multiple, but rather indicate that the corresponding capacitor can be formed by combining a number of unit capacitors. For example, it can be two, three, four, five, or other integer multiples, and different numbers of unit capacitors can be selected to form the corresponding capacitance value according to the capacitance value requirements corresponding to different place weights. This application does not limit these aspects. Similarly, this application does not limit the specific structure of the unit capacitors. As long as the different capacitors in the entire capacitor array can be formed in the manner of unit capacitors or integer multiples of unit capacitors, they fall within the protection scope of this application.

[0078] Finally, it should be noted that this embodiment not only uniformly uses single-unit capacitance or integer multiples of single-unit capacitance for the capacitor units in the low-position, middle-position, and high-position capacitor regions, but also forms the low-to-middle and middle-to-high-position bridging capacitors in the same way. This ensures that all types of capacitors constituting the entire three-segment capacitor array use a unified capacitance value configuration. Therefore, the entire capacitor array, from ordinary position-weighted capacitors to bridging capacitors, uses the same basic capacitors for combination, maintaining a consistent layout implementation. There is no need to use a separate capacitance value configuration for the bridging capacitors, thus ensuring a uniform capacitor composition for the entire capacitor array.

[0079] In one specific implementation, the mid-to-high-level bridging capacitor can be composed of two unit capacitors. Here, "two unit capacitors" refers to two unit capacitors forming corresponding branches, which together constitute the mid-to-high-level bridging capacitor. Using this method, the mid-to-high-level bridging capacitor still uses unit capacitors, eliminating the need for fractional capacitors, thus maintaining the same capacitance value as other capacitor units in the capacitor array. In this application, the specific connection method between the two unit capacitors can be determined based on the circuit structure, and this application does not limit this. After each unit capacitor forms a corresponding capacitor unit, it is connected to the switch array through a corresponding switching unit. Each switching unit is used to control the conduction relationship between the corresponding capacitor unit and the reference voltage, input signal, or ground potential.

[0080] In a preferred embodiment, the three-segment capacitor array is divided into multiple capacitor groups, each capacitor group including multiple capacitor units arranged longitudinally, and switch arrays are respectively disposed on both sides of each capacitor group, with each switch unit in the switch array connected to the capacitor unit in the corresponding capacitor group. Alternatively, three capacitor arrays can be arranged in a continuous manner to form an overall capacitor array, with the switch array located around the overall capacitor array.

[0081] This embodiment provides two different layout methods, both applicable to the aforementioned three-segment capacitor array. The first method divides the entire three-segment capacitor array into multiple capacitor groups, each group serving as a relatively independent arrangement unit. The second method arranges the entire three-segment capacitor array continuously to form a single, continuous array, without further division into multiple capacitor groups. Both layout methods can realize the three-segment capacitor array described in this application. The specific method used can be selected based on chip area, wiring resources, or actual layout requirements; this application does not limit this selection.

[0082] In the first embodiment, the three-segment capacitor array is divided into multiple capacitor groups. A capacitor group, as described here, refers to an arrangement unit composed of several capacitor cells. Each capacitor group may include one or more capacitor cells corresponding to different bit weights, or it may include some capacitor cells corresponding to different bit weights, as long as the entire capacitor array can be composed of multiple capacitor groups. This application does not limit this. After dividing the entire capacitor array into multiple capacitor groups, each capacitor group can be arranged as a relatively independent layout unit, facilitating the combination of the entire capacitor array.

[0083] Each capacitor bank comprises multiple capacitor cells arranged longitudinally. The term "longitudinal" here refers to the arrangement direction of the three-segment capacitor array shown in the accompanying drawings, indicating the direction in which multiple capacitor cells within the same capacitor bank are arranged sequentially. This direction can correspond to the column direction in the chip layout, or it can correspond to other directions after rotation based on the actual layout. The "longitudinal" direction used in this application is only used to illustrate the relative arrangement relationship between the capacitor cells and does not limit the actual placement direction of the chip. After the capacitor cells are arranged longitudinally, the capacitor cells within the same capacitor bank remain continuously distributed, while different capacitor banks can be arranged at predetermined intervals to form the entire capacitor array.

[0084] Corresponding to the capacitor banks mentioned above, switch arrays are respectively positioned on both sides of each capacitor bank. "Both sides" refers to the positions on either side relative to the longitudinal direction of the capacitor banks. For example, when the capacitor cells are arranged longitudinally, the switch arrays can be positioned on the left and right sides of each capacitor bank, allowing each switch cell to establish a connection with its corresponding capacitor cell. Because the switch arrays are located on both sides of each capacitor bank, each capacitor bank can form a relatively independent connection area. Each capacitor cell maintains a relatively direct connection with its corresponding switch cell, and wiring between different capacitor banks is also convenient.

[0085] In another implementation, the entire three-segment capacitor array is no longer divided into multiple capacitor groups, but is arranged continuously to form a whole capacitor array. This continuous arrangement means that each capacitor unit is arranged continuously in a predetermined order, with no gaps between adjacent capacitor units used to divide capacitor groups, thus forming a whole capacitor array. In this implementation, the capacitor units in each capacitor region are still arranged according to their corresponding position weights, maintaining the aforementioned central symmetry and geometric center relationships; only the layout arrangement is changed from multiple independent capacitor groups to a whole continuous arrangement.

[0086] For the overall capacitor array, the switch array is located on the periphery of the overall capacitor array. Here, "periphery" refers to a position located outside the overall capacitor array. The switch array can be arranged around one or more edge regions of the overall capacitor array, allowing each switch unit to connect to its corresponding capacitor unit. In this application, it is not limited that the periphery must completely surround the entire capacitor array, nor is it limited to a position corresponding only to one side, as long as the switch array is located entirely outside the capacitor array and can complete the connection control of the corresponding capacitor units.

[0087] From a layout perspective, the first implementation uses multiple capacitor groups arranged separately, each capacitor group serving as a relatively independent layout unit, facilitating the connection of different capacitor groups. The second implementation uses a continuous overall arrangement, with the entire capacitor array maintaining a continuous distribution and the switch array concentrated on the periphery, forming a relatively complete overall layout. These two implementations correspond to different layout forms, but both can achieve the corresponding connection relationship between the three-segment capacitor array and switch array described in this application, and therefore both fall within the protection scope of this application.

[0088] It should be noted that the number of capacitor groups, the number of capacitor units in each capacitor group, and the specific arrangement of the overall capacitor array are not limited in this application. For example, it can be divided into two, three, four, or more capacitor groups; the number of capacitor units in each capacitor group can be the same or different; the overall capacitor array can form a rectangular arrangement, an approximately rectangular arrangement, or other continuous arrangement, as long as it meets the layout relationship described in this application, and this application does not limit any of these.

[0089] After completing the main layout of the three-segment capacitor array, the following explanation will be given in conjunction with the setting of virtual capacitor units to further illustrate the layout implementation of the three-segment capacitor array.

[0090] In a preferred embodiment, virtual capacitor units are provided around each capacitor group, and / or, virtual capacitor units are provided around the periphery of the three-segment capacitor array.

[0091] In this embodiment, the virtual capacitor unit is disposed in the peripheral area of ​​the three-segment capacitor array. A virtual capacitor unit refers to a capacitor structure located at the edge of the three-segment capacitor array in the layout. It can be formed using the same or similar manufacturing process as a capacitor unit, but the virtual capacitor unit is not used as an effective capacitor in the three-segment capacitor array to participate in position weight formation or charge redistribution; instead, it is disposed as a peripheral capacitor structure at the edge of the layout. In this application, whether the virtual capacitor unit is connected to the circuit and what connection method is used can be determined according to the actual circuit requirements, and this application does not impose any limitations on this.

[0092] When a three-segment capacitor array uses multiple capacitor groups arranged separately, virtual capacitor cells can be set around the perimeter of each capacitor group. The perimeter refers to the area surrounding the edge of the corresponding capacitor group, such as the left and right sides, top and bottom sides, or the four edges of the capacitor group. After setting virtual capacitor cells around the perimeter of each capacitor group, each capacitor group forms an edge region surrounded by virtual capacitor cells. This ensures that the capacitor cells located at the edge of the capacitor group maintain a closer surrounding environment than those located inside the capacitor group, thereby reducing the differences between the edge and interior locations caused by different surrounding structures. In this way, each capacitor group can maintain similar layout conditions, eliminating the need for different perimeter processing methods for different capacitor groups.

[0093] When the entire three-segment capacitor array is arranged continuously to form a complete capacitor array, virtual capacitor units can be placed on the periphery of the complete capacitor array. The overall periphery refers to the outermost area formed by the outermost edge of the entire three-segment capacitor array. After the virtual capacitor units are placed around the entire three-segment capacitor array, the capacitor units located on the outer edge are all adjacent to virtual capacitor units, and not directly adjacent to blank areas or other functional modules. Therefore, the periphery of the entire three-segment capacitor array forms a relatively consistent boundary form, keeping the edge area and the middle area in a similar layout environment.

[0094] When a three-segment capacitor array is divided into multiple capacitor groups, each capacitor group forms a relatively independent arrangement unit. Therefore, virtual capacitor units can be set around each capacitor group. When the three-segment capacitor array is arranged continuously as a whole, virtual capacitor units can be set directly around the entire capacitor array. Both methods correspond to the two layout arrangements mentioned above, so the choice can be made based on the actual layout.

[0095] The size, shape, and arrangement of the virtual capacitor cells can be determined based on adjacent capacitor cells. In one implementation, the virtual capacitor cells can maintain the same cell size as adjacent capacitor cells; in another implementation, the virtual capacitor cells can also be formed by combining multiple unit capacitors, as long as they can form an outer capacitor structure. This application does not impose any limitations on this. Similarly, virtual capacitor cells can be arranged continuously or intermittently, and their specific number can be determined based on the length of the outer boundary, without needing to be consistent with the number of internal capacitor cells.

[0096] It should be noted that the virtual capacitor cells in this application are mainly located in the peripheral area of ​​the three-segment capacitor array or capacitor bank. They do not participate in the formation of corresponding bit weights or in the successive approximation conversion process, and therefore do not change the original capacitance relationship and bit weight allocation method of the three-segment capacitor array. The virtual capacitor cells, as peripheral structures, together with the internal capacitor cells, form a complete layout, ensuring that the edges of the entire three-segment capacitor array maintain a consistent structural form, such as making the capacitor bank or the overall capacitor array form a square arrangement, while not affecting the normal sampling and successive approximation conversion of the three-segment capacitor array.

[0097] From a layout perspective, the environment surrounding capacitor cells located at the edges of a three-segment capacitor array typically differs from that of capacitor cells in the center. This embodiment sets virtual capacitors around the capacitor bank or the entire capacitor array, creating a continuous capacitor structure at the outer edge, thereby reducing the impact of the outer boundary on the edge capacitor cells. Furthermore, the virtual capacitors do not alter the connection relationships between capacitor regions, nor do they change the capacitance values ​​of each capacitor cell and the bridging capacitors; therefore, they can be used in conjunction with the two aforementioned layout arrangements.

[0098] Besides being placed around the capacitor bank or the entire capacitor array, some virtual capacitors can also be placed inside the capacitor array in locations where no effective capacitor cells are located. "Inside" refers to local empty areas within the capacitor array created by the layout arrangement. Depending on the layout requirements, virtual capacitors can be placed in these locations to ensure that the internal local areas maintain the same arrangement as the surrounding capacitor cells. This application does not limit the specific number or location of virtual capacitors.

[0099] As a preferred embodiment, it also includes a low-position ground supplementary capacitor and a middle-position ground supplementary capacitor. One end of the low-position ground supplementary capacitor is connected to the connection node between the low-position capacitor area and the low-to-middle-position bridging capacitor, and the other end is grounded. One end of the middle-position ground supplementary capacitor is connected to the connection node between the middle-position capacitor area and the middle-to-high-position bridging capacitor, and the other end is grounded.

[0100] In this embodiment, a low-position ground supplementary capacitor and a middle-position ground supplementary capacitor are added to the three-segment capacitor array. The ground supplementary capacitor is an additional capacitor connected between the corresponding capacitor region and the bridging capacitor, used to form a corresponding capacitive connection relationship with the corresponding capacitor region and the bridging capacitor. "Ground" refers to the ground reference node corresponding to the supplementary capacitor. Its specific grounding method can be determined according to the circuit structure of the successive approximation analog-to-digital converter, such as connecting to analog ground, a common reference node, or other equivalent reference potential; this application does not limit this.

[0101] The low-level capacitor region is connected to the low-to-mid-level bridging capacitor, and a low-level ground supplementary capacitor is provided at the connection node between them. The other end of the low-level ground supplementary capacitor is grounded. The locations indicated by "between" represent the electrical connection relationships, not specific geometric locations in the layout. During layout implementation, the low-level ground supplementary capacitor can be placed on the side of the low-level capacitor region adjacent to the low-to-mid-level bridging capacitor, or it can be placed in other locations depending on the wiring method, as long as it is within the corresponding connection relationship. This application does not impose any limitations on this.

[0102] Correspondingly, the middle-position grounding supplementary capacitor is connected between the middle-position capacitor area and the middle-high-position bridging capacitor, thus forming a corresponding grounding supplementary structure between the middle-position capacitor area and the middle-high-position bridging capacitor. After setting grounding supplementary capacitors on the low-position and middle-position sides respectively, the two bridging positions adopt the same type of circuit composition, ensuring a consistent connection between the low-position and middle-position capacitor areas, and between the middle-position and high-position capacitor areas, thereby maintaining a unified capacitor composition throughout the entire three-segment capacitor array.

[0103] From a layout perspective, the low-position ground supplementary capacitor is located near the low-position capacitor area, and the middle-position ground supplementary capacitor is located near the middle-position capacitor area. Therefore, a relatively short connection path can be formed between the corresponding supplementary capacitor and adjacent capacitor areas and bridging capacitors. Since corresponding supplementary capacitors are used on both the low-position and middle-position sides, the two bridging positions maintain a similar layout organization, eliminating the need for different connection structures for different bridging positions. This ensures a consistent layout for the entire three-segment capacitor array.

[0104] It should be noted that this application does not limit the specific capacitance values ​​of the low-position and mid-position grounding supplementary capacitors. Their capacitance values ​​can be determined based on the position weighting method of the corresponding capacitor region, the capacitance ratio, and the capacitance value of the bridging capacitor. Similarly, this application does not limit whether the grounding supplementary capacitor is formed by a single capacitor or a combination of multiple capacitors. For example, the grounding supplementary capacitor can be formed by a single unit capacitor or by a combination of multiple unit capacitors to form the corresponding capacitance value, as long as the required grounding supplementary capacitor can be formed.

[0105] Furthermore, this application does not limit the specific layout shape and arrangement of the low-position ground supplementary capacitor and the middle-position ground supplementary capacitor. For example, the same cell structure as ordinary capacitor cells can be used, or other capacitor structures that can achieve the corresponding capacitance value can be used; they can be arranged continuously with the corresponding capacitor area, or they can be appropriately adjusted according to wiring requirements, as long as the aforementioned connection relationship is met.

[0106] By setting up supplementary capacitors for low-position and middle-position, supplementary capacitor structures are formed between the low-position capacitor area and the low-to-middle-position bridging capacitor, and between the middle-position capacitor area and the middle-to-high-position bridging capacitor. This ensures that the entire three-segment capacitor array maintains a consistent capacitor composition at the two bridging positions, without altering the original positional weighting of the low-position, middle-position, and high-position capacitor areas, and without affecting the basic function of the bridging capacitors in connecting adjacent capacitor areas.

[0107] In a preferred embodiment, the low-position ground supplement capacitor, the low-to-middle-position bridging capacitor, and the middle-position ground supplement capacitor together constitute the scaling capacitor.

[0108] In this embodiment, the low-ground supplementary capacitor, the low-to-middle bridging capacitor, and the middle-ground supplementary capacitor are defined as a whole as a scaling capacitor. The scaling capacitor is not a single capacitor, but a combination of multiple capacitors. It is called a scaling capacitor because these multiple capacitors collectively participate in forming the capacitance ratio between the low-ground and middle-ground capacitor regions, thus functioning as a whole, rather than being considered independently. Therefore, the scaling capacitor described in this application refers to a capacitor network composed of multiple capacitors, and is not limited to a specific structure or a single independent device.

[0109] "Common configuration" means that the function corresponding to the scaling capacitor is achieved by the three capacitors mentioned above, rather than requiring the three capacitors to form an integrated structure or to adopt a fixed connection method. For example, the three capacitors can be set in different layout positions, or can be appropriately adjusted according to the actual wiring method, as long as the three together form the corresponding capacitor combination. In this application, the specific physical positional relationship between the three capacitors is not limited, nor is it limited to a continuous arrangement.

[0110] From a layout perspective, the low-position ground supplement capacitor, the low-to-middle bridging capacitor, and the middle-position ground supplement capacitor are all located near the low-position capacitor area and the middle-position capacitor area, and therefore can be arranged as relatively concentrated functional units. When the above three capacitors are configured together as scaling capacitors, their layout can be considered uniformly without having to arrange them independently according to different types of capacitors, so that the corresponding areas maintain a consistent capacitor composition, while maintaining the connection relationship with the low-position capacitor area and the middle-position capacitor area.

[0111] In this application, the three capacitors mentioned above are uniformly defined as scaling capacitors. When describing the composition of the capacitor array, the originally dispersed multiple capacitors can be described as a whole. In this way, while ensuring that the low-position capacitor region, the middle-position capacitor region, the high-position capacitor region, and the bridging relationship remain unchanged, the corresponding capacitor combinations in the capacitor array have a unified name, making the composition relationship of the entire three-segment capacitor array clearer, and facilitating the explanation of the correspondence between the scaling capacitors and other capacitor units.

[0112] It should be noted that this application does not limit the specific capacitance value relationship of each capacitor in the scaling capacitor, nor does it limit the three capacitors to be formed using the same specifications. The capacitance value of each capacitor can be determined according to the position weighting configuration of the corresponding capacitor region, or it can be formed using a unit capacitance or an integer multiple of a unit capacitance, as long as the above three capacitors together constitute the scaling capacitor. This application does not impose any restrictions on this.

[0113] In a preferred embodiment, the capacitor unit is formed using a metal-insulator-metal capacitor, and each capacitor unit is surrounded by a protective ring located on the same metal layer as the metal-insulator-metal capacitor, and the protective ring is grounded.

[0114] In this embodiment, each capacitor unit is formed using a metal-insulator-metal capacitor. A metal-insulator-metal capacitor refers to a capacitor structure formed by two layers of metal electrodes and an insulating medium between them, often abbreviated as MIM capacitor (Metal-Insulator-Metal Capacitor). Since MIM capacitors are formed using integrated circuit technology, they can be directly arranged on a chip layout and used as basic capacitor units in a three-segment capacitor array. In this application, each capacitor unit in the low-position capacitor region, middle-position capacitor region, and high-position capacitor region can be formed using the above structure, or it can be combined with the aforementioned unit capacitors to form corresponding capacitance values; this application does not limit this.

[0115] Each capacitor cell is surrounded by a protective ring. The protective ring is a ring-shaped conductor structure surrounding the corresponding capacitor cell. It can be continuously surrounding the capacitor cell, or it can consist of multiple conductor segments forming a ring around the capacitor cell; as long as it surrounds the corresponding capacitor cell, this application does not impose any limitations. After the protective ring is placed around the capacitor cell, a continuous or nearly continuous conductor boundary is formed around the capacitor cell, giving each capacitor cell a similar peripheral structure.

[0116] The guard ring and the metal-insulator-metal capacitor reside on the same metal layer. This means that the conductor forming the guard ring and the metal forming the corresponding electrode of the MIM capacitor are located on the same process metal layer, not on other metal layers or spanning multiple metal layers. By using the same metal layer, the guard ring and the corresponding capacitor unit can be arranged within the same layout layer without the need for additional metal layers. Furthermore, the guard ring can be continuously positioned along the periphery of the corresponding capacitor unit, maintaining a consistent layout across the entire board.

[0117] Grounding can refer to connecting to chip ground, analog ground, or other grounding nodes that serve as a reference potential; this application does not limit this. When the guard ring remains grounded, a stable reference potential is formed around the guard ring, ensuring a consistent potential environment around each capacitor unit. Different capacitor units can also maintain similar external conditions, thus maintaining a consistent external environment for each capacitor unit in the entire capacitor array.

[0118] From a layout perspective, guard rings are arranged around each capacitor cell, thus forming a relatively independent peripheral protection structure for each capacitor cell. When the capacitor cells are arranged in the aforementioned centrosymmetric manner, the corresponding guard rings are also arranged synchronously with each capacitor cell, maintaining a regular distribution of guard rings throughout the capacitor array without affecting the original arrangement between the capacitor cells. Furthermore, the guard rings are formed using the same metal layer as the MIM capacitors, therefore, there is no need to change the original layout organization of the capacitor array.

[0119] It should be noted that this application does not limit the specific width, shape, or spacing between the guard ring and the capacitor unit. For example, the guard ring can be formed in the form of a rectangle, square, polygon, or other closed structure; the spacing between the guard ring and the capacitor unit can be determined according to manufacturing process requirements; the guard ring can also be formed by a continuous conductor or multiple conductor segments, as long as it can be set around the corresponding capacitor unit and grounded, this application does not limit these aspects.

[0120] Furthermore, this application does not limit which specific metal layer is used to form the metal-insulator-metal capacitor. In different process platforms, the corresponding MIM capacitor forming layer can be selected based on the metal layer provided by the process, and a corresponding guard ring can be formed on the same metal layer. Therefore, the "same metal layer" mentioned in this application refers to the guard ring and the corresponding MIM capacitor being implemented using the same process metal layer, rather than limiting it to a specific metal layer number.

[0121] The MIM capacitor is only one implementation method in this embodiment. In other embodiments, each capacitor unit can also be implemented using a polysilicon-insulator-polysilicon capacitor (PIP capacitor), a metal interconnect capacitor (MOM capacitor), or other integrated capacitor structures that can form corresponding capacitance values, as long as the capacitance value configuration and layout arrangement requirements of the three-segment capacitor array can be met. This application does not limit this.

[0122] In summary, combining Figure 3 As shown, both the P-terminal and N-terminal capacitor arrays include a low-position capacitor region, a middle-position capacitor region, and a high-position capacitor region. Taking the P-terminal capacitor array as an example, one end of the low-position capacitor region is connected to the switch array, and the other end is connected to the low-position ground supplement capacitor and the low-to-middle-position bridging capacitor, respectively. The other side of the low-to-middle-position bridging capacitor is connected to the middle-position capacitor region, which is simultaneously connected to the middle-position ground supplement capacitor and the middle-to-high-position bridging capacitor. The other side of the middle-to-high-position bridging capacitor is connected to the high-position capacitor region. The N-terminal capacitor array adopts the same connection method as the P-terminal capacitor array, and the two form a differential capacitor array. The above capacitors, according to their corresponding connection relationships, together form a three-segment capacitor array, thereby completing the capacitor array configuration corresponding to the successive approximation analog-to-digital converter.

[0123] After completing the above three-segment capacitor array configuration, the successive approximation conversion process can be completed by splitting the capacitor array timing. Splitting the capacitor array timing means splitting the originally high-weight capacitor corresponding to the highest bit into multiple smaller-weight capacitors, and controlling each capacitor to complete the charge redistribution according to the corresponding timing, instead of directly using a single highest-weight capacitor to complete the successive comparison.

[0124] Taking a 4-bit conversion as an example, the weighted capacitors corresponding to a traditional capacitor array can be represented as 8, 4, 2, 1, 1. Splitting the capacitor array timing divides the 8-fold unit capacitor corresponding to the highest bit into 4, 2, 1, and 1-fold unit capacitors, i.e., 8 = 4 + 2 + 1 + 1. The capacitor array can then be represented as 4, 4, 2, 2, 1, 1, 1, 1. The split weighted capacitors are then divided into a first capacitor set and a second capacitor set, each containing 4, 2, 1, and 1 respectively. The above 4-bit conversion is merely an example; this application does not limit the specific number of bits in the successive approximation analog-to-digital converter. For analog-to-digital converters with different bit widths, the corresponding highest bit capacitor can also be split using the same approach.

[0125] When comparing 1 / 2Vref, all capacitors in the first capacitor set are connected to the reference voltage Vref, and all capacitors in the second capacitor set are connected to ground. When the MSB (Most Significant Bit) corresponding to the comparison result is 0, the capacitors in the first capacitor set corresponding to 4 times the unit capacitance are switched from the reference voltage Vref to ground; when the MSB corresponding to the comparison result is 1, the capacitors in the second capacitor set corresponding to 4 times the unit capacitance are switched from ground to the reference voltage Vref. The comparison of subsequent bits continues according to the successive approximation process. It is understood that the above switching process only illustrates one operating mode; this application does not limit the specific switching order or control method, as long as the corresponding successive approximation conversion can be completed.

[0126] Compared to the traditional successive approximation process, the traditional structure usually requires the pre-switching of the highest-order capacitor first, and then the corresponding capacitor is switched again according to the comparison result. In the split capacitor array timing, the capacitor corresponding to each comparison is switched only once according to the comparison result. Therefore, the number of capacitor switching times during the conversion process is reduced, and the energy consumption generated by switching is reduced accordingly.

[0127] The high-position capacitor region is formed using capacitor splitting technology. Capacitor splitting refers to dividing the capacitor originally corresponding to a high-position weight into two or more capacitors with the same capacitance value to jointly achieve the corresponding weight, rather than using a single large-capacity capacitor to achieve the corresponding position weight. In this application, the high-position capacitor region can be split into multiple capacitors with the same capacitance value as described above, for example, splitting it into four capacitors with the same capacitance value to form the corresponding high-position capacitor region.

[0128] In traditional DAC (Digital to Analog Converter) capacitor arrays, each capacitor not only samples the input signal but also participates in subsequent charge redistribution. During actual operation, the capacitance value changes with the voltage across the capacitor. When the input signal amplitude is small, this effect is relatively minor; however, as the input signal amplitude increases, the capacitor voltage effect gradually increases, affecting the actual capacitance value. Therefore, this embodiment employs a capacitor splitting method, dividing the corresponding high-order capacitor into two equal parts, with each part sampling in opposite ways.

[0129] Specifically, the two split capacitors are sampled based on the reference voltage Vref and ground, respectively. After sampling, the corresponding output nodes of the two capacitors are connected together, thus forming a sampling method based on the common-mode voltage Vcm. Because the two split capacitors have opposite connection relationships, the impact of capacitor voltage changes can be reduced, allowing the high-order capacitance region to maintain a relatively stable capacitance value during the conversion process. Simultaneously, since the split capacitors participate in their respective sampling processes, the energy consumption caused by partial switching during the conversion process is also reduced.

[0130] It should be noted that this application does not limit the high-level capacitor to be split into two or four capacitors, nor does it limit the fixed connection method of each split capacitor. The number of splits, the connection relationship, and the specific sampling method can all be adjusted according to the resolution, capacitance configuration, and conversion requirements of the successive approximation analog-to-digital converter, as long as the corresponding high-level capacitor area can be formed. This application does not impose any restrictions on these aspects.

[0131] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0132] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A three-segment capacitor array for a successive approximation analog-to-digital converter, characterized in that, The system includes a P-terminal capacitor array and an N-terminal capacitor array. Both the P-terminal capacitor array and the N-terminal capacitor array include a low-position capacitor region, a middle-position capacitor region, and a high-position capacitor region arranged in sequence. The low-position capacitor region and the middle-position capacitor region are connected by a low-to-middle-position bridging capacitor, and the middle-position capacitor region and the high-position capacitor region are connected by a middle-to-high-position bridging capacitor to form the three-segment capacitor array. The geometric center point of the P-terminal capacitor array coincides with the geometric center point of the N-terminal capacitor array. The multiple capacitor units in the low-position capacitor region, the middle-position capacitor region, and the high-position capacitor region of the P-end capacitor array and the N-end capacitor array are arranged in a centrally symmetrical manner about the geometric center point of their respective capacitor regions.

2. The three-segment capacitor array for a successive approximation analog-to-digital converter as described in claim 1, characterized in that, It also includes a switch array, which comprises multiple switch units, each of which is connected to a corresponding capacitor unit to control the connection state between the corresponding capacitor unit and different potential nodes.

3. The three-segment capacitor array for a successive approximation analog-to-digital converter as described in claim 2, characterized in that, The low-position capacitor region includes multiple low-position capacitor units and low-position redundant capacitor units. The median capacitor region includes multiple median capacitor units and median redundant capacitor units; The high-level capacitor region includes multiple high-level capacitor units.

4. The three-segment capacitor array for a successive approximation analog-to-digital converter as described in claim 3, characterized in that, The low-position capacitor region includes a low-position redundant bit capacitor unit for forming two low-position redundant bits, and the middle-position capacitor region includes a middle-position redundant bit capacitor unit for forming one middle-position redundant bit.

5. The three-segment capacitor array for a successive approximation analog-to-digital converter as described in claim 3, characterized in that, The capacitor units in the low-position capacitor region, the middle-position capacitor region, and the high-position capacitor region, as well as the low-to-middle-position bridging capacitor and the middle-to-high-position bridging capacitor, are all composed of a unit capacitor or an integer multiple of a unit capacitor. Each capacitor unit in the low-position capacitor region, the middle-position capacitor region, and the high-position capacitor region, as well as the low-to-middle-position bridging capacitor and the middle-to-high-position bridging capacitor, are connected to the reference voltage, the input signal, or the ground potential through corresponding switching units.

6. The three-segment capacitor array for a successive approximation analog-to-digital converter as described in claim 2, characterized in that, The three-segment capacitor array is divided into multiple capacitor groups, each capacitor group including multiple capacitor units arranged longitudinally, and the switch array is respectively disposed on both sides of each capacitor group, and each switch unit in the switch array is connected to the capacitor unit in the corresponding capacitor group. Alternatively, the three-segment capacitor array can be arranged continuously to form an overall capacitor array, and the switch array can be disposed around the overall capacitor array.

7. The three-segment capacitor array for a successive approximation analog-to-digital converter as described in claim 6, characterized in that, Virtual capacitor units are provided around each of the capacitor groups, and / or, virtual capacitor units are provided around the three-segment capacitor array.

8. The three-segment capacitor array for a successive approximation analog-to-digital converter as described in claim 1, characterized in that, It also includes a low-position ground supplement capacitor and a middle-position ground supplement capacitor. One end of the low-position ground supplement capacitor is connected to the connection node between the low-position capacitor area and the low-to-middle-position bridging capacitor, and the other end is grounded. One end of the middle-position ground supplement capacitor is connected to the connection node between the middle-position capacitor area and the middle-to-high-position bridging capacitor, and the other end is grounded.

9. The three-segment capacitor array for a successive approximation analog-to-digital converter as described in claim 8, characterized in that, The low-position ground supplement capacitor, the low-to-mid-position bridging capacitor, and the mid-position ground supplement capacitor together constitute the scaling capacitor.

10. The three-segment capacitor array for a successive approximation analog-to-digital converter as described in any one of claims 1 to 9, characterized in that, The capacitor unit is formed using a metal-insulator-metal capacitor, and each capacitor unit is surrounded by a protective ring located on the same metal layer as the metal-insulator-metal capacitor. The protective ring is grounded.

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