Ldpc code rate adaptive adjustment method and system for storage control chip

Abstract

This application relates to the field of error correction coding technology for storage devices, and discloses a method and system for adaptive LDPC code rate adjustment for storage control chips. The method includes: obtaining the decoding resource state tensor and log-likelihood ratio confidence drift distribution of the storage control chip; generating candidate control tuples, each candidate control tuple containing a set of LDPC decoding parameter configuration schemes; determining the candidate control tuple with the minimum joint loss of resource constraints as the target control tuple; routing the access task to the target decoding path and configuring LDPC parameters according to the target control tuple; performing online convergence verification on the access task during the decoding operation of the decoder; if the verification result of the online convergence verification does not meet the preset verification boundary, performing a downgrade rollback operation and writing the execution result back to the code rate strategy table. This application improves the reliability of adaptive LDPC code rate adjustment for storage control chips.

Description

Technical Field

[0001] This application relates to the field of error correction coding technology for storage devices, and in particular to an LDPC code rate adaptive adjustment method and system for storage control chips. Background Technology

[0002] Solid-state storage devices rely on flash memory to store data. However, flash memory cells undergo physical degradation during repeated erase and write operations, causing the stored charge state to gradually deviate from the standard threshold, thus increasing the original bit error rate. To ensure data integrity, storage controller chips generally use low-density parity check codes for error correction protection. However, as flash memory usage time increases, charge interference between adjacent cells intensifies, and voltage boundaries become blurred, making it difficult for decoders to accurately determine the original data.

[0003] Existing error correction schemes typically pre-set fixed code rate configurations and decoding parameters during system initialization. This static strategy has significant limitations: when the flash memory is in a healthy state, an excessively high code rate configuration wastes valuable decoder computing resources; when the media is severely aged, the pre-set error correction strength is insufficient to cope with the surge in error bits. The core problem lies in the lack of real-time awareness of the current decoder resource load status and the degree of flash memory channel degradation, which may cause critical business data to miss the optimal error correction opportunity because the decoder is occupied by low-priority tasks. Summary of the Invention

[0004] To address the aforementioned technical issues, this application provides an LDPC code rate adaptive adjustment method and system for storage control chips, which automatically selects the optimal code rate, quantization precision, number of iterations, and decoding path to maximize decoding resource utilization efficiency while ensuring data error correction reliability.

[0005] In a first aspect, this application provides an LDPC code rate adaptive adjustment method for a storage control chip, the method comprising: Obtain the decoding resource state tensor and log-likelihood ratio confidence drift distribution of the storage control chip; generate candidate control tuples based on the decoding resource state tensor and the log-likelihood ratio confidence drift distribution, each candidate control tuple containing a set of LDPC decoding parameter configuration schemes; Calculate the joint resource constraint loss of each candidate control tuple, and determine the candidate control tuple with the minimum joint resource constraint loss as the target control tuple; The access task is routed to the target decoding path according to the resource constraint joint loss, and the LDPC parameters are configured according to the target control tuple so that the decoder of the storage control chip performs the decoding operation. During the decoding operation, the access task is checked online. If the result of the online convergence check does not meet the preset check boundary, a downgrade rollback operation is performed, and the execution result is written back to the code rate strategy table.

[0006] Secondly, this application provides an LDPC rate adaptive adjustment system for a storage control chip, the system comprising: The acquisition unit is used to acquire the decoding resource state tensor and the log-likelihood ratio confidence drift distribution of the storage control chip; and to generate candidate control tuples based on the decoding resource state tensor and the log-likelihood ratio confidence drift distribution, wherein each candidate control tuple contains a set of LDPC decoding parameter configuration schemes. The resource constraint unit is used to calculate the joint resource constraint loss of each candidate control tuple and determine the candidate control tuple with the minimum joint resource constraint loss as the target control tuple. The routing configuration unit is used to route the access task to the target decoding path according to the resource constraint joint loss, and configure LDPC parameters according to the target control tuple so that the decoder of the storage control chip performs the decoding operation; The verification backoff unit is used to perform online convergence verification on the access task during the decoding operation of the decoder; if the verification result of the online convergence verification does not meet the preset verification boundary, a downgrade backoff operation is performed, and the execution result is written back to the code rate strategy table.

[0007] Compared with the prior art, the beneficial effects of the present invention are at least as follows: First, by constructing a two-dimensional perception mechanism of the decoding resource state tensor and the log-likelihood ratio confidence drift distribution, the hardware resource load of the decoder and the degree of flash channel degradation are quantified in real time. This ensures that subsequent decoding parameter selection is based on accurate state perception, overcoming the blind-state problem in existing technologies where the decoder cannot perceive its own resources and channel quality. Candidate control tuples are generated through Cartesian product combination and a three-stage hierarchical screening strategy involving storage, time, and channel. This ensures diversity in the decision space while avoiding combinatorial explosion, allowing the decoding parameter configuration space to accurately match the current resource constraints and channel conditions. Then, a three-dimensional weighted joint loss model using the first, second, and third loss values ​​unifies the constraints of decoding performance, hardware resource consumption, and system throughput into a single loss value, achieving optimal configuration selection under multi-objective constraints. The dynamic weight allocation mechanism allows the loss assessment to flexibly adapt to different resource bottleneck scenarios. Finally, a three-path intelligent routing driven by service priority and decoding core occupancy ensures the success rate of critical data error correction while maximizing system throughput. Finally, through the extrapolation prediction mechanism of online convergence verification, it is possible to predict whether the configuration can converge before the decoding is completed, so as to achieve predictive intervention rather than ex-post verification. Combined with the decision tree degradation backoff strategy and the self-learning write-back of the bitrate strategy table, the system has the ability to continuously evolve. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a flowchart of an LDPC code rate adaptive adjustment method for a storage control chip according to an embodiment of this application; Figure 2 This is a schematic diagram comparing the effects of different bitrate configurations in an embodiment of this application. Figure 3 This is a schematic diagram of the structure of an LDPC code rate adaptive adjustment system for a storage control chip according to an embodiment of this application. Detailed Implementation

[0010] This application provides an LDPC code rate adaptive adjustment method and system for a storage control chip. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" or "having" and any variations thereof are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0011] For ease of understanding, the specific process of the embodiments of this application is described below. Please refer to [link / reference]. Figure 1 An LDPC code rate adaptive adjustment method for a storage control chip, as described in this application embodiment, includes: Step S1: Obtain the decoding resource state tensor and log-likelihood ratio confidence drift distribution of the storage control chip; generate candidate control tuples based on the decoding resource state tensor and log-likelihood ratio confidence drift distribution, with each candidate control tuple containing a set of LDPC decoding parameter configuration schemes.

[0012] Furthermore, the confidence drift distribution of the decoding resource state tensor and log-likelihood ratio of the memory control chip is obtained, including: The LDPC decoding core occupancy rate, on-chip memory remaining capacity, decoding queue depth, device temperature, power budget, access task deadline, and current raw bit error rate estimate are periodically collected by hardware counters and status registers. The collected parameters are then processed according to the corresponding normalization strategy to construct a decoding resource state tensor.

[0013] During soft read operations, a voltage sequence including the default read reference voltage and corresponding upper and lower offset reference voltages is applied to the flash memory cells. The comparison results under each reference voltage are recorded as soft read reference voltage sampling data. Based on the soft read reference voltage sampling data, the log-likelihood ratio of each bit is calculated by looking up the log-likelihood ratio mapping table obtained in advance through channel model training. The log-likelihood ratio of each bit is compared with the historical log-likelihood ratio mean of the corresponding position to calculate the offset. The number of bits is counted according to the offset amplitude interval to construct a confidence drift histogram. Combined with the log-likelihood ratio variance of each bit position, the parser convergence slope of the historical decoding task, and the failed codeword position information, a multi-dimensional feature vector is constructed as the log-likelihood ratio confidence drift distribution.

[0014] Further, candidate control tuples are generated, including: The candidate value sets for LDPC code rate, log-likelihood ratio quantization bits, maximum number of iterations, number of soft read reference voltages, and decoding parallelism are obtained respectively. The candidate value sets are combined by Cartesian product to generate an initial candidate control tuple set. A hierarchical screening strategy is used to screen the tuples. The combinations remaining after hierarchical screening constitute the candidate control tuples.

[0015] Furthermore, the tiered screening strategy comprises three phases executed sequentially: The first stage filters combinations where the storage demand exceeds the remaining on-chip memory capacity based on the remaining on-chip memory capacity in the decoding resource state tensor by looking up a pre-established storage demand table. The second stage filters combinations where the expected decoding delay exceeds the access task deadline based on the access task deadline in the decoding resource state tensor by using a decoding delay estimation model. The third stage filters combinations that match the current channel quality based on the mean offset of the log-likelihood ratio confidence drift distribution. When the mean offset is less than a first drift threshold, combinations consisting of candidate values ​​with a code rate greater than the first code rate threshold, candidate values ​​with a quantization bit count less than the first quantization threshold, and candidate values ​​with a maximum iteration count less than the first iteration threshold are retained. When the mean offset is greater than a second drift threshold, combinations consisting of candidate values ​​with a code rate less than the second code rate threshold, candidate values ​​with a quantization bit count greater than the second quantization threshold, and candidate values ​​with a maximum iteration count greater than the second iteration threshold are retained.

[0016] Specifically, the storage control chip needs to simultaneously acquire the decoding resource state tensor reflecting its own hardware resource status, and the log-likelihood ratio confidence drift distribution reflecting the degree of flash memory channel degradation. These two types of information together form the decision basis for subsequent adaptive adjustment of decoding parameters.

[0017] For constructing the decoding resource state tensor, the storage control chip periodically collects seven parameters through internal hardware counters and status registers. The LDPC decoding core occupancy rate is obtained by reading the task allocation table of the decoding scheduling unit; the remaining on-chip memory capacity is obtained through the address allocation record of the memory controller; the decoding queue depth is calculated from the difference between the tail pointer and the head pointer of the first-in-first-out queue; the device temperature is collected by the chip's built-in digital temperature sensor; the power budget is obtained through interaction with the power management unit; the access task deadline is carried in the quality of service field of the host command; and the current raw bit error rate estimate is obtained by using a moving average window to statistically analyze the initial verification results of the most recent read operations. The collection methods for all the above parameters are all routine state reading operations of the storage control chip's internal hardware modules.

[0018] The seven parameters mentioned above have different physical dimensions and numerical ranges, therefore they need to be processed according to the corresponding normalization strategies to uniformly map each parameter to a numerical range of zero to one: the LDPC decoding core occupancy rate and the current original bit error rate estimate, which are themselves proportional values, are used directly; the remaining capacity of on-chip memory is divided by the total capacity, the decoding queue depth is divided by the maximum queue capacity, the device temperature is subtracted from the minimum operating temperature and then divided by the temperature operating range, and the power budget is divided by the rated power of the decoding subsystem; the access task deadline is normalized by the ratio of the remaining time relative to the current moment to the expected execution time of the task. It should be noted that the access task deadline uses the above normalized ratio when constructing the decoding resource state tensor for dimensionless operations in subsequent joint loss calculations; at the same time, the storage control chip retains the original absolute value of the deadline during the command parsing stage for direct comparison with the expected decoding delay in subsequent hierarchical filtering strategies. The seven normalized parameters are arranged in a preset order to construct a one-dimensional vector form of the decoding resource state tensor.

[0019] The construction of the log-likelihood ratio confidence drift distribution needs to start from the signal characteristics of the flash memory read process. During repeated erase and write operations, factors such as manufacturing process deviations, read / write interference, and charge leakage cause the threshold voltage distribution of flash memory cells to shift and broaden, resulting in a drift in the log-likelihood ratio distribution. The log-likelihood ratio confidence drift distribution is a multi-dimensional feature vector used to quantify this drift phenomenon.

[0020] The construction of the log-likelihood ratio confidence drift distribution first requires obtaining soft-read reference voltage sampling data: During a soft-read operation, the memory controller chip applies a voltage sequence to the flash memory cell, including the default read reference voltage and its upper and lower offset reference voltages. For each applied reference voltage, the chip's comparator outputs a result determining whether the cell threshold voltage is high or low under that reference voltage. The comparison results under all reference voltages are concatenated in the order of application to form the soft-read reference voltage sampling data. This sampling data records the distribution information of the cell threshold voltage near each reference voltage point, serving as the basic input for subsequent log-likelihood ratio calculations.

[0021] After obtaining the soft read reference voltage sampling data, the storage control chip uses this data to look up the log-likelihood ratio mapping table pre-trained through the channel model to calculate the log-likelihood ratio of each bit. This mapping table is constructed during the channel calibration phase before chip delivery, using the Bayesian criterion to calculate the natural logarithm of the posterior probability ratio for different flash memory aging states and then discretizing it. The input data is the soft read reference voltage sampling sequence, and the output data is the log-likelihood ratio value for each bit position. Since the mapping table constructs corresponding sub-tables for different flash memory aging states, during runtime, the storage control chip jointly determines the aging state level based on the current flash memory block's erase / write cycle count value and the current raw bit error rate estimate in the decoding resource state tensor: the erase / write cycle count value is divided into several intervals, each interval corresponding to an aging state level. Simultaneously, the current raw bit error rate estimate is used as an auxiliary check; when the raw bit error rate estimate exceeds the reference bit error rate range corresponding to the current interval, the aging state level is upgraded or downgraded. Based on the finally determined aging state level, the corresponding sub-table is selected for a lookup operation.

[0022] After calculating the log-likelihood ratio of each bit, it is compared with the historical mean log-likelihood ratio of the corresponding bit position to calculate the offset. The historical mean log-likelihood ratio is calculated using a sliding window method, which is the arithmetic mean of the log-likelihood ratio values ​​at that position in the most recent preset number (e.g., 100) of successful decoding tasks. When the cumulative number of attempts has not reached the preset number, all existing historical data is used to calculate the mean. When the cumulative number of attempts reaches the preset number, the data is added to the window for each new successful decoding task, while the oldest data in the window is removed. The offset is the difference between the current log-likelihood ratio and the historical mean. The confidence drift histogram is constructed by counting the number of bits according to the offset amplitude interval. The horizontal axis of the confidence drift histogram is the offset amplitude interval, and the vertical axis is the number of bits falling into each interval. Its center position reflects the overall confidence drift trend direction, and the distribution width reflects the degree of unevenness of the drift.

[0023] Based on the confidence drift histogram, a multi-dimensional feature vector is constructed as the log-likelihood ratio confidence drift distribution by combining the log-likelihood ratio variance of each bit position, the parser convergence slope of historical decoding tasks, and the location information of failed codewords. The log-likelihood ratio variance characterizes the dispersion of confidence at each bit position, the parser convergence slope reflects the rate of decrease in the number of erroneous parsers during decoding iterations, and the location of failed codewords records the addresses of erroneous bits that could not be corrected in historical decoding failures.

[0024] Specifically, a candidate control tuple refers to a set of discrete configuration schemes for LDPC decoding parameters. Each candidate control tuple contains a specific set of decoding parameter settings to guide the decoder in performing error correction operations. The components of a candidate control tuple include: the LDPC code rate, defined as the ratio of the number of information bits to the total number of bits in the codeword; a lower code rate results in more redundancy check bits and stronger error correction capability; the number of quantization bits in the log-likelihood ratio determines the accuracy of the soft-decision information representation; more quantization bits result in a richer confidence level that the log-likelihood ratio can represent; the maximum number of iterations limits the computational budget of the decoding algorithm; more iterations result in more error correction opportunities; the number of soft-read reference voltages affects the accuracy of obtaining the log-likelihood ratio; a higher number results in higher threshold voltage sampling resolution; and the decoding parallelism characterizes the number of decoding cores that execute decoding tasks simultaneously; higher parallelism results in greater throughput.

[0025] The process of generating candidate control tuples consists of two stages: combination and screening. In the combination stage, candidate value sets for each of the five parameters are obtained, and then these five candidate value sets are combined using a Cartesian product. The Cartesian product combination involves selecting one value from each parameter's candidate value set, enumerating all possible combinations, and generating an initial set of candidate control tuples. The size of this set is equal to the product of the number of candidate values ​​for the five parameters, covering all theoretically feasible decoding parameter configuration schemes.

[0026] However, the initial set of candidate control tuples contains many combinations that are not feasible in real-world systems, so a hierarchical screening strategy is needed for selection.

[0027] The first stage is storage constraint filtering, which filters combinations with excessive storage requirements by looking up a storage requirement table based on the remaining on-chip memory capacity. The storage requirement table records the total storage requirements for the parity check matrix, log-likelihood ratio vector storage, and iterative message buffer under different code rate and quantization bit combinations. The second stage is time constraint filtering, which filters combinations with expected decoding delay exceeding the limit based on the access task deadline (raw absolute value) using a decoding delay estimation model. The third stage is channel matching filtering, which extracts the mean offset from the log-likelihood ratio confidence drift distribution as a quantitative indicator of channel quality. The mean offset is the weighted sum of all bit offsets in the confidence drift histogram, weighted by the soft-read sampling confidence of each bit. The soft-read sampling confidence is determined by the consistency of the comparison results for that bit under various reference voltages.

[0028] Specifically, the storage requirement table is constructed based on the following principle: On-chip memory consumption during LDPC decoding mainly consists of three parts: parity check matrix storage (LDPC parity check matrix is ​​a sparse matrix, using a compressed storage format to store only the positions and values ​​of non-zero elements; storage size is related to the code rate and matrix design); log-likelihood ratio vector storage (its storage size is equal to the codeword length multiplied by the number of quantization bits); and iterative message buffer (used to store messages transmitted between variable nodes and parity check nodes; buffer size is related to the number of sides of the parity check matrix and the message representation precision). The input data for this table is the code rate index and the number of quantization bits, and the output data is the corresponding total storage requirement in bytes.

[0029] The decoding delay estimation model is an estimation function that maps the parameter configuration of candidate control tuples to the estimated decoding delay. Its working principle is as follows: the estimated decoding delay consists of two parts: the soft read operation time and the iterative calculation time. The soft read operation time is proportional to the number of soft read reference voltages, because each additional reference voltage requires additional voltage setup time and comparator settling time. The iterative calculation time depends on the codeword length, the maximum number of iterations, and the computational throughput of the decoding core. Each iteration of the decoding core requires traversing all non-zero elements of the parity check matrix to perform addition and table lookup operations. The iteration time of a single codeword can be obtained by dividing the product of the codeword length and the number of iterations by the core throughput.

[0030] When the average offset is less than the first drift threshold, it indicates that the current channel condition is good and the decoding error correction requirement is low. In this case, the combination of candidate values ​​with a code rate greater than the first code rate threshold, candidate values ​​with a quantization bit count less than the first quantization threshold, and candidate values ​​with a maximum number of iterations less than the first iteration threshold is retained. This is a lightweight configuration with low resource consumption, allowing the decoder to complete error correction at the lowest cost under high code rate and low precision conditions. When the average offset is greater than the second drift threshold, it indicates that the current channel is severely degraded and the decoding error correction requirement is high. In this case, the combination of candidate values ​​with a code rate less than the second code rate threshold, candidate values ​​with a quantization bit count greater than the second quantization threshold, and candidate values ​​with a maximum number of iterations greater than the second iteration threshold is retained. This is a reinforced configuration with stronger error correction capability, ensuring that the decoder can cope with a surge in error bits. When the average offset is greater than or equal to the first drift threshold and less than or equal to the second drift threshold, it indicates that the current channel condition is at a moderate degradation level. At this point, no threshold constraints are imposed on the code rate, quantization bits, and maximum iteration count. All combinations remaining after the first and second stages of filtering are retained, allowing subsequent joint loss calculations to automatically select the optimal value within the complete decision space. The first and second drift thresholds, the first and second code rate thresholds, the first and second quantization thresholds, and the first and second iteration thresholds are all pre-calibrated during the system initialization phase based on the characteristic parameters of the flash memory medium and historical operating data.

[0031] Step S2: Calculate the joint resource constraint loss of each candidate control tuple, and determine the candidate control tuple with the minimum joint resource constraint loss as the target control tuple.

[0032] Further, the joint loss due to resource constraints for each candidate control tuple is calculated, including: For each candidate control tuple, a first loss value is determined based on the target bit error rate margin and the expected decoding delay. When the target bit error rate margin is negative, the first loss value is set as the maximum penalty value to exclude the corresponding candidate control tuple. When the target bit error rate margin is positive, the first loss value is obtained by weighting the reciprocal of the target bit error rate margin and the delay term after nonlinear transformation of the ratio of the expected decoding delay to the access task deadline.

[0033] The second loss value is determined by dynamically weighted summation of on-chip memory occupancy ratio and power consumption temperature rise normalization value. When the on-chip memory occupancy ratio exceeds the preset storage threshold, a penalty factor is introduced to make the second loss value grow non-linearly. The weights of the dynamic weighted summation are allocated according to the relative tension between the remaining on-chip memory capacity and the device temperature in the decoding resource state tensor.

[0034] The third loss value is determined by a linear combination of the queue blocking probability and the log-likelihood ratio confidence drift penalty term. The log-likelihood ratio confidence drift penalty term is obtained by nonlinear mapping the absolute value of the difference between the error correction capability index of the candidate control tuple and the dispersion of the log-likelihood ratio confidence drift distribution.

[0035] The resource-constrained joint loss is obtained by weighted summation of the first, second, and third loss values.

[0036] Specifically, the resource-constrained joint loss is composed of weighted sub-loss values ​​from three dimensions, which quantify the cost of candidate control tuples from the perspectives of decoding performance and time constraints, hardware resource consumption and system stability, and system throughput and channel adaptability.

[0037] The first loss value represents a trade-off between decoding performance and time constraints, calculated based on the target bit error rate margin and the expected decoding delay. The target bit error rate margin refers to the safety margin between the residual bit error rate after decoding and the system's acceptable bit error rate. It is obtained by estimating the residual bit error rate after decoding for each candidate control tuple under the current original bit error rate and log-likelihood ratio confidence drift conditions using a channel coding theory model, and then normalizing it. The channel coding theory model is a mathematical model describing the relationship between the error correction performance of LDPC codes and the input signal-to-noise ratio under different code rates and iteration parameters. Its input data includes the code rate, number of quantization bits, maximum number of iterations, and the current original bit error rate and log-likelihood ratio confidence drift parameters for the candidate control tuple. The output data is the expected residual bit error rate after decoding under this configuration condition. This model is built upon density evolution theory, which predicts the decoding convergence threshold by tracking the evolution of the probability density function of the log-likelihood ratio message during iteration. When the parameters of the candidate control tuple enable the message density to converge towards the correct decision direction during iteration, the expected residual bit error rate of this configuration is low. The expected decoding latency consists of the time consumed by soft read operations and the time consumed by iterative computation. When decoding multiple codewords in parallel, a parallel efficiency reduction factor is introduced for correction.

[0038] After obtaining the target bit error rate margin and the expected decoding delay, the two are combined into a first loss value. When the target bit error rate margin is negative, the first loss value is set as the maximum penalty value. This maximum penalty value is ten times the maximum first loss value among all candidate control tuples where the target bit error rate margin is positive. If the margins of all candidate control tuples are negative, a preset constant is used as the maximum penalty value.

[0039] When the target bit error rate margin is positive, the formula for calculating the first loss value is: Where m is the target bit error rate margin, To prevent division by zero, a regularization constant (with a value of...) ), This is the ratio of the expected decoding latency to the access task deadline. It is an exponential function, and k is the kurtosis coefficient (with a value of 5 to 10). and These are weighting coefficients, and their sum is 1. The reciprocal term. Its function is as follows: the smaller the margin, the larger the reciprocal term, prompting the system to tend to choose a more conservative configuration in terms of error correction capability; when the margin is sufficient, the reciprocal term decreases, and the weight of the delay term relatively increases, guiding the system to choose a configuration with faster decoding speed. The function of the exponential function is: when the ratio... As the value approaches 1, the function value increases. The growth rate increases dramatically, mapping the region to a steeply growing loss curve to ensure that timeout risk is fully penalized.

[0040] The second loss value focuses on hardware resource consumption and system stability. The on-chip memory usage ratio is obtained by summing the storage requirements of the parity check matrix, the log-likelihood ratio vector storage, and the iterative message cache, and then dividing by the total capacity. The parity check matrix storage uses a sparse LDPC parity check matrix, employing a compressed storage format to store only the positions and values ​​of non-zero elements; its storage size is related to the code rate and matrix design. The log-likelihood ratio vector storage's storage size equals the codeword length multiplied by the number of quantization bits. The iterative message cache stores messages transmitted between variable nodes and parity check nodes; its size is related to the number of sides of the parity check matrix and the message representation precision. Summing the storage requirements of these three parts and dividing by the total on-chip memory capacity yields the on-chip memory usage ratio. The power consumption and temperature rise normalization value describes the proportion of the chip temperature rise caused by the execution of the candidate control tuple relative to the temperature margin. This value is calculated based on a power consumption model, which is an estimation model that maps the parameter configuration of the candidate control tuple to the average chip power consumption increment and predicts the temperature change. Its input data includes the code rate, maximum number of iterations, and decoding parallelism of the candidate control tuple; the output data is the average power consumption increment and the expected temperature change for that configuration. The model works as follows: It determines the power consumption of logic operations based on the number of active decoding cores in the candidate control tuples; it determines the cumulative power consumption by determining the number of operations per unit time based on the maximum number of iterations; and it determines the memory access power consumption by determining the number of data path flips per iteration based on the codeword length. The power consumption of these three types is then summed and converted into a temperature change by combining the chip's thermal resistance parameters with the current heat dissipation conditions. This temperature change is then normalized by dividing by the temperature margin, resulting in the power consumption-temperature rise normalized value. A larger value indicates a greater pressure on thermal management under this configuration.

[0041] When the on-chip memory usage exceeds a preset storage threshold, the system faces the risk of memory overflow. A penalty factor is introduced to cause the second loss value to grow non-linearly. The specific form of the penalty factor is as follows: ,in This represents the percentage of on-chip memory usage. To preset storage threshold, For the penalty gain coefficient, when Exceed The post-penalty factor increases with the square of the excess, ensuring that configurations with high storage consumption are downweighted in subsequent selections.

[0042] The weights of the dynamic weighted summation are allocated based on the relative stress levels of the remaining on-chip memory capacity and device temperature in the decoded resource state tensor. The specific allocation rule is as follows: Let the normalized value of the remaining on-chip memory capacity be... (From the decoded resource state tensor, values ​​range from zero to one, with larger values ​​indicating more sufficiency), the normalized value of the device temperature is... (From the decoded resource state tensor, the value ranges from zero to one, with larger values ​​indicating closer to the temperature limit), then the weight of the on-chip memory occupancy ratio. Weight of normalized power consumption and temperature rise ,in To prevent division by zero regularity constants. This mapping rule makes it possible when temperature stress ( Storage occupancy weight when it is large Increase, when storage is tight ( The power consumption term has a smaller weight when the normalized value is smaller. (Increase), guiding the system to impose a greater penalty on the loss in the direction of resource scarcity.

[0043] The third loss value assesses the impact of candidate control tuples on system throughput and channel adaptability. The queue blocking probability refers to the probability that the decoding queue depth exceeds a safety threshold when decoding is performed using a certain candidate control tuple, estimated using a queuing theory model. The queuing theory model is a mathematical model that abstracts the decoding queue as a multi-server queuing system and calculates the probability distribution of queue states. Its input data includes the number of decoding cores, task arrival rate, and expected decoding latency; the output data is the probability that the queue depth exceeds the safety threshold. This model abstracts each decoding core as a server, the task arrival rate is obtained from historical access pattern statistics, the service time is taken as the expected decoding latency of the candidate control tuple, and the probability value of the queue depth exceeding the safety threshold is calculated according to the steady-state probability distribution formula of the multi-server queuing system.

[0044] The log-likelihood ratio confidence drift penalty term is used to quantify the matching degree between the error correction capability configuration of candidate control tuples and the current channel degradation level. The construction logic of this penalty term is as follows: First, calculate the error correction capability index of the candidate control tuples, which is approximately represented by the product of the code rate and the maximum number of iterations; the smaller the product, the stronger the error correction capability. Simultaneously, extract the dispersion of the log-likelihood ratio confidence drift distribution, which is represented by the standard deviation of each bit offset in the confidence drift histogram; the larger the standard deviation, the more severe the channel degradation. The normalization method for the error correction capability index is as follows: During the system initialization phase, traverse all candidate control tuples, calculate the product of the code rate and the maximum number of iterations for each tuple, and record the maximum value among all products. and minimum value Normalize the product P of the current candidate control tuples to The normalization method for the dispersion is: the minimum dispersion value under the statistical channel good condition during the system calibration phase. Maximum dispersion under severe channel degradation Normalize the current discreteness S to The normalized error correction capability index With normalized dispersion The difference, D, is the absolute value of the mismatch degree. This mismatch degree is then transformed into a penalty value through a nonlinear mapping. The nonlinear mapping is implemented using the complement function of a Gaussian kernel, in the form: ,in, For bandwidth / scale parameters, the characteristic is that when the deviation is small, the output value is close to zero, that is, the penalty is slight; when the deviation is large, the output value increases rapidly and tends to 1, that is, the penalty is rapidly amplified.

[0045] After obtaining the queue blocking probability and the log-likelihood ratio confidence drift penalty, these two are linearly combined into a third loss value. The weights of the combination are dynamically adjusted according to the decoding queue depth, specifically as follows: Let the normalized value of the decoding queue depth be... (From the decoded resource state tensor, the value ranges from zero to one; a larger value indicates the queue is closer to saturation), then the weight of the queue blocking probability term. The weight of the log-likelihood ratio confidence drift penalty term The mapping rule uses a square function to make the weight of the blocking probability term grow at an accelerated rate when the queue depth is close to saturation. This prompts the system to prioritize the configuration that best matches the channel when the queue is idle, and to force the selection of a low-latency configuration to accelerate queue digestion when the queue is saturated.

[0046] After calculating the first, second, and third loss values ​​separately, the three are weighted and summed to obtain the joint resource constraint loss of the candidate control tuple. The sum of the three weighting coefficients is normalized to 1, and its value is determined by a combination of offline training and online tuning.

[0047] During the offline training phase, historical decoding task data from different application scenarios were collected. Input features included the decoding resource state tensor, the log-likelihood ratio confidence drift distribution, and candidate control tuple parameters. Output labels were the final decoding success (zero or one), actual latency (microseconds), and peak on-chip memory usage (bytes). Based on this data, a multi-objective optimization model was trained. This model employed a three-layer fully connected neural network structure. The number of nodes in the input layer equaled the sum of the dimensions of the decoding resource state tensor and the log-likelihood ratio confidence drift distribution. The number of nodes in the hidden layer was twice the number of nodes in the input layer, using the ReLU activation function. The number of nodes in the output layer was three (corresponding to three weighting coefficients), and Softmax normalization was used to ensure the sum of the three output values ​​was one. Training employed the Adam optimizer with a learning rate of 0.001 and 1000 training iterations. After training, the neural network parameters were fixed into a weight lookup table. During the online optimization phase, the initial weights are obtained by querying the weight coefficient lookup table obtained from offline training based on the current decoding resource state tensor and the log-likelihood ratio confidence drift distribution. Then, the weight coefficients are fine-tuned using the gradient descent algorithm based on the execution feedback of the most recent decoding tasks, so that the optimization direction of the joint loss is aligned with the actual system performance indicators.

[0048] The storage control chip identifies the candidate control tuple with the minimum joint loss value as the target control tuple. This target control tuple achieves the optimal balance between error correction capability, time constraints, resource consumption, and system stability under the current resource state and channel conditions.

[0049] Step S3: Route the access task to the target decoding path according to the resource constraint joint loss, and configure the LDPC parameters according to the target control tuple so that the decoder of the storage control chip can perform the decoding operation.

[0050] Furthermore, the access task is routed to the target decoding path, including: The system obtains the service priority of the access task, determines the minimum loss candidate control tuple based on the joint loss of resource constraints, and introduces a handover penalty mechanism. When the minimum loss candidate control tuple differs from the previously used configuration, a handover penalty related to the degree of configuration difference is added to the joint loss value of the minimum loss candidate control tuple, and the effective joint loss of each candidate control tuple is re-compared to suppress frequent configuration switching. If the service priority is higher than the preset priority threshold and the expected decoding latency corresponding to the minimum loss candidate control tuple is less than the deadline of the access task, the access task is routed to the high-reliability soft decoding path. If the service priority is not higher than the preset priority threshold and the decoding core occupancy rate in the decoding resource state tensor is lower than the preset occupancy rate threshold, the access task is routed to the balanced soft decoding path. If the service priority is not higher than the preset priority threshold and the decoding core occupancy rate is not lower than the preset occupancy rate threshold, the access task is routed to the low-latency hard decoding path.

[0051] Furthermore, LDPC parameters are configured based on the target control tuple, including: Based on the target decoding path, obtain the corresponding LDPC matrix index, target code rate, log-likelihood ratio quantization bits, iteration limit, soft read voltage group, and decoding core parallelism. Through atomic operations, write the LDPC matrix index to the decoder's matrix selection register, the target code rate to the code rate configuration register, the log-likelihood ratio quantization bits to the quantizer control register, the iteration limit to the iteration control register, the soft read voltage group to the soft read controller's voltage configuration register, and the decoding core parallelism to the core enable register. The atomic operations are completed in a single configuration transaction. During the transaction, the configuration interface is locked to prevent concurrent access. After the transaction ends, the decoder state machine is reset to make the new configuration take effect.

[0052] Specifically, the target control tuple determined in step S2 is directly used as the optimal configuration scheme for the current access task. When the system resource status or channel conditions change after the calculation in S2, the storage control chip can re-trigger the joint loss calculation process in S2 to update the target control tuple.

[0053] Service priority is a service level identifier carried by an access task, reflecting the task's scheduling order and quality of service guarantee level in system resource contention. It is obtained through the priority field in the access command sent by the host, using numerical encoding; a larger value indicates a higher priority. Service priority can also be dynamically adjusted: Let the normalized value of the remaining time until the access task's deadline be... ,when If the value is less than the first-time security threshold (e.g., 1.2), the business priority value will be increased by one level. If the priority is less than the second time safety threshold (e.g., 1.0), it will be upgraded by two levels. The upgraded effective priority will only take effect in the current routing decision of the current task.

[0054] When there are multiple candidate control tuples with the same and smallest joint loss values, a four-level priority sorting is adopted: first, select the one with the lowest decoding parallelism; if there are still ties, select the one with the fewest maximum iterations; if there are still ties, select the one with the fewest log-likelihood ratio quantization bits; if there are still ties, select the one with the highest LDPC code rate.

[0055] A switching penalty mechanism is introduced during the process of determining the candidate control tuples for minimum loss. This mechanism means that when the currently determined candidate control tuple for minimum loss differs from the configuration used in the previous decoding task, a switching penalty term is added to the joint loss value of the resource constraints of that candidate control tuple, and then the effective joint loss of each candidate control tuple is re-compared to suppress frequent configuration switching. The reason for this mechanism is that switching between different configuration parameters requires hardware state reinitialization and parity check matrix reloading, resulting in additional configuration overhead and latency. The formula for calculating the switching penalty term is as follows: ,in , , , , These represent the differences in parameters between the current candidate control tuple and the previous configuration. , , , , The penalty gain coefficient is the gain coefficient for bitrate changes. Maximum (due to the need to reload the parity matrix), the degree of parallelism change Secondly, the specific process of re-comparing after adding the switching penalty term is as follows: For each candidate control tuple in the candidate set that is different from the previous configuration, add the corresponding switching penalty term to its original joint loss value to obtain the effective joint loss, while for candidate control tuples that are the same as the previous configuration, do not add the penalty term, and then find the minimum value again among the effective joint losses of all candidate control tuples.

[0056] The three decoding paths are designed to meet the different needs for error correction capabilities and response speeds in different application scenarios, forming a complete gradient coverage from extreme reliability to extreme speed.

[0057] The first path is the high-reliability soft decoding path. This path is specifically designed for high-priority access tasks with ample time. It employs a low code rate, high quantization bit count, multiple iterations, and multi-level soft read voltage configuration strategy to maximize error correction capabilities and ensure decoding success rate. This path is suitable for scenarios requiring fault-tolerant data access, such as reading critical operating system metadata and accessing file system indexes. Routing to this path requires meeting two conditions simultaneously: First, the task's priority must be higher than a preset priority threshold, indicating sufficient business importance justifying the system's investment of additional decoding resources to ensure its success rate. Second, the expected decoding latency must be less than the access task's deadline, meaning that even with longer decoding times due to multi-level soft reads and multiple iterations, the task can still be completed within the specified time. Both conditions are indispensable. If a task has a high priority but its expected decoding latency exceeds the deadline, even with increased decoding resources, the real-time requirements cannot be met, and this task should not be routed to the high-reliability path. When a business priority is higher than a preset priority threshold, but the estimated decoding latency corresponding to the lowest loss candidate control tuple is greater than or equal to the access task deadline, it indicates that although the task is of business importance, the current system resources cannot support high-reliability decoding within the specified time. In this case, the access task is routed to a low-latency hard decoding path to complete the initial decoding attempt with the shortest decoding latency. If the low-latency path decoding fails, the degradation and fallback mechanism in subsequent step S4 is triggered, and decoding is retried with a stronger error correction configuration by increasing the soft read voltage or reducing the code rate. This supplementary routing rule ensures that high-priority timeout tasks are not suspended due to unroutable conditions, but rather prioritize time constraints and then ensure reliability through the degradation and fallback mechanism.

[0058] The second path is the balanced soft decoding path. This path is designed for regular access tasks with normal priority, striking a trade-off between error correction capability and system resource consumption. It employs a moderate code rate, a reasonable number of quantization bits, and a moderate number of iterations, which can handle most flash channel conditions without excessively consuming system resources. When routing to this path, a service priority not exceeding a preset priority threshold indicates that the task is not critical, allowing for a slight reduction in service quality when resources are scarce. A decoding core utilization rate below a preset utilization rate threshold indicates a light system load and sufficient idle decoding cores, allowing for a more relaxed configuration to fully utilize idle resources for the task. When the decoding core utilization rate approaches the preset utilization rate threshold, continuing with a medium resource configuration will further strain resources; in this case, the task should be redirected to a low-latency path to maintain system responsiveness.

[0059] The third path is the low-latency hard decoding path. Designed for rapid response under high system load, this path employs a high code rate, low quantization bit count, or hard-decision decoding configuration, sacrificing some error correction capabilities for extremely short decoding latency and minimal resource consumption. This path is triggered when the system is under heavy load, with the decoding cores heavily active and the decoding queue depth continuously increasing. Continuing with a high-resource-consuming configuration would exacerbate congestion and lead to queue overflow. The low-latency path acts as a pressure relief valve by quickly processing ordinary priority tasks, reducing the time a single task occupies the decoding core, and accelerating queue digestion.

[0060] After determining the target decoding path, the corresponding six parameters are obtained based on the target decoding path and written to the corresponding registers of the decoder through atomic operations. The LDPC matrix index is written to the matrix selection register to trigger the loading of the parity matrix data; the target code rate is written to the code rate configuration register for the address generation unit to calculate the codeword length; the log-likelihood ratio quantization bits are written to the quantizer control register to trigger quantization table reloading; the iteration upper limit is written to the iteration control register; the soft read voltage group is written to the voltage configuration register of the soft read controller; and the decoding core parallelism is written to the core enable register. Atomic operations are completed within a single configuration transaction. During the transaction, the configuration interface is locked, and after the transaction ends, the decoder state machine is reset to make the new configuration effective. Atomic operations ensure that the decoder operates either entirely according to the old configuration or entirely according to the new configuration at any given time, without any intermediate inconsistent states. The locking scope of the configuration interface is limited to six configuration registers: the matrix selection register, the code rate configuration register, the quantizer control register, the iteration control register, the voltage configuration register of the soft read controller, and the core enable register. The decoder's data path registers and status readout registers are not affected by the locking.

[0061] Step S4: During the decoding operation of the decoder, online convergence verification is performed on the access task; if the verification result of the online convergence verification does not meet the preset verification boundary, a downgrade rollback operation is performed, and the execution result is written back to the bitrate strategy table.

[0062] Furthermore, online convergence verification is performed on the access task, including: During the iterative process of the decoder performing the decoding operation, the parity residual decrease rate, cumulative iteration time, peak on-chip memory usage, and temperature change are recorded in real time, and each recorded data is compared with its respective preset boundary conditions.

[0063] If the parser residual decay rate decays to zero or turns negative, the error correction capability boundary is not met. If the total decoding time extrapolated from the cumulative iteration time and the parser residual decay rate exceeds the access task deadline, the time boundary is not met. If the peak on-chip memory usage exceeds the safety threshold, the storage boundary is not met. If the temperature change exceeds the preset temperature rise limit, the temperature boundary is not met.

[0064] Verification results are generated through multidimensional boundary logic AND operations. The verification result is determined to meet the preset verification boundary only when the error correction capability boundary, time boundary, storage boundary and temperature boundary are all satisfied. Otherwise, it is determined to not meet the boundary and the specific boundary type violated is recorded.

[0065] Furthermore, the downgrade rollback operation is performed, including: Based on the specific boundary type violated in the verification results, the corresponding degradation and rollback strategy is matched through the decision tree. If the error correction capability boundary is violated, the strategy of increasing the soft read voltage and / or reducing the LDPC code rate is selected. If the time boundary is violated, the strategy of reducing the number of concurrent decodings and / or returning the rate limiting instruction is selected. If the storage boundary or temperature boundary is violated, the strategy of reducing the number of concurrent decodings or pausing the decoding task is selected. The degradation and rollback strategies are executed in order of increasing cost, and the refresh migration strategy is the backup option with the highest cost.

[0066] After the downgrade rollback strategy is completed, the rollback event information is written back to the bitrate strategy table. The bitrate strategy table is indexed by the flash block address. If the rollback is successful and decoding is restored, the recommended configuration is updated to the rollback configuration. If the rollback still fails, the corresponding flash block is marked as a high-risk block so that subsequent accesses can directly use the strongest error correction configuration or trigger a refresh migration.

[0067] Specifically, online convergence verification is a real-time monitoring mechanism, fundamentally different from the traditional method of verifying the final result after decoding is complete: the latter can only determine success or failure after decoding is finished, and if it fails, all decoding time and resources have been wasted; the former continuously evaluates the decoding trajectory during the iteration process, and can predict whether the current configuration can converge before decoding is complete. Online convergence verification adopts a segmented triggering strategy: in the initial stage (less than five iterations completed), verification is triggered after each iteration; in the mid-stage (five to thirty iterations), verification is triggered every three iterations; in the late stage (more than thirty iterations), verification is triggered after each iteration; when the rate of change of any monitored indicator exceeds a preset mutation threshold, additional verification is immediately triggered.

[0068] The first type of metric is the parity residual decay rate. The parity residual refers to the number of parities that do not satisfy the parity check equation in the current iteration. Each row of the LDPC parity check matrix corresponds to a parity check equation; if an equation in a row is not satisfied, the parity is set to one. Successful decoding is indicated by all parities returning to zero. In an ideal decoding process, the parity residual should monotonically decrease with increasing iterations, eventually converging to zero. The parity residual decay rate is calculated by dividing the residual difference between two adjacent iterations by the iteration interval. A positive value indicates that decoding is converging; a value decaying to zero or turning negative indicates that decoding has entered a stagnant or oscillating state, meaning that the currently configured error correction capability is insufficient to correct the erroneous bits in the flash memory. After each iteration, the monitoring module reads the current residual value from the decoder's parity calculation unit and calculates the decay rate, fitting the decay rates of the most recent iterations into a trend curve to smooth out instantaneous fluctuations.

[0069] The second type of metric is the cumulative iteration time. Cumulative iteration time refers to the total time consumed from the start of the decoding task to the current moment, encompassing all completed iterations. This time is obtained by measuring the start and end times of each iteration using a hardware timer within the monitoring module and summing the results. The actual time consumed in a single iteration is affected by parallelism configuration, on-chip memory bandwidth contention, and core pipeline efficiency, and may deviate from theoretical estimates. Therefore, it needs to be obtained through actual measurements rather than theoretical calculations.

[0070] The third metric is peak on-chip memory usage. Peak on-chip memory usage refers to the maximum amount of on-chip static random access memory used during the decoding task. During the decoding iteration, memory usage dynamically changes with the update of message caches between variable nodes and check nodes. Peak usage reflects the resource requirements under worst-case conditions. The monitoring module periodically reads the address allocation watermark register maintained by the memory controller and records the maximum usage value indicated by this register during the decoding task's lifecycle. If the peak usage exceeds expectations, it may indicate insufficient cache isolation between parallel tasks under the current configuration or that the sparsity of the check matrix is ​​lower than the design assumptions, putting the system at risk of memory overflow.

[0071] The fourth type of indicator is temperature change. Temperature change refers to the increase in chip temperature relative to the baseline temperature at task startup during the decoding task execution. Decoding operations are intensive and power consumption is concentrated. The high parallelism and multiple iterations generate a large amount of heat in a short period of time, causing local temperature rise. The monitoring module periodically reads the values ​​from the chip's built-in temperature sensor, records the baseline temperature at task startup and the highest temperature during execution, and the difference between the two is the temperature change.

[0072] The four types of indicators are compared with their respective preset boundary conditions. For the residual decrease rate of the checker, if the value decays below the preset convergence threshold or turns negative, it is determined that the error correction capability boundary is not met. For the cumulative iteration time, the time boundary extrapolation adopts an automatic selection of fitting model: first, curve fitting is performed on the residual values ​​of the most recent preset number of iterations (e.g., 5 times). If the difference between adjacent residuals tends to be constant in the most recent preset number of iterations (i.e., the residuals show an approximately linear decrease), a linear fitting model is used; if the difference between adjacent residuals gradually decreases (i.e., the residuals show an exponential decay trend), an exponential decay fitting model is used. ,in This represents the residual value at the nth iteration. To fit the starting point residual value, The attenuation coefficient is determined by performing linear regression after taking the logarithm of the residuals from the most recent preset number of iterations. The selected fitting model is used to predict when the residuals will decrease to a preset convergence threshold. The required number of remaining iterations, for a linear fitting model, is: ,in This is the current residual value. The slope is linearly decreasing; for the exponentially decaying fitting model, the remaining number of iterations is: Then, by combining the average measured time of a single iteration, the remaining time required to complete the decoding is estimated. The sum of the accumulated iteration time and the remaining time is used as the extrapolated total decoding time. If this extrapolated total time exceeds the access task deadline, the time boundary is not met. When the number of remaining iterations predicted by the fitted model exceeds the difference between the maximum iteration limit and the number of iterations already executed, it is directly determined that the time boundary is not met. For peak on-chip memory usage, if it exceeds the safety threshold (usually 90% of the total capacity), the memory boundary is not met. For temperature changes, if it exceeds the preset temperature rise limit or the current absolute temperature is close to the chip's maximum operating temperature, the temperature boundary is not met.

[0073] Verification results are generated through multi-dimensional boundary logic AND operations. A verification result is considered satisfactory only if all four boundaries are met. When a verification result violates multiple boundary types simultaneously, it is processed in descending order of violation priority: error correction capability boundary, storage boundary, temperature boundary, and time boundary. This order is based on the severity of the consequences of each boundary violation. A violation of the error correction capability boundary means decoding is destined to fail; violations of the storage and temperature boundaries may lead to hardware damage or data loss; and a time boundary violation only causes task timeout. After processing the highest priority boundary violation, a full-dimensional online convergence verification is re-executed. If other boundary violations have been mitigated, no additional strategies are needed; otherwise, processing continues according to priority.

[0074] If the verification result does not meet the preset verification boundary, a downgrade rollback operation is triggered. The selection of the downgrade rollback strategy is implemented through a decision tree. The root node of the decision tree receives the violation boundary type recorded in the verification result as input, and routes along the corresponding branch to the strategy marked on the leaf node according to the violation boundary type. The strategy of increasing soft read voltage means that the soft read controller adds more reference voltages on the basis of the current voltage group to improve the log-likelihood ratio sampling accuracy. The strategy of reducing LDPC code rate means that a lower code rate parity matrix is ​​reloaded to increase parity bit redundancy. The strategy of reducing concurrent decoding number means that some low-priority decoding tasks are suspended to free up decoding core and memory bandwidth. The strategy of returning a rate-limiting instruction means that the host returns a busy status code to reduce the command sending rate of the host. The above strategies are arranged in ascending order of execution cost. The specific rules for serial execution are as follows: after each strategy is executed, decoding is restarted from the first iteration under the new configuration, triggering a full-dimensional online convergence check; the termination condition is one of three: if the re-check after a certain strategy is satisfied, it is considered successful; if all strategies in the current branch have been executed and the re-check is still not satisfied, it is considered a failure and a high-risk block is marked; if the cumulative downgrade rollback execution time exceeds the access task deadline, it is forcibly terminated. The refresh migration strategy, as the highest-cost backup option, refers to reading the data from the original storage location, correcting errors, and then writing it to the new location.

[0075] After the downgrade rollback strategy is executed, the storage controller chip writes the detailed information of this rollback event back to the bitrate policy table. The bitrate policy table is a historical statistical database maintained by the storage controller chip, indexed by flash block addresses. Each entry records the original bit error rate trend of the corresponding flash block, the configuration parameter combinations for successful decoding in history, and the configuration information for failures. The specific process of the write-back operation is as follows: The bitrate policy table is queried based on the flash block address involved in the current access task. If the entry corresponding to the address already exists, the entry is updated; otherwise, a new entry is created. The write-back operation uses a pre-write log mechanism to ensure atomicity: Before executing the policy table update, the complete entry data to be written (including flash block address, recommended configuration parameters, high-risk flag, and historical record fields) is first written to a separate log area. After the log writing is completed, a commit flag is appended to the log. Then, the formal update of the policy table is executed, writing the entry data to the main storage area of ​​the policy table. After the formal update is completed, the commit flag in the log is deleted. If an abnormal interruption occurs during the above process, the system will scan the log area upon restart. If an entry with a commit flag but not yet deleted is found, its data will be rewritten to the main storage area of ​​the policy table to restore consistency. If an entry without a commit flag is found, it will be discarded. This mechanism ensures that the policy table at any given time either fully reflects the state before the update or fully reflects the state after the update, with no intermediate inconsistent states.

[0076] If the degradation rollback successfully restores decoding, the recommended configuration in that entry will be updated to the actual configuration used after the rollback. This allows subsequent accesses to the same flash block to directly use the verified and effective configuration without having to go through the entire candidate generation and loss calculation process again. If the degradation rollback still fails, the flash block will be marked as a high-risk block, so subsequent accesses to that block will directly use the strongest error correction configuration or trigger a refresh migration, avoiding further waste of decoding resources. The continuous accumulation of the rate policy table enables the storage control chip to have self-learning capabilities. As runtime increases and policy table data becomes richer, the accuracy of the decoding configuration continuously improves, the trigger frequency of degradation rollback gradually decreases, and the system stability and reliability continuously improve.

[0077] For example, Figure 2 The diagram illustrates the effect comparison of different code rate configurations. Sub-figure (a) shows the change in decoding success rate with the number of flash erase / write cycles. As shown in the figure, the adaptive code rate adjustment method of this application dynamically adjusts the code rate and iteration parameters by sensing the log-likelihood ratio confidence drift distribution in real time, maintaining a high decoding success rate throughout the entire lifecycle. Sub-figure (b) shows the change in average decoding latency with decoding queue depth. As shown in the figure, this application uses the three-path intelligent routing driven by the service priority and decoding core occupancy rate in step S3 to route ordinary priority tasks to low-latency hard decoding paths in high-load scenarios, shortening the time a single task occupies the decoding core, accelerating queue digestion, and making the increase in average decoding latency significantly lower than that of the fixed code rate configuration.

[0078] The above describes an LDPC rate adaptive adjustment method for a storage control chip according to an embodiment of this application. The following describes an LDPC rate adaptive adjustment system for a storage control chip according to an embodiment of this application. Please refer to [link to relevant documentation]. Figure 3 An LDPC rate adaptive adjustment system for a storage control chip, as described in this application embodiment, includes: The acquisition unit is used to acquire the decoding resource state tensor and log-likelihood ratio confidence drift distribution of the storage control chip; and to generate candidate control tuples based on the decoding resource state tensor and log-likelihood ratio confidence drift distribution, with each candidate control tuple containing a set of LDPC decoding parameter configuration schemes.

[0079] The resource constraint unit is used to calculate the joint resource constraint loss of each candidate control tuple, and the candidate control tuple with the minimum joint resource constraint loss is determined as the target control tuple.

[0080] The routing configuration unit is used to route access tasks to the target decoding path based on the joint loss of resource constraints, and configure LDPC parameters according to the target control tuple so that the decoder of the storage control chip can perform decoding operations.

[0081] The verification backoff unit is used to perform online convergence verification of the access task during the decoding operation of the decoder. If the verification result of the online convergence verification does not meet the preset verification boundary, a downgrade backoff operation is performed, and the execution result is written back to the bitrate strategy table.

[0082] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0083] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0084] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for adaptive adjustment of LDPC code rate for a storage control chip, characterized in that, The method includes: Obtain the decoding resource state tensor and log-likelihood ratio confidence drift distribution of the storage control chip; generate candidate control tuples based on the decoding resource state tensor and the log-likelihood ratio confidence drift distribution, each candidate control tuple containing a set of LDPC decoding parameter configuration schemes; Calculate the joint resource constraint loss of each candidate control tuple, and determine the candidate control tuple with the minimum joint resource constraint loss as the target control tuple; The access task is routed to the target decoding path according to the resource constraint joint loss, and the LDPC parameters are configured according to the target control tuple so that the decoder of the storage control chip performs the decoding operation. During the decoding operation, the access task is checked online. If the result of the online convergence check does not meet the preset check boundary, a downgrade rollback operation is performed, and the execution result is written back to the code rate strategy table.

2. The LDPC code rate adaptive adjustment method for a storage control chip according to claim 1, characterized in that, Obtain the decoding resource state tensor and log-likelihood ratio confidence drift distribution of the memory control chip, including: The LDPC decoding core occupancy rate, on-chip memory remaining capacity, decoding queue depth, device temperature, power budget, access task deadline, and current raw bit error rate estimate are periodically collected by hardware counters and status registers. The collected parameters are then processed according to the corresponding normalization strategy to construct the decoding resource state tensor. During a soft read operation, a voltage sequence including a default read reference voltage and corresponding upper and lower offset reference voltages is applied to the flash memory cell. The comparison results under each reference voltage are recorded as soft read reference voltage sampling data. Based on the soft read reference voltage sampling data, the log-likelihood ratio of each bit is calculated by looking up the log-likelihood ratio mapping table obtained in advance through channel model training. The log-likelihood ratio of each bit is compared with the historical log-likelihood ratio mean of the corresponding position to calculate the offset. The number of bits is counted according to the offset amplitude interval to construct a confidence drift histogram. Combined with the log-likelihood ratio variance of each bit position, the parser convergence slope of the historical decoding task, and the failed codeword position information, a multi-dimensional feature vector is constructed as the log-likelihood ratio confidence drift distribution.

3. The LDPC code rate adaptive adjustment method for a storage control chip according to claim 1, characterized in that, Generate candidate control tuples, including: Candidate sets of values ​​for LDPC code rate, log-likelihood ratio quantization bits, maximum number of iterations, number of soft read reference voltages, and decoding parallelism are obtained respectively. The candidate sets of values ​​are combined by Cartesian product to generate an initial set of candidate control tuples. A hierarchical screening strategy is used to screen them. The combinations that remain after hierarchical screening constitute the candidate control tuples.

4. The LDPC code rate adaptive adjustment method for a storage control chip according to claim 3, characterized in that, The tiered screening strategy consists of three phases executed sequentially: In the first stage, based on the remaining on-chip memory capacity in the decoding resource state tensor, combinations of storage requirements exceeding the remaining on-chip memory capacity are filtered by looking up a pre-established storage requirement table. The second stage uses the decoding delay estimation model to filter combinations where the expected decoding delay exceeds the access task deadline based on the access task deadline in the decoding resource state tensor. The third stage involves selecting combinations that match the current channel quality based on the log-likelihood ratio confidence drift distribution.

5. The LDPC code rate adaptive adjustment method for a storage control chip according to claim 1, characterized in that, Calculate the joint resource constraint loss for each of the candidate control tuples, including: For each candidate control tuple, a first loss value is determined based on the target bit error rate margin and the expected decoding delay; a second loss value is determined based on the dynamic weighted sum of the on-chip memory occupancy ratio and the power consumption temperature rise normalization value; a third loss value is determined based on the linear combination of the queue blocking probability and the log-likelihood ratio confidence drift penalty term; and the first loss value, the second loss value, and the third loss value are weighted and summed to obtain the resource constraint joint loss.

6. The LDPC code rate adaptive adjustment method for a storage control chip according to claim 1, characterized in that, Routing the access task to the target decoding path includes: The service priority of the access task is obtained, the minimum loss candidate control tuple is determined according to the resource constraint joint loss, and a switching penalty mechanism is introduced. When the minimum loss candidate control tuple is different from the configuration used last time, a switching penalty term related to the degree of configuration difference is superimposed on the resource constraint joint loss value of the minimum loss candidate control tuple, and the effective joint loss of each candidate control tuple is re-compared to suppress frequent configuration switching. If the service priority is higher than the preset priority threshold and the expected decoding delay corresponding to the lowest loss candidate control tuple is less than the access task deadline, then the access task will be routed to a highly reliable soft decoding path. If the service priority is not higher than the preset priority threshold and the decoding core occupancy rate in the decoding resource state tensor is lower than the preset occupancy rate threshold, then the access task will be routed to the balanced soft decoding path. If the service priority is not higher than the preset priority threshold and the decoding core occupancy rate is not lower than the preset occupancy rate threshold, then the access task will be routed to a low-latency hard decoding path.

7. The LDPC code rate adaptive adjustment method for a storage control chip according to claim 6, characterized in that, Configure LDPC parameters according to the target control tuple, including: Based on the target decoding path, obtain the corresponding LDPC matrix index, target code rate, log-likelihood ratio quantization bits, iteration limit, soft read voltage group, and decoding core parallelism. Through atomic operations, write the LDPC matrix index into the decoder's matrix selection register, write the target code rate into the code rate configuration register, write the log-likelihood ratio quantization bits into the quantizer control register, write the iteration limit into the iteration control register, write the soft read voltage group into the soft read controller's voltage configuration register, and write the decoding core parallelism into the core enable register. The atomic operation is completed in a single configuration transaction. During the transaction, the configuration interface is locked to prevent concurrent access. After the transaction ends, the decoder state machine is reset to make the new configuration take effect.

8. The LDPC code rate adaptive adjustment method for a storage control chip according to claim 1, characterized in that, Perform online convergence verification on the access task, including: During the iterative process of the decoder performing the decoding operation, the parity residual decrease rate, cumulative iteration time, peak on-chip memory usage, and temperature change are recorded in real time, and each recorded data is compared with its respective preset boundary conditions. If the rate of decrease of the check residual decays to zero or turns negative, it is determined that the error correction capability boundary is not met. If the total decoding time extrapolated from the cumulative iteration time and the rate of decrease of the check residual exceeds the access task deadline, it is determined that the time boundary is not met. If the peak occupancy of the on-chip memory exceeds the safety threshold, it is determined that the storage boundary is not met. If the temperature change exceeds the preset temperature rise limit, it is determined that the temperature boundary is not met. The verification result is generated by multidimensional boundary logic AND operation. The verification result is determined to satisfy the preset verification boundary only when the error correction capability boundary, the time boundary, the storage boundary and the temperature boundary are all satisfied. Otherwise, it is determined to be unsatisfied and the specific boundary type violated is recorded.

9. The LDPC code rate adaptive adjustment method for a storage control chip according to claim 8, characterized in that, Perform a downgrade rollback operation, including: Based on the specific boundary type violated in the verification results, a corresponding degradation and rollback strategy is matched using a decision tree. If the error correction capability boundary is violated, a strategy to increase the soft read voltage and / or reduce the LDPC code rate is selected. If the time boundary is violated, a strategy to reduce the number of concurrent decodes and / or a rate-limiting instruction is selected. If the storage boundary or the temperature boundary is violated, a strategy to reduce the number of concurrent decodes or suspend the decoding task is selected. The degradation and rollback strategies are executed in ascending order of cost, with the refresh migration strategy serving as the backup option with the highest cost. After the downgrade rollback strategy is completed, the rollback event information is written back to the bitrate strategy table. The bitrate strategy table is indexed by the flash block address. If the rollback is successful and decoding is restored, the recommended configuration is updated to the rollback configuration. If the rollback still fails, the corresponding flash block is marked as a high-risk block so that subsequent accesses can directly use the strongest error correction configuration or trigger a refresh migration.

10. An LDPC rate adaptive adjustment system for a storage control chip, used to implement the LDPC rate adaptive adjustment method for a storage control chip as described in any one of claims 1-9, characterized in that, The system includes: The acquisition unit is used to acquire the decoding resource state tensor and the log-likelihood ratio confidence drift distribution of the storage control chip; and to generate candidate control tuples based on the decoding resource state tensor and the log-likelihood ratio confidence drift distribution, wherein each candidate control tuple contains a set of LDPC decoding parameter configuration schemes. The resource constraint unit is used to calculate the joint resource constraint loss of each candidate control tuple and determine the candidate control tuple with the minimum joint resource constraint loss as the target control tuple. The routing configuration unit is used to route the access task to the target decoding path according to the resource constraint joint loss, and configure LDPC parameters according to the target control tuple so that the decoder of the storage control chip performs the decoding operation; The verification backoff unit is used to perform online convergence verification on the access task during the decoding operation of the decoder; if the verification result of the online convergence verification does not meet the preset verification boundary, a downgrade backoff operation is performed, and the execution result is written back to the code rate strategy table.

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