Communication method and communication apparatus

Abstract

A communication method and a communication apparatus, the method comprising: when K′=M, a first communication apparatus encoding a first codeword sequence based on an M-row N-column first generator matrix and K′ bits to be encoded, wherein the K′ bits to be encoded include K information bits and K... P K padding bits P =M-K; When K′=K, the first communication device encodes the second codeword sequence according to the second generator matrix with K′ rows and N columns and K′ bits to be encoded. The second generator matrix is ​​composed of K′ rows from the first generator matrix. This method enables RM codes to support the encoding of information bits with a length less than M, making the application scenarios of RM codes more flexible.

Description

Technical Field

[0001] This application relates to the field of wireless communication technology, and more specifically, to a communication method and a communication device. Background Technology

[0002] Reed-Muller (RM) codes are linear block codes characterized by recursive construction and efficient decoding algorithms. Generally, the parameters (e.g., m and r) of an RM code are fixed values. Since the bit length k supported by an RM code is determined based on parameters m and r, the bit length of the encoded information is fixed, resulting in a fixed code length. In practical transmission scenarios, the length of the information bits to be encoded is flexible and variable, while the current RM code supports a fixed bit length, limiting its applicability to different scenarios and restricting its scope of application. Summary of the Invention

[0003] This application provides a communication method and a communication device, aiming to enable RM codes to flexibly support different scenarios and support encoding of more different bit lengths of information to be encoded.

[0004] Firstly, a communication method is provided, which can be executed by a first communication device (or encoding device). Unless otherwise specified, "first communication device" can refer to a communication device (e.g., a network device, a terminal device, an encoding device, etc.), a component of the communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software that implements all or part of the communication device. The component used in the communication device can be a component within the communication device, or it can be independent of the communication device but coupled to it. For ease of understanding, the following description uses the execution of the first communication device as an example.

[0005] The method may include: a first communication device acquiring K information bits, where K is a positive integer; the first communication device determining a first generator matrix of the RM code based on parameters m and r, the first generator matrix comprising M rows and N columns, where K < M. N=2 m m, r, M, and N are all positive integers. The first communication device encodes a first codeword sequence based on a first generator matrix and K′ bits to be encoded, where the K′ bits to be encoded include K information bits and K... P 1 padding bit, K′=M, K P =MK; or, the first communication device encodes the second codeword sequence according to the second generator matrix and K′ bits to be encoded. The second generator matrix is ​​composed of K′ rows of the first generator matrix, K′=K, and the second generator matrix includes K′ rows and N columns.

[0006] For example, the first generating matrix can be a polynomial generating matrix of the RM code determined by parameters m and r, or a recursive generating matrix of the RM code. Both the polynomial matrix and the recursive generating matrix can be obtained through row and column transformations.

[0007] For example, the codeword lengths corresponding to the first codeword sequence and the second codeword sequence are equal.

[0008] According to the method provided in this application, when the number K of the acquired K information bits is less than the number M of information bits supported by the RM code, the first communication device can pad the K information bits so that the number of bits to be encoded after padding is equal to M, thereby using the first generator matrix corresponding to the RM code to encode a first codeword sequence; or, the first communication device can select K rows from the first generator matrix as a second generator matrix based on the K information bits, thereby using the second generator matrix to encode the K information bits to obtain a second codeword sequence. Therefore, this method makes the RM code not limited to only supporting... The length of the information bit encoding allows RM codes to support more information bit encodings of different lengths, which helps to make the application scenarios of RM codes more flexible.

[0009] In conjunction with the first aspect, in some possible implementations, the first generating matrix satisfies: Here, G(m,r) represents the first generating matrix.

[0010] Specifically, the first generating matrix is ​​a recursive generating matrix.

[0011] The first generating matrix can be constructed by multiple low-order generating matrices.

[0012] For example, G(m,r) consists of a submatrix satisfying the first condition and a matrix of all zeros. The first condition is that for a submatrix G(a,b) in G(m,r), a = b or b = 0. Specifically, when b = 0 in G(a,b), G(a,b) is a 1-row, 2-matrix matrix. a A matrix consisting entirely of 1s; when a = b in G(a, b), G(a, b) is a matrix of 2s. a Line 2 a Unit matrix.

[0013] Specifically, when G(m,r) does not satisfy the first condition (i.e., m ≠ r or r ≠ 0), G(m,r) can be split into two G(m-1,r), one G(m-1,r-1), and a matrix of all zeros. Specifically, when G(m-1,r) does not satisfy the first condition (i.e., m-1 ≠ r, or r ≠ 0), G(m-1,r) is split into two G(m-1-1,r), one G(m-1-1,r-1), and a matrix of all zeros. When G(m-1,r-1) does not satisfy the first condition (m-1 ≠ r-1, or r-1 ≠ 0), G(m-1,r-1) is split into two G(m-1-1,r-1), one G(m-1-1,r-1-1), and a matrix of all zeros, until the resulting submatrices satisfy the first condition.

[0014] In other words, for a given G(m,r) that does not satisfy the first condition (i.e., m ≠ r or r ≠ 0), G(m,r) can include two G(m-1,r), one G(m-1,r-1), and a matrix of all zeros. Specifically, when G(m-1,r) does not satisfy the first condition (i.e., m-1 ≠ r, or r ≠ 0), G(m-1,r) can include two G(m-1-1,r), one G(m-1-1,r-1), and a matrix of all zeros. When G(m-1,r-1) does not satisfy the first condition (m-1 ≠ r-1, or r-1 ≠ 0), G(m-1,r-1) can include two G(m-1-1,r-1), one G(m-1-1,r-1-1), and a matrix of all zeros, until the submatrices included in G(m,r) satisfy the first condition.

[0015] In conjunction with the first aspect, in some possible implementations, when K′=M, K P The padding bits are located after the K information bits in the K′ bits to be encoded; when K′ = K, the K′ row in the second generator matrix is ​​the first K′ row in the first generator matrix.

[0016] Based on the above technical solution, in K′ bits to be encoded, the K... P The padding bits are located after the K information bits; or, the second generator matrix is ​​the first K' rows of the first generator matrix. This type of implementation helps the decoding device to fix the bit values ​​at positions in the codeword sequence corresponding to non-K information bits during the decoding process, thereby reducing the number of enumerations, reducing the complexity of decoding, saving codeword space, and improving decoding accuracy.

[0017] In conjunction with the first aspect, among some possible implementations, the method also includes: determining K based on the first index table. PThe positions of the padding bits and / or the positions of the K information bits in the bit sequence to be encoded, the bit sequence to be encoded includes K′ bits to be encoded, the bits to be encoded in the bit sequence to be encoded correspond to the rows in the first generating matrix, wherein the first index table includes X indices, the X indices correspond one-to-one with the X rows in the first generating matrix, and X is a positive integer less than or equal to M.

[0018] For example, the indices in the first index table correspond to the positions in the bit sequence to be encoded, and the X indices in the first index table correspond one-to-one with the X rows in the first generator matrix, and the positions in the bit sequence to be encoded correspond to the rows in the first generator matrix.

[0019] Based on the above technical solution, the K is determined through the first index table. P The specific positions of the padding bits and / or K information bits in the bit sequence to be encoded reduce the dependence on K P The difficulty in updating or changing the specific positions of the padding bits and / or K information bits in the bit sequence to be encoded is simply that the order of the indices in the first index table needs to be changed.

[0020] In conjunction with the first aspect, in some possible implementations, the first generating matrix includes a first type of submatrix and a second type of submatrix. The first type of submatrix is ​​an identity matrix, and the second type of submatrix is ​​an all-1 matrix. The second type of submatrix includes 1 row and s columns, where s is an integer greater than or equal to 2.

[0021] In conjunction with the first aspect, in some possible implementations, the first generating matrix includes a third type of submatrix and a fourth type of submatrix. The third type of submatrix is ​​the submatrix obtained by performing T1 first operations on the first generating matrix, where T1 is an integer greater than or equal to a first threshold. The fourth type of submatrix is ​​the submatrix obtained by performing T2 first operations on the first generating matrix, where T2 is an integer less than the first threshold. The third and fourth type of submatrixes are matrices that satisfy a first condition, which includes: a = b in matrix (a, b), or b = 0, where a is a positive integer. The first operation is to split the matrix (x, y) that does not satisfy the first condition to obtain two first submatrices (x-1, y), one second submatrix (x-1, y-1), and a matrix of all zeros. The two first submatrices (x-1, y) are located in the first... The first submatrix, consisting entirely of zeros, is located in the bottom left corner of matrix (x, y). It has the same number of rows as the second submatrix. The second submatrix, (x-1, y-1), is located in the bottom right corner of matrix (x, y). The second submatrix is ​​the last submatrix in matrix (x, y). Line 2 ( x- 1)In the case where the first generating matrix satisfies the first condition and r = 0, the number of times the first operation is processed in each row of the first generating matrix is ​​0. If the first generating matrix does not satisfy the first condition, the rows corresponding to the third type of sub-matrix and the rows corresponding to the fourth type of sub-matrix are determined based on the first generating matrix and the first operation. The first generating matrix is ​​denoted as G(m, r). The first operation performed on the first generating matrix is ​​applied to G(m, r), and includes performing the first operation on G(m, r) to obtain two first sub-generating matrices (m-1, r) and one second sub-generating matrix. Generate a matrix (m-1, r-1) and a matrix of all zeros. If the first sub-generated matrix (m-1, r) satisfies the first condition, the first operation is not performed on the first sub-generated matrix (m-1, r). If the second sub-generated matrix (m-1, r-1) satisfies the first condition, the first operation is not performed on the second sub-generated matrix (m-1, r-1). If the first sub-generated matrix (m-1, r) does not satisfy the first condition, the first operation is performed on the first sub-generated matrix (m-1, r-1). If the second sub-generated matrix (m-1, r-1) does not satisfy the first condition, the first operation is performed on the second sub-generated matrix (m-1, r-1).

[0022] In conjunction with the first aspect, in some possible implementations, K is determined based on the first index table. P The positions of the padding bits in the bit sequence to be encoded include: according to the first K bits in the first index table. P Each index determines K. P The positions of the padding bits in the bit sequence to be encoded are given, where X indices include x1 first indices and x2 second indices, and x1 first indices are located before x2 second indices in the first index table. x1 first indices correspond to x1 row in the first generating matrix, and x2 second indices correspond to x2 row in the first generating matrix. x1 row includes the row corresponding to the first type of submatrix, and x2 row includes the row corresponding to the second type of submatrix. x1 and x2 are both positive integers.

[0023] Based on the above technical solution, K P The positions of the padding bits in the bit sequence to be encoded are determined according to the first K bits in the first index table. P The indexes are determined, and in the first index table, the x1 first indices precede the x2 second indices. The first indices correspond to the rows of the first type of submatrix, and the second indices correspond to the rows of the second type of submatrix. In this method, K P The padding bits are preferentially placed at the bit positions in the bit sequence to be encoded that correspond to the rows of the first type of submatrix. In particular, the first type of submatrix is ​​an identity matrix, and placing padding bits at the positions in the bit sequence to be encoded that correspond to the rows of the first type of submatrix is ​​equivalent to reducing the local code rate, which helps to improve decoding reliability.

[0024] In conjunction with the first aspect, in some possible implementations, K is determined based on the first index table. P The positions of the padding bits in the bit sequence to be encoded include: according to the first K bits in the first index table. P Each index determines K. P The positions of the padding bits in the bit sequence to be encoded are given, where X indices include x3 third indices and x4 fourth indices, and the x3 third indices are located before the x4 fourth indices in the first index table. The x3 third indices correspond to the x3 row in the first generating matrix, and the x4 fourth indices correspond to the x4 row in the first generating matrix. The x3 row includes the row corresponding to the third type of sub-matrix, and the x4 row includes the row corresponding to the fourth type of sub-matrix. Both x3 and x4 are positive integers.

[0025] Based on the above technical solution, K P The positions of the padding bits in the bit sequence to be encoded are determined according to the first K bits in the first index table. P The indexes are determined, and in the first index table, the x3 third indices precede the x4 fourth indices. The third indices correspond to the rows of the third type of submatrix, and the fourth indices correspond to the rows of the fourth type of submatrix. In this method, K P The padding bits are preferentially filled into the bit positions corresponding to the rows of the third type submatrix in the bit sequence to be encoded. In particular, the third type submatrix is ​​a submatrix obtained by performing the first operation T1 times (greater than or equal to the first threshold) on the first generator matrix. Preferentially using the bit positions corresponding to the rows of the third type submatrix in the bit sequence to be encoded to place padding bits can reduce the computational complexity of the second communication device during the decoding process, while also reducing the local code rate and improving the decoding reliability.

[0026] In conjunction with the first aspect, in some possible implementations, determining the positions of K information bits in the bit sequence to be encoded according to the first index table includes: determining the positions of K information bits in the bit sequence to be encoded according to the first K indices in the first index table, wherein the X indices include x1 first indices and x2 second indices, and the x2 second indices are located before the x1 first indices in the first index table, the x1 first indices correspond to the x1 row in the first generating matrix, the x2 second indices correspond to the x2 row in the first generating matrix, the x1 row includes the rows corresponding to the first type of sub-matrices, the x2 row includes the rows corresponding to the second type of sub-matrices, and x1 and x2 are both positive integers.

[0027] Based on the above technical solution, the positions of the K information bits in the bit sequence to be encoded are determined according to the first K indices in the first index table. The x2 second indices in the first index table precede the x1 first indices, and the x2 second indices correspond to the x2 row of the second type of sub-matrix. In this method, the K information bits are preferentially placed at the positions of the bits to be encoded corresponding to the rows of the second type of sub-matrix. In other words, K... P The padding bits are filled into the positions of the bits to be encoded corresponding to the rows of the first type of submatrix. The first type of submatrix is ​​an identity matrix. Placing padding bits in the positions of the bits to be encoded corresponding to the rows of the first type of submatrix is ​​equivalent to reducing the local code rate, which helps to improve the decoding reliability.

[0028] In conjunction with the first aspect, in some possible implementations, determining the positions of K information bits in the bit sequence to be encoded according to the first index table includes: determining the positions of K information bits in the bit sequence to be encoded according to the first K indices in the first index table, wherein the X indices include x3 third indices and x4 fourth indices, and the x4 fourth indices are located before the x3 third indices in the first index table, the x3 third indices correspond to the x3 row in the first generating matrix, the x4 fourth indices correspond to the x4 row in the first generating matrix, the x3 row includes the row corresponding to the third type of submatrix, the x4 row includes the row corresponding to the fourth type of submatrix, and x3 and x4 are both positive integers.

[0029] Based on the above technical solution, the positions of the K information bits in the bit sequence to be encoded are determined according to the first K indices of the first index table. In the first index table, the x4 fourth indices precede the x3 third indices. The third indices correspond to the rows of the third type of sub-matrix, and the fourth indices correspond to the rows of the fourth type of sub-matrix. In this method, the K information bits are preferentially placed at the positions of the bits to be encoded corresponding to the rows of the fourth type of sub-matrix. In other words, K... P The padding bits are filled in the corresponding bit positions of the rows of the third type sub-matrix. The third type sub-matrix is ​​a sub-matrix obtained by performing the first operation (greater than or equal to the first threshold) on the first generator matrix T1 times. The priority of using the bit positions corresponding to the rows of the third type sub-matrix in the bit sequence to be encoded to place padding bits can reduce the computational complexity of the second communication device during the decoding process, while also reducing the local code rate and improving the decoding reliability.

[0030] In conjunction with the first aspect, in some possible implementations, K is determined based on the first index table. P The positions of the padding bits and the K information bits in the bit sequence to be encoded include: based on the first K bits in the first index table. P Each index determines K. PThe positions of the padding bits in the bit sequence to be encoded are determined according to the last K indices in the first index table. The positions of the K information bits in the bit sequence to be encoded are determined, wherein the X indices include x1 first indices and x2 second indices, and the x1 first indices are located before the x2 second indices in the first index table.

[0031] or;

[0032] According to the last K in the first index table P Each index determines K. P The positions of the padding bits in the bit sequence to be encoded are determined based on the first K indices in the first index table. Here, the X indices include x1 first indices and x2 second indices, with the x2 second indices preceding the x1 first indices in the first index table. The x1 first indices correspond to the x1 row in the first generating matrix, and the x2 second indices correspond to the x2 row in the first generating matrix. The x1 row includes rows corresponding to the first type of submatrix, and the x2 row includes rows corresponding to the second type of submatrix. Both x1 and x2 are positive integers.

[0033] In conjunction with the first aspect, in some possible implementations, K is determined based on the first index table. P The positions of the padding bits and the K information bits in the bit sequence to be encoded include: based on the first K bits in the first index table. P Each index determines K. P The positions of the padding bits in the bit sequence to be encoded are determined according to the last K indices in the first index table. The positions of the K information bits in the bit sequence to be encoded are determined, where the X indices include x3 third indices and x4 fourth indices, and the x3 third indices are located before the x4 fourth indices in the first index table.

[0034] or;

[0035] According to the last K in the first index table P Each index determines K. P The positions of the padding bits in the bit sequence to be encoded are determined based on the first K indices in the first index table. Here, the X indices include x3 third indices and x4 fourth indices, with the x4 fourth indices preceding the x3 third indices in the first index table. The x3 third indices correspond to the x3 row in the first generating matrix, and the x4 fourth indices correspond to the x4 row in the first generating matrix. The x3 row includes rows corresponding to the third type of submatrices, and the x4 row includes rows corresponding to the fourth type of submatrices. x3 and x4 are both positive integers.

[0036] In conjunction with the first aspect, in some possible implementations, when the second codeword sequence is obtained by encoding based on the second generator matrix and K′ bits to be encoded, the second generator matrix is ​​composed of K′ rows of the first generator matrix corresponding to the first K′ indices in the first index table. Here, the X indices include x1 first indices and x2 second indices, and the x2 second indices are located before the x1 first indices in the first index table. The x1 first indices correspond to the x1 row in the first generator matrix, and the x2 second indices correspond to the x2 row in the first generator matrix. The x1 row includes the rows corresponding to the first type of submatrix, and the x2 row includes the rows corresponding to the second type of submatrix. Both x1 and x2 are positive integers.

[0037] In conjunction with the first aspect, in some possible implementations, when the second codeword sequence is obtained by encoding based on the second generating matrix and K′ bits to be encoded, the second generating matrix is ​​composed of the K′ rows of the first generating matrix corresponding to the first K′ indices in the first index table. Here, the X indices include x3 third indices and x4 fourth indices, and the x4 fourth indices are located before the x3 third indices in the first index table. The x3 third indices correspond to the x3 row in the first generating matrix, and the x4 fourth indices correspond to the x4 row in the first generating matrix. The x3 row includes the row corresponding to the third type of submatrix, and the x4 row includes the row corresponding to the fourth type of submatrix. Both x3 and x4 are positive integers.

[0038] In conjunction with the first aspect, in some possible implementations, when the first codeword sequence is obtained by encoding based on the first generator matrix and K′ bits to be encoded, K P Each padding bit can be either 1 or 0.

[0039] In conjunction with the first aspect, among some possible implementation methods, in K P When the padding bits are all 1, the method further includes: determining the third generating matrix based on the first generating matrix, wherein the third generating matrix is ​​formed by K P K of the first generator matrix corresponding to the padding bits P The first codeword sequence is composed of a line; the third codeword sequence is determined based on the first codeword sequence and the third generator matrix; the third codeword sequence is then sent.

[0040] In conjunction with the first aspect, in some possible implementations, the third codeword sequence c2 satisfies: Where c1 represents the first codeword sequence, This represents the third generating matrix.

[0041] Secondly, a communication method is provided, which can be executed by a second communication device (or decoding device). Unless otherwise specified, "second communication device" can refer to a communication device (e.g., a terminal device, network device, decoding device, etc.), a component of a communication device (e.g., a processor, chip, or chip system, etc.), or a logic module or software that implements all or part of the communication device. The component used in the communication device can be a component within the communication device, or it can be independent of the communication device but coupled to it. For ease of understanding, the following description uses execution by a second communication device as an example.

[0042] The method includes: a second communication device acquiring a received sequence, the received sequence corresponding to K′ bits to be decoded, where K′ is a positive integer; the second communication device determining a first generator matrix of the RM code based on parameters m and r, the first generator matrix comprising M rows and N columns. N = 2m, where m, r, M, and N are all positive integers; where K′ = K + K P =M, and K P When it is not 0, the second communication device uses the first generating matrix and K. P The second communication device decodes the received sequence using a padding bit to obtain K information bits; or, when K′=K<M, the second communication device decodes the received sequence using the second generating matrix to obtain K information bits. The second generating matrix is ​​composed of K′ rows from the first generating matrix and includes K′ rows and N columns.

[0043] It should be understood that the second aspect corresponds to the first aspect, and detailed descriptions and technical effects can be found in the description of the first aspect above.

[0044] In conjunction with the second aspect, in some possible implementations, the first generating matrix satisfies:

[0045] Here, G(m,r) represents the first generating matrix.

[0046] For example, G(m,r) consists of a submatrix satisfying the first condition and a matrix of all zeros. The first condition is that for a submatrix G(a,b) in G(m,r), a = b or b = 0. Specifically, when b = 0 in G(a,b), G(a,b) is a 1-row, 2-matrix matrix. a A matrix consisting entirely of 1s; when a = b in G(a, b), G(a, b) is a matrix of 2s. a Line 2 a Unit matrix.

[0047] In conjunction with the second aspect, in some possible implementations, when K′=M, K PThe padding bits are located after the K information bits in the K′ bits to be decoded; when K′ = K, the K′ row in the second generator matrix is ​​the first K′ row in the first generator matrix.

[0048] In conjunction with the second aspect, in some possible implementations, the method further includes: the second communication device determining K according to the first index table. P The positions of the padding bits and / or the positions of the K information bits in the bit sequence to be decoded, the bit sequence to be decoded includes K′ bits to be decoded, the bits to be decoded in the bit sequence to be decoded correspond to the rows in the first generator matrix, wherein the first index table includes X indices, the X indices correspond one-to-one with the X rows in the first generator matrix, and X is a positive integer less than or equal to M.

[0049] In conjunction with the second aspect, in some possible implementations, the first generating matrix includes a first type of submatrix and a second type of submatrix. The first type of submatrix is ​​an identity matrix, and the second type of submatrix is ​​an all-1 matrix. The second type of submatrix includes 1 row and s columns, where s is an integer greater than or equal to 2.

[0050] In conjunction with the second aspect, in some possible implementations, the first generating matrix includes a third type of submatrix and a fourth type of submatrix. The third type of submatrix is ​​the submatrix obtained by performing T1 first operations on the first generating matrix, where T1 is an integer greater than or equal to a first threshold. The fourth type of submatrix is ​​the submatrix obtained by performing T2 first operations on the first generating matrix, where T2 is an integer less than the first threshold. The third and fourth type of submatrixes are matrices that satisfy a first condition. The first condition includes: in matrix (a, b), a = b, or b = 0, where a is a positive integer. The first operation is to split the matrix (x, y) that does not satisfy the first condition to obtain two first submatrices (x-1, y), one second submatrix (x-1, y-1), and a matrix of all zeros. The two first submatrices (x-1, y) are located in the first... The first submatrix, consisting entirely of zeros, is located in the bottom left corner of matrix (x, y). It has the same number of rows as the second submatrix. The second submatrix, (x-1, y-1), is located in the bottom right corner of matrix (x, y). The second submatrix is ​​the last submatrix in matrix (x, y). Line 2 ( x- 1)In the case where the first generating matrix satisfies the first condition and r = 0, the number of times the first operation is processed in each row of the first generating matrix is ​​0. If the first generating matrix does not satisfy the first condition, the rows corresponding to the third type of sub-matrix and the rows corresponding to the fourth type of sub-matrix are determined based on the first generating matrix and the first operation. The first generating matrix is ​​denoted as G(m, r). The first operation performed on the first generating matrix is ​​applied to G(m, r), and includes performing the first operation on G(m, r) to obtain two first sub-generating matrices (m-1, r) and one second sub-generating matrix. Generate a matrix (m-1, r-1) and a matrix of all zeros. If the first sub-generated matrix (m-1, r) satisfies the first condition, the first operation is not performed on the first sub-generated matrix (m-1, r). If the second sub-generated matrix (m-1, r-1) satisfies the first condition, the first operation is not performed on the second sub-generated matrix (m-1, r-1). If the first sub-generated matrix (m-1, r) does not satisfy the first condition, the first operation is performed on the first sub-generated matrix (m-1, r-1). If the second sub-generated matrix (m-1, r-1) does not satisfy the first condition, the first operation is performed on the second sub-generated matrix (m-1, r-1).

[0051] In conjunction with the second aspect, in some possible implementations, K is determined based on the first index table. P The positions of the padding bits in the bit sequence to be decoded include: according to the first K bits in the first index table. P Each index determines K. P The positions of the padding bits in the bit sequence to be decoded are given, where X indices include x1 first indices and x2 second indices, and x1 first indices are located before x2 second indices in the first index table. x1 first indices correspond to x1 row in the first generating matrix, and x2 second indices correspond to x2 row in the first generating matrix. x1 row includes the row corresponding to the first type of submatrix, and x2 row includes the row corresponding to the second type of submatrix. x1 and x2 are both positive integers.

[0052] In conjunction with the second aspect, in some possible implementations, K is determined based on the first index table. P The positions of the padding bits in the bit sequence to be decoded include: according to the first K bits in the first index table. P Each index determines K. P The positions of the padding bits in the bit sequence to be decoded are given, where X indices include x3 third indices and x4 fourth indices. The x3 third indices are located before the x4 fourth indices in the first index table. The x3 third indices correspond to the x3 row in the first generating matrix, and the x4 fourth indices correspond to the x4 row in the first generating matrix. The x3 row includes the row corresponding to the third type of submatrix, and the x4 row includes the row corresponding to the fourth type of submatrix. Both x3 and x4 are positive integers.

[0053] In conjunction with the second aspect, in some possible implementations, determining the positions of the K information bits in the bit sequence to be decoded according to the first index table includes: determining the positions of the K information bits in the bit sequence to be decoded according to the first K indices in the first index table, wherein the X indices include x1 first indices and x2 second indices, and the x2 second indices are located before the x1 first indices in the first index table, the x1 first indices correspond to the x1 row in the first generator matrix, the x2 second indices correspond to the x2 row in the first generator matrix, the x1 row includes the rows corresponding to the first type of submatrix, the x2 row includes the rows corresponding to the second type of submatrix, and x1 and x2 are both positive integers.

[0054] In conjunction with the second aspect, in some possible implementations, determining the positions of K information bits in the bit sequence to be decoded according to the first index table includes: determining the positions of K information bits in the bit sequence to be decoded according to the first K indices in the first index table, wherein the X indices include x3 third indices and x4 fourth indices, and the x4 fourth indices are located before the x3 third indices in the first index table, the x3 third indices correspond to the x3 row in the first generating matrix, the x4 fourth indices correspond to the x4 row in the first generating matrix, the x3 row includes the row corresponding to the third type of submatrix, the x4 row includes the row corresponding to the fourth type of submatrix, and x3 and x4 are both positive integers.

[0055] In conjunction with the second aspect, in some possible implementations, K is determined based on the first index table. P The positions of the padding bits and the K information bits in the bit sequence to be decoded include: based on the first K bits in the first index table. P Each index determines K. P The positions of the padding bits in the bit sequence to be decoded are determined according to the last K indices in the first index table. The positions of the K information bits in the bit sequence to be decoded are determined, wherein the X indices include x1 first indices and x2 second indices, and the x1 first indices are located before the x2 second indices in the first index table.

[0056] or;

[0057] According to the last K in the first index table P Each index determines K. PThe positions of the padding bits in the bit sequence to be decoded are determined based on the first K indices in the first index table. Here, the X indices include x1 first indices and x2 second indices, with the x2 second indices preceding the x1 first indices in the first index table. The x1 first indices correspond to the x1 row in the first generator matrix, and the x2 second indices correspond to the x2 row in the first generator matrix. The x1 row includes rows corresponding to the first type of submatrix, and the x2 row includes rows corresponding to the second type of submatrix. Both x1 and x2 are positive integers.

[0058] In conjunction with the second aspect, in some possible implementations, K is determined based on the first index table. P The positions of the padding bits and the K information bits in the bit sequence to be decoded include: based on the first K bits in the first index table. P Each index determines K. P The positions of the padding bits in the bit sequence to be decoded are determined according to the last K indices in the first index table. Among them, the X indices include x3 third indices and x4 fourth indices, and the x3 third indices are located before the x4 fourth indices in the first index table.

[0059] or;

[0060] According to the last K in the first index table P Each index determines K. P The positions of the padding bits in the bit sequence to be decoded are determined based on the first K indices in the first index table. Here, the X indices include x3 third indices and x4 fourth indices, with the x4 fourth indices preceding the x3 third indices in the first index table. The x3 third indices correspond to the x3 row in the first generating matrix, and the x4 fourth indices correspond to the x4 row in the first generating matrix. The x3 row includes rows corresponding to the third type of submatrices, and the x4 row includes rows corresponding to the fourth type of submatrices. x3 and x4 are both positive integers.

[0061] In conjunction with the second aspect, in some possible implementations, when decoding K information bits based on the second generating matrix and K′ bits to be decoded, the second generating matrix is ​​composed of K′ rows of the first generating matrix corresponding to the first K′ indices in the first index table. Here, the X indices include x1 first indices and x2 second indices, and the x2 second indices are located before the x1 first indices in the first index table. The x1 first indices correspond to the x1 row in the first generating matrix, and the x2 second indices correspond to the x2 row in the first generating matrix. The x1 row includes the rows corresponding to the first type of submatrices, and the x2 row includes the rows corresponding to the second type of submatrices. Both x1 and x2 are positive integers.

[0062] In conjunction with the second aspect, in some possible implementations, when decoding K information bits based on the second generating matrix and K′ bits to be decoded, the second generating matrix is ​​composed of K′ rows of the first generating matrix corresponding to the first K′ indices in the first index table. Here, X indices include x3 third indices and x4 fourth indices, and the x4 fourth indices are located before the x3 third indices in the first index table. The x3 third indices correspond to the x3 row in the first generating matrix, and the x4 fourth indices correspond to the x4 row in the first generating matrix. The x3 row includes the row corresponding to the third type of submatrix, and the x4 row includes the row corresponding to the fourth type of submatrix. Both x3 and x4 are positive integers.

[0063] In conjunction with the second aspect, in some possible implementations, based on the first generating matrix and K... P When K' bits are decoded using 1 padding bit to obtain K information bits, K P Each padding bit can be either 1 or 0.

[0064] Thirdly, a communication device is provided, which has the function of implementing the method in the first aspect or any possible implementation of the first aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0065] Fourthly, a communication device is provided, which has the function of implementing the method in the second aspect or any possible implementation of the second aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0066] Fifthly, a communication device is provided, comprising at least one processor configured to cause the communication device to perform the method of the first aspect or any possible implementation thereof; or to perform the method of the second aspect or any possible implementation thereof.

[0067] Optionally, the at least one processor is coupled to at least one memory for storing computer programs or instructions, and the at least one processor is used to call and run the computer programs or instructions from the at least one memory, causing the communication device to perform the method in the first aspect or any possible implementation thereof; or to perform the method in the second aspect or any possible implementation thereof.

[0068] Optionally, the at least one processor may be included in the communication device or configured outside the communication device. Optionally, the communication device may also include the at least one memory.

[0069] Optionally, the communication device further includes at least one communication interface. As an example, the communication interface may include an input interface and / or an output interface, or it may be an interface circuit.

[0070] Sixthly, a communication device is provided, comprising a communication interface and a circuit. The communication interface is configured to receive a signal to be processed and transmit the signal to the circuit. The circuit is configured to process the signal to perform a method as described in the first aspect or any possible implementation thereof; or to perform a method as described in the second aspect or any possible implementation thereof. Optionally, the communication interface is further configured to output a signal processed by the circuit. Optionally, the signal may include information and / or data. Optionally, the communication device may be a chip (e.g., a baseband chip) or a chip system.

[0071] A seventh aspect provides a computer-readable storage medium storing computer program code or instructions that, when executed on a computer, cause the method of the first aspect or any possible implementation thereof to be implemented; or, the method of the second aspect or any possible implementation thereof to be implemented.

[0072] Eighthly, a computer program product is provided, the computer program product comprising computer program code or instructions, which, when executed on a computer, cause the method in the first aspect or any possible implementation thereof to be implemented; or, as in the second aspect or any possible implementation thereof, the method to be implemented.

[0073] A ninth aspect provides a wireless communication system, including a communication device as described in the third aspect and a communication device as described in the fourth aspect. Attached Figure Description

[0074] Figure 1 This is an example of a communication system applicable to the technical solutions of this application.

[0075] Figure 2 This is a schematic diagram of the basic process of wireless communication.

[0076] Figure 3 This is a flowchart of a communication method provided in an embodiment of this application.

[0077] Figure 4 This is a schematic diagram of the first generator matrix corresponding to an RM code with m=4 and r=2 provided in an embodiment of this application.

[0078] Figure 5 This is a schematic diagram of a recursion tree corresponding to an RM code with m=4 and r=2 provided in an embodiment of this application.

[0079] Figure 6 A schematic structural diagram of a communication device provided in this application.

[0080] Figure 7 A schematic structural diagram of another communication device provided in this application.

[0081] Figure 8 A schematic structural diagram of the chip provided in this application. Detailed Implementation

[0082] The technical solutions of this application can be applied to various existing and future communication systems, including but not limited to: satellite communication systems, fifth-generation (5G) systems or new radio (NR) systems, long-term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, and future communication systems. Furthermore, they can also be applied to sidelink (SL) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), and Internet of Things (IoT) communication systems, or other communication systems, etc., which are not limited herein.

[0083] Figure 1 This is an example of a communication system applicable to the technical solution of this application. For example... Figure 1 The communication system may include one or more first communication devices and one or more second communication devices. Optionally, one of the first and second communication devices may be a terminal device, and the other may be a network device. The method provided in this application is applicable to... Figure 1 The communication between the network device and the terminal device shown is either uplink or downlink communication. For example, in downlink communication, the first communication device in this embodiment is a network-side device, and the second communication device is a terminal-side device; in uplink communication, the first communication device in this embodiment is a terminal-side device, and the second communication device is a network-side device.

[0084] For example, a terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user apparatus. In the embodiments of this application, the terminal device may be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as a handheld device with wireless connectivity, in-vehicle equipment, etc. The terminal device in the embodiments of this application may be a mobile phone, tablet computer, laptop computer, PDA, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, etc. Optionally, the UE may be used to act as a base station. For example, the UE may act as a scheduling entity, providing sidelink signals between UEs in V2X or SL, etc.

[0085] In this embodiment, the device used to implement the functions of the terminal device can be the terminal device itself, or any device capable of supporting the terminal device in implementing the corresponding functions, such as a chip, processor, circuit, hardware, and / or software combination. This device is located on the terminal side and can be configured within or used in conjunction with the terminal device. The chip system can consist of chips or include chips and other discrete components. In this embodiment, the terminal device is used as an example to illustrate the device for implementing the corresponding functions of the terminal device.

[0086] The network device in this application embodiment may include a device for communicating with a terminal device. This network device may include an access network device or a radio access network device; for example, the network device may be a base station. In this application embodiment, the access network device may refer to a radio access network (RAN) node (or device) that connects the terminal device to the wireless network. A base station can broadly encompass, or be replaced by, various names such as: NodeB, evolved NodeB (eNB), next-generation NodeB (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station, auxiliary station, motor slide retainer (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. A base station can be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station can also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station can also be a mobile switching center, a device performing base station functions in D2D, V2X, and M2M communications, a network device (e.g., a base station) in a future communication network, or a device performing network device functions. A base station can support networks using the same or different access technologies. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). The embodiments of this application do not limit the specific technology or device form used in the network equipment.

[0087] Base stations can be fixed or mobile. For example, a helicopter or drone can be configured to act as a mobile base station, and one or more cells can move depending on the location of the mobile base station. In other examples, a helicopter or drone can be configured as a device to communicate with another base station.

[0088] In some deployments, the network device in this application embodiment may be a device including a CU, or a DU, or a device including both CU and DU, or a control plane CU node (central unit-control plane (CU-CP)) and a user plane CU node (central unit-user plane (CU-UP)) and a DU node. For example, the network device may include gNB-CU-CP, gNB-CU-UP, and gNB-DU.

[0089] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes each implementing some of the base station's functions. For example, RAN nodes can be CUs, DUs, CU-CPs, CU-UPs, or RUs. CUs and DUs can be configured separately or included in the same network element, such as a BBU. RUs can be included in radio frequency equipment or radio frequency units, such as RRUs, AAUs, or RRHs.

[0090] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open radio access network (ORAN / O-RAN) system, CU can also be called an open CU (open CU, O-CU), and DU can also be called an open DU (open DU, O-DU). CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0091] In this embodiment, the device used to implement the functions of the network device can be the network device itself; it can also be a device capable of supporting the network device in implementing the corresponding functions, such as a chip, processor, circuit, hardware, and / or software combination. This device is located on the network side and can be configured within or used in conjunction with the network device. In this embodiment, only the network device is used as an example to illustrate the implementation of the corresponding functions of the network device.

[0092] Figure 2 This is a schematic diagram of the basic process of wireless communication. For example... Figure 2As shown, at the signal transmitting end, the signal source is transmitted after sequentially undergoing source coding, channel coding, and digital modulation. At the signal receiving end, the received signal is sequentially processed through digital demodulation, channel decoding, and source decoding before outputting the signal to the destination. Channel coding and decoding is one of the core technologies in the field of wireless communication. The complete channel coding process includes one or more of the following: adding cyclic redundancy check (CRC) codes, code block segmentation, error correction coding, rate adaptation, code block concatenation, data interleaving, and data scrambling. Error correction coding is a particularly crucial part. The purpose of error correction coding is to ensure that the receiving device can automatically correct errors that occur during data transmission with minimal redundancy overhead. At the same bit error rate, the smaller the overhead required, the higher the coding efficiency. Traditional channel coding and decoding generally include linear block codes (such as Hamming codes, Gray codes, BCH codes, RS codes, etc.), convolutional codes, and concatenated codes. These codes have their own different characteristics and performance, and are suitable for different scenarios.

[0093] In third-generation (3G) and fourth-generation (4G) mobile communication systems, Turbo codes, defined by the 3rd Generation Partnership Project (3GPP) standard, are convolutional codes with excellent performance, approaching the limits of Shannon's theory. In the 5G era, data transmission rates are orders of magnitude higher than in 4G. For Turbo codes, their serial-processing-based decoders struggle to effectively support such high-speed data transmission. Simultaneously, the 5G era has brought about richer service applications and new requirements for channel coding. For example, massive machine-type communication (mMTC) requires smaller data packets, while ultra-reliable low-latency communications (URLLC) demands high levels of encoding / decoding latency and low error rates. Therefore, based on the key channel coding requirements of these three major 5G application scenarios, the 5G standard ultimately adopted low-density parity-check codes (LDPC) and polar codes. Compared to traditional linear block codes and convolutional codes, these two types of codes have superior performance and can approach the limits of Shannon theory very closely. However, they also have their own characteristics in terms of applicable scenarios and the complexity of the codec.

[0094] The method provided in this application can be used in channel coding and decoding, and can be used in dedicated network devices or general-purpose devices. It can be applied to the various network devices (e.g., base stations) and the various terminal devices mentioned above. Specifically, the channel coding scheme is mainly implemented by the channel coding unit (e.g., encoder or device that supports the coding device to implement the corresponding function) in these devices; the channel decoding scheme is mainly implemented by the channel decoding unit (e.g., decoder or device that supports the decoding device to implement the corresponding function) in these devices.

[0095] Optionally, the functions of the encoding or decoding device can be implemented by application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or by software (e.g., program code in memory), or by a combination of both, without limitation.

[0096] To facilitate understanding of the embodiments provided in this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0097] 1. RM code

[0098] Rectifying Rand (RM) codes are among the oldest, simplest, and most unique error-correcting codes. Proposed by Demuller in 1954, they are over 70 years old. Due to their unique and rich structural characteristics, RM codes have attracted extensive research from scholars in wireless communication, computer science, cryptography, and discrete mathematics. Modeling and characterizing RM codes have employed various methods, including finite geometry, polynomial rings, and Boolean functions. This paper introduces a definition of RM codes based on polynomial rings:

[0099] Binary RM codes contain multivariate polynomials in the binary field. The evaluation results are as follows. Consider a polynomial ring with m variables. For a polynomial and a binary vector Define Eval z (f)=f(z1,z2,…,z mLet f be the value of the polynomial f in the binary vector z. Based on this, the evaluation vector of the polynomial f can be defined. That is, a coordinate of Eval(f) is the evaluation result of the polynomial f at a certain binary vector. Since The CCP has 2 m There are m-dimensional binary vectors, therefore the evaluation vector Eval(f) has a total of 2 m Each dimension. For an RM code with parameters m and r, its codeword set can be defined as the set of evaluation vectors for all polynomials of order no higher than r, i.e., an RM(m,r) code can be represented as:

[0100]

[0101] Here, deg(f) represents the order of the polynomial f. Without ambiguity, the parameter m can be called the code length parameter of the RM(m,r) code (or the first parameter of the RM code), and the parameter r can be called the order of the RM(m,r) code (or the second parameter of the RM code). According to the above definitions, the number of information bits k in the RM(m,r) code is the number of m-ary binary monomials, which can be expressed as: in This represents the number of combinations. Furthermore, the generator matrix of the RM(m,r) code can be easily written based on the evaluation vector of the monomial. For example, for m=3 and r=2, the generator matrix of the corresponding RM code can be expressed as:

[0102]

[0103] From the generator matrix G of the RM code, its inverse matrix G- can be easily written. 1 Therefore, for any valid RM codeword x∈RM(m,r), G- 1 Obtain its corresponding information bit u = xG -1 .

[0104] The recursive generator matrix of RM codes is another way to define RM code generator matrices, which utilizes the recursive property of RM codes. For any valid codeword x in an RM(m,r) code, this codeword can be divided into a first half and a second half, for example, it can be represented as: x = (x1, x2). Then x1, x2 ∈ RM(m-1, r), and Suppose the generator matrix of the RM(m,r) code is represented as G. m,r Alternatively, G(m,r), when the information sequence is u, the corresponding generated RM codeword sequence is x = u·G. m,r Based on the aforementioned recursive properties of RM codes, the generator matrix G can be... m,r Decomposed into the following form:

[0105]

[0106] Among them, G m,r In this context, 0 generally refers to a matrix consisting entirely of zeros, and its dimension is the same as G. m-1,r-1 The sizes are the same. For some special m and r, there are special code types, so their generator matrices can be easily written. For example, based on the recursive property, G can be... m,r It can be decomposed into a matrix that includes the following two special cases:

[0107] 1) When r = 0, the RM code corresponds to a 1-bit repeat code, which means that the 1-bit information bit is repeated twice. m Therefore, the generator matrix corresponding to the RM code with r=0 is 1 row and 2 columns. m A matrix of all 1s in each column;

[0108] 2) When r = m, the RM code corresponds to a code rate of 1. Therefore, the generator matrix corresponding to this RM code with r = m is of size 2. m The identity matrix.

[0109] Based on the two generator matrices of RM codes mentioned above and the recursive definition of generator matrices, the generator matrix of any RM code can be easily obtained. For example, for the RM(3,1) code, it is known that the RM(3,1) code can be constructed from RM(2,0) codes and RM(2,1) codes; while the RM(2,1) code can be constructed from RM(1,0) codes and RM(1,1) codes. Therefore, the generator matrix of RM(3,1) can be expressed as:

[0110]

[0111] Generally, the RM code generation matrix defined in the above manner is also called a recursive generation matrix.

[0112] RM codes have many important characteristics that greatly aid in their decoding algorithms. Below is a brief introduction to the characteristics of RM codes:

[0113] 1) The self-purchase and exchange nature of RM codes

[0114] For a valid codeword x in an RM(m,r) code, its 2 m The bits of a codeword can be represented by an m-dimensional binary vector z = (z1, ..., z2). m Use ) as the index. For any binary full-rank matrix and vectors Define coordinate transformation That is, placing the bit at position z of codeword x into Position, so that we can get a new length of 2 m The code

[0115] 2) Decomposition properties of RM codes

[0116] For any valid codeword x of an RM(m,r) code (or any of its automorphic permutation codewords) (See the aforementioned properties), this codeword can be divided into a first half and a second half: x = (x1, x2). At this point, x1, x2 ∈ RM(m-1, r), and (for automorphic permutation codewords)

[0117] 3) Projection properties of RM codes

[0118] definition Let be an s-dimensional subspace of an m-dimensional binary vector space, denoted as . It is a subspace The set of all cosets, i.e. Special There are 2 in the middle m-s A coset. Define an RM codeword y in a subspace. The projection of the subspace is but

[0119] 2. RM code decoding algorithm

[0120] Decoding algorithms for RM codes can include fast hadamard transform (FHT) decoding, single parity check (SPC) decoding, Dumer decoding, and recursive projection aggregation (RPA) decoding.

[0121] 1) FHT decoding

[0122] The FHT decoding algorithm is primarily designed for efficient decoding of first-order RM codes. For example, for an RM(m,1) code, the length of its information bits can be represented as m+1. If a maximum likelihood estimation (ML) decoding algorithm is used, it would require enumerating 2... m+1 Given m+1 different information bit sequences, each sequence is RM-encoded. For each encoded sequence, the likelihood is calculated based on the log-likelihood ratio (LLR) of each received bit, and all 2^m bits are used. m+1 The codeword with the highest likelihood value among the candidate information bit sequences is used as the decoding result. Even without considering encoding complexity, this method requires a certain number of floating-point additions. (That is, the complexity is approximately the square of the code length).

[0123] The FHT decoding algorithm utilizes the inherent characteristics of RM codes to accelerate the calculation of LLR in the aforementioned process. For a codeword sequence... Its likelihood can be expressed as Where L z This is the bit received LLR at coordinate z. Since the FHT decoding algorithm is designed for first-order RM codes, its RM codeword bits can be represented as... Therefore, maximizing the likelihood is equivalent to finding the information bits {u0,…,u m} makes maximize.

[0124] For binary variables Can be defined If all of them Arranged into vectors It is essentially L z The Hadamard transform of the first-order RM code can be solved quickly using the FHT algorithm, thus completing the ML decoding of the first-order RM code.

[0125] 2) SPC decoding

[0126] The SPC decoding algorithm is primarily a high-efficiency decoding algorithm for m-1 order RM codes. In fact, RM(m, m-1) codes are essentially SPC codes. SPC codes have only one parity bit, and after adding the parity bit, the XOR result of all codeword bits is 0. The decoding method for SPC codes is relatively simple: first, perform a hard decision on each bit based on the LLR value. If the number of 1s after the hard decision is even, the hard decision result is used as the decoding result; otherwise, flip the hard decision bit with the smallest absolute LLR value and output it. Its overall computational complexity is O(n log n).

[0127] 3) Dumer decoding

[0128] Dumer decoding is a classic RM code decoding algorithm. It cleverly utilizes the decomposition and order reduction property of RM codes, solving them through a serial recursive approach. For example, suppose the receiving device (e.g., Figure 3 The second communication device in the system received the LLR sequence L0,…,L n This corresponds to the RM(m, r) code, where n = 2m is the code length or the length of the received LLR sequence. From the decomposition and order reduction property of RM codes, we know that for an RM codeword y∈RM(m, r) = (y... l ,y r ), where y l It's the first half of the typing, y rThis is the second half of the code. Among them, y l ∈RM(m-1, r), The Dumer decoding algorithm utilizes this property for decoding, first processing the first half L of the received sequence. l and the second half L r Element-by-element merging yields the merged LLR sequence:

[0129]

[0130] in, This represents the merging method for LLR fields, such as tanh merging, which can be represented as:

[0131] L c =sign(L l )·sign(L r )·min(|L l |,|L r |)

[0132] Here, sign(·) represents the sign operation. The merged sequence L c Corresponding to RM(m-1, r-1) codes, the decoded result y can be obtained by aligning and performing a reduction in order. c Next, we will use y c The first half and the second half of the received sequence are merged a second time:

[0133] L d =L l +(1-2·y c )·L r

[0134] Among them, L d For the corresponding RM(m-1, r) code, it can be decoded by reducing its order. The above decoding process can be recursively repeated until some special RM nodes are reached. For example, RM(s, 1) can be decoded using the FHT algorithm, while RM(s, 0), RM(s, s), and RM(s, s-1) can be solved efficiently using the maximum likelihood decoding algorithm.

[0135] 3) RPA decoding

[0136] The RPA decoding algorithm cleverly utilizes several properties of RM codes, completing the decoding process recursively and iteratively. The following example, decoding RM(m, r) codes, exemplifies the decoding flow of the RPA algorithm. Here, the code length n = 2^n. m The LLR sequence of the received codeword is The RPA algorithm process can be described as follows.

[0137] Step 1 (Projection): First, using the projection property of RM codes, project the received codeword LLR sequence onto 2. m -1 subspace, resulting in 2 m -1 with a length of 2 m-1 The projected LLR sequence. For the i-th subspace (1≤i≤2), m -1)B i ,remember It is its corresponding projection LLR sequence.

[0138] Step Two (Recursive Decoding): Based on the projection properties of RM codes, step 2 in step one above... m -1 with a length of 2 m-1 The projected LLR sequences correspond to RM(m-1, r-1) codewords. Therefore, the RPA algorithm is used to recursively decode each projected LLR sequence. Obtain the decoding result In particular, if r-1 = 1, the projected code corresponds to a first-order RM code, which can be decoded using the FHT algorithm.

[0139] Step 3 (Aggregation): The codeword bits decoded in each projection subspace in Step 2 are essentially the XOR result of two bits in the codeword to be decoded. Therefore, the decoding result of each subspace can be used to correct the received LLR value. Specifically, for projection subspace B... i ,That

[0140]

[0141] Since each subspace has an estimate for each bit, the received LLR can be updated by averaging the estimates of all subspaces for a given bit. The pseudocode for the aggregation step is shown below:

[0142]

[0143]

[0144] After step three is completed, a hard decision can be made based on the updated received LLR value to obtain the decision result (0 or 1) for each codeword bit, or the currently updated received LLR value can be used to return to step one and restart the next round of recursive decoding. A complete decoding process from step one to step three is also called an iteration. There are two conditions for the iteration to terminate: condition 1, the number of iterations has reached the upper limit, the upper limit value is generally taken as... ( (Indicates rounding up); Condition 2, the received LLR value does not change much between two adjacent iterations, and can generally be expressed as Where |·| represents the norm, such as the 1-norm, 2-norm, etc.; θ is a pre-set threshold. If θ is smaller, more iterations are generally required. It can usually be optimized according to the trade-off between performance and complexity in the actual simulation process.

[0145] The complexity of each iteration of the RPA algorithm is Where n = 2 m Assuming iterates it it times, the complexity is O(it).

[0146] Given that existing RM codes only support certain fixed values ​​for 'm' and 'r', and since the length of information bits supported by an RM code is determined by 'm', the supported information bits are of a fixed length. Furthermore, different RM codes have different values ​​for 'm', resulting in significant differences in the supported information bit lengths. In actual transmission scenarios, the length of information bits is flexible and varied. Currently, RM codes that support fixed information bit lengths cannot flexibly support different scenarios, thus limiting the scope of application of RM codes.

[0147] Given that existing RM codes cannot flexibly support the encoding of information bits of different lengths, this application provides a communication method that aims to enable RM codes to support different lengths of information bits to be encoded, thereby expanding the application scenarios of RM codes.

[0148] The communication method provided in this application is described in detail below.

[0149] Figure 3 A schematic flowchart of the communication method 300 provided in this application. The method includes the following steps.

[0150] It is understood that method 300 can be executed by a first communication device and a second communication device. Unless otherwise specified, "first communication device" or "second communication device" can refer to a communication device, a component of a communication device, or a logic module or software capable of implementing all or part of the communication device. For example, the first communication device can be a terminal device or a network device, and the second communication device can be a terminal device or a network device; alternatively, the first communication device can be an encoding device, and the second communication device can be a decoding device. For ease of description, the terms "first communication device" and "second communication device" will be used consistently below.

[0151] 301, The first communication device acquires K information bits.

[0152] It is understandable that if the first communication device needs to communicate with the second communication device, that is, if the first communication device needs to send a signal to the second communication device, then the first communication device needs to first obtain the information bits (e.g., K information bits) corresponding to the signal to be sent to the second communication device.

[0153] Wherein, the first communication device acquiring K information bits can mean: the first communication device performs source encoding on the source symbol to generate K information bits; or, the first communication device acquiring K information bits can also mean: the first communication device receives K information bits from other communication devices. This application does not limit the specific method of acquiring K information bits.

[0154] 302. The first communication device determines the first generator matrix of the RM code based on the parameters m and r.

[0155] It is understandable that parameters m and r can be predefined, preconfigured, or indicated by signaling information. For example, assuming that there are at least one set of values ​​for predefined parameters m and r, the first communication device can determine a set of parameters m and r from at least one set of parameters m and r based on the value of K in the K information bits obtained in step 301. This set of parameters m and r corresponds to... The value of is greater than or equal to K. The specific values ​​of the parameters m and r are not limited here; for example, m can be a positive integer less than or equal to 8.

[0156] It should be understood that after the first communication device obtains the parameters m and r, it determines the first generator matrix corresponding to the RM code based on the parameters m and r.

[0157] For example, the first generating matrix consists of M rows and N columns, where, N=2 m It is understandable that the number of rows M of the first generator matrix is ​​equal to the number of the maximum information bits encoded by the RM code, and the number of columns N of the first generator matrix is ​​equal to the length of the codeword sequence corresponding to the RM code.

[0158] For example, the first generating matrix can be understood as either the polynomial generating matrix corresponding to the RM code or the recursive generating matrix corresponding to the RM code. For a detailed explanation of the polynomial generating matrix and the recursive generating matrix corresponding to the RM code, please refer to the above-described introduction to RM codes; it will not be repeated here. To facilitate understanding of the method provided in this application, the first generating matrix will be described below using a recursive generating matrix as an example. Similarly, the method provided in this application also applies when the first generating matrix is ​​a polynomial generating matrix.

[0159] Suppose that the first generating matrix is ​​a recursive generating matrix, then the first generating matrix G(m,r) can be represented as: Here, G(m,r) consists of a submatrix satisfying the first condition and a matrix of all zeros. The first condition is: for any matrix G(a,b), a = b or b = 0. A specific example of G(m,r) can be found in the above representation of the recursively generated matrix G(3,1).

[0160] Specifically, when G(m,r) does not satisfy the first condition (i.e., m≠r or r≠0), G(m,r) can include two G(m-1,r), one G(m-1,r-1), and a matrix of all zeros. Specifically, when G(m-1,r) does not satisfy the first condition (i.e., m-1≠r or r≠0), G(m-1,r) can include two G(m-1-1,r), one G(m-1-1,r-1-1), and a matrix of all zeros, until the submatrices included in G(m,r) satisfy the first condition.

[0161] 303. The first communication device encodes the codeword sequence based on K information bits and the first generator matrix.

[0162] For example, after the first communication device determines the first generator matrix based on parameters m and r, it encodes the obtained K information bits and the first generator matrix to obtain a codeword sequence.

[0163] Assuming that the number K of information bits acquired by the first communication device is equal to the number M of the first generator matrix corresponding to the RM code, the first communication device can use existing encoding methods to encode the K information bits and the first generator matrix to obtain a codeword sequence. For example, the first generator matrix can be represented as G(m, r), and the K information bits can be represented as u = (μ0, ..., μ0). k-1 If the codeword sequence is c = (c0, ..., c...), then the codeword sequence is c = (c0, ..., c...). N-1 This can be represented as:

[0164]

[0165] It should be understood that the above operations all use binary field operations.

[0166] Furthermore, assuming that the number of information bits K acquired by the first communication device is less than the number of rows M of the first generator matrix corresponding to the RM code, a specific example of the first communication device encoding the codeword sequence based on the K information bits and the first generator matrix is ​​as follows:

[0167] Method 1,

[0168] The first communication device encodes the first generator matrix and K′ bits to be encoded to obtain codeword sequence #1 (or the first codeword sequence), wherein the K′ bits to be encoded include K information bits and K… P There are 100 padding bits. Where K′ = M, and K... P =MK.

[0169] In one possible implementation, of the K′ bits to be encoded, the K information bits are located at K. PBefore the padding bits, or to put it another way, in the K′ bits to be encoded, K P The padding bits are located after the K information bits.

[0170] Alternatively, it can be understood that the first communication device encodes the codeword sequence #1 based on the first generator matrix and the bit sequence to be encoded. This bit sequence includes K′ bits to be encoded, and the K information bits are located at position K in the bit sequence to be encoded. P Before the padding bits.

[0171] Assume K = 7, m = 4, r = 2. The first communication device acquires K = 7 information bits. Based on m = 4 and r = 2, the first communication device obtains a first generator matrix G(4, 2), which consists of 11 rows and 16 columns. Since 7 < 11, K′ = 11 bits to be encoded includes 7 information bits and 4 padding bits, and these 4 padding bits are located after the 7 information bits in the 11 bits to be encoded. Figure 4 As shown, assume that K′ = 11 bits to be encoded correspond to μ0, ..., μ 10 Where μ0, ..., μ6 are used to store 7 information bits, and μ7, ..., μ6 are used to store 7 information bits. 10 This is used to place 4 padding bits. The first communication device uses K′ = 11 bits to be encoded and... Figure 4 The first generator matrix G(4,2) shown is encoded to obtain codeword sequence #1.

[0172] In another possible implementation, among the K′ bits to be encoded, K information bits and / or K P The specific position of each padding bit in the bit sequence to be encoded can be determined according to the first index table. Alternatively, it can be understood that the first communication device can determine K based on the first index table. P The positions of the padding bits and / or the positions of the K information bits in the bit sequence to be encoded. The bits in the bit sequence to be encoded correspond to rows in the first generator matrix. The first index table includes X indices, each corresponding one-to-one with an X row in the first generator matrix, where X is a positive integer less than or equal to M.

[0173] For example, the X indices in the first index table can be represented as [0 2 1 3…=X-1], where X≤K′=M. Here, "0" in the first index table corresponds to the 0th row in the first generator matrix, and the "0"th row in the first generator matrix corresponds to the position of the "0"th bit to be encoded in the bit sequence to be encoded. Similarly, "X-1" in the first index table corresponds to the (X-1)th row in the first generator matrix, and the "X-1"th row in the first generator matrix corresponds to the position of the "X-1"th bit to be encoded in the bit sequence to be encoded.

[0174] Assumption 1: The order of the indices in the first index table is associated with the bit positions in the bit sequence to be encoded corresponding to each row from row 0 to row M-1 of the first generator matrix. For example, the X indices in the first index table can be represented as [0 = 1 = 2 = 3 ... = X-1].

[0175] As an example, in K′ bits to be encoded, the specific positions of the K information bits in the bit sequence are determined according to a first index table. Combining the example above where K = 7, m = 4, and r = 2, this first index table includes X indices, where X ≤ 11. Each index in this first index table corresponds to each bit in the bit sequence to be encoded, and also corresponds to each row in G(4, 2). Assuming X = 8, the first index table can be represented as [0 1 2 3 4 5 6 7], where the specific positions of the K = 7 information bits in the bit sequence to be encoded can be selected according to the first 7 indices in this first index table. Assuming X = 11, the first index table can be represented as [0 1 2 3 4 5 6 7 8 9 10], where the specific positions of the K = 7 information bits in the bit sequence to be encoded can be selected according to the first 7 indices in this first index table.

[0176] The specific distribution of these 7 information bits in positions 0 to 6 of the bit sequence to be encoded is not limited in this application.

[0177] As another example, in K′ bits to be encoded, K P The specific position of each padding bit in the bit sequence to be encoded is determined according to the first index table. Combining the above example, K=7, m=4, r=2, K P =4, and the first index table includes X indices, where X ≤ 11. For example, the first index table can be represented as [0 1 2 3 4 5 6 7 8 9 10], where K = 4. P The specific positions of the 4 padding bits in the bit sequence to be encoded can be selected according to the last 4 bits of the first index table. For example, the 4 padding bits are located at positions 7 to 10 in the bit sequence to be encoded.

[0178] As another example, in K′ bits to be encoded, the specific positions of the K information bits in the bit sequence and K P The specific position of each padding bit in the bit sequence to be encoded is determined according to the first index table. Combining the above example, K=7, m=4, r=2, K P=4, and the first index table includes X indices, where X = M. For example, the first index table can be represented as [0 1 2 3 4 5 6 7 8 9 10], where the specific positions of the K = 7 information bits in the bit sequence to be encoded can be selected according to the first 7 indices in the first index table. The specific distribution of these 7 information bits from position 0 to position 6 in the sequence to be encoded is not limited in this application. K P =The specific positions of the 4 padding bits in the bit sequence to be encoded can be selected according to the last 4 indexes in the first index table. For example, the 4 padding bits are located at positions 7 to 10 in the bit sequence to be encoded.

[0179] Assumption 2: The index order in the first index table is associated with the rows corresponding to the first and second type submatrices in the first generating matrix. The first type submatrix is ​​the identity matrix in the first generating matrix, and the second type submatrix is ​​a matrix of all 1s, consisting of 1 row and s columns, where s is an integer greater than or equal to 2. The X indices in the first index table include x1 first indices and x2 second indices. The x1 first indices correspond to the x1 row of the first type submatrix in the first generating matrix, and the x2 second indices correspond to the x2 row of the second type submatrix in the first generating matrix. Both x1 and x2 are positive integers.

[0180] The following will use K=3, m=4, r=2, K P =8, the first index table includes X indexes, and X = M = 11 is used as an example for illustration. Combined with Figure 4 As shown in the figure, the first type of submatrix can be Figure 4 The lightest and second lightest gray regions shown are represented by matrices, with the first type of sub-matrices corresponding to rows 0-3, 4-5, and 7-8 respectively in the first generated matrix; the second type of sub-matrices can be... Figure 4 The matrix corresponding to the darkest gray area shown is used to represent the second type of submatrix, which corresponds to rows 6, 9, and 10 in the first generating matrix, respectively.

[0181] Suppose that in the first index table, the first index x1 precedes the second index x2. The first index table can be represented as [0 1 2 3 4 5 7 8 69 10] or [3 2 1 0 5 4 8 7 10 9 6], etc. The order of the indices within the parentheses "()" in the first index table [(01 2 3 4 5 7 8)(6 9 10)] can be changed; examples will not be provided here. The following explanation uses the first index table [0 1 2 3 4 5 7 8 6 9 10] as an example.

[0182] As an example, in K′ bits to be encoded, the specific positions of the K information bits in the bit sequence to be encoded are determined according to the first index table. The specific positions of the K = 3 information bits in the bit sequence to be encoded can be determined according to the last 3 indexes [6 910] of the first index table. For example, if the 3 information bits are located at the 6th, 9th, and 10th positions in the bit sequence to be encoded, the first communication device will place the acquired 3 information bits at the 6th, 9th, and 10th positions in the bit sequence to be encoded, respectively.

[0183] As another example, in K′ bits to be encoded, K P The specific positions of the padding bits in the bit sequence to be encoded are determined according to the first index table. This K P The specific positions of the 8 padding bits in the bit sequence to be encoded can be determined according to the first 8 index bits [01 2 3 4 5 7 8] in the first index table. For example, if the 8 padding bits are located at positions 0 to 5 and positions 7 to 8 in the bit sequence to be encoded, the first communication device will pad positions 0 to 5 and positions 7 to 8 in the bit sequence to be encoded.

[0184] As another example, in K′ bits to be encoded, the specific positions of the K information bits in the bit sequence and K P The specific positions of the padding bits in the bit sequence to be encoded are determined according to the first index table. This K P The specific positions of the 8 padding bits in the bit sequence to be encoded can be determined according to the first 8 index bits [0 1 2 3 4 57 8] in the first index table; the specific positions of the K=3 information bits in the bit sequence to be encoded can be determined according to the last 3 index bits [6 9 10] in the first index table.

[0185] Suppose that in the first index table, the first index x1 follows the second index x2. The first index table can be represented as [6 9 10 0 1 2 3 45 7 8] or [10 9 6 3 2 1 0 5 4 8 7], etc. The order of the indices within the parentheses in the first index table [(6 910)(0 1 2 3 4 5 7 8)] can be changed, which will not be listed here. The following explanation uses the first index table [6 9 10 0 1 2 3 4 5 7 8] as an example.

[0186] As an example, in K′ bits to be encoded, the specific positions of the K information bits in the bit sequence to be encoded are determined according to the first index table. The specific positions of the K = 3 information bits in the bit sequence to be encoded can be determined according to the first 3 indexes [6 910] of the first index table. For example, if the 3 information bits are located at the 6th, 9th, and 10th positions in the bit sequence to be encoded, the first communication device will place the acquired 3 information bits at the 6th, 9th, and 10th positions in the bit sequence to be encoded, respectively.

[0187] As another example, in K′ bits to be encoded, K P The specific positions of the padding bits in the bit sequence to be encoded are determined according to the first index table. This K P The specific positions of the 8 padding bits in the bit sequence to be encoded can be determined according to the last 8 bits of the first index table [01 2 3 4 5 7 8]. For example, if the 8 padding bits are located at positions 0 to 5 and positions 7 to 8 in the bit sequence to be encoded, the first communication device will pad positions 0 to 5 and positions 7 to 8 in the bit sequence to be encoded.

[0188] As another example, in K′ bits to be encoded, the specific positions of the K information bits in the bit sequence and K P The specific positions of the padding bits in the bit sequence to be encoded are determined according to the first index table. This K P The specific positions of the 8 padding bits in the bit sequence to be encoded can be determined according to the last 8 bits of the first index table [0 1 2 3 4 57 8]; the specific positions of the K=3 information bits in the bit sequence to be encoded can be determined according to the first 3 bits of the first index table [6 9 10].

[0189] Assumption 3: The index order in the first index table is associated with the rows corresponding to the third and fourth type submatrices in the first generating matrix. Specifically, the X indices in the first index table include x3 third indices and x4 fourth indices. The x3 third indices correspond to the x3 row of the third type submatrices in the first generating matrix, and the x4 fourth indices correspond to the x4 row of the fourth type submatrices in the first generating matrix. Both x3 and x4 are positive integers.

[0190] Among them, the third type of submatrix is ​​the submatrix obtained by performing the first operation T1 times in the first generating matrix, where T1 is an integer greater than or equal to the first threshold. The fourth type of submatrix is ​​the submatrix obtained by performing the first operation T2 times in the first generating matrix, where T2 is an integer less than the first threshold. The third type of submatrix and the fourth type of submatrix are matrices that satisfy the first condition. The first condition includes: a = b in matrix (a, b), or b = 0, where a is a positive integer.

[0191] It should be understood that the first threshold can be predefined, preconfigured, or signaled.

[0192] The first operation involves splitting the matrix (x, y) that does not satisfy the first condition into two first submatrices (x-1, y), one second submatrix (x-1, y-1), and a matrix of all zeros. The two first submatrices (x-1, y) are located in the first few rows of the matrix (x, y). The first submatrix, consisting entirely of zeros, is located in the bottom left corner of matrix (x, y). It has the same number of rows as the second submatrix. The second submatrix, (x-1, y-1), is located in the bottom right corner of matrix (x, y). The second submatrix is ​​the last submatrix in matrix (x, y). Line 2 ( x- 1) List.

[0193] In other words, when matrix (x, y) does not satisfy the first condition (i.e., x ≠ y or y ≠ 0), the first operation makes matrix (x, y) include two first submatrices (x-1, y), one second submatrix (x-1, y-1), and a matrix of all zeros. The two first submatrices (x-1, y) are located in the first few rows of matrix (x, y). The first submatrix, consisting entirely of zeros, is located in the bottom left corner of matrix (x, y). It has the same number of rows as the second submatrix. The second submatrix, (x-1, y-1), is located in the bottom right corner of matrix (x, y). The second submatrix is ​​the last submatrix in matrix (x, y). Line 2 ( x- 1) List.

[0194] If the first generating matrix satisfies the first condition and r = 0, the first operation is performed 0 times for each row in the first generating matrix. For example, if the first generating matrix is ​​G(3,3), then G(3,3) satisfies the first condition, and no first operation needs to be performed.

[0195] If the first generating matrix does not satisfy the first condition, the rows corresponding to the third type of submatrix and the rows corresponding to the fourth type of submatrix are determined based on the first generating matrix and the first operation. The first generating matrix is ​​denoted as G(m, r). In the first generating matrix, the first operation is performed on G(m, r). The first operation includes performing the first operation on G(m, r) to obtain two first sub-generating matrices (m-1, r), one second sub-generating matrix (m-1, r-1), and one all-zero matrix. If the first sub-generating matrix (m-1, r) satisfies the first condition, the first operation is no longer performed on the first sub-generating matrix (m-1, r); if the second sub-generating matrix (m-1, r-1) satisfies the first condition, the first operation is no longer performed on the second sub-generating matrix (m-1, r-1); if the first sub-generating matrix (m-1, r) does not satisfy the first condition, the first operation continues to be performed on the first sub-generating matrix (m-1, r-1); if the second sub-generating matrix (m-1, r-1) does not satisfy the first condition, the first operation continues to be performed on the second sub-generating matrix (m-1, r-1).

[0196] The following will combine Figure 4 In the example, assuming the first threshold is 3 and the matrix (x,y) is G(4,2), this matrix can include two first submatrices G(3,2), one second submatrice G(3,1), and a matrix of all zeros. The first submatrice G(3,2) does not satisfy the first condition; it can be further divided into two G(2,2), one G(2,1), and a matrix of all zeros. G(2,2) satisfies the first condition, so the first operation is not performed again; this G(2,2) is a submatrix obtained from the first generating matrix after two first operations. G(2,1) does not satisfy the first condition; it can be further divided into two G(1,1), one G(1,0), and a matrix of all zeros. G(1,1) and G(1,0) both satisfy the first condition, so the first operation is not performed again; these G(1,1) and G(1,0) are submatrices obtained from the first generating matrix after three first operations.

[0197] Based on the above introduction, it can be seen that the third type of submatrices in the first generating matrix include G(1,1) and G(1,0), and the fourth type of submatrices include G(2,2) and G(2,0). In the first generating matrix, G(1,1) corresponds to rows 4-5 and 7-8; G(1,0) corresponds to rows 6 and 9; G(2,2) corresponds to rows 0-3; G(1,0) corresponds to rows 6 and 9; and G(2,0) corresponds to row 10. The third type of submatrices in the first generating matrix correspond to rows 4, 5, 7, 8, 6, and 9; and the fourth type of submatrices correspond to rows 0-3 and 10. That is, x3 = 6 and x4 = 4.

[0198] Suppose that in the first index table, x3 third indices precede x4 fourth indices. The first index table can be represented as [4 5 7 8 6 9 0 1 23 10] or [5 4 6 8 7 9 3 2 1 0 10], and so on. The order of the indices within the parentheses in the first index table [(4 5 78 6 9)(0 1 2 3 10)] can be changed, which will not be listed here. The following explanation uses the first index table [4 5 7 8 6 9 0 1 2 3 10] as an example.

[0199] As an example, in K′ bits to be encoded, the specific positions of the K information bits in the bit sequence to be encoded are determined according to the first index table. The specific positions of the K = 3 information bits in the bit sequence to be encoded can be determined according to the last 3 indexes [2 310] of the first index table. For example, if the 3 information bits are located at the 2nd, 3rd, and 10th positions in the bit sequence to be encoded, the first communication device will place the acquired 3 information bits at the 2nd, 3rd, and 10th positions in the bit sequence to be encoded, respectively.

[0200] As another example, in K′ bits to be encoded, K P The specific positions of the padding bits in the bit sequence to be encoded are determined according to the first index table. This K P The specific positions of the 8 padding bits in the bit sequence to be encoded can be determined according to the first 8 index bits [45 7 8 6 9 0 1] in the first index table. For example, if the 8 padding bits are located at positions 0 to 1, 4 to 6, and 9 in the bit sequence to be encoded, the first communication device will pad positions 0 to 1, 4 to 6, and 9 in the bit sequence to be encoded.

[0201] As another example, in K′ bits to be encoded, the specific positions of the K information bits in the bit sequence and K P The specific positions of the padding bits in the bit sequence to be encoded are determined according to the first index table. This K P The specific positions of the 8 padding bits in the bit sequence to be encoded can be determined according to the first 8 indexes [4 5 7 8 6 90 1] in the first index table; the specific positions of the K=3 information bits in the bit sequence to be encoded can be determined according to the last 3 indexes [2 3 10] in the first index table.

[0202] Based on the introduction of assumptions 1 to 3 above, this K P The value of each padding bit can be 0 or 1.

[0203] For example, when K P When the value of each padding bit is 1, the first communication device can also perform the following steps:

[0204] The first communication device determines a third generating matrix based on the first generating matrix, the third generating matrix being derived from K. P K of the first generator matrix corresponding to the padding bits P The third generating matrix consists of rows, and includes K. P The first communication device determines the codeword sequence #3 based on the codeword sequence #1 and the third generator matrix, and sends the codeword sequence #3.

[0205] For example, suppose the codeword sequence #3 can be represented as: Where c1 represents codeword sequence #1, and c3 represents codeword sequence #3. Let represent the third generating matrix. Here, the additions and multiplications mentioned above are all additions and multiplications in a binary field.

[0206] As an example, K = 7, m = 4, r = 2, the first index table includes 11 indices, which can be represented as [0 1 2 34 5 6 7 8 9 10]. The specific positions of the K = 7 information bits in the bit sequence to be encoded can be selected according to the first 7 indices in the first index table. The K′ bits to be encoded include 11 bits. The 7 information bits are located at positions 0 to 6 of the 11 bits to be encoded, and positions 7 to 10 are padding bits. Assuming the padding bits at these 4 positions are 1, the first communication device encodes the bit sequence to be encoded (including 7 information bits and 4 padding bits) with the first generator matrix to obtain codeword sequence #1. The first communication device further determines codeword sequence #3 based on codeword sequence #1 and the third generator matrix, and sends codeword sequence #3. The third generating matrix is ​​determined based on the first generating matrix and four padding bits. For example, combining... Figure 4 As shown, the four padding bits are located in μ7, ..., μ7 of the bit sequence to be encoded. 10 Position, the third generating matrix It consists of the last four rows of the first generator matrix. The first communication device further determines the codeword sequence #3 based on the third generator matrix and the codeword sequence #1, and sends the codeword sequence #3.

[0207] Method 2,

[0208] The first communication device encodes the codeword sequence #2 (or the second codeword sequence) based on the second generator matrix and K′ bits to be encoded. The K′ bits to be encoded include K information bits, where K′ = K. The second generator matrix is ​​composed of K (or K′) rows from the first generator matrix, and the second generator matrix consists of K′ rows and N columns.

[0209] In one possible implementation, the K′ rows of the second generating matrix are the first K′ rows of the first generating matrix. Alternatively, it can be understood as using the first K′ rows and N columns of the first generating matrix as the second generating matrix.

[0210] Assume K = 7, m = 4, r = 2. The first communication device acquires K = 7 information bits. Based on m = 4 and r = 2, the first communication device obtains a first generator matrix G(4, 2), which consists of 11 rows and 16 columns. Since 7 < 11, K′ = 7 bits to be encoded include 7 information bits. Figure 4 The first 7 rows of G(4,2) shown are used as the second generating matrix, which consists of 7 rows and 16 columns, as follows: Figure 4As shown, the second generator matrix includes the rows corresponding to μ0, ..., μ6 in the first generator matrix, where μ0, ..., μ6 are used to place 7 information bits. The first communication device encodes the 7 bits to be encoded using the second generator matrix to obtain codeword sequence #2.

[0211] In another possible implementation, the K′ row in the second generating matrix is ​​determined from the M rows of the first generating matrix according to the first index table.

[0212] It should be understood that the second generator matrix comprises K′ rows and N columns, with each of the K′ rows corresponding one-to-one with each of the K information bits. This second generator matrix is ​​encoded with the bit sequence to be encoded to obtain codeword sequence #2. The bit sequence to be encoded comprises K information bits. The first communication device determines the K′ row of the second generator matrix from the M rows of the first generator matrix according to the first index table, and encodes the K information bits according to the second generator matrix. In other words, the first communication device selects K bit positions from the M bit positions to be encoded according to the first index table to place the K information bits, and selects the row corresponding to these K bit positions from the first generator matrix to encode the K information bits, obtaining codeword sequence #2.

[0213] It should also be understood that the first communication device determines the K′ row constituting the second generation matrix from the M rows corresponding to the first generation matrix according to the first index table, which is similar to how the first communication device in Method 1 above determines the specific positions of K information bits in the bit sequence to be encoded according to the first index table.

[0214] For example, the X indices in the first index table can be represented as [0 = 2 = 1 = 3 … = X-1], where X ≤ K′ = N. Here, "0" in the first index table corresponds to the 0th row in the first generator matrix, and the "0"th row in the first generator matrix corresponds to the position of the "0"th bit to be encoded in the bit sequence to be encoded. Similarly, "X-1" in the first index table corresponds to the (X-1)th row in the first generator matrix, and the "X-1"th row in the first generator matrix corresponds to the position of the "X-1"th bit to be encoded in the bit sequence to be encoded.

[0215] Assumption 4: The order of the indices in the first index table is associated with the bit positions in the bit sequence to be encoded corresponding to each row from row 0 to row M-1 of the first generator matrix. For example, the X indices in the first index table can be represented as [0=1=2=3…=X-1].

[0216] As an example, the K′ rows of the second generator matrix are determined from the M rows of the first generator matrix based on the first K′ indices of the first index table. Combining the example above (K=7, m=4, r=2), the first index table contains X indices, where X≤11. Assuming X=8, each index in the first index table corresponds to each bit in the bit sequence to be encoded, and also to each row in G(4,2). For example, the first index table can be represented as [0 1 2 3 4 5 6 7], where the specific positions of the K=7 information bits in the bit sequence to be encoded can be selected according to the first 7 indices in the first index table. Correspondingly, the second generator matrix is ​​constructed based on the 7 rows of the first generator matrix corresponding to the first 7 indices in the first index table.

[0217] Assumption 5: The index order in the first index table is associated with the rows corresponding to the first and second sub-matrices in the first generated matrix.

[0218] The first index table contains X indices, including x1 first indices and x2 second indices. The x1 first indices correspond to the x1 row of the first type of submatrix in the first generating matrix, and the x2 second indices correspond to the x2 row of the second type of submatrix in the first generating matrix. Both x1 and x2 are positive integers.

[0219] It should be understood that a detailed description of the first and second type of submatrices can be found in the description of Assumption 3 above.

[0220] The following will use K=3, m=4, r=2, K P =8, the first index table includes X indexes, and X = M = 11 is used as an example for illustration. Combined with Figure 4 As shown in the figure, the first type of submatrix can be Figure 4 The lightest and second lightest gray regions shown are represented by matrices, with the first type of sub-matrices corresponding to rows 0-3, 4-5, and 7-8 respectively in the first generated matrix; the second type of sub-matrices can be... Figure 4 The matrix corresponding to the darkest gray area shown is used to represent the second type of submatrix, which corresponds to rows 6, 9, and 10 in the first generating matrix, respectively.

[0221] For example, in the first index table, the first index x1 precedes the second index x2. The first index table can be represented as [0 1 2 3 4 5 7 8 6 9 10] or [3 2 1 0 5 4 8 7 10 9 6], etc. The order of the indices within the parentheses "()" in the first index table [(0 1 2 3 4 5 7 8)(6 9 10)] can be changed, but these will not be listed here. The following explanation uses the first index table [0 1 2 3 4 5 7 8 6 9 10] as an example.

[0222] As an example, the K′ rows in the second generating matrix are determined based on the K′ rows of the first generating matrix corresponding to the last K′ indices in the first index table. Since K = 3, the K′ rows included in the second generating matrix can be determined by the last 3 indices [6 9 10] in the first index table, which identify the rows in the first generating matrix that constitute the second generating matrix. That is, the second generating matrix is ​​composed of the 6th, 9th, and 10th rows of the first generating matrix.

[0223] For example, in the first index table, the first index x1 follows the second index x2. The first index table can be represented as [6 9 10 0 1 2 34 5 7 8] or [10 9 6 3 2 1 0 5 4 8 7], etc. The order of the indices within the parentheses in the first index table [(6 910)(0 1 2 3 4 5 7 8)] can be changed, which will not be listed here. The following explanation uses the first index table [6 9 10 0 1 2 3 4 5 7 8] as an example.

[0224] As an example, the K′ rows of the second generating matrix are determined based on the K′ rows of the first generating matrix corresponding to the first K′ indices in the first index table. Assuming K = 3, the K′ rows of the second generating matrix can be determined by the first 3 indices [6 9 10] in the first index table, which identify the rows in the first generating matrix that constitute the second generating matrix. That is, the second generating matrix is ​​composed of the 6th, 9th, and 10th rows of the first generating matrix.

[0225] Assumption 6: The index order in the first index table is associated with the rows corresponding to the third and fourth sub-matrices in the first generated matrix.

[0226] Among them, the X indices in the first index table include x3 third indices and x4 fourth indices. The x3 third indices correspond to the x3 row of the third type submatrix in the first generating matrix, and the x4 fourth indices correspond to the x4 row of the fourth type submatrix in the first generating matrix. Both x3 and x4 are positive integers.

[0227] It should be understood that a detailed description of the third and fourth type of submatrices can be found in the description of Hypothesis 3 above.

[0228] The following will combine Figure 4 In the example, suppose the first threshold is 3, the first generating matrix is ​​G(4,2), the third type of submatrices in the first generating matrix include G(1,1) and G(1,0), and the fourth type of submatrices include G(2,2) and G(2,0).

[0229] For example, in the first index table, the x3 third indices precede the x4 fourth indices. The first index table can be represented as [4 5 7 8 6 9 0 12 3 10] or [5 4 6 8 7 9 3 2 1 0 10], etc. The order of the indices within the parentheses in the first index table [(4 57 8 6 9)(0 1 2 3 10)] can be changed, which will not be listed here. The following explanation uses the first index table [4 5 7 8 6 9 0 1 2 3 10] as an example.

[0230] As an example, the K′ rows of the second generating matrix are determined based on the K′ rows of the first generating matrix corresponding to the last K′ indices in the first index table. Assuming K = 4, the K′ rows of the second generating matrix can be determined by the last 4 indices [1 2 3 10] in the first index table, which identify the rows in the first generating matrix that constitute the second generating matrix. That is, the second generating matrix is ​​composed of the 1st, 2nd, 3rd, and 10th rows of the first generating matrix.

[0231] For example, in the first index table, x3 third indices follow x4 fourth indices. The first index table can be represented as [0 1 2 3 10 4 57 8 6 9] or [3 2 1 0 10 5 4 6 8 7 9], etc. The order of the indices within the parentheses in the first index table [(0 12 3 10)(4 5 7 8 6 9)] can be changed, which will not be listed here. The following explanation uses the first index table [0 1 2 3 10 4 5 7 8 6 9] as an example.

[0232] As an example, the K′ rows in the second generating matrix are determined based on the K′ rows of the first generating matrix corresponding to the first K′ indices in the first index table. Since K = 3, the K′ rows of the second generating matrix can be determined by the first 3 indices [0 1 2] in the first index table, which define the rows that constitute the second generating matrix from the first generating matrix. That is, the second generating matrix is ​​composed of the 0th, 1st, and 2nd rows of the first generating matrix.

[0233] It should be understood that the examples in Methods 1 and 2 above illustrate that the first generating matrix may include a first type of sub-matrix and a second type of sub-matrix; or, the first generating matrix may include a third type of sub-matrix and a fourth type of sub-matrix. Specifically, the first type of sub-matrix is ​​the matrix corresponding to the leaf node r=m in the recursion tree corresponding to the RM code, the second type of sub-matrix is ​​the matrix corresponding to the leaf node r=0 in the recursion tree corresponding to the RM code, the third type of sub-matrix is ​​the matrix corresponding to the leaf node with a leaf depth greater than or equal to a first threshold in the recursion tree corresponding to the RM code, and the fourth type of sub-matrix is ​​the matrix corresponding to the leaf node with a leaf depth less than the first threshold in the recursion tree corresponding to the RM code.

[0234] For example, the recursive tree includes at least one leaf node, which corresponds to M bits to be encoded in the RM code. Each leaf node in the at least one leaf node corresponds to at least one bit in the M bits to be encoded.

[0235] For example, in a recursive tree, each leaf node corresponds to a leaf depth. The recursive tree includes a first leaf node, which corresponds to a first leaf depth. The first leaf depth represents the number of times the second operation is performed from the root node (4, 2) to the first leaf node in the recursive tree. The second operation is to split the node (x, y) to obtain the first node (x-1, y) and the second node (x-1, y-1). The first node (x-1, y) is located to the left of the second node (x-1, y-1). The node (x, y) and Corresponding to each bit to be encoded, the first node (x-1, y) is... Corresponding to the bits to be encoded, the second node (x-1, y-1) and For each bit to be encoded, k2 bits are located before k3 bits in the k1 bits to be encoded. x and y are both positive integers, and x and y are not equal.

[0236] In the case that the root node (m, r) satisfies the second condition and r is not 0, the recursion tree only includes the root node (m, r), the root node is a leaf node, and the second condition includes: a = b in node (a, b), or b = 0, and a is a positive integer;

[0237] In this case, if the root node (m, r) does not satisfy the second condition, at least one leaf node in the recursion tree is obtained based on the root node (m, r) and the second operation. When the first node (x-1, y) satisfies the second condition, the first node (x-1, y) is a leaf node; when the second node (x-1, y-1) satisfies the second condition, the second node (x-1, y-1) is a leaf node; when the first node (x-1, y) does not satisfy the second condition, the second operation is performed on the first node (x-1, y) until the split node satisfies the second condition; when the second node (x-1, y-1) does not satisfy the second condition, the second operation is performed on the second node (x-1, y-1) until the split node satisfies the second condition; the first second operation performed in the recursion tree is performed on the root node (m, r). The second operation performed includes: performing the second operation on the root node (m, r) to obtain the first child node (m-1, r) and the second child node (m-1, r-1). The first child node (m-1, r) satisfies the second condition and is a leaf node; the second child node (m-1, r-1) satisfies the second condition and is a leaf node; the first child node (m-1, r) does not satisfy the second condition, so the second operation is performed on the first child node (m-1, r); the second child node (m-1, r-1) does not satisfy the second condition, so the second operation is performed on the second child node (m-1, r-1).

[0238] In combination with the above Figure 4 Example of the first generating matrix in the example, Figure 5 A schematic diagram of the recursion tree corresponding to RM(4,2) is shown. The root node (4,2) is associated with {u0, ...,u...}. 10 The positions of the bits to be encoded correspond, such as... Figure 5 As shown, the root node (4,2) includes 6 leaf nodes. From left to right, leaf node (2,2) corresponds to the {u3,u2,u1,u0} bit positions to be encoded in the root node (4,2); leaf node (1,1) corresponds to the {u5,u4} bit positions to be encoded in the root node (4,2); leaf node (1,0) corresponds to the {u6} bit positions to be encoded in the root node (4,2); leaf node (1,1) corresponds to the {u8,u7} bit positions to be encoded in the root node (4,2); leaf node (1,0) corresponds to the {u9} bit positions to be encoded in the root node (4,2); and leaf node (1,0) corresponds to the {u... 10 The positions of the bits to be encoded correspond.

[0239] Combination Figure 5The recursion tree shown has the following sub-matrices: the first type corresponds to the leaf nodes where r = m, for example, the first type corresponds to leaf nodes (2, 2) and (1, 1), or it can be understood as the matrix corresponding to leaf nodes (2, 2) and (1, 1). The rows occupied by the first type of sub-matrices in the first generator matrix include the rows corresponding to the bits to be encoded {u3, u2, u1, u0}, {u5, u4}, and {u8, u7}. The second type corresponds to the leaf nodes where r = 0, for example, the second type corresponds to leaf node (1, 0), or it can be understood as the matrix corresponding to leaf node (1, 0). The rows occupied by the second type of sub-matrices in the first generator matrix include the rows corresponding to the bits to be encoded {u6}, {u9}, and {u7}. 10 The row corresponding to}.

[0240] Combination Figure 5 The recursion tree shown has the following sub-matrices: the third type corresponds to the leaf nodes in the recursion tree whose leaf depth is greater than or equal to the first threshold, and the fourth type corresponds to the leaf nodes in the recursion tree whose leaf depth is less than the first threshold. Assuming the first threshold is 3, the third type corresponds to the leaf nodes (1, 1) and (1, 0) in the last row of the recursion tree. The rows occupied by the third type in the first generator matrix include the rows corresponding to the bits to be encoded {u5, u4}, {u6}, {u8, u7}, and {u9}. The fourth type corresponds to the leaf nodes (2, 2) and (1, 0) in the second-to-last row of the recursion tree. The rows occupied by the fourth type in the first generator matrix include the rows corresponding to the bits to be encoded {u3, u2, u1, u0} and {u9}. 10 The row corresponding to}.

[0241] 304, The first communication device sends a codeword sequence.

[0242] For example, the first communication device acquires K information bits and encodes them into a codeword sequence (e.g., codeword sequence #1, codeword sequence #2, or codeword sequence #3) according to a generator matrix, and then transmits the codeword sequence. For instance, in step 303, the first communication device determines codeword sequence #1 and transmits it. In step 303, the first communication device determines codeword sequence #2 and transmits it. In step 303, the first communication device determines codeword sequence #3 and transmits it.

[0243] In one possible implementation, after the first communication device sends the codeword sequence, the codeword sequence may undergo one or more of the following processes: modulation, layer mapping, precoding, framing, etc. The final sequence sent by the first communication device to the second communication device can be called a symbol sequence. For example, the first communication device maps the obtained symbol sequence onto physical resources for transmission.

[0244] It should be understood that detailed descriptions of specific channel coding, modulation, layer mapping, precoding, and frame rate matching can be found in the descriptions of existing schemes, and will not be repeated here.

[0245] 305. The second communication device acquires the received sequence and decodes the received sequence to obtain K information bits.

[0246] It is understandable that channel noise signals may be introduced during the transmission of the sequence sent by the transmitting end. For example, the sequence #1 sent by the first communication device may be different from the sequence #2 received by the second communication device. In this embodiment of the application, the method is described using the example of the second communication device obtaining the received sequence from the first communication device.

[0247] For example, the second communication device acquires a received sequence, which corresponds to K′ bits to be decoded, where K′ is a positive integer. The second communication device determines a first generator matrix and decodes the received sequence to obtain K information bits. The determination of the first generator matrix by the second communication device is similar to that by the first communication device; please refer to the detailed explanation in step 302 above.

[0248] Specifically, the second communication device decodes the received sequence, similar to the process in step 303 above where the first communication device encodes the K′ bits to be encoded. This can be achieved in the following ways:

[0249] Method 3

[0250] When K′=K+K P =M, and K P When it is not 0, the second communication device uses the first generating matrix and K. P The first padding bit is used to decode the received sequence to obtain K information bits. Alternatively, it can be understood that the second communication device decodes the received sequence based on the first generator matrix and K... P K filling bits are used to decode K′ bits to obtain K information bits.

[0251] For example, the second communication device determines K. P K filling bits are used to decode K′ bits to obtain K information bits. The following will illustrate this with an example. P The specific positions of the padding bits within the K′ bits to be decoded:

[0252] In one possible implementation, when d′=M, K P The padding bits are located after the K information bits in the K′ bits to be decoded. The second communication device will place the last K bits of the K′ bits to be decoded. P The bits to be encoded are determined as padding bits, and 0 or 1 is filled into the K bits. P K bits are to be decoded, and K' bits are decoded.

[0253] In one possible implementation, the second communication device determines K based on the first index table. P The positions of the padding bits and / or the positions of the K information bits in the bit sequence to be decoded. The bit sequence to be decoded includes K′ bits, and these bits correspond to rows in the first generator matrix.

[0254] It should be understood that the first index table is similar to the first index table described in step 303 above. For details, please refer to the description in step 303 above. It will not be repeated here.

[0255] As an example, the second communication device determines K based on the first index table. P The positions of the padding bits in the bit sequence to be decoded are determined by the second communication device based on the first K bits in the first index table. P Each index determines K. P The positions of the padding bits in the bit sequence to be decoded. Specifically, x1 first indices in the first index table precede x2 second indices in the first index table; these x1 first indices correspond to row x1 in the first generator matrix, which includes rows corresponding to the first type of sub-matrices; the x2 second indices correspond to row x2 in the first generator matrix, which includes rows corresponding to the second type of sub-matrices. For detailed descriptions of the first and second type of sub-matrices, please refer to the description in step 303 above.

[0256] As an example, the second communication device determines K based on the first index table. P The positions of the padding bits in the bit sequence to be decoded are determined by the second communication device based on the first K bits in the first index table. P Each index determines K. PThe positions of the padding bits in the bit sequence to be decoded. Specifically, the x3 third indices in the first index table precede the x4 fourth indices in the first index table. These x3 third indices correspond to the x3 row in the first generator matrix, which includes the row corresponding to the third type of sub-matrix. The x4 fourth indices correspond to the x4 row in the first generator matrix, which includes the row corresponding to the fourth type of sub-matrix. For a detailed description of the third and fourth type of sub-matrixes, please refer to the description in step 303 above.

[0257] As an example, the second communication device determines the positions of K information bits in the bit sequence to be decoded based on a first index table. Specifically, the second communication device determines the positions of the K information bits in the bit sequence to be decoded based on the first K indices of the first index table. Here, x2 second indices in the first index table precede the x1 first indices in the first index table. The second communication device determines the positions of the K information bits in the bit sequence to be decoded based on the first K indices of the first index table.

[0258] As an example, the second communication device determines the positions of K information bits in the bit sequence to be decoded based on a first index table. Specifically, the second communication device determines the positions of the K information bits in the bit sequence to be decoded based on the first K indices of the first index table. Here, the x4 fourth indices in the first index table precede the x3 third indices in the first index table. The second communication device determines the positions of the K information bits in the bit sequence to be decoded based on the first K indices of the first index table.

[0259] As an example, the second communication device determines K based on the first index table. P The positions of the padding bits and K information bits in the bit sequence to be decoded. Specifically, the first index x1 in the first index table precedes the second index x2, and the second communication device determines the positions of the first K bits in the first index table. P Each index determines K P The position of each padding bit in the bit sequence to be decoded is determined by the K information bits in the bit sequence to be decoded, based on the last K indices in the first index table; or, if x1 first indices in the first index table follow x2 second indices, the second communication device determines the position of each of the K information bits in the bit sequence to be decoded based on the last K indices in the first index table. P Each index determines K P The positions of the padding bits in the bit sequence to be decoded are determined based on the first K indices in the first index table, and the positions of the K information bits in the bit sequence to be decoded are determined.

[0260] As an example, the second communication device determines K based on the first index table. PThe positions of the padding bits and K information bits in the bit sequence to be decoded. Specifically, the x3 third indices in the first index table precede the x4 fourth indices, and the second communication device determines the positions based on the first K bits in the first index table. P Each index determines K P The positions of the padding bits in the bit sequence to be decoded are determined by the K information bits in the bit sequence to be decoded, based on the last K indices in the first index table; or, if the x3 third indices in the first index table are located after the x4 fourth indices, the second communication device determines the positions of the K information bits in the bit sequence to be decoded based on the last K indices in the first index table. P Each index determines K P The positions of the padding bits in the bit sequence to be decoded are determined based on the first K indices in the first index table, and the positions of the K information bits in the bit sequence to be decoded are determined.

[0261] In one possible implementation, the second communication device determines a second generation matrix based on the first generation matrix, and decodes K information bits based on the second generation matrix and K′ bits to be decoded. The method for determining the second generation matrix is ​​similar to the method used by the first communication device in step 303 above; a specific example can be found in the description of step 303 above.

[0262] For example, the second generating matrix is ​​determined based on the first K′ indices of the first index table, where the K′ rows of the first generating matrix corresponding to these first K′ indices constitute the second generating matrix. The first index table includes x1 first indices and x2 second indices, with the x1 first indices following the x2 second indices. The x1 first indices correspond to rows in the first type of submatrices of the first generating matrix, and the x2 second indices correspond to rows in the second type of submatrices of the first generating matrix. Alternatively, the first index table includes x3 third indices and x4 fourth indices, with the x3 third indices following the x4 fourth indices. The x3 third indices correspond to rows in the third type of submatrices of the first generating matrix, and the x4 fourth indices correspond to rows in the fourth type of submatrices of the first generating matrix.

[0263] For example, the second communication device can use the RM code decoding algorithm described above for decoding. For instance, using the Dumer algorithm, the second communication device enumerates all valid codeword bits and selects the value with the highest decoding likelihood as the return value for that position. Furthermore, when decoding the padding bits in the bit sequence to be decoded, the second communication device directly determines the value at that bit position, thereby significantly reducing the codeword space occupied during the decoding process.

[0264] Method 4

[0265] When K′=K<M, the second communication device decodes the received sequence according to the second generator matrix to obtain K information bits. Alternatively, it can be understood that the second communication device decodes K′ bits to be decoded according to the second generator matrix to obtain K information bits.

[0266] For example, the second communication device determines that K′ bits to be decoded correspond to K information bits, where K′ = K. The second communication device decodes the K information bits based on the second generator matrix and the K′ bits to be decoded. The method for determining the second generator matrix will be described below as an example:

[0267] In one possible implementation, the second generating matrix comprises K′ rows, which are the first K′ rows of the first generating matrix.

[0268] In one possible implementation, the second generating matrix is ​​formed by the K′ rows of the first generating matrix corresponding to the first K′ indices in the first index table. The first index table includes x1 first indices and x2 second indices, where the x1 first indices follow the x2 second indices; in other words, the x2 second indices precede the x1 first indices. Alternatively, the first index table includes x3 third indices and x4 fourth indices, where the x3 third indices follow the x4 fourth indices; in other words, the x4 fourth indices precede the x3 third indices.

[0269] The above is a detailed description of the channel coding or decoding method provided in this application.

[0270] It should be understood that the second communication device determines the second generating matrix in a similar way to the first communication device determining the second generating matrix in Method 2 above. For details, please refer to the description in Method 2 above.

[0271] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes described above do not imply a specific order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0272] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0273] It is also understood that, in the above-described method embodiments, the methods and operations implemented by the device (first communication device or second communication device) can also be implemented by components of the device (e.g., chips or circuits), without limitation.

[0274] The communication device provided in this application is described below.

[0275] Figure 6 This is a schematic structural diagram of the communication device 600 provided in this application. The communication device 600 can be an encoding-side device (e.g., a first communication device), or it can be a device applied to the encoding-side device that can implement the corresponding functions of the encoding-side device in the method embodiments of this application, such as a chip, processor, or circuit. Alternatively, the communication device 600 can be a decoding-side device (or a second communication device), or it can be a device applied to the decoding-side device that can implement the corresponding functions of the decoding-side device in the method embodiments of this application, such as a chip, processor, or circuit.

[0276] Optionally, the communication device 600 includes a processing module 601. The processing module can be a processor, a processing board, a processing unit, or a processing device, etc. When the communication device 600 is an encoding-side device or a device applied to an encoding-side device, the processing module 601 is used to determine a first generator matrix of the RM code based on parameters m and r. The first generator matrix includes M rows and N columns, where K < M. N=2 m m, r, M, and N are all positive integers. Processing module 601 is further configured to encode a first codeword sequence based on the first generator matrix and K′ bits to be encoded, wherein the K′ bits to be encoded include K information bits and K… P 1 padding bit, K′=M, K P =MK; or, the processing module 601 is further configured to encode the second codeword sequence based on the second generator matrix and K′ bits to be encoded, wherein the second generator matrix is ​​composed of K′ rows from the first generator matrix, K′ = K, and the second generator matrix includes K′ rows and N columns. For details of the process, please refer to the detailed description of the corresponding steps in the method embodiment; it will not be repeated here.

[0277] When the communication device 600 is a decoding-side device or a device applied to a decoding-side device, the processing module 601 is used to determine a first generator matrix of the RM code based on parameters m and r. The first generator matrix includes M rows and N columns. N = 2m, where m, r, M, and N are all positive integers. When K′ = K + K P =M, and K P When the value is not 0, the processing module 601 is also used to determine the value based on the first generator matrix and K. P The processing module 601 decodes the received sequence using a padding bit to obtain K information bits; or, when K′=K<M, the processing module 601 is further configured to decode the received sequence according to the second generating matrix to obtain K information bits. The second generating matrix is ​​composed of K′ rows from the first generating matrix, and includes K′ rows and N columns, etc. For details of the process, please refer to the detailed description of the corresponding steps in the method embodiment, which will not be repeated here.

[0278] Optionally, the communication device 600 further includes a communication module 602, which may also be referred to as a transceiver module, transceiver, transceiver unit, or transceiver device, etc., for performing receiving (or input) and / or sending (or output) operations. For example, when the communication device 600 is an encoding-side device or a device applied to an encoding-side device, the communication module 602 can be used to acquire a bit sequence to be encoded (e.g., K information bits) and transmit the bit sequence to be encoded to the processing module 601; and output the encoded sequence obtained by the processing module 601. Similarly, when the communication device 600 is a decoding-side device or a device applied to a decoding-side device, the communication module 602 can be used to receive information to be decoded (e.g., a received sequence) and send the received sequence to the processing module 601; and output the decoded bit sequence obtained by the processing module 601 decoding the received sequence.

[0279] It should be understood that the aforementioned communication module and / or processing module can be implemented through virtual modules. For example, the processing module can be implemented through software functional units or virtual devices, and the communication module can be implemented through software functions or virtual devices. Alternatively, the processing module or communication module can also be implemented through physical devices, such as chips / circuits (e.g., integrated circuits or logic circuits). The communication module can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module is an integrated processor, microprocessor, or circuit (e.g., integrated circuits, logic circuits).

[0280] The module division in this application is illustrative and represents only one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in the various examples of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware, as software functional modules, or a combination of hardware and software.

[0281] Figure 7This is a schematic structural diagram of another communication device provided in this application. The communication device 700 can be used to implement the functions of any communication device (e.g., an encoding-side device or a decoding-side device) in the communication system described in the foregoing examples. The communication device 700 may include at least one processor 710. Optionally, the processor 710 (or processing device) is coupled to a memory, which may be located within the communication device, integrated with the processor, or located outside the communication device. For example, the communication device 700 may also include at least one memory 720. The memory 720 stores computer programs, instructions, or data necessary for implementing any of the above method embodiments; the processor 710 may execute the computer programs, instructions, or data stored in the memory 720 to perform the corresponding functions of the encoding-side device or decoding-side device in any of the above embodiments.

[0282] Optionally, the communication device 700 may further include a communication interface 730, through which the communication device 700 can interact with other devices. For example, the communication interface 730 may be a transceiver, circuit, bus, module, pin, or other type of communication interface. When the communication device 700 is a chip-based device or circuit, the communication interface 730 may also be an input / output circuit, capable of inputting information (or receiving information) and / or outputting information (or sending information). The processor may be an integrated circuit or logic circuit, etc., and the processor can determine the output information based on the input information.

[0283] The coupling in this application refers to indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. The processor 710 may operate in conjunction with the memory 720 and the communication interface 730. This application does not limit the connection medium between the processor 710, the memory 720, and the communication interface 730.

[0284] Figure 8 This is a schematic structural diagram of the chip provided in this application. Chip 830 includes circuit 801 and communication interface 802. Circuit 801 can be a logic circuit, integrated circuit, etc., and communication interface 802 can also be called input / output circuit, input / output interface, interface circuit, etc., which can input information (or receive information) or output information (or send information). Chip 830 can execute the methods executed by the encoding-side device or decoding-side device in the various embodiments of this application.

[0285] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause operations and / or processes performed by a first communication device or a second communication device in the various method embodiments of this application to be executed.

[0286] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the first communication device or the second communication device in the various method embodiments of this application are executed.

[0287] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, so that operations and / or processes performed by a first communication device or a second communication device in any method embodiment are executed. Further, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Further, the chip may also include the memory.

[0288] This application provides a communication system, including a first communication device and a second communication device in the above method embodiments.

[0289] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0290] In the embodiments of this application, "instruction" can include direct instruction, indirect instruction, explicit instruction, and implicit instruction. When describing a certain instruction information for instructing A, it can be understood that the instruction information carries A, which can be a direct instruction to A or an indirect instruction to A. Indirect instruction can refer to directly instructing B through the instruction information, and the correspondence between B and A, to achieve the purpose of instructing A through the instruction information. The correspondence between B and A can be predefined by the protocol, pre-stored, or obtained through configuration between network elements.

[0291] The processor in this application embodiment has signal processing capabilities and can be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in this application can be directly implemented by the hardware processor, or implemented by a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0292] In the embodiments of this application, the memory can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0293] The technical solutions provided in this application can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal device, an access network device, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media, etc.

[0294] In the embodiments of this application, "at least one" refers to one or more items. "More than one" means two or more items. "And / or" is used to describe the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0295] The term "comprising" and any variations thereof used in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0296] In this application, examples may reference each other without logical contradiction. For example, methods and / or terms between method embodiments may reference each other, functions and / or terms between device embodiments may reference each other, and functions and / or terms between device examples and method examples may reference each other.

[0297] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0298] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0299] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0300] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0301] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A communication method, characterized in that, include: Obtain K information bits, where K is a positive integer; The first generator matrix of the RM code is determined based on parameters m and r. The first generator matrix consists of M rows and N columns, where K < M. N=2 m m, r, M and N are all positive integers; in, The first codeword sequence is obtained by encoding the first generator matrix and K′ bits to be encoded, wherein the K′ bits to be encoded include the K information bits and K P 1 padding bit, K′=M, K P =MK; or, The second codeword sequence is obtained by encoding the second generator matrix and the K′ bits to be encoded. The second generator matrix is ​​composed of K′ rows from the first generator matrix, where K′ = K, and the second generator matrix includes K′ rows and N columns.

2. The method according to claim 1, characterized in that, The first generating matrix satisfies: Wherein, G(m,r) represents the first generating matrix.

3. The method according to claim 2, characterized in that, The G(m,r) consists of a submatrix satisfying a first condition and a matrix of all zeros, wherein the first condition is for the submatrix G(a,b) in G(m,r) such that a = b or b = 0.

4. The method according to any one of claims 1 to 3, characterized in that, When K′=M, the K P The padding bits are located after the K information bits in the K′ bits to be encoded; When K′=K, the K′ row in the second generating matrix is ​​the first K′ row in the first generating matrix.

5. The method according to any one of claims 1 to 3, characterized in that, The method further includes: Determine K according to the first index table. P The positions of the padding bits in the bit sequence to be encoded and / or the positions of the K information bits in the bit sequence to be encoded, wherein the bit sequence to be encoded includes the K′ bits to be encoded, and the bits to be encoded in the bit sequence to be encoded correspond to the rows in the first generator matrix. The first index table includes X indices, which correspond one-to-one with X rows in the first generated matrix, where X is a positive integer less than or equal to M.

6. The method according to claim 5, characterized in that, The first generated matrix includes a first type of submatrix and a second type of submatrix. The first type of submatrix is ​​an identity matrix, and the second type of submatrix is ​​an all-1 matrix. The second type of submatrix includes 1 row and s columns, where s is an integer greater than or equal to 2.

7. The method according to claim 5 or 6, characterized in that, The first generated matrix includes a third type of submatrix and a fourth type of submatrix. The third type of submatrix is ​​a submatrix obtained by performing the first operation T1 times on the first generated matrix, where T1 is an integer greater than or equal to a first threshold. The fourth type of submatrix is ​​a submatrix obtained by performing the first operation T2 times on the first generated matrix, where T2 is an integer less than the first threshold. The third type of submatrix and the fourth type of submatrix are matrices that satisfy a first condition, which includes: in matrix (a, b), a = b, or b = 0, where a is a positive integer. The first operation involves splitting the matrix (x, y) that does not satisfy the first condition into two first sub-matrices (x-1, y), one second sub-matrix (x-1, y-1), and a matrix of all zeros. The two first sub-matrices (x-1, y) are located in the first position of the matrix (x, y). The zero-matrix is ​​located at the bottom left corner of the matrix (x, y), and has the same number of rows as the second submatrix. The second submatrix (x-1, y-1) is located at the bottom right corner of the matrix (x, y), and is located at the last row of the matrix (x, y). Line 2 ( x- 1) List; When the first generating matrix satisfies the first condition and r = 0, the number of times the first operation is processed in each row of the first generating matrix is ​​0. If the first generating matrix does not satisfy the first condition, the rows corresponding to the third type of sub-matrix and the rows corresponding to the fourth type of sub-matrix are determined based on the first generating matrix and the first operation. Wherein, the first generating matrix is ​​denoted as G(m, r), and the first operation executed for the first time in the first generating matrix is ​​performed on G(m, r), and the first operation executed for the first time includes: Performing the first operation on G(m, r) yields two first sub-generating matrices (m-1, r), one second sub-generating matrix (m-1, r-1), and a matrix of all zeros. If the first sub-generating matrix (m-1, r) satisfies the first condition, the first operation is not performed on the first sub-generating matrix (m-1, r); The second sub-generating matrix (m-1, r-1) satisfies the first condition, so the first operation is not performed on the second sub-generating matrix (m-1, r-1); If the first sub-generating matrix (m-1, r) does not satisfy the first condition, the first operation is continued to be performed on the first sub-generating matrix (m-1, r); If the second sub-generating matrix (m-1, r-1) does not satisfy the first condition, the first operation is continued to be performed on the second sub-generating matrix (m-1, r-1).

8. The method according to claim 6, characterized in that, The K is determined according to the first index table. P The positions of the padding bits in the bit sequence to be encoded include: According to the first K in the first index table P An index is used to determine the K. P The positions of the padding bits in the bit sequence to be encoded. Wherein, the X indices include x1 first indices and x2 second indices, and the x1 first indices are located before the x2 second indices in the first index table. The x1 first indices correspond to the x1 row in the first generated matrix, and the x2 second indices correspond to the x2 row in the first generated matrix. The x1 row includes the row corresponding to the first type of sub-matrix, and the x2 row includes the row corresponding to the second type of sub-matrix. x1 and x2 are both positive integers.

9. The method according to claim 7, characterized in that, The K is determined according to the first index table. P The positions of the padding bits in the bit sequence to be encoded include: According to the first K in the first index table P An index is used to determine the K. P The positions of the padding bits in the bit sequence to be encoded. Wherein, the X indices include x3 third indices and x4 fourth indices, and the x3 third indices are located before the x4 fourth indices in the first index table. The x3 third indices correspond to the x3 row in the first generating matrix, and the x4 fourth indices correspond to the x4 row in the first generating matrix. The x3 row includes the row corresponding to the third type of sub-matrix, and the x4 row includes the row corresponding to the fourth type of sub-matrix. x3 and x4 are both positive integers.

10. The method according to claim 6, characterized in that, Determining the positions of the K information bits in the bit sequence to be encoded according to the first index table includes: Based on the first K indices in the first index table, determine the positions of the K information bits in the bit sequence to be encoded. Wherein, the X indices include x1 first indices and x2 second indices, and the x2 second indices are located before the x1 first indices in the first index table. The x1 first indices correspond to the x1 row in the first generated matrix, and the x2 second indices correspond to the x2 row in the first generated matrix. The x1 row includes the row corresponding to the first type of sub-matrix, and the x2 row includes the row corresponding to the second type of sub-matrix. x1 and x2 are both positive integers.

11. The method according to claim 7, characterized in that, Determining the positions of the K information bits in the bit sequence to be encoded according to the first index table includes: Based on the first K indices in the first index table, determine the positions of the K information bits in the bit sequence to be encoded. Wherein, the X indices include x3 third indices and x4 fourth indices, and the x4 fourth indices are located before the x3 third indices in the first index table. The x3 third indices correspond to the x3 row in the first generating matrix, and the x4 fourth indices correspond to the x4 row in the first generating matrix. The x3 row includes the row corresponding to the third type of sub-matrix, and the x4 row includes the row corresponding to the fourth type of sub-matrix. x3 and x4 are both positive integers.

12. The method according to claim 6, characterized in that, The K is determined according to the first index table. P The positions of the padding bits in the bit sequence to be encoded and the positions of the K information bits in the bit sequence to be encoded include: According to the first K in the first index table P An index is used to determine the K. P The positions of the padding bits in the bit sequence to be encoded; Based on the last K indices in the first index table, determine the positions of the K information bits in the bit sequence to be encoded. Wherein, the X indexes include x1 first indexes and x2 second indexes, and the x1 first indexes are located before the x2 second indexes in the first index table; or; According to the last K in the first index table P An index is used to determine the K. P The position of each padding bit in the bit sequence to be encoded Based on the first K indices in the first index table, determine the positions of the K information bits in the bit sequence to be encoded. The X indices include x1 first indices and x2 second indices, and the x2 second indices precede the x1 first indices in the first index table. Wherein, the x1 first indices correspond to the x1 row in the first generated matrix, the x2 second indices correspond to the x2 row in the first generated matrix, the x1 row includes the row corresponding to the first type of sub-matrix, the x2 row includes the row corresponding to the second type of sub-matrix, and x1 and x2 are both positive integers.

13. The method according to claim 7, characterized in that, The K is determined according to the first index table. P The positions of the padding bits in the bit sequence to be encoded and the positions of the K information bits in the bit sequence to be encoded include: According to the first K in the first index table P An index is used to determine the K. P The positions of the padding bits in the bit sequence to be encoded; Based on the last K indices in the first index table, determine the positions of the K information bits in the bit sequence to be encoded. Wherein, the X indexes include x3 third indexes and x4 fourth indexes, and the x3 third indexes are located before the x4 fourth indexes in the first index table; or; According to the last K in the first index table P An index is used to determine the K. P The position of each padding bit in the bit sequence to be encoded Based on the first K indices in the first index table, determine the positions of the K information bits in the bit sequence to be encoded. The X indices include x3 third indices and x4 fourth indices, and the x4 fourth indices precede the x3 third indices in the first index table. Wherein, the x3 third indices correspond to the x3 row in the first generating matrix, the x4 fourth indices correspond to the x4 row in the first generating matrix, the x3 row includes the row corresponding to the third type of sub-matrix, the x4 row includes the row corresponding to the fourth type of sub-matrix, and x3 and x4 are both positive integers.

14. The method according to claim 6, characterized in that, When the second codeword sequence is obtained by encoding based on the second generator matrix and the K′ bits to be encoded, the second generator matrix is ​​composed of the K′ rows of the first generator matrix corresponding to the first K′ indices in the first index table. Wherein, the X indices include x1 first indices and x2 second indices, and the x2 second indices are located before the x1 first indices in the first index table. The x1 first indices correspond to the x1 row in the first generated matrix, and the x2 second indices correspond to the x2 row in the first generated matrix. The x1 row includes the row corresponding to the first type of sub-matrix, and the x2 row includes the row corresponding to the second type of sub-matrix. x1 and x2 are both positive integers.

15. The method according to claim 7, characterized in that, When the second codeword sequence is obtained by encoding based on the second generator matrix and the K′ bits to be encoded, the second generator matrix is ​​composed of the K′ rows of the first generator matrix corresponding to the first K′ indices in the first index table. Wherein, the X indices include x3 third indices and x4 fourth indices, and the x4 fourth indices are located before the x3 third indices in the first index table. The x3 third indices correspond to the x3 row in the first generating matrix, and the x4 fourth indices correspond to the x4 row in the first generating matrix. The x3 row includes the row corresponding to the third type of sub-matrix, and the x4 row includes the row corresponding to the fourth type of sub-matrix. x3 and x4 are both positive integers.

16. The method according to any one of claims 1 to 15, characterized in that, When the first codeword sequence is obtained by encoding according to the first generator matrix and the K′ bits to be encoded, the K P Each padding bit can be either 1 or 0.

17. The method according to claim 16, characterized in that, In the K P When each padding bit is 1, the method further includes: Based on the first generating matrix, a third generating matrix is ​​determined, wherein the third generating matrix is ​​derived from the K... P The K bits corresponding to the first generated matrix P Line composition; The third codeword sequence is determined based on the first codeword sequence and the third generator matrix; Send the third codeword sequence.

18. The method according to claim 17, characterized in that, The third codeword sequence c2 satisfies: Where c1 represents the first codeword sequence, This represents the third generating matrix.

19. A communication method, characterized in that, include: Obtain the received sequence, which corresponds to K′ bits to be decoded, where K′ is a positive integer; The first generator matrix of the RM code is determined based on parameters m and r. The first generator matrix consists of M rows and N columns. N=2 m m, r, M and N are all positive integers; in, When K′=K+K P =M, and K P When it is not 0, according to the first generating matrix and K P The received sequence is decoded using 1 padding bit to obtain K information bits; or... When K′=K<M, K information bits are obtained by decoding according to the second generating matrix and the received sequence. The second generating matrix is ​​composed of K′ rows from the first generating matrix and includes K′ rows and N columns.

20. The method according to claim 19, characterized in that, The first generating matrix satisfies: Wherein, G(m,r) represents the first generating matrix.

21. The method according to claim 20, characterized in that, The G(m,r) consists of a submatrix satisfying a first condition and a matrix of all zeros, wherein the first condition is for the submatrix G(a,b) in G(m,r) such that a = b or b = 0.

22. The method according to any one of claims 19 to 21, characterized in that, When K′=M, the K P The padding bits are located after the K information bits in the K′ bits to be decoded; When K′=K, the K′ row in the second generating matrix is ​​the first K′ row in the first generating matrix.

23. The method according to any one of claims 19 to 21, characterized in that, The method further includes: Determine K according to the first index table. P The positions of the padding bits in the bit sequence to be decoded and / or the positions of the K information bits in the bit sequence to be decoded, wherein the bit sequence to be decoded includes the K′ bits to be decoded, and the bits to be decoded in the bit sequence to be decoded correspond to the rows in the first generator matrix. The first index table includes X indices, which correspond one-to-one with X rows in the first generated matrix, where X is a positive integer less than or equal to M.

24. The method according to claim 23, characterized in that, The first generated matrix includes a first type of submatrix and a second type of submatrix. The first type of submatrix is ​​an identity matrix, and the second type of submatrix is ​​an all-1 matrix. The second type of submatrix includes 1 row and s columns, where s is an integer greater than or equal to 2.

25. The method according to claim 22 or 24, characterized in that, The first generated matrix includes a third type of submatrix and a fourth type of submatrix. The third type of submatrix is ​​a submatrix obtained by performing the first operation T1 times on the first generated matrix, where T1 is an integer greater than or equal to a first threshold. The fourth type of submatrix is ​​a submatrix obtained by performing the first operation T2 times on the first generated matrix, where T2 is an integer less than the first threshold. The third type of submatrix and the fourth type of submatrix are matrices that satisfy a first condition, which includes: in matrix (a, b), a = b, or b = 0, where a is a positive integer. The first operation involves splitting the matrix (x, y) that does not satisfy the first condition into two first sub-matrices (x-1, y), one second sub-matrix (x-1, y-1), and a matrix of all zeros. The two first sub-matrices (x-1, y) are located in the first position of the matrix (x, y). The zero-matrix is ​​located at the bottom left corner of the matrix (x, y), and has the same number of rows as the second submatrix. The second submatrix (x-1, y-1) is located at the bottom right corner of the matrix (x, y), and is located at the last row of the matrix (x, y). Line 2 (x-1) List; When the first generating matrix satisfies the first condition and r = 0, the number of times the first operation is processed in each row of the first generating matrix is ​​0. If the first generating matrix does not satisfy the first condition, the rows corresponding to the third type of sub-matrix and the rows corresponding to the fourth type of sub-matrix are determined based on the first generating matrix and the first operation. Wherein, the first generating matrix is ​​denoted as G(m, r), and the first operation executed for the first time in the first generating matrix is ​​performed on G(m, r), and the first operation executed for the first time includes: Performing the first operation on G(m, r) yields two first sub-generating matrices (m-1, r), one second sub-generating matrix (m-1, r-1), and a matrix of all zeros. If the first sub-generating matrix (m-1, r) satisfies the first condition, the first operation is not performed on the first sub-generating matrix (m-1, r); The second sub-generating matrix (m-1, r-1) satisfies the first condition, so the first operation is not performed on the second sub-generating matrix (m-1, r-1); If the first sub-generating matrix (m-1, r) does not satisfy the first condition, the first operation is continued to be performed on the first sub-generating matrix (m-1, r); If the second sub-generating matrix (m-1, r-1) does not satisfy the first condition, the first operation is continued to be performed on the second sub-generating matrix (m-1, r-1).

26. The method according to claim 24, characterized in that, The K is determined according to the first index table. P The positions of the padding bits in the bit sequence to be decoded include: According to the first K in the first index table P An index is used to determine the K. P The positions of the padding bits in the sequence of bits to be decoded. Wherein, the X indices include x1 first indices and x2 second indices, and the x1 first indices are located before the x2 second indices in the first index table. The x1 first indices correspond to the x1 row in the first generated matrix, and the x2 second indices correspond to the x2 row in the first generated matrix. The x1 row includes the row corresponding to the first type of sub-matrix, and the x2 row includes the row corresponding to the second type of sub-matrix. x1 and x2 are both positive integers.

27. The method according to claim 25, characterized in that, The K is determined according to the first index table. P The positions of the padding bits in the bit sequence to be decoded include: According to the first K in the first index table P An index is used to determine the K. P The positions of the padding bits in the sequence of bits to be decoded. Wherein, the X indices include x3 third indices and x4 fourth indices, and the x3 third indices are located before the x4 fourth indices in the first index table. The x3 third indices correspond to the x3 row in the first generating matrix, and the x4 fourth indices correspond to the x4 row in the first generating matrix. The x3 row includes the row corresponding to the third type of sub-matrix, and the x4 row includes the row corresponding to the fourth type of sub-matrix. x3 and x4 are both positive integers.

28. The method according to claim 24, characterized in that, Determining the positions of the K information bits in the sequence of bits to be decoded according to the first index table includes: Based on the first K indices in the first index table, determine the positions of the K information bits in the sequence of bits to be decoded. Wherein, the X indices include x1 first indices and x2 second indices, and the x2 second indices are located before the x1 first indices in the first index table. The x1 first indices correspond to the x1 row in the first generated matrix, and the x2 second indices correspond to the x2 row in the first generated matrix. The x1 row includes the row corresponding to the first type of sub-matrix, and the x2 row includes the row corresponding to the second type of sub-matrix. x1 and x2 are both positive integers.

29. The method according to claim 25, characterized in that, Determining the positions of the K information bits in the sequence of bits to be decoded according to the first index table includes: Based on the first K indices in the first index table, determine the positions of the K information bits in the sequence of bits to be decoded. Wherein, the X indices include x3 third indices and x4 fourth indices, and the x4 fourth indices are located before the x3 third indices in the first index table. The x3 third indices correspond to the x3 row in the first generating matrix, and the x4 fourth indices correspond to the x4 row in the first generating matrix. The x3 row includes the row corresponding to the third type of sub-matrix, and the x4 row includes the row corresponding to the fourth type of sub-matrix. x3 and x4 are both positive integers.

30. The method according to claim 24, characterized in that, The K is determined according to the first index table. P The positions of the padding bits in the bit sequence to be decoded and the positions of the K information bits in the bit sequence to be decoded include: According to the first K in the first index table P An index is used to determine the K. P The positions of the padding bits in the sequence of bits to be decoded; Based on the last K indices in the first index table, determine the positions of the K information bits in the sequence of bits to be decoded. Wherein, the X indexes include x1 first indexes and x2 second indexes, and the x1 first indexes are located before the x2 second indexes in the first index table; or; According to the last K in the first index table P An index is used to determine the K. P The positions of the padding bits in the sequence of bits to be decoded. Based on the first K indices in the first index table, determine the positions of the K information bits in the sequence of bits to be decoded. The X indices include x1 first indices and x2 second indices, and the x2 second indices precede the x1 first indices in the first index table. Wherein, the x1 first indices correspond to the x1 row in the first generated matrix, the x2 second indices correspond to the x2 row in the first generated matrix, the x1 row includes the row corresponding to the first type of sub-matrix, the x2 row includes the row corresponding to the second type of sub-matrix, and x1 and x2 are both positive integers.

31. The method according to claim 25, characterized in that, The K is determined according to the first index table. P The positions of the padding bits in the bit sequence to be decoded and the positions of the K information bits in the bit sequence to be decoded include: According to the first K in the first index table P An index is used to determine the K. P The positions of the padding bits in the sequence of bits to be decoded; Based on the last K indices in the first index table, determine the positions of the K information bits in the sequence of bits to be decoded. Wherein, the X indexes include x3 third indexes and x4 fourth indexes, and the x3 third indexes are located before the x4 fourth indexes in the first index table; or; According to the last K in the first index table P An index is used to determine the K. P The positions of the padding bits in the sequence of bits to be decoded. Based on the first K indices in the first index table, determine the positions of the K information bits in the sequence of bits to be decoded. The X indices include x3 third indices and x4 fourth indices, and the x4 fourth indices precede the x3 third indices in the first index table. Wherein, the x3 third indices correspond to the x3 row in the first generating matrix, the x4 fourth indices correspond to the x4 row in the first generating matrix, the x3 row includes the row corresponding to the third type of sub-matrix, the x4 row includes the row corresponding to the fourth type of sub-matrix, and x3 and x4 are both positive integers.

32. The method according to claim 24, characterized in that, When decoding the K information bits based on the second generator matrix and the K' bits to be decoded, the second generator matrix is ​​composed of the K' rows of the first generator matrix corresponding to the first K' indices in the first index table. Wherein, the X indices include x1 first indices and x2 second indices, and the x2 second indices are located before the x1 first indices in the first index table. The x1 first indices correspond to the x1 row in the first generated matrix, and the x2 second indices correspond to the x2 row in the first generated matrix. The x1 row includes the row corresponding to the first type of sub-matrix, and the x2 row includes the row corresponding to the second type of sub-matrix. x1 and x2 are both positive integers.

33. The method according to claim 25, characterized in that, When decoding the K information bits based on the second generator matrix and the K' bits to be decoded, the second generator matrix is ​​composed of the K' rows of the first generator matrix corresponding to the first K' indices in the first index table. Wherein, the X indices include x3 third indices and x4 fourth indices, and the x4 fourth indices are located before the x3 third indices in the first index table. The x3 third indices correspond to the x3 row in the first generating matrix, and the x4 fourth indices correspond to the x4 row in the first generating matrix. The x3 row includes the row corresponding to the third type of sub-matrix, and the x4 row includes the row corresponding to the fourth type of sub-matrix. x3 and x4 are both positive integers.

34. The method according to any one of claims 19 to 33, characterized in that, Based on the first generating matrix and the K P When the K' bits to be decoded are decoded using the padding bits to obtain the K information bits, the K... P Each padding bit can be either 1 or 0.

35. A communication device, characterized in that, The communication device includes at least one processor, the at least one processor being configured to cause the method of any one of claims 1-18 to be performed by the communication device, or the at least one processor being configured to cause the communication device to perform the method of any one of claims 19-34.

36. A chip or chip system, characterized in that, The chip or chip system includes: At least one processor and an interface, the at least one processor being configured to call and execute instructions from the interface, such that when the at least one processor executes the instructions, the method as claimed in any one of claims 1-18 is executed, or the method as claimed in any one of claims 19-34 is executed.

37. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, implement the method as described in any one of claims 1-34.

38. A computer program product, characterized in that, The computer program product includes a computer program that, when run on a computer, causes the method as described in any one of claims 1-18 to be performed, or causes the method as described in any one of claims 19-34 to be performed.

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