FPGA-based multi-band multi-channel signal adaptive selection and output system and method

Abstract

This invention belongs to the field of FPGA digital signal processing and discloses an FPGA-based multi-band, multi-channel adaptive signal selection and output system and method. The system includes a signal acquisition and calibration module, a threshold detection and filtering module, a channel contention and arbitration module, and a multi-band output strategy control module. After receiving digital signals from multiple channels in multiple bands, the system performs digital offset calibration on a channel-by-channel basis. Hysteresis-based validity determination is performed based on signal and noise thresholds to obtain the determined channel signals. Then, within the same band, the system identifies the candidate maximum signal, and confirms the winning channel when its difference relative to other channels meets the fluctuation threshold, generating a channel selection signal and a bandwidth-preserving signal. Finally, based on the operating mode configuration information, the winning channel information, and the bandwidth-preserving signal, one signal is selected for output. This scheme can reduce misselection caused by channel amplitude deviation, noise floor, and critical fluctuations, and supports switching to another effective band when the output band is unavailable.

Description

Technical Field

[0001] This invention belongs to the field of electronic communication and signal processing technology, and particularly relates to a multi-band, multi-channel signal adaptive selection and output system and method based on FPGA. Background Technology

[0002] In systems such as wireless communication, radar detection, and electronic countermeasures, the receiving front end may simultaneously receive signals from multiple bands and channels. The timing, duration, and amplitude variations of signals from different bands are not entirely consistent, and subsequent demodulation, measurement, or triggering units typically require a continuous, stable, and clearly defined digital signal. Due to its parallel processing capabilities and deterministic timing, FPGAs are often used to perform real-time signal selection at the front end of the receiving link.

[0003] Existing multi-channel signal selection schemes can usually complete channel acquisition, threshold judgment, or fixed rule output within a single band, but in complex electromagnetic environments or scenarios where multiple receiving links work together, the following problems may still occur.

[0004] 1. Differences exist in the analog front-end devices, amplification links, and analog-to-digital conversion links of different receiving links. When the same external signal enters different channels, the digital sampled values ​​may carry link deviations, leading to inconsistencies in the basis for subsequent amplitude comparisons.

[0005] 2. When the received signal is near the noise floor or the amplitudes of multiple channels are similar, the effective state of the channels and the object of the maximum amplitude are prone to change back and forth within adjacent decision periods. This change will cause the output source to jump frequently, affecting the continuous processing of the same signal by the subsequent stages.

[0006] 3. When multiple bands are input simultaneously, methods such as fixed priority, fixed polling order, or simply selecting one signal based on instantaneous amplitude are insufficient to promptly reflect whether a stable, outputtable signal exists for each band. If the currently available output band is unavailable, the output link may experience pauses, interruptions, or switching lags.

[0007] 4. Applications such as radar, satellite communication, and electronic warfare typically require signal selection logic to be completed within the FPGA with low latency. Relying solely on backend software judgment or manual configuration switching is insufficient to meet the requirements for real-time output and state maintenance.

[0008] Therefore, a multi-band, multi-channel signal selection output scheme suitable for implementation within an FPGA is needed, which provides a stable basis for comparing channel amplitudes and enables cross-band output strategies to select one signal output based on the confirmed winning channel status. Summary of the Invention

[0009] The purpose of this invention is to address the problem of unstable channel selection in multi-band, multi-channel FPGA signal selection and output scenarios, and to provide an FPGA-based adaptive selection and output system and method for multi-band, multi-channel signals. The aforementioned instability mainly stems from inconsistent channel amplitudes, noise floor, critical fluctuations, and a lack of effective state data for cross-band output.

[0010] To achieve the above-mentioned objectives, the technical solution provided by this invention includes: An FPGA-based multi-band, multi-channel adaptive signal selection and output system includes: The signal acquisition and calibration module is used to receive digital signals from multiple channels in multiple bands and perform digital offset calibration on a channel-by-channel basis. The threshold detection and filtering module is used to perform hysteresis validity determination on each channel signal after calibration based on the signal threshold and noise threshold, and obtain the determined channel signal. The channel competition and arbitration module is used to determine the candidate maximum signal among the determined channel signals in the same band, and to confirm the winning channel when the difference between the candidate maximum signal and other channel signals in the same band meets the fluctuation threshold, and to generate a channel selection signal and a width preservation signal to characterize that the winning channel is in an effective holding state. The multi-band output strategy control module is used to select one signal output based on the working mode configuration information, the winning channel information of different bands, and the bandwidth preservation signal.

[0011] Preferably, the digital offset calibration includes: configuring a digital offset for each channel, and performing an addition or subtraction calibration operation between the digital offset and the digital sample value of the channel configured with the digital offset, so as to compensate for the inconsistency of the amplitude of each channel.

[0012] Preferably, the hysteresis validity determination includes: retaining the channel signal amplitude when the channel signal amplitude is higher than the signal threshold, and suppressing the channel signal amplitude to a preset minimum value when the channel signal amplitude is lower than the noise threshold.

[0013] Preferably, the channel competition and arbitration module compares the candidate maximum signal with the channel signals in the same band other than the candidate maximum signal, and confirms the channel where the candidate maximum signal is located as the winning channel when all differences meet the fluctuation threshold.

[0014] Preferably, the bandwidth preservation signal is triggered by the valid determination result of the winning channel and remains valid while the preset holding condition is met. The multi-band output strategy control module determines whether the band to which the bandwidth preservation signal belongs has an output winning channel based on the valid state of the bandwidth preservation signal.

[0015] Preferably, the output strategy defined by the operating mode configuration information includes at least one of a single-band priority output mode, a maximum value output mode, and a polling output mode configured based on the number of outputs. When the bandwidth-preserving signal of the current output band is invalid and the bandwidth-preserving signal of another band is valid, the multi-band output strategy control module selects the winning channel signal of the other band for output.

[0016] This invention also provides a method for adaptive selection and output of multi-band, multi-channel signals based on FPGA, comprising: It receives digital signals from multiple channels across multiple bands and performs digital offset calibration for each channel. Hysteresis validity determination is performed on each channel signal after calibration based on signal threshold and noise threshold to obtain the determined channel signal; Within the same band, a candidate maximum signal is determined among the channel signals after the judgment, and the winning channel is confirmed when the difference between the candidate maximum signal and other channel signals within the same band meets the fluctuation threshold. A channel selection signal and a width-preserving signal are generated to characterize that the winning channel is in an effective holding state. Based on the operating mode configuration information, the winning channel information for different bands, and the bandwidth preservation signal, select one signal output.

[0017] Preferably, the hysteresis validity determination includes: retaining the channel signal amplitude when the channel signal amplitude is higher than the signal threshold, and suppressing the channel signal amplitude to a preset minimum value when the channel signal amplitude is lower than the noise threshold.

[0018] Preferably, confirming the winning channel includes: comparing the candidate maximum signal with the channel signals other than the candidate maximum signal in the same band using difference values, and confirming the channel containing the candidate maximum signal as the winning channel when all differences meet the fluctuation threshold.

[0019] Preferably, when the working mode configuration information defines a polling output mode, the effective number of bandwidth-preserving signals is counted according to a preset number of outputs for different bands, and the output band is switched after the preset number of outputs is reached. When the bandwidth-preserving signal of the output band is invalid and the bandwidth-preserving signal of another band is valid, the winning channel signal of the other band is selected for output.

[0020] Beneficial effects 1. This invention performs digital offset calibration on a channel-by-channel basis within the FPGA. Subsequent threshold determination and channel competition within the same band are based on the calibrated digital signal, reducing the interference of analog front-end differences on the selection results.

[0021] 2. This invention uses signal threshold and noise threshold to form a hysteresis validity determination, and suppresses the amplitude of invalid signals to a preset minimum value, making it difficult for invalid or noise-dominated channels to enter the candidate maximum signal competition, thus reducing the possibility of noise triggering subsequent arbitration.

[0022] 3. After determining the candidate maximum signal, the present invention further performs a difference comparison. Only when the candidate maximum signal meets the fluctuation threshold relative to other channel signals in the same band is the winning channel confirmed, thus avoiding repeated channel selection jumps caused by short-term amplitude proximity.

[0023] 4. This invention provides the winning channel information and bandwidth protection signal together to the multi-band output strategy control module. The output strategy not only considers the working mode configuration information, but also combines the effective status of bandwidth protection signals in different bands. When the current output band cannot be output, it can switch to another band where the bandwidth protection signal is effective. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a multi-band, multi-channel signal adaptive selection and output system based on FPGA provided in a preferred embodiment of the present invention; Figure 2 This is a flowchart illustrating a preferred embodiment of the FPGA-based multi-band multi-channel signal adaptive selection and output method provided by the present invention. Figure 3 This is a schematic diagram of the multi-band output strategy control sub-process of step S4 provided in a preferred embodiment of the present invention. Detailed Implementation

[0025] The following description, in conjunction with the accompanying drawings and embodiments, further illustrates the FPGA-based multi-band, multi-channel signal adaptive selection and output system and method. The following embodiments focus on system implementation, first explaining the module connections, signal transmission relationships, and state control logic within the FPGA, and then describing the method flow formed during system operation. This arrangement is because the core of this solution lies not in a single comparison action, but in the continuous processing link formed between the signal acquisition and calibration module, the threshold detection and filtering module, the channel contention and arbitration module, and the multi-band output strategy control module.

[0026] In this continuous processing link, digital signals from multiple channels across multiple bands enter the FPGA. First, digital offset calibration is performed channel-by-channel, followed by hysteresis-based validity determination using signal and noise thresholds. Subsequently, the determined channel signals within the same band enter the channel contention and arbitration module. This module completes the determination of the candidate maximum signal, confirmation of the difference threshold, confirmation of the winning channel, generation of the channel selection signal, and generation of the bandwidth-preserving signal within a single processing step. The multi-band output strategy control module then selects one signal for output based on the operating mode configuration information, the winning channel information for different bands, and the bandwidth-preserving signal.

[0027] Example 1 like Figure 1 As shown, this embodiment provides a multi-band, multi-channel adaptive signal selection and output system based on FPGA. The modules of this system can be arranged within the same FPGA device or distributed across different processing areas of the same logic project according to resource availability. The signals transmitted between modules include not only signal amplitude but also band identifiers, channel identifiers, validity status, winning channel information, and bandwidth-preserving signals. Based on the above description, the following sections describe the optimal implementation methods of each module within the FPGA.

[0028] The signal acquisition and calibration module receives digital signals from multiple channels across multiple bands and performs digital offset calibration on a channel-by-channel basis. The digital offset calibration includes configuring a digital offset for each channel and performing an addition or subtraction calibration operation between the digital offset and the digital sample value of the channel with the configured digital offset to compensate for amplitude inconsistencies between channels. In a preferred embodiment, this module may include an input register, an offset register, and a calibration operation unit. The input register latches the digital sample value of each channel; the offset register stores the corresponding digital offset for each channel; and the calibration operation unit performs the addition or subtraction calibration operation according to the channel correspondence. The calibrated signal is output as the calibrated channel signal to the threshold detection and filtering module.

[0029] In one specific embodiment, the system includes a first band and a second band, each band comprising four channels. The four channels of the first band correspond to four sets of input registers and offset registers, respectively, and the four channels of the second band also correspond to four sets of input registers and offset registers, respectively. The four-channel and dual-band configurations are merely preferred configurations for illustrative purposes; in other embodiments, the number of channels per band can be expanded or reduced according to the number of receiving links, and the number of bands can also be set according to the number of operating frequency bands of the device.

[0030] The digital offset can be written during system initialization. Preferably, in maintenance calibration mode, the system inputs equal-amplitude test signals to multiple channels within the same band. The signal acquisition and calibration module reads the digital sampled values ​​of each channel after they enter the FPGA and adjusts the digital offset of each channel accordingly, ensuring that the calibrated sampled values ​​of the same test signal on different channels are within the allowable error range. After this calibration is completed, the digital offset is written to the offset register. In operational mode, the signal acquisition and calibration module directly uses the digital offset in the offset register for calibration.

[0031] In other embodiments, the digital offset can also be written by an external control interface or loaded from factory calibration data. Regardless of whether the digital offset comes from initialization calibration, an external interface, or preset calibration data, each digital offset corresponds to the digital sample value of the channel for which it is configured and is not used across channels. By first completing the digital offset calibration by channel, subsequent threshold determination and channel competition within the same band are established on a more consistent amplitude basis.

[0032] A threshold detection and filtering module is used to perform hysteresis validity determination on each calibrated channel signal based on a signal threshold and a noise threshold, obtaining the determined channel signal. The hysteresis validity determination includes: retaining the channel signal amplitude when its amplitude is higher than the signal threshold, and suppressing the channel signal amplitude to a preset minimum value when its amplitude is lower than the noise threshold. In a preferred embodiment, this module may include a threshold register, an amplitude comparison unit, a status holding register, and an invalid signal suppression unit. The threshold register stores the signal threshold and the noise threshold; the amplitude comparison unit determines the relationship between the channel signal amplitude and the two thresholds; the status holding register stores the validity status of the previous determination cycle; and the invalid signal suppression unit performs preset minimum value suppression.

[0033] In one specific embodiment, when the channel signal amplitude is higher than the signal threshold, the threshold detection and filtering module retains the channel signal amplitude and sets the channel's validity state to valid; when the channel signal amplitude is lower than the noise threshold, the module suppresses the channel signal amplitude to a preset minimum value and sets the channel's validity state to invalid. When the channel signal amplitude is between the signal threshold and the noise threshold, the state holding register can maintain the validity state of the previous determination cycle. This hysteretic validity determination is used to reduce state reversals caused by channel signal fluctuations near the threshold.

[0034] The signal threshold can be set according to the desired useful signal amplitude, while the noise threshold can be set according to the noise floor level when there is no signal input. For channels with similar noise levels, a set of signal and noise thresholds can be shared by band; for channels with significant link differences, corresponding thresholds can be set for each channel. The preset minimum value can be a fixed value in the FPGA data format that is below the effective amplitude range, or it can be a preset low value that matches the channel data bit width. Channels suppressed to the preset minimum value still retain band and channel identifiers, but their amplitudes are less likely to become candidate maximum signals in subsequent maximum value comparisons.

[0035] The channel competition and arbitration module is used to determine the candidate maximum signal among the determined channel signals within the same band, and to confirm the winning channel when the difference between the candidate maximum signal and other channel signals within the same band meets a fluctuation threshold, generating a channel selection signal and a width preservation signal to characterize that the winning channel is in an effective hold state. In a preferred embodiment, this module may include a maximum value comparison unit, a difference comparison unit, a winning channel register, a channel selection signal generation unit, and a width preservation signal generation unit. The maximum value comparison unit first determines the candidate maximum signal among the determined channel signals within the same band. The candidate maximum signal only represents the channel signal with the largest amplitude in the current determination period and is not directly equivalent to the final winning channel.

[0036] After the candidate maximum signal is determined, the difference comparison unit compares the candidate maximum signal with the channel signals in the same band, excluding the candidate maximum signal. If all differences meet the fluctuation threshold, the channel competition and arbitration module confirms the channel containing the candidate maximum signal as the winning channel and updates the winning channel register. If any difference does not meet the fluctuation threshold, it indicates that the lead of the candidate maximum signal relative to other channels is insufficient. The channel competition and arbitration module may retain the previous valid winning channel or not output a new winning channel confirmation result, waiting for the next judgment cycle to re-judge.

[0037] The aforementioned determination of the candidate maximum signal, confirmation of the difference threshold, confirmation of the winning channel, generation of the channel selection signal, and generation of the bandwidth preservation signal belong to the same processing stage. The bandwidth preservation signal is triggered by the valid determination result of the winning channel and remains valid while the preset holding conditions are met. The multi-band output strategy control module determines whether the band to which the bandwidth preservation signal belongs has an outputtable winning channel based on the valid state of the bandwidth preservation signal. In a specific implementation, the channel selection signal can be represented by a channel number, one-hot encoding, or a bus field, used to indicate the selected channel within the current band. This bandwidth preservation signal, along with the winning channel information, is provided to the multi-band output strategy control module.

[0038] In a preferred implementation of a four-channel band, the maximum value comparison unit can employ a two-stage comparison structure. The first stage compares two channel pairs separately, and the second stage compares the output of the first stage to obtain the candidate maximum signal. The difference comparison unit then compares the candidate maximum signal with the determined channel signals of the remaining three channels. For bands with more channels, the maximum value comparison unit can be expanded into a multi-stage comparator tree, and the difference comparison unit can increase the number of comparison paths according to the number of channels. For devices with limited FPGA resources, a time-division multiplexed comparison unit can also be used to process the determined channel signals of different bands in batches according to the band identifier.

[0039] The fluctuation threshold can be stored in a fluctuation threshold register. The value of the fluctuation threshold can be written via an external control interface, loaded from initialization calibration results, or given by preset engineering parameters. This fluctuation threshold uses the same or comparable data scale as the determined channel signal to confirm that the candidate maximum signal has a sufficient leading amplitude relative to other channel signals within the same band. This prevents ordinary instantaneous maximum values ​​from directly triggering the winning channel switch when multiple channel amplitudes are close.

[0040] The bandwidth maintenance signal generation unit may include a status register, a hold counter, and edge detection logic. After the winning channel is confirmed, the bandwidth maintenance signal generation unit sets the bandwidth maintenance signal for the corresponding band. If the winning channel still meets the validity criteria in subsequent decision periods, and preset hold conditions such as the hold count, the continuous valid state of the winning channel, or the external operating state window are still met, the bandwidth maintenance signal remains valid. If the winning channel fails, the hold count ends, or the operating state window closes, the bandwidth maintenance signal is reset.

[0041] Edge detection logic can identify the valid start and end of the bandwidth-preserving signal. When the bandwidth-preserving signal changes from invalid to valid, the hold counter starts counting, and the band status register is written with the information of the currently winning channel for that band. When the bandwidth-preserving signal changes from valid to invalid, the band status register can retain the historical winning channel information, but at the same time, it sets the output state of that band to non-output. In this way, the bandwidth-preserving signal provides state boundaries and also avoids the subsequent output strategy from directly relying on instantaneous sampling points.

[0042] A multi-band output strategy control module is used to select one signal for output based on operating mode configuration information, winning channel information of different bands, and bandwidth protection signals. The output strategy defined by the operating mode configuration information includes at least one of a single-band priority output mode, a maximum value output mode, and a polling output mode based on the number of outputs configured. When the bandwidth protection signal of the currently output band is invalid and the bandwidth protection signal of another band is valid, the multi-band output strategy control module selects the winning channel signal of the other band for output. In a preferred embodiment, this module may include a mode register, a band status register, an output count counter, and an output selection unit. The mode register stores the operating mode configuration information; the band status register stores the current valid status of the bandwidth protection signal and the winning channel information for each band; the output count counter is used to poll the output mode; and the output selection unit determines the final winning channel signal to be output based on the above information.

[0043] From a system connectivity perspective, the input of the multi-band output strategy control module is not directly connected to the raw digital signals of each channel, but rather to the output of the channel contention and arbitration module. The information sent to this module for each band includes at least the winning channel information and a bandwidth maintenance signal for that band. The winning channel information indicates which channel within the band has passed the intra-band contention and arbitration, while the bandwidth maintenance signal indicates whether the winning channel is in a valid hold-up state. The output selection unit only includes a band in the current output candidate when the bandwidth maintenance signal for the corresponding band is valid.

[0044] In one specific embodiment, the band status register stores multiple sets of status fields for each band. Each set of status fields may include a band identifier, a winning channel identifier, a winning channel amplitude, a bandwidth protection signal validity status, and the current number of valid outputs. After the channel contention and arbitration module confirms a new winning channel, the status field of the corresponding band is updated; after the bandwidth protection signal is reset, the bandwidth protection signal validity status of the corresponding band is cleared. In this way, the multi-band output strategy control module can obtain the status information required for cross-band selection within one register read cycle.

[0045] The operating mode configuration information may include the output strategy type field, priority band field, current band to be output field, preset output count field, and output order field. The output strategy type field is used to distinguish between single-band priority output mode, maximum value output mode, and polling output mode configured based on the number of outputs; the priority band field is used to specify the priority band in the single-band priority output mode; the current band to be output field is used to record the bands currently being served in the polling output mode; the preset output count field is used to limit the effective number of outputs for each band in the polling output mode; and the output order field is used for sequential switching between two or more bands.

[0046] To avoid conflicts between configuration updates and real-time output selection, the multi-band output strategy control module can latch the operating mode configuration information at the beginning of the decision period. The latched operating mode configuration information remains unchanged throughout the decision period until the output selection for that period ends. If the external control interface writes new operating mode configuration information midway through the decision period, this new information can be deferred to the next decision period. This process ensures that the same batch of winning channel information and bandwidth-protected signals are selected under the same output strategy.

[0047] In single-band priority output mode, the output selection unit first checks the validity status of the bandwidth preservation signal for the designated band. If the bandwidth preservation signal of the priority band is valid, the output selection unit outputs the winning channel signal for that band; if the bandwidth preservation signal of the currently to-be-output band is invalid and the bandwidth preservation signal of another band is valid, the output selection unit selects the winning channel signal of the other band for output. This process preserves priority in single-band priority output mode while preventing output from being stuck on unoutputtable bands.

[0048] In maximum output mode, the output selection unit first filters bands where the bandwidth-preserving signal is valid, and then selects a signal that satisfies the maximum output strategy from the winning channel information of these bands. Bands with invalid bandwidth-preserving signals are not included in the cross-band comparison, and even if the winning channel register of that band still stores historical amplitudes, they are not considered as current output candidates. This avoids historical winning channel information from misleading the current output selection.

[0049] In the polling output mode based on the number of outputs configured, the multi-band output strategy control module counts the effective number of bandwidth-preserving signals according to the preset number of outputs for different bands, and switches the output band after reaching the preset number of outputs. The output count counter can count only when the corresponding band is actually output and its bandwidth-preserving signal is valid. If the bandwidth-preserving signal of the output band is invalid, the output selection unit switches to another band with a valid bandwidth-preserving signal, but does not count the invalid period in the effective output count of the output band.

[0050] When the bandwidth-preserving signals for all bands are invalid, the multi-band output strategy control module can enter a waiting state. In the waiting state, the output selection unit can either maintain the latched state of the last valid output or output a preset idle value; the specific method is determined by the subsequent processing unit's requirements for continuity. Once the bandwidth-preserving signal for any band becomes valid again, the multi-band output strategy control module will re-determine the target band based on the current operating mode configuration information.

[0051] In a preferred embodiment, after the output selection unit determines a winning channel signal, it simultaneously writes the winning channel signal, band identifier, channel selection signal, and bandwidth protection signal into the output latch register. When the subsequent processing unit reads the output latch register, it can simultaneously obtain signal data and status data, avoiding cross-cycle mismatch between signal data and status identifier. If the subsequent processing unit only needs one digital signal, the band identifier, channel selection signal, and bandwidth protection signal can be used as accompanying status outputs.

[0052] After the output latch register, output hold logic can also be configured. This logic holds the previous valid output until a new target band is confirmed, or outputs a preset idle value when there are no valid bandwidth-holding signals in all bands. If subsequent processing units prioritize continuous input, they can choose to hold the previous valid output; if they need to explicitly identify the absence of valid input, they can choose to output a preset idle value and simultaneously pull the bandwidth-holding signal low. Neither of these output methods changes the basic logic of the multi-band output strategy control module's selection based on the valid state of the bandwidth-holding signal.

[0053] The system can also be configured with unified state clearing logic. This logic clears the temporary states in the winning channel register, band status register, output count counter, and output latch register upon system reset, operating mode switching, or the end of an external operating status window. After clearing, each band needs to undergo digital offset calibration, hysteresis validity determination, candidate maximum signal determination, and difference threshold confirmation before outputtable winning channel information and bandwidth-preserving signals can be generated again. This process prevents historical states from the previous task phase from affecting output selection in the next task phase.

[0054] To meet the timing convergence requirements of FPGAs, one or more pipelined registers can be configured between the signal acquisition and calibration module, threshold detection and filtering module, channel contention and arbitration module, and multi-band output strategy control module. Each register stores the intermediate state of the current channel or band and carries the band and channel identifiers for subsequent propagation. Even if data from multiple bands is interleaved in the pipeline, the winning channel information and bandwidth-preserving signal of the corresponding band can be restored at the output.

[0055] In a preferred embodiment, the determined channel signals competing within the same band are synchronously latched before entering the maximum value comparison unit. Synchronous latching can be performed by a channel synchronization register within the band. This register simultaneously latches the determined channel signals, channel identifiers, and validity status of each channel within the same determination period, and then sends them uniformly to the channel competition and arbitration module. If the data from multiple channels comes from different sampling times, the candidate maximum signal may be affected by cross-period data mismatch; after synchronous latching, the candidate maximum signal and difference comparison within the same band are both based on data from the same determination period.

[0056] To facilitate system debugging and subsequent processing, band identifiers, channel identifiers, channel selection signals, and bandwidth-preserving signals can be passed between modules as a single state group. This state group is updated progressively with the calibration channel signal, the decision channel signal, and the winning channel signal. If a module at a certain level determines that the state group is invalid, subsequent modules can stop updating the corresponding band's output candidates accordingly. This state group design helps maintain consistency and traceability between signal amplitude, channel source, and effective state preservation.

[0057] In some preferred embodiments, update protection logic for the operating mode configuration information is also included. This update protection logic latches the operating mode configuration information at the beginning of a decision cycle and keeps it unchanged until the end of the decision cycle. If the external control interface writes new operating mode configuration information midway through a decision cycle, the new configuration information can be delayed until the next decision cycle. This process can prevent the same batch of winning channel information from being affected by inconsistent operating modes during the output selection process.

[0058] In other embodiments, the signal acquisition and calibration module, threshold detection and filtering module, and channel contention and arbitration module can be replicated multiple times per band, or a single logic can be time-division multiplexed according to bands. When replicated by band, the winning channel information for multiple bands can be generated in parallel within the same decision period; when time-division multiplexed, the FPGA resource consumption can be reduced. The different hardware implementations described above do not change the functional relationship between the modules, nor do they change the role of the bandwidth-preserving signal as the basis for cross-band output selection.

[0059] Example 2 like Figure 2 As shown, based on the system structure of Embodiment 1, this embodiment illustrates a multi-band, multi-channel signal adaptive selection and output method based on FPGA. This method is executed by the modules in Embodiment 1 and forms a complete processing flow in four steps.

[0060] Step S1: Receive digital signals from multiple channels in multiple bands and perform digital offset calibration for each channel.

[0061] The signal acquisition and calibration module receives digital signals from multiple channels across multiple bands, configures a digital offset for each channel, and performs an addition or subtraction calibration operation between the digital offset and the digital sampled value of the channel with the configured digital offset. This step outputs the calibrated channel signal, retaining the band and channel identifiers. This step can be performed by an input register, an offset register, and a calibration calculation unit; the specific structure can adopt the method described in Embodiment 1.

[0062] Step S2: Perform hysteresis validity determination on each channel signal after calibration based on the signal threshold and noise threshold to obtain the determined channel signal.

[0063] The threshold detection and filtering module compares the channel signal amplitude with a signal threshold and a noise threshold. When the channel signal amplitude is higher than the signal threshold, the channel signal amplitude is retained; when the channel signal amplitude is lower than the noise threshold, the channel signal amplitude is suppressed to a preset minimum value. When the channel signal amplitude is between the two thresholds, the validity of the previous judgment cycle can be maintained. This step outputs the judged channel signal for use in subsequent competition and arbitration within the same band.

[0064] Step S3: Determine the candidate maximum signal in the channel signals after judgment within the same band, and confirm the winning channel when the difference between the candidate maximum signal and other channel signals in the same band meets the fluctuation threshold, and generate a channel selection signal and a width preservation signal to characterize that the winning channel is in an effective holding state.

[0065] The channel contention and arbitration module first identifies the candidate maximum signal within the same band, and then compares the candidate maximum signal with the difference values ​​of other channel signals within the same band. If all differences meet the fluctuation threshold, the channel containing the candidate maximum signal is confirmed as the winning channel. After the winning channel is confirmed, the same module generates a channel selection signal and a width-preserving signal. Therefore, the determination of the candidate maximum signal, the confirmation of the difference threshold, the confirmation of the winning channel, and the generation of the channel selection signal and the width-preserving signal are executed as a complete processing step in step S3, rather than being split into two independent steps.

[0066] In a preferred embodiment, step S3 further includes maintaining control over the bandwidth protection signal. The bandwidth protection signal is triggered by the valid determination result of the winning channel and remains valid while the preset holding conditions are met. When the bandwidth protection signal is valid, the subsequent stage can determine that the band to which the bandwidth protection signal belongs has an outputable winning channel; when the bandwidth protection signal is invalid, even if the band has historical winning channel information, it is not considered as a currently outputtable object. This refined processing is integrated with the channel competition and arbitration module in Embodiment 1.

[0067] Step S4: Select one signal output based on the working mode configuration information, the winning channel information of different bands, and the bandwidth preservation signal.

[0068] The multi-band output strategy control module reads the operating mode configuration information and, in conjunction with the winning channel information and bandwidth-preserving signals for different bands, selects one signal for output. For example... Figure 3 As shown, step S4 may further include: S401: Read working mode configuration information; S402: Acquire winning channel information and bandwidth-preserving signals for different frequency bands; S403: Determine the candidate bands with output winning channels based on the effective state of the bandwidth-preserving signal; S404: Select the target band and its winning channel signal according to the single-band priority, maximum value or polling output strategy; S405: Outputs the selected winning channel signal; switches output when the current output band is invalid and another band is valid.

[0069] In single-band priority output mode, step S4 prioritizes outputting the winning channel signal of the specified band; when the bandwidth-preserving signal of the specified band is invalid and the bandwidth-preserving signal of another band is valid, the winning channel signal of the other band is selected for output. In maximum value output mode, step S4 first filters the bands with valid bandwidth-preserving signals, and then selects a signal based on the winning channel information. In polling output mode based on output count configuration, step S4 counts the number of valid bandwidth-preserving signals according to the preset output count for different bands, and switches the output band after reaching the preset output count.

[0070] If the bandwidth-preserving signal of the current output band is invalid while the bandwidth-preserving signal of another band is valid, step S4 selects the winning channel signal of the other band for output. If the bandwidth-preserving signals of all bands are invalid, the latched state of the previous valid output can be maintained or a preset idle value can be output. After a valid bandwidth-preserving signal reappears in any band, the target band is re-determined according to the operating mode configuration information. The above processing keeps the method flow consistent with the system structure of Embodiment 1.

[0071] For systems with more than two bands, step S4 can be extended to multi-band polling or multi-band priority search. The multi-band output strategy control module saves the preset number of outputs, the current number of valid outputs, and the validity status of the bandwidth-preserving signal for each band. After the current band to be output reaches the preset number of outputs, the module switches to the next band in the order specified by the working mode configuration information; if the bandwidth-preserving signal of the next band is invalid, the module continues to search for other bands with valid bandwidth-preserving signals.

[0072] Without altering the system structure of Embodiment 1 and the four method steps described above, the number of channels, number of bands, register bit width, output encoding method, comparator tree level, hold counting method, and interface form can all be adjusted according to FPGA resources and application scenarios. These adjustments are still based on channel-based digital offset calibration, hysteresis-based validity determination, difference threshold confirmation of the winning channel, and multi-band output selection based on width-preserving signals.

[0073] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A multi-band, multi-channel adaptive signal selection and output system based on FPGA, characterized in that, include: The signal acquisition and calibration module is used to receive digital signals from multiple channels in multiple bands and perform digital offset calibration on a channel-by-channel basis. The threshold detection and filtering module is used to perform hysteresis validity determination on each channel signal after calibration based on the signal threshold and noise threshold, and obtain the determined channel signal. The channel competition and arbitration module is used to determine the candidate maximum signal among the determined channel signals in the same band, and to confirm the winning channel when the difference between the candidate maximum signal and other channel signals in the same band meets the fluctuation threshold, and to generate a channel selection signal and a width preservation signal to characterize that the winning channel is in an effective holding state. The multi-band output strategy control module is used to select one signal output based on the working mode configuration information, the winning channel information of different bands, and the bandwidth preservation signal.

2. The FPGA-based multi-band multi-channel signal adaptive selection and output system according to claim 1, characterized in that, The digital offset calibration includes: configuring a digital offset for each channel, and performing an addition or subtraction calibration operation between the digital offset and the digital sample value of the channel configured with the digital offset, in order to compensate for the inconsistency in the amplitude of each channel.

3. The FPGA-based multi-band multi-channel signal adaptive selection and output system according to claim 1, characterized in that, The hysteresis validity determination includes: retaining the channel signal amplitude when the channel signal amplitude is higher than the signal threshold, and suppressing the channel signal amplitude to a preset minimum value when the channel signal amplitude is lower than the noise threshold.

4. The FPGA-based multi-band multi-channel signal adaptive selection and output system according to claim 1, characterized in that, The channel competition and arbitration module is used to compare the candidate maximum signal with the channel signals in the same band other than the candidate maximum signal, and confirm the channel where the candidate maximum signal is located as the winning channel when all differences meet the fluctuation threshold.

5. The FPGA-based multi-band multi-channel signal adaptive selection and output system according to claim 1, characterized in that, The bandwidth preservation signal is triggered by the valid determination result of the winning channel and remains valid while the preset holding conditions are met. The multi-band output strategy control module determines whether the band to which the bandwidth preservation signal belongs has an output winning channel based on the valid state of the bandwidth preservation signal.

6. The FPGA-based multi-band multi-channel signal adaptive selection and output system according to claim 1, characterized in that, The output strategy defined by the working mode configuration information includes at least one of the following: single-band priority output mode, maximum value output mode, and polling output mode based on the number of outputs. When the bandwidth preservation signal of the current output band is invalid and the bandwidth preservation signal of another band is valid, the multi-band output strategy control module selects the winning channel signal of the other band for output.

7. A method for adaptive selection and output of multi-band, multi-channel signals based on FPGA, characterized in that, include: It receives digital signals from multiple channels across multiple bands and performs digital offset calibration for each channel. Hysteresis validity determination is performed on each channel signal after calibration based on signal threshold and noise threshold to obtain the determined channel signal; Within the same band, a candidate maximum signal is determined among the channel signals after the judgment, and the winning channel is confirmed when the difference between the candidate maximum signal and other channel signals within the same band meets the fluctuation threshold. A channel selection signal and a width-preserving signal are generated to characterize that the winning channel is in an effective holding state. Based on the operating mode configuration information, the winning channel information for different bands, and the bandwidth preservation signal, select one signal output.

8. The FPGA-based multi-band multi-channel signal adaptive selection and output method according to claim 7, characterized in that, The hysteresis validity determination includes: retaining the channel signal amplitude when the channel signal amplitude is higher than the signal threshold, and suppressing the channel signal amplitude to a preset minimum value when the channel signal amplitude is lower than the noise threshold.

9. The FPGA-based multi-band multi-channel signal adaptive selection and output method according to claim 7, characterized in that, Confirming the winning channel includes: comparing the candidate maximum signal with the channel signals in the same band other than the candidate maximum signal, and confirming the channel where the candidate maximum signal is located as the winning channel when all differences meet the fluctuation threshold.

10. The FPGA-based multi-band multi-channel signal adaptive selection and output method according to claim 7, characterized in that, When the working mode configuration information defines the polling output mode, the effective number of bandwidth-preserving signals is counted according to the preset number of outputs for different bands, and the output band is switched after the preset number of outputs is reached; when the bandwidth-preserving signal of the output band is invalid and the bandwidth-preserving signal of another band is valid, the winning channel signal of the other band is selected for output.

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