A signal control circuit, electronic device, controller

Abstract

This application provides a signal control circuit, electronic device, and controller, relating to the field of communication technology, to reduce the complexity of a radio frequency (RF) front-end circuit with the signal control circuit while supporting multiple communication frequency bands. In this signal control circuit, the controller outputs a first control signal based on a first control signal input terminal, or outputs a second control signal based on a signal from a second control signal input terminal. A first switch includes a first RF input terminal and a second RF input terminal, respectively used to receive different first and second RF signals. The first switch is coupled to the controller, and selects either the first or second RF input terminal based on the first or second control signal. While supporting multiple communication frequency bands, the controller can be compatible with different interfaces, reducing the complexity of the signal control circuit compared to solutions that require independently setting different RF front-end modules.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a signal control circuit, electronic device, and controller. Background Technology

[0002] As a core component of wireless communication technology, the radio frequency (RF) front-end is crucial to the wireless communication performance of electronic devices. With the continuous development of wireless communication technology, the requirements for wireless communication bandwidth are increasing. Therefore, the RF front-end needs to support multiple frequency bands. Currently, RF devices for different frequency bands are set up independently, and each RF device uses different interfaces, leading to increased complexity in the design of the RF front-end in electronic devices. Summary of the Invention

[0003] This application provides a signal control circuit, electronic device, and controller, which reduces the complexity of the radio frequency front-end circuit while supporting multiple communication frequency bands.

[0004] To achieve the above objectives, this application adopts the following technical solution:

[0005] In one aspect, this application provides a signal control circuit, which may include a controller and a first switch. The controller may include a first control signal input terminal and a second control signal input terminal. The first control signal input terminal and the second control signal input terminal transmit data of different types. The controller is used to output a first control signal based on the signal from the first control signal input terminal, or the controller is used to output a second control signal based on the signal from the second control signal input terminal. Furthermore, the first switch includes a first radio frequency (RF) input terminal and a second RF input terminal, respectively used to receive different first and second RF signals. The type of data transmitted by the first control signal input terminal matches the first RF signal, and the type of data transmitted by the second control signal input terminal matches the second RF signal. The first switch is coupled to the controller and is used to select either the first RF input terminal or the second RF input terminal based on the first or second control signal.

[0006] In the signal control circuit provided in this application embodiment, the controller can output a first control signal based on the signal from the first control signal input terminal, or the controller can output a second control signal based on the signal from the second control signal input terminal. Furthermore, under the control of the first or second control signal, the first switch selects the first radio frequency input terminal to transmit the first radio frequency signal (e.g., a cellular communication radio frequency signal) from the first radio frequency input terminal to other circuit structures or components coupled to the first switch. Alternatively, under the control of the first or second control signal, the first switch selects the second radio frequency input terminal, coupling the second radio frequency input terminal to the input terminal of the first radio frequency amplifier to transmit the second radio frequency signal (e.g., a short-range communication radio frequency signal or a satellite positioning radio frequency signal) from the second radio frequency input terminal to other circuit structures or components coupled to the first switch. In contrast, in electronic devices provided by related technologies, radio frequency front-end modules for different signals, such as cellular communication radio frequency signals, satellite communication radio frequency signals, and short-range communication radio frequency signals (or satellite positioning), are typically set independently. Different radio frequency front-end modules set interfaces matching the radio frequency signals they need to receive and / or transmit, and the interfaces of the various radio frequency front-end modules are incompatible. The signal control circuit provided in this application can receive and / or transmit at least two different signals (e.g., two of cellular communication radio frequency signals, satellite communication radio frequency signals, short-range communication radio frequency signals, and satellite positioning signals). Therefore, it eliminates the need for separate radio frequency front-end modules for receiving and / or transmitting different signals in the electronic device and radio frequency chip. Furthermore, while supporting multiple communication frequency bands, the controller in this signal control circuit can be compatible with different interfaces, reducing the complexity of the signal control circuit compared to solutions that require separate radio frequency front-end modules.

[0007] In one optional implementation, the controller further includes an interface circuit and a logic output circuit. The interface circuit is coupled to a first control signal input terminal and a second control signal input terminal. The interface circuit decodes the signal from the first control signal input terminal into a first control signal and the signal from the second control signal input terminal into a second control signal. The logic output circuit is coupled to the interface circuit and outputs the first and second control signals. In this way, the controller can decode the signals from the first and second control signal input terminals through the interface circuit. The logic output circuit can directly output the decoded first or second control signal to the controlled element, such as a first switch.

[0008] In one optional implementation, the interface circuit includes a first decoder and a second decoder. The first decoder is coupled to a first control signal input terminal and is used to decode the signal from the first control signal input terminal into a first control signal. The second decoder is coupled to a second control signal input terminal and is used to decode the signal from the second control signal input terminal into a second control signal. In this way, the signals from the first and second control signal input terminals can be decoded by two different decoders to generate the aforementioned first and second control signals.

[0009] In one optional embodiment, the controller further includes an arbitration signal terminal, and an interface circuit is coupled to the arbitration signal terminal. The interface circuit is used to decode the signal from the arbitration signal terminal into an arbitration signal. The logic output circuit is also used to output a first control signal or a second control signal according to the arbitration signal. Furthermore, the interface circuit includes a third decoder coupled to the arbitration signal terminal, which is used to decode the signal from the arbitration signal terminal into an arbitration signal. The logic output circuit can output the first control signal or the second control signal to the controlled element after arbitration of the arbitration signal according to a preset control protocol. The preset control protocol can determine the data of the arbitration signal. This application does not limit the preset control protocol, and users can also define the above control protocol as needed.

[0010] In one optional implementation, the logic output circuit includes an inverter, a first buffer, and a second buffer. The input of the inverter is coupled to a third decoder. The input of the first buffer is coupled to the first decoder, and the enable terminal of the first buffer is coupled to the input of the inverter. The first buffer is used to output a first control signal based on the state of the enable terminal. The input of the second buffer is coupled to a second decoder, and the enable terminal of the second buffer is coupled to the output of the inverter. The second buffer is used to output a second control signal based on the state of the enable terminal. As can be seen from the above, the enable terminals of the first and second buffers are respectively coupled to the input and output of the inverter. Since the level of the arbitration signal received at the input of the inverter is opposite to the level of the signal at the output of the inverter, when the first buffer is in the working state to output the first control signal, the second buffer is in the non-working state and cannot output the second control signal. Conversely, when the second buffer is in the working state to output the second control signal, the first buffer is in the non-working state and cannot output the first control signal. In this way, by controlling the level of the arbitration signal received at the input of the inverter, the purpose of controlling the first buffer to output the first control signal or the second buffer to output the second control signal can be achieved.

[0011] In one optional implementation, the first switch includes a first strobe terminal. The first strobe terminal is coupled to a first decoder and is used to receive a first control signal. For example, when the first switch needs to select a first radio frequency (RF) input, and the type of data transmitted at the first control signal input (e.g., a MIPI signal) matches the first RF signal (e.g., a cellular communication RF signal) at the first RF input and the first control signal, the first control signal output by the first decoder can be directly transmitted to the first strobe terminal of the first switch without arbitration by an arbitration signal. Alternatively, the first strobe terminal is coupled to a second decoder and is used to receive a second control signal. For example, when the first switch needs to select a second RF input, and the type of data transmitted at the second control signal input (e.g., a GPIO signal) matches the second RF signal (e.g., a short-range communication RF signal or a satellite positioning RF signal) at the second RF input and the second control signal, the second control signal output by the second decoder can be directly transmitted to the first strobe terminal of the first switch without arbitration by an arbitration signal. Alternatively, the first strobe terminal is coupled to the output terminals of both the first and second buffers, and is used to receive either the first or second control signal. In this case, the first control signal output by the first decoder or the second control signal output by the second decoder needs to be arbitrated by an arbitration signal before being transmitted to the first strobe terminal of the first switch.

[0012] In one optional embodiment, the first switch further includes a third radio frequency (RF) input terminal for receiving a third RF signal. The third RF signal is different from both the first and second RF signals. At least one of the first or second control signal input terminals transmits data of a type that matches the third RF signal. The first switch is also used to select the third RF input terminal based on the first or second control signal. In this way, the three different RF input terminals can each receive RF signals of different standards.

[0013] In one optional embodiment, the signal control circuit further includes a radio frequency (RF) amplifier coupled to the controller. A first switch is coupled to the input terminal of the RF amplifier. The first switch is used to connect the first RF input terminal to the input terminal of the RF amplifier to select the first RF input terminal. The RF amplifier can amplify the first RF signal (e.g., a cellular communication RF signal) under the control of a first control signal or a second control signal. Alternatively, the first switch is used to connect the second RF input terminal to the input terminal of the RF amplifier to select the second RF input terminal. The RF amplifier can amplify the second RF signal (e.g., a short-range communication RF signal or a satellite positioning RF signal) under the control of the first control signal or the second control signal.

[0014] In one optional embodiment, the first switch further includes a third radio frequency (RF) input terminal for receiving a third RF signal. The type of data transmitted at the second control signal input terminal matches the second and third RF signals. The RF amplifier includes a first amplifier and a second amplifier. The first switch is used to connect the first RF input terminal to the input terminal of the first amplifier according to the first control signal. This allows the first amplifier to amplify the first RF signal, such as a cellular communication RF signal, from the first RF input terminal under the control of the first control signal. In this case, the first amplifier only needs to amplify one type of RF signal, such as a cellular communication RF signal, so the transmit power of the signals targeted by the first amplifier is the same, thereby improving the power efficiency of the first amplifier. This power efficiency refers to the ratio of the RF signal power output by the RF amplifier to the DC power input. The second amplifier includes a first input terminal and a second input terminal. The first switch is used to connect the second RF input terminal and the third RF input terminal to the first and second input terminals, respectively, according to the second control signal. In this way, a single amplifier, namely the second amplifier mentioned above, can be used to amplify the second radio frequency signal, such as a short-range communication radio frequency signal, and the third radio frequency signal, such as a satellite communication radio frequency signal, thereby reducing the number of amplifiers and simplifying the structure.

[0015] In one optional embodiment, the bias level control terminal of the first amplifier is coupled to a first decoder. The first amplifier is used to adjust the bias level according to a first control signal. The first decoder decodes the signal from the first control signal input terminal to generate a first control signal, which is directly transmitted to the bias level control terminal of the first amplifier without arbitration by an arbitration signal. Based on this, the first amplifier can be used to adjust the bias level according to the first control signal to achieve the purpose of adjusting the gain of the first amplifier. The bias level control terminal of the second amplifier is coupled to a second decoder. The second amplifier is used to adjust the bias level according to a second control signal. The second decoder decodes the signal from the second control signal input terminal to generate a second control signal, which is directly transmitted to the bias level control terminal of the second amplifier without arbitration by an arbitration signal. Based on this, the second amplifier can be used to adjust the bias level according to the second control signal to achieve the purpose of adjusting the gain of the second amplifier.

[0016] In one optional embodiment, the first switch further includes a third radio frequency (RF) input terminal for receiving a third RF signal. The type of data transmitted by the first or second control signal input terminal matches the third RF signal. The RF amplifier includes a third amplifier and a fourth amplifier. The third amplifier includes a third input terminal and a fourth input terminal. The first switch is used to connect the first RF input terminal to the third input terminal according to a first control signal, and to connect the second RF input terminal to the fourth input terminal according to a second control signal. This allows the third amplifier to amplify the high-frequency portion of the first RF signal, such as a cellular communication RF signal, from the first RF input terminal under the control of the first control signal. Furthermore, the first switch connects the second RF input terminal and the fourth input terminal according to the second control signal. This allows the third amplifier to amplify the second RF signal, such as a short-range communication RF signal, from the second RF input terminal under the control of the second control signal. Thus, the third amplifier can amplify both the high-frequency portion of the first RF signal, such as a cellular communication RF signal, and the second RF signal, such as a short-range communication RF signal. At this point, the high-frequency component of the cellular communication radio frequency signal can be the same as or similar to the frequency of the short-range communication radio frequency signal, thus reducing the bandwidth requirement for the third amplifier and lowering its performance requirements. Furthermore, the fourth amplifier includes a fifth input terminal and a sixth input terminal. A first switch is used to connect the first radio frequency input terminal to the fifth input terminal according to a first control signal, and to connect the third radio frequency input terminal to the sixth input terminal according to either a first or second control signal. This allows the fourth amplifier to amplify the low-frequency component of the first radio frequency signal (e.g., the cellular communication radio frequency signal) from the first radio frequency input terminal under the control of the first control signal. The first switch is also used to connect the third and sixth input terminals according to either the first or second control signal. This allows the fourth amplifier to amplify the third radio frequency signal (e.g., the satellite communication radio frequency signal) from the third radio frequency input terminal under the control of either the first or second control signal. Therefore, the fourth amplifier can amplify both the low-frequency component of the first radio frequency signal (e.g., the cellular communication radio frequency signal) and the third radio frequency signal (e.g., the satellite communication radio frequency signal). At this point, the low-frequency portion of the cellular communication radio frequency signal can be the same as or similar to the frequency of the satellite communication radio frequency signal, thus requiring less bandwidth from the fourth amplifier. Furthermore, when the satellite communication radio frequency signal is a low-Earth orbit (LEO) satellite communication radio frequency signal, the transmit power of the low-frequency portion of the cellular communication radio frequency signal can be the same as or similar to the transmit power of the LEO satellite communication radio frequency signal, thereby reducing the performance requirements for the fourth amplifier.

[0017] In one optional embodiment, the bias level control terminal of the third amplifier is coupled to the output terminals of the first and second buffers, and the third amplifier is used to adjust the bias level according to the first or second control signal. The bias level control terminal of the fourth amplifier is coupled to the output terminals of the first and second buffers, and the fourth amplifier is used to adjust the bias level according to the first or second control signal. In this case, the first or second control signal can be transmitted to the bias level control terminal of the third amplifier or the bias level control terminal of the fourth amplifier after arbitration by an arbitration signal.

[0018] In one optional embodiment, the signal control circuit further includes a power switching circuit coupled to the power supply terminal of the RF amplifier. The power switching circuit is also coupled to the output terminals of the first buffer and the second buffer, and is used to provide a supply voltage to the RF amplifier according to a first control signal or a second control signal. In this case, the first or second control signal can be transmitted to the power switching circuit after arbitration by an arbitration signal. The supply voltage provided by the power switching circuit to the RF amplifier can determine the linearity of the RF amplifier.

[0019] In one optional implementation, the first radio frequency signal is a cellular communication radio frequency signal, the second radio frequency signal is a short-range communication radio frequency signal, and the third radio frequency signal is a satellite communication radio frequency signal. These three types of radio frequency signals can cover the user's commonly used communication needs.

[0020] Another aspect of this application provides a radio frequency (RF) chip, including a package structure and a bare die. The bare die is packaged within the package structure, and at least a portion of the aforementioned signal control circuit is integrated within the bare die. The RF chip described above has the same technical effects as the signal control circuit provided in the foregoing embodiments, and will not be repeated here.

[0021] In another aspect, this application provides an electronic device comprising at least one antenna radiator, a processor, and any of the signal control circuits described above. The signal control circuit is coupled to the processor and the antenna radiator. The above-described electronic device has the same technical effects as the signal control circuits provided in the foregoing embodiments, and will not be repeated here.

[0022] In one optional embodiment, the processor further includes a first baseband circuit and a second baseband circuit. The first baseband circuit is coupled at least to a first control signal input terminal of the controller. The first baseband circuit is coupled to a first radio frequency (RF) input terminal of the signal control circuit, and is used to provide a first RF signal to the first RF input terminal. The second baseband circuit is coupled at least to a second control signal input terminal of the controller. The second baseband circuit is coupled to a second RF input terminal of the signal control circuit, and is used to provide a second RF signal to the second RF input terminal. The first baseband circuit can provide at least a control signal matching the first RF signal to the first control signal input terminal, enabling the controller to control the transmit and receive links in the signal control circuit to transmit and process the first RF signal, thereby enabling the signal control circuit to achieve at least one of transmitting or receiving the first RF signal. Similarly, the second baseband circuit can provide at least a control signal matching the second RF signal to the second control signal input terminal, enabling the controller to control the transmit and receive links in the signal control circuit to transmit and process the second RF signal, thereby enabling the signal control circuit to achieve at least one of transmitting or receiving the second RF signal.

[0023] In another aspect, this application provides a controller including a first control signal input terminal or a second control signal input terminal. The first and second control signal input terminals transmit different types of data. The controller is used to output a first control signal based on the first control signal input terminal, or to output a second control signal based on the signal from the second control signal input terminal. The first control signal input terminal is used to transmit Mobile Industry Processor Interface (MIPI) signals. The type of data transmitted by the first control signal input terminal is a MIPI signal, and the first control signal input terminal can be referred to as a MIPI port, which can have multiple control states. The second control signal input terminal is used to transmit General Purpose Input / Output Interface (GPIO) signals. The type of data transmitted by the second control signal input terminal can be a GPIO signal, and the second control signal input terminal can be referred to as a GPIO port, which has low latency characteristics. The above controller has the same technical effects as the signal control circuit provided in the foregoing embodiments, and will not be repeated here.

[0024] In one optional embodiment, the controller further includes an interface circuit and a logic output circuit. The interface circuit is coupled to a first control signal input terminal and a second control signal input terminal; the interface circuit is used to decode the signal from the first control signal input terminal into a first control signal, and to decode the signal from the second control signal input terminal into a second control signal. The logic output circuit is coupled to the interface circuit, and is used to output the first control signal and the second control signal. The technical effects of the interface circuit and the logic output circuit described above are the same as those described previously, and will not be repeated here.

[0025] In an optional implementation, the controller further includes an arbitration signal terminal, and an interface circuit is coupled to the arbitration signal terminal. The interface circuit is used to decode the signal from the arbitration signal terminal into an arbitration signal. The logic output circuit is also used to output a first control signal or a second control signal based on the arbitration signal. The technical effects of the arbitration signal terminal described above are the same as those described above, and will not be repeated here.

[0026] In one optional embodiment, a controller is coupled to a first switch and controls the first switch to select either a first radio frequency (RF) input terminal or a second RF input terminal based on a first control signal or a second control signal. The first and second RF input terminals are respectively used to receive different first and second RF signals. At least one of the first or second control signal input terminals transmits data of a type matching at least one of the first or second RF signals. The technical effect of the controller controlling the first switch to select either the first or second RF input terminal is the same as described above and will not be repeated here.

[0027] In an optional embodiment, the controller is further configured to control the first switch to select a third radio frequency (RF) input terminal based on a first control signal or a second control signal; the third RF input terminal is configured to receive a third RF signal. The third RF signal differs from the first and second RF signals; at least one of the first or second control signal input terminals transmits data of a type that matches the third RF signal. The technical effect of the controller controlling the first switch to select the third RF input terminal is the same as described above, and will not be repeated here.

[0028] In one optional implementation, the controller is coupled to an RF amplifier and is used to adjust the bias level of the RF amplifier. The technical effect of the controller adjusting the bias level of the RF amplifier is the same as described above, and will not be repeated here. Alternatively, the controller is coupled to a power switching circuit and is used to control the supply voltage provided by the power switching circuit to the RF amplifier. The technical effect of the controller adjusting the supply voltage provided by the power switching circuit to the RF amplifier is the same as described above, and will not be repeated here. Attached Figure Description

[0029] Figure 1 A schematic diagram of a communication scenario for an electronic device provided in an embodiment of this application;

[0030] Figure 2 for Figure 1 A schematic diagram of an exploded structure of the electronic device shown;

[0031] Figure 3A schematic diagram of the structure of an electronic device provided in this application embodiment;

[0032] Figure 4 A schematic diagram of another radio frequency front-end circuit in an electronic device provided in this application embodiment;

[0033] Figure 5 A schematic diagram of a packaging structure provided in an embodiment of this application;

[0034] Figure 6 A schematic diagram of the structure of a signal control circuit in an electronic device provided in this application embodiment;

[0035] Figure 7 A schematic diagram of another signal control circuit in an electronic device provided in an embodiment of this application;

[0036] Figure 8 A schematic diagram of another signal control circuit in an electronic device provided in this application embodiment;

[0037] Figure 9 A schematic diagram of another signal control circuit in an electronic device provided in an embodiment of this application;

[0038] Figure 10 This is a schematic diagram of a signal control circuit provided in an embodiment of this application;

[0039] Figure 11 This is a schematic diagram of another signal control circuit provided in an embodiment of this application;

[0040] Figure 12 for Figure 11 A schematic diagram of a controller structure is shown below;

[0041] Figure 13 for Figure 11 Another schematic diagram of the controller structure is shown;

[0042] Figure 14 This is a schematic diagram of another signal control circuit provided in an embodiment of this application;

[0043] Figure 15 This is a schematic diagram of another signal control circuit provided in an embodiment of this application;

[0044] Figure 16 This is a schematic diagram of another signal control circuit provided in an embodiment of this application;

[0045] Figure 17 A schematic diagram of another signal control circuit in an electronic device provided in an embodiment of this application;

[0046] Figure 18 A schematic diagram of another signal control circuit in an electronic device provided in an embodiment of this application;

[0047] Figure 19 This is a schematic diagram of another signal control circuit provided in an embodiment of this application;

[0048] Figure 20 This is a schematic diagram of another signal control circuit provided in an embodiment of this application;

[0049] Figure 21 A schematic diagram of another signal control circuit in an electronic device provided in an embodiment of this application;

[0050] Figure 22 for Figure 21 A schematic diagram of a signal control circuit is shown.

[0051] Figure 23 A schematic diagram of another signal control circuit in an electronic device provided in an embodiment of this application;

[0052] Figure 24 for Figure 23 The diagram shows a structural schematic of a signal control circuit.

[0053] Figure 25 This is a schematic diagram of another signal control circuit in an electronic device provided in an embodiment of this application.

[0054] Figure label:

[0055] 100 - Electronic device; 10 - Display screen; 11 - Housing; 12 - Mid-frame; 13 - Rear shell; 14 - PCB; 15 - Cover plate; 20 - Antenna radiator; 30 - RF front-end circuit; 3001 - Signal control circuit; 40 - Processor; 401 - First baseband circuit; 402 - Second baseband circuit; 50 - Transceiver; 403 - Third baseband circuit; 300 - RF chip; 301 - Packaging structure; 3011 - Packaging cover plate; 3012 - Packaging substrate; 311 - Controller; S1 - First switch; 3110 - Interface circuit; 3111 - Logic output circuit; 31 - First decoder; 32 - Second decoder; 33 - Third decoder; 304 - Fourth decoder; 305 - Fifth decoder; 34 - Inverter; 35 - First buffer; 36 - Second buffer; 37 - Third buffer; 38 - Fourth buffer; 321 - RF amplifier; S3 - Third switch; S4 - Fourth switch; 330 - Filter circuit; 3211 - First amplifier; 3212 - Second amplifier; S5 - Fifth switch; 3213 - Third amplifier; 3214 - Fourth amplifier. Detailed Implementation

[0056] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0057] In the following description, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0058] Furthermore, in the embodiments of this application, directional terms such as "upper" and "lower" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation in which the components are placed in the accompanying drawings.

[0059] In this application, unless otherwise expressly specified and limited, the term "connection" shall be interpreted broadly. For example, "connection" may be a fixed mechanical connection, a detachable mechanical connection, or an integral part; or, "connection" may be a direct connection or an indirect connection through an intermediate medium.

[0060] Furthermore, unless otherwise explicitly specified and limited, the term "coupling" should be interpreted broadly. For example, "coupling" can be a direct electrical connection, such as physical contact and electrical conduction between two components; it can also be understood as the electrical connection between different components in a circuit structure through physical lines capable of transmitting electrical signals, such as copper foil or wires on a printed circuit board (PCB), to transmit electrical signals. Alternatively, "coupling" can be an indirect electrical connection between two components through an intermediate medium; or, "coupling" can be an electrical connection between two components in a non-contact manner, such as a capacitive coupling between two components to transmit electrical signals. Furthermore, in the embodiments of this application, "connection" refers to the connection or conduction between two or more components through the above-mentioned "coupling" or "indirect coupling" methods for signal / energy transmission; all of these can be referred to as connection.

[0061] This application provides an electronic device that can be applied to various communication systems or protocols, such as: Global System for Mobile Communication (GSM), Code Division Multiple Access (CDMA) system, Wideband Code Division Multiple Access (WCDMA), General Packet Radio Service (GPRS), Long Term Evolution (LTE), etc.

[0062] For example, such as Figure 1 As shown, depending on the type of communication protocol, electronic devices can communicate with base stations via cellular networks, communicate or locate satellites via satellite, or communicate with nearby devices such as routers or headphones via short-range communication, to meet the needs of different scenarios. Cellular communication is a type of terrestrial communication. The frequency bands for cellular communication can include low bands (LB), such as 300MHz–1024MHz, middle high bands (MHB), such as 1800MHz–2700MHz, and the 5G new radio (NR) band.

[0063] Satellite communication belongs to non-terrestrial network (NTN) communication. Satellite communication includes low Earth orbit (LEO), medium Earth orbit (MEO), and high Earth orbit (HEO) satellite communication. For example, LEO satellite communication orbits at altitudes of 500–2000 km, and the communication frequency bands can include uplink (e.g., 1668 MHz–1675 MHz) and downlink (e.g., 1518 MHz–1525 MHz). MEO satellite communication orbits at altitudes of 8000–20000 km. HEO satellite communication orbits at an altitude of approximately 35786 km above the Earth's surface. The communication frequency bands can include uplink (e.g., 1980 MHz–2010 MHz) and downlink (e.g., 2170 MHz–2200 MHz). Alternatively, uplink frequency bands (e.g., 1610 MHz to 1626 MHz) and downlink frequency bands (e.g., 2483 MHz to 2500 MHz). Satellite communication can support sending and receiving text messages, making and receiving phone calls, and data services such as voice calls and internet access.

[0064] In addition, satellite positioning can be a Global Navigation Satellite System (GNSS). This GNSS can include the Global Positioning System (GPS), the BeiDou Navigation Satellite System (BDS), and so on.

[0065] Short-range communication can be classified as terrestrial communication, including wireless fidelity (WiFi), Bluetooth (BT), Bluetooth Low Energy (BLE), Nearlink, Sparklink Low Energy (SLE), location-based services (LBS), near-field communication (NFC), radio frequency identification (RFID), and Zigbee.

[0066] The aforementioned electronic devices may include mobile phones, tablets, headphones, televisions, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, positioning devices, etc. This application does not impose any special limitations on the specific form of the aforementioned electronic devices. For ease of explanation, a mobile phone will be used as an example below.

[0067] In some embodiments of this application, such as Figure 2 As shown, the electronic device 100 may include a display screen 10 and a housing 11 (or outer casing) located on the back of the display screen 10 (opposite to the display surface of the display screen 10). The display screen 10 may be connected to the housing 11. The display screen 10 may be an organic light-emitting diode (OLED) display panel, or a quantum dot light-emitting diode (QLED) display panel, etc. This application does not limit the type of the above-mentioned display panel; for ease of explanation, the following description uses an OLED display panel as an example. To protect the display screen 10, the electronic device 100 may also include a cover plate 15 covering the display surface of the display screen 10. The cover plate 15 may be made of a transparent material.

[0068] For example, continue as follows Figure 2 As shown, the aforementioned housing 11 may include a middle frame 12 and a rear shell 13. The middle frame 12 may be located between the display screen 10 and the rear shell 13, and the middle frame 12 may be connected to both the display screen 10 and the rear shell 13, so that the display screen 10 can be connected to the entire housing 11. The middle frame 12 is used to support the display screen 10. It should be understood that the housing 11 (or outer shell) may be used to refer to part or all of either the middle frame 12 or the rear shell 13.

[0069] Furthermore, the aforementioned electronic device 100 may also include a PCB. For example, the PCB 14 may be made of flame-retardant material (FR-4) dielectric, Rogers dielectric, or a hybrid dielectric of Rogers and FR-4, etc. Here, FR-4 is a designation for a flame-retardant material grade, and Rogers dielectric is a high-frequency board. The PCB 14 is used to carry electronic components, such as processing chips, control chips, and radio frequency chips. The PCB 14 may be disposed within the mounting space formed between the rear housing 13 and the middle frame 12.

[0070] In some embodiments, PCB 14 may include multiple dielectric layers and multiple metal pattern layers. A metal pattern layer may be located between two adjacent dielectric layers. The metal pattern layer may include metal traces and metal blocks (e.g., copper drain areas). Metal traces of different layers can be connected through vias penetrating the dielectric layers. The aforementioned metal traces can be coupled to the electronic components carried on PCB 14 so that signal transmission can be achieved between different electronic components through the metal traces. In addition, the metal blocks are used for grounding the electronic components carried on PCB 14, and can also be used for grounding other components, such as bracket antennas, frame antennas, etc. This metal layer may be referred to as a ground plane, grounding plane, or grounding layer. The aforementioned metal pattern layer can be formed by patterning a metal layer carried by a dielectric layer (including: metal etching, printing, inkjet printing, etc.). Electronic devices may also have other ground planes / grounding planes. In some embodiments, PCB 14 may include a motherboard and a daughterboard, and the battery of electronic device 100 may be disposed between the motherboard and the daughterboard, wherein the motherboard may be disposed near the upper edge of the middle frame 12, and the daughterboard may be disposed near the lower edge of the middle frame.

[0071] For ease of description, an XYZ coordinate axis is established in the accompanying drawings. The XY surface formed by the X and Y directions can be parallel to the display surface (the surface used to display images) of the display screen 10. The Z direction can be perpendicular to the display surface of the display screen 10, that is, the Z direction can be the stacking direction of the housing 11 and the display screen 10.

[0072] To enable the electronic device 100 to perform the aforementioned cellular communication, satellite communication, and short-range communication, the electronic device 100 may include, for example: Figure 3 The diagram shows at least one antenna radiator (ANT) 20, a radio frequency (RF) front-end circuitry 30, a processor 40, and at least one transceiver 50. For example, the processor 40 may include at least one baseband circuit. Figure 3 This example illustrates the process using a processor 40 comprising a first baseband circuit 401 and a second baseband circuit 402. The first baseband circuit 401 and the second baseband circuit 402 can be coupled to a radio frequency (RF) front-end circuit 30, which is coupled to an antenna radiator 20. A transceiver 50 is coupled between the processor 40 and the RF front-end circuit 30. For example, the processor 40 can be a central processing unit (CPU) or a system-on-chip (SoC).

[0073] The first baseband circuit 401 and the second baseband circuit 402 can be configured in Figure 2On the PCB14 shown, the first baseband circuit 401 and the second baseband circuit 402 can process digital signals, i.e., the low-frequency portion of the signal. The first baseband circuit 401 and the second baseband circuit 402 are used for digital signal processing, modulation and demodulation, channel coding, protocol management, etc., thereby enabling the extraction of required signal or data bits from the received baseband signal, or the conversion of information or data bits into baseband signals to be transmitted. These information or data bits can represent user data or control information such as voice, text, or video. For example, the first baseband circuit 401 and the second baseband circuit 402 may include a digital signal processor (DSP), a modem, a codec, etc.

[0074] For example, when the electronic device 100 supports two different communication methods, the first baseband circuit 401 and the second baseband circuit 402 described above can respectively process the baseband signals of the two different communication methods. For instance, the first baseband circuit 401 can process cellular communication baseband signals, and the second baseband circuit 402 can process short-range communication baseband signals. As another example, the first baseband circuit 401 can process cellular communication baseband signals, and the second baseband circuit 402 can process satellite communication baseband signals.

[0075] For example, when electronic device 100 supports three different communication methods (e.g., cellular communication, short-range communication, and satellite communication), the first baseband circuit 401 can process cellular communication baseband signals and satellite communication baseband signals, and the second baseband circuit 402 can process cellular communication baseband signals and short-range communication baseband signals. In this case, the low-frequency portion (e.g., <2GHz) of the cellular communication baseband signal can be fused with the satellite communication baseband signal into a single baseband circuit, such as the first baseband circuit 401. Furthermore, the high-frequency portion (e.g., ≥2GHz) of the cellular communication baseband signal can be fused with the short-range communication baseband signal into another baseband circuit, such as the second baseband circuit 402.

[0076] In this way, by segmenting the relatively wide-bandwidth cellular communication baseband signal and integrating it with different baseband signals into the same processing circuit, the number of baseband circuits can be reduced while the electronic device 100 supports three different communication methods, thus simplifying the structure. Furthermore, in some embodiments, the low-frequency portion of the cellular communication baseband signal processed by the first baseband circuit 401 can be the same as or approximately the same as the frequency band of the satellite communication baseband signal. Similarly, the high-frequency portion of the cellular communication baseband signal processed by the second baseband circuit 402 can be the same as or approximately the same as the frequency band of the short-range communication baseband signal. This allows the same baseband circuit to handle two different signals while reducing the performance requirements of the baseband circuit.

[0077] The above example illustrates the use of a processor 40 comprising two baseband circuits. In other embodiments of this application, the processor 40 may include one baseband circuit capable of handling two or more different communication methods. Alternatively, as... Figure 4 The processor 40 shown may include three baseband circuits: a first baseband circuit 401, a second baseband circuit 402, and a third baseband circuit 403. The first baseband circuit 401, the second baseband circuit 402, and the third baseband circuit 403 can respectively process cellular communication baseband signals, short-range communication baseband signals, and satellite communication baseband signals. This application does not limit the number of baseband circuits in the processor. Furthermore, when the electronic device 100 supports satellite positioning, Figure 3 and Figure 4 The second baseband circuit 402 shown can process satellite positioning baseband signals.

[0078] like Figure 4 The transceiver 50 shown can be connected to a baseband circuit, such as the first baseband circuit 401. The transceiver 50 has functions such as signal conversion, frequency conversion, power amplification and control, filtering and interference suppression, and an antenna interface. The transceiver 50 may include a transmit (TX) path and a receive (RX) path. The transmit path converts the baseband signal from the processor 40 into an analog signal using a digital-to-analog converter (DAC). Then, after up-conversion, amplification, and filtering, it is transmitted to the RF front-end circuit 30. Similarly, the receive path filters, amplifies, and down-converts the RF signal from the RF front-end circuit 30. Then, it converts the RF signal into a digital signal using an analog-to-digital converter (ADC) and transmits it to the baseband circuit coupled to the transceiver 50, such as the first baseband circuit 401.

[0079] Figure 3 and Figure 4 This example illustrates the concept of each baseband circuit being coupled to one transceiver 50. In other embodiments of this application, multiple baseband circuits may be connected to the same transceiver 50. This application does not limit the number of transceivers 50.

[0080] In addition, continue as Figure 4As shown, the RF front-end circuit 30 is used to filter, amplify, and perform other processing on the RF signal. For example, the RF front-end circuit 30 can amplify and filter the RF signal from the transceiver 50 and transmit it through the antenna radiator 20. Alternatively, the RF front-end circuit 30 can amplify and filter the RF signal received by the antenna radiator 20 to the operating range of the transceiver 50 and transmit it to the transceiver 50.

[0081] This application embodiment can provide an radio frequency chip 300, such as Figure 5 As shown, the RF chip 300 may include a package structure 301 and a bare die 302. The bare die 302 can be packaged within the package structure 301, and the bare die 302 may integrate [missing information - likely related to components or features]. Figure 3 or Figure 4 At least a portion of the radio frequency front-end circuit 30 shown. The radio frequency chip 300 described above can be sold as a single unit. For example, the package structure 301 described above may include a package cover 3011 and a package substrate 3012, with a receiving cavity formed between the package cover 3011 and the package substrate 3012 to accommodate the bare chip 302.

[0082] Alternatively, in some other embodiments, the bare chip 302 may also integrate Figure 3 The first baseband circuit 401, the second baseband circuit 402, and the transceiver 50 are shown. Alternatively, Figure 3 The first baseband circuit 401, the second baseband circuit 402, the transceiver 50, and the RF front-end circuit 30 shown can be integrated into different bare chips, and all of these bare chips are packaged in the same package structure 301. Alternatively, one of the first baseband circuit 401, the second baseband circuit 402, the transceiver 50, and the RF front-end circuit 30 can be integrated into one bare chip, and the other two circuits can be integrated into another bare chip. These different bare chips can be packaged in the same package structure 301. Alternatively, the first baseband circuit 401, the second baseband circuit 402, the transceiver 50, and the RF front-end circuit 30 can be integrated into different bare chips, and these bare chips are packaged in different package structures. The above are examples illustrating the integrated circuits within the bare chip 302, and this application does not limit this.

[0083] also, Figure 3 The antenna radiator 20 is a key component in the electronic device 100 for transmitting and receiving radio frequency (RF) signals. The antenna radiator 20 can radiate RF signals from the RF front-end circuit 30 into space, or receive RF signals from space and transmit them to the RF front-end circuit 30. For example, the antenna radiator 20 can be positioned in... Figure 2The exterior of the housing 11 shown can be, for example, in the form of a bracket antenna. Alternatively, the antenna radiator 20 can be disposed inside the housing 11. The antenna radiator 20 can be in the form of an antenna radiator based on a flexible printed circuit (FPC), an antenna radiator based on laser-direct-structuring (LDS), or a microstrip disk antenna (MDA), etc.

[0084] In one embodiment, the antenna radiator may also be a transparent or semi-transparent structure embedded within the display screen 10 of the electronic device, making it a transparent antenna element embedded within the display screen 10. Alternatively, when the frame portion of the middle frame 12 is a metal frame, the antenna radiator 20 may share a portion of the metal frame. The antenna radiator may also include slots or gaps formed on the metal frame, for example, closed or semi-closed slots or gaps formed on a grounded conductor surface. In one embodiment, a slotted or slit-shaped radiator may be simply referred to as a slot antenna or a gap antenna.

[0085] Impedance is a measure of the resistance of an antenna radiator 20 to an electrical signal. The input impedance of the antenna radiator 20 is related to factors such as the geometry, size, feed point location, operating wavelength, and surrounding environment of the antenna radiator 20. In some embodiments, the electronic device 100 may further include an impedance matching network circuit (…). Figure 3 (Not shown in the image). This impedance matching network circuit can be set between the RF front-end circuit 30 and the antenna radiator 20. This impedance matching network circuit can make the impedance between the RF front-end circuit 30 and the antenna radiator 20 match, so as to ensure that the signal can be transmitted efficiently between the two, reduce signal reflection, and improve transmission efficiency.

[0086] In order to enable the electronic device 100 and the radio frequency chip 300 provided in this application embodiment to support a variety of different communication methods, such as at least two of the above-mentioned cellular communication, satellite communication and short-range communication (or satellite positioning), the structure of the radio frequency front-end circuit 30 in the electronic device 100 and the radio frequency chip 300 will be described in detail below.

[0087] In some embodiments of this application, the radio frequency front-end circuit 30 described above may include, for example: Figure 6 The signal control circuit 3001 shown may include a controller 311 and a first switch S1. The controller 311 may include a first control signal input terminal CP1 and a second control signal input terminal CP2. Alternatively, in some embodiments, the controller 311 may also include an arbitration signal terminal ASP. The first switch S1 is coupled to the controller 311.

[0088] The first control signal input terminal CP1 and the second control signal input terminal CP2 transmit different types of data. For example, the first control signal input terminal CP1 can be a Mobile Industry Processor Interface (MIPI), and the data transmitted by this first control signal input terminal CP1 is a MIPI signal. The first control signal input terminal CP1 can be referred to as a MIPI port. The MIPI port can conform to the MIPI radio frequency front-end control interface (RFFE) protocol, which can define various configurable parameters, including clock frequency, data bit width, signal level, and transmission rate. Through flexible configuration of these parameters, the MIPI port can adapt to different operating conditions and device requirements, thus exhibiting various operating states. MIPI signals can include differential data (actual data) and clock data, etc.

[0089] The second control signal input terminal CP2 can be a general purpose input / output (GPIO) interface. The data transmitted by CP2 can be a GPIO signal, and CP2 can be referred to as a GPIO port, which features low latency. Furthermore, each pin of CP2 can independently input a high or low level, and the high and low levels output by these multiple pins can constitute a GPIO signal. The arbitration signal terminal ASP can transmit data of either a MIPI signal or a GPIO signal. In this embodiment, cellular communication RF signals can be matched with MIPI signals, short-range communication RF signals or satellite positioning RF signals can be matched with GPIO signals, and satellite communication RF signals can be matched with either MIPI signals or GPIO signals.

[0090] In this embodiment, matching the cellular communication radio frequency signal with the MIPI signal means that the MIPI signal can control the receiving link and transmitting link of the radio frequency front-end circuit 30 to transmit the cellular communication radio frequency signal. Matching the short-range communication radio frequency signal with the GPIO signal means that the GPIO signal can control the receiving link and transmitting link of the radio frequency front-end circuit 30 to transmit the short-range communication radio frequency signal. In other embodiments, the short-range communication radio frequency signal can be matched with both the MIPI signal and the GPIO signal. In this case, the GPIO signal can control a portion of the receiving link and a portion of the transmitting link of the radio frequency front-end circuit 30 to transmit the short-range communication radio frequency signal, and the MIPI signal can control another portion of the receiving link and another portion of the transmitting link of the radio frequency front-end circuit 30 to transmit the short-range communication radio frequency signal.

[0091] Furthermore, matching the satellite positioning radio frequency signal with the GPIO signal means that the GPIO signal can control the receiving link of the radio frequency front-end circuit 30 to transmit the satellite positioning radio frequency signal. Matching the satellite communication radio frequency signal with the MIPI signal or GPIO signal means that the MIPI signal or GPIO signal can control the receiving link and transmitting link of the radio frequency front-end circuit 30 to transmit the satellite communication radio frequency signal.

[0092] Alternatively, as another example, the first control signal input terminal CP1 may be a MIPI interface, and the second control signal input terminal CP2 may be a GPIO interface; this application does not limit this. For ease of explanation, the following examples will use the first control signal input terminal CP1 as a GPIO interface and the second control signal input terminal CP2 as a MIPI interface. Furthermore, this application does not limit the number of the first control signal input terminal CP1 and the second control signal input terminal CP2. The accompanying drawings are merely schematic diagrams of the first control signal input terminal CP1 and the second control signal input terminal CP2 and do not constitute a limitation on the number of the first control signal input terminal CP1 and the second control signal input terminal CP2.

[0093] Based on this Figure 6 The controller 311 shown can be used to output a first control signal Ctr1 based on the signal from the first control signal input terminal CP1. Alternatively, the controller 311 can output a second control signal Ctr2 based on the signal from the second control signal input terminal CP2. Alternatively, the controller 311 can be used to output the first control signal Ctr1 and the second control signal Ctr2 based on the signals from the first control signal input terminal CP1, the second control signal input terminal CP2, and the arbitration signal terminal ASP. The controller 311 is compatible with different interfaces, such as the first control signal input terminal CP1 (e.g., a MIPI interface) and the second control signal input terminal CP2 (e.g., a GPIO interface).

[0094] Furthermore, the first switch S1 may include at least a first radio frequency (RF) input terminal RFIN1 and a second RF input terminal RFIN2, which are used to receive different first and second RF signals, respectively. For example, in order for the signal control circuit 3001 to support cellular communication and short-range communication (or satellite positioning), the first RF signal from the first RF input terminal RFIN1 can be a cellular communication RF signal, and the second RF signal from the second RF input terminal RFIN2 can be a short-range communication RF signal or a satellite positioning RF signal.

[0095] Since cellular communication RF signals are matched with MIPI signals, and short-range communication RF signals or satellite positioning RF signals are matched with GPIO signals, the type of data transmitted at the first control signal input terminal CP1 (e.g., MIPI signal) can be matched with the first RF signal (e.g., cellular communication RF signal). That is, the type of data transmitted at the first control signal input terminal CP1 (e.g., MIPI signal) can control the receiving and transmitting links of the RF front-end circuit 30 to transmit the first RF signal (e.g., cellular communication RF signal). Similarly, the type of data transmitted at the second control signal input terminal CP2 (e.g., GPIO signal) can be matched with the second RF signal (e.g., short-range communication RF signal or satellite positioning RF signal). That is, the type of data transmitted at the second control signal input terminal CP2 (e.g., GPIO signal) can control the receiving and transmitting links of the RF front-end circuit 30 to transmit the second RF signal (e.g., short-range communication RF signal or satellite positioning RF signal).

[0096] Alternatively, as another example, in order for the signal control circuit 3001 to support cellular communication and satellite communication, the first radio frequency signal from the first radio frequency input terminal RFIN1 can be a cellular communication radio frequency signal, and the second radio frequency signal from the second radio frequency input terminal RFIN2 can be a satellite communication radio frequency signal.

[0097] At this time, the type of data transmitted at the first control signal input terminal CP1 (e.g., MIPI signal) can be matched with the first radio frequency signal (e.g., cellular communication radio frequency signal). The type of data transmitted at the second control signal input terminal CP2 (e.g., GPIO signal) or the type of data transmitted at the first control signal input terminal CP1 (e.g., MIPI signal) can be matched with the second radio frequency signal (e.g., satellite communication radio frequency signal). That is, the type of data transmitted at the second control signal input terminal CP2 (e.g., GPIO signal) or the type of data transmitted at the first control signal input terminal CP1 (e.g., MIPI signal) can control the receiving link and transmitting link of the radio frequency front-end circuit 30 to transmit the second radio frequency signal (e.g., satellite communication radio frequency signal).

[0098] For example, the first switch S1 can be a single-pole multi-throw (SPMT) switch, such as a single-pole two-throw (SP2T) switch. Alternatively, it can be a combination of multiple (e.g., two) single-pole single-throw (SPST) switches. Or, it can be a multi-pole multi-throw (MPMT) switch; this application is not limited to this. Taking the first switch S1 as an SP2T switch as an example, the SP2T can include two selectable terminals and one common terminal. The two selectable terminals are respectively coupled to the first RF input terminal RFIN1 and the second RF input terminal RFIN2. Figure 6 As shown, the first switch S1 may include a first gating terminal ST1, which may be coupled to the controller 311. The first gating terminal ST1 is used to receive a first control signal Ctr1 or a second control signal Ctr2.

[0099] Based on this, the first switch S1 is used to select either the first RF input terminal RFIN1 or the second RF input terminal RFIN2 according to the first control signal Ctr1 or the second control signal Ctr2. (Example provided.) Figure 6 As shown, the controller 311 is used to control the first switch S1 to select the first radio frequency input terminal RFIN1 according to the first control signal Ctr1. For example, the first switch S1 can couple the selectable terminal connected to the first radio frequency input terminal RFIN1 with the common terminal according to the first control signal Ctr1 from the controller 311, thereby selecting the first radio frequency input terminal RFIN1 so that the first radio frequency signal from the first radio frequency input terminal RFIN1 can be transmitted through the first switch S1 to other circuit structures or components coupled to the first switch S1.

[0100] Alternatively, controller 311 can control first switch S1 to select the second RF input terminal RFIN2 according to the second control signal Ctr2. For example, first switch S1 can couple the selectable terminal connected to the second RF input terminal RFIN2 to the common terminal according to the second control signal Ctr2 from controller 311, thereby selecting the second RF input terminal RFIN2 so that the second RF signal from the second RF input terminal RFIN2 can be transmitted through first switch S1 to other circuit structures or components coupled to the first switch S1.

[0101] Alternatively, the first switch S1 can, based on the second control signal Ctr2, couple the optional terminal connected to the first RF input terminal RFIN1 to the common terminal. The first switch S1 can, based on the first control signal Ctr2, couple the optional terminal connected to the second RF input terminal RFIN2 to the common terminal.

[0102] The above example illustrates that the first radio frequency signal is a cellular communication radio frequency signal, and the second radio frequency signal is a short-range communication radio frequency signal or a satellite positioning radio frequency signal. In other embodiments of this application, the first radio frequency signal can be a cellular communication radio frequency signal, and the second radio frequency signal can be a satellite communication radio frequency signal. Alternatively, the first radio frequency signal can be a satellite communication radio frequency signal, and the second radio frequency signal can be a short-range communication radio frequency signal or a satellite positioning radio frequency signal. Alternatively, the first radio frequency signal can be at least one of a cellular communication radio frequency signal and a satellite communication radio frequency signal, and the second radio frequency signal can be at least one of a cellular communication radio frequency signal, a short-range communication radio frequency signal, and a satellite communication radio frequency signal.

[0103] In comparison, in electronic devices provided by related technologies, the radio frequency (RF) front-end modules for different signals, such as cellular communication RF signals, satellite communication RF signals, and short-range communication RF signals, are typically set up independently. Different RF front-end modules are configured with interfaces matching the RF signals they need to receive and / or transmit, and the interfaces of the various RF front-end modules are incompatible. The signal control circuit 3001 provided in this application embodiment can realize the reception and / or transmission of at least two different signals (e.g., two of cellular communication RF signals, satellite communication RF signals, short-range communication RF signals, and satellite positioning RF signals), thus eliminating the need to independently configure RF front-end modules for receiving and / or transmitting different signals in the electronic device 100 and the RF chip 300. Furthermore, while supporting multiple communication frequency bands, the controller 311 in the signal control circuit 3001 can be compatible with different interfaces, such as the first control signal input terminal CP1 (e.g., MIPI interface) and the second control signal input terminal CP2 (e.g., GPIO interface), which reduces the complexity of the signal control circuit compared to the scheme of independently configuring different RF front-end modules.

[0104] The following provides examples illustrating the signal sources of the first control signal input terminal CP1, the second control signal input terminal CP2, or the arbitration signal terminal ASP. In some embodiments of this application, such as... Figure 7 As shown, in the case where the processor 40 of the electronic device 100 includes a first baseband circuit 401 and a second baseband circuit 402, the first baseband circuit 401 can be coupled at least to the first control signal input terminal CP1 of the controller 311, and the second baseband circuit 402 can be coupled at least to the second control signal input terminal CP2 of the controller 311. Furthermore, the processor 40 is also coupled to the arbitration signal terminal ASP, so that the processor 40 can provide an arbitration signal AS to the arbitration signal terminal ASP. Wherein, Figure 7The transceiver located between the processor 40 and the signal control circuit 3001 is omitted from the diagram; similar diagrams will not be described in detail below.

[0105] The first baseband circuit 401 being coupled at least to the first control signal input terminal CP1 of the controller 311 means, for example, that when the first baseband circuit 401 processes cellular communication baseband signals and the second baseband circuit 402 processes short-range communication baseband signals or satellite positioning baseband signals, the first baseband circuit 401 may be coupled only to the first control signal input terminal CP1, and the second baseband circuit 402 may be coupled only to the second control signal input terminal CP2. The first baseband circuit 401 may provide a MIPI signal to the first control signal input terminal CP1, and the second baseband circuit 402 may provide a GPIO signal to the second control signal input terminal CP2.

[0106] Or, for example, such as Figure 8 As shown, the first switch S1 may further include a third radio frequency (RF) input terminal RFIN3, which is used to receive a third radio frequency (RF) signal (e.g., a satellite communication RF signal). The third RF signal is different from both the first and second RF signals. At least one of the first control signal input terminal CP1 or the second control signal input terminal CP2 transmits data of a type that matches the third RF signal. For example, when the third RF signal is a satellite communication RF signal, it can be matched with a MIPI signal or a GPIO signal. The controller 311 is also used to control the first switch S1 to select the third RF input terminal RFIN3 of the first switch S1 according to the first control signal Ctr1 or the second control signal Ctr2. For example, the first switch S1 may be an SP2T switch. The SP2T may include three selectable terminals and one common terminal. The three selectable terminals are respectively coupled to the first RF input terminal RFIN1, the second RF input terminal RFIN2, and the third RF input terminal RFIN3.

[0107] Furthermore, when the first baseband circuit 401 processes cellular communication baseband signals and satellite communication baseband signals, and the second baseband circuit 402 processes cellular communication baseband signals and short-range communication baseband signals (or satellite positioning baseband signals), the first baseband circuit 401 can be coupled to the first control signal input terminal CP1 and the second control signal input terminal CP2, and the second baseband circuit 402 can be coupled to both the first control signal input terminal CP1 and the second control signal input terminal CP2. The first baseband circuit 401 can provide a MIPI signal to the first control signal input terminal CP1 and a GPIO signal to the second control signal input terminal CP2. The second baseband circuit 402 can provide a MIPI signal to the first control signal input terminal CP1 and a GPIO signal to the second control signal input terminal CP2.

[0108] The first baseband circuit 401 described above can provide at least a control signal matching the first radio frequency signal to the first control signal input terminal CP1, so that the controller 311 can control the transmit link and receive link in the signal control circuit 3001 to transmit and process the first radio frequency signal, thereby enabling the signal control circuit 3001 to achieve at least one of transmitting or receiving the first radio frequency signal. Similarly, the second baseband circuit 402 described above can provide at least a control signal matching the second radio frequency signal to the second control signal input terminal CP2, so that the controller 311 can control the transmit link and receive link in the signal control circuit 3001 to transmit and process the second radio frequency signal, thereby enabling the signal control circuit 3001 to achieve at least one of transmitting or receiving the second radio frequency signal.

[0109] Or for example, such as Figure 9 As shown, when the processor 40 includes a first baseband circuit 401 (for processing cellular communication baseband signals), a second baseband circuit 402 (for processing short-range communication radio frequency signals), and a third baseband processor 403 (for processing satellite communication radio frequency signals), since the cellular communication radio frequency signal is matched with the MIPI signal, the short-range communication radio frequency signal or satellite positioning radio frequency signal is matched with the GPIO signal, and the satellite communication radio frequency signal is matched with the MIPI signal or the GPIO signal, the first baseband circuit 401 can be coupled to the first control signal input terminal CP1, and the first baseband circuit 401 can provide the MIPI signal to the first control signal input terminal CP1. The second baseband circuit 402 can be coupled to the second control signal input terminal CP2, and the second baseband circuit 402 can provide the GPIO signal to the second control signal input terminal CP2. The third baseband circuit 403 can be coupled to the first control signal input terminal CP1 and the second control signal input terminal CP2, and the third baseband circuit 403 is used to provide the MIPI signal to the first control signal input terminal CP1 or the GPIO signal to the second control signal input terminal CP2.

[0110] In addition, continue as Figure 7 , Figure 8 or Figure 9 As shown, the controller 311 can decode the signals from the first control signal input terminal CP1, the second control signal input terminal CP2, and the arbitration signal terminal ASP, respectively, and output the decoded signal from the first control signal input terminal CP1 as the first control signal Ctr1. Alternatively, it can output the decoded signal from the second control signal input terminal CP2 as the second control signal CP2. In this case, the controller 311 can directly output the first control signal Ctr1 or the second control signal Ctr2 without arbitration by the arbitration signal (AS) from the arbitration signal terminal ASP.

[0111] For another example, controller 311 can output either a first control signal Ctr1 or a second control signal Ctr2 based on the decoded arbitration signal AS from the arbitration signal terminal ASP. In this case, the first control signal Ctr1 or the second control signal Ctr2 output by controller 311 needs to be arbitrated by the arbitration signal AS from the arbitration signal terminal ASP. The arbitration signal AS can determine, according to pre-set arbitration rules, which control signal Ctr1 or the second control signal Ctr2 can be prioritized as the control signal output.

[0112] In order for the controller 311 to decode the signals from the first control signal input terminal CP1, the second control signal input terminal CP2, and the arbitration signal terminal ASP, and to directly output the generated first control signal Ctr1 or second control signal Ctr2, or output according to the arbitration signal AS, in some embodiments of this application, such as Figure 10 As shown, the controller 311 may further include an interface circuit 3110 and a logic output circuit 3111. The interface circuit 3110 may be coupled to a first control signal input terminal CP1 and a second control signal input terminal CP2. The interface circuit 3110 is used to decode the signal from the first control signal input terminal CP1 into a first control signal Ctr1, and to decode the signal from the second control signal input terminal CP2 into a second control signal Ctr2.

[0113] Alternatively, interface circuit 3110 can also be coupled to arbitration signal terminal ASP. Interface circuit 3110 can decode the signal from arbitration signal terminal ASP into arbitration signal AS. In addition, logic output circuit 3111 can be coupled to interface circuit 3110. Logic output circuit 3111 is used to directly output the first control signal Ctr1 or the second control signal CP2, or to output the first control signal Ctr1 and the second control signal CP2 according to the arbitration signal AS.

[0114] In this way, the controller 311 can decode the signals from the first control signal input terminal CP1, the second control signal input terminal CP2, and the arbitration signal terminal ASP through the interface circuit 3110. The logic output circuit 3111 can directly output the first control signal Ctr1 or the second control signal CP2 generated after decoding to the controlled element, such as the first switch S1. Alternatively, the logic output circuit 3111 can output the first control signal Ctr1 or the second control signal CP2 to the controlled element, such as the first switch S1, after arbitration by the arbitration signal AS according to a preset control protocol. The preset control protocol can determine the data of the arbitration signal AS. This application does not limit the preset control protocol, and users can also define the above control protocol as needed.

[0115] The above example illustrates how the controller 311 outputs a first control signal Ctr1 or a second control signal Ctr2 based on the arbitration signal AS from the arbitration signal terminal ASP. In other embodiments of this application, the controller 311 may not need to set the arbitration signal terminal ASP, and the processor 40 (e.g., Figure 9 (As shown) Internally, arbitration can be performed before providing the MIPI signal to the first control signal input terminal CP1 or the GPIO signal to the second control signal input terminal CP2.

[0116] The structure of the interface circuit 3110 is illustrated below. In some embodiments of this application, the interface circuit 3110 may include, for example: Figure 11 The diagram shows a first decoder 31 and a second decoder 32. The first decoder 31 is coupled to a first control signal input terminal CP1 and is used to decode the signal from the first control signal input terminal CP1 into a first control signal Ctr1. The second decoder 32 is coupled to a second control signal input terminal CP2 and is used to decode the signal from the second control signal input terminal CP2 into a second control signal Ctr2.

[0117] Alternatively, the interface circuit 3110 may also include a third decoder 33, which is coupled to the arbitration signal terminal AS and is used to decode the signal from the arbitration signal terminal ASP into the arbitration signal AS. Furthermore, at least one of the first decoder 31, the second decoder 32, and the third decoder 33 may also store the decoded data.

[0118] As described above, in the example, the data transmitted at the first control signal input terminal CP1 is a MIPI signal. Based on this, in some embodiments, the first decoder 31 can be a serial-to-parallel decoder state machine. The first decoder 31 may have a voltage terminal VIO for providing a reference voltage, a clock signal terminal SCK for providing a clock signal, a data signal terminal SDA for providing data, and a ground terminal GND for grounding.

[0119] In the process of decoding the received signal, the first decoder 31 can convert the received serial signal into a parallel signal to realize the protocol conversion. Specifically, in the decoding process, various data and control information in the MIPI signal can be converted from their specific encoding format into a general format that can be understood and processed by other circuit structures in the signal control circuit 3001 (e.g., the first switch S1).

[0120] For another example, when decoding MIPI signals, controller 311 can perform data extraction and parsing. For instance, it can separate control signals mixed in the MIPI signal and used to control different circuit structures coupled to controller 311, so as to accurately transmit various control signals to the corresponding circuit structures or electronic devices. As yet another example, when decoding MIPI signals, controller 311 can recover the clock signal from the MIPI signal stream, providing an accurate clock reference for receiving data from various circuit structures of controller 311, ensuring correct data processing.

[0121] In addition, continue as Figure 11 As shown in the example, the data transmitted at the second control signal input terminal CP2 is of the type of GPIO signal. Based on this, in some embodiments, the second decoder 32 can be a level state machine, which can have multiple GPIO pins, each of which can be used to input a high level (e.g., 1) or a low level (e.g., 0).

[0122] The second decoder 32 can configure pin functions during the decoding of GPIO signals from the second control signal input terminal CP2. For example, when the first switch S1 has a GPIO pin, the GPIO pin can be configured as an input, output, or other special function. GPIO signal decoding can convert the GPIO signal from the second control signal input terminal CP2 into a specific setting for the function of the GPIO pin according to preset configuration information. As another example, the controller 311 can perform level conversion and adaptation when decoding GPIO signals. For example, circuit structures (e.g., the first switch S1) may use different level standards, and GPIO signal decoding can convert the logic level of the GPIO signal from the second control signal input terminal CP2 into a level that matches different circuit structures.

[0123] In addition, continue as Figure 11 As shown, the arbitration signal AS from the arbitration signal terminal APS can be a MIPI signal or a GPIO signal. For example, when the arbitration signal AS is a MIPI signal, the third decoder 33 can be a serial-to-parallel state machine. Alternatively, when the arbitration signal AS is a GPIO signal, the third decoder 33 can be a level-shifting state machine. The decoding process of the third decoder 33 is similar and will not be elaborated here. The above is only an example of GPIO signal or MIPI signal decoding and does not constitute a limitation on the above signal decoding. Other decoding processes will not be elaborated here.

[0124] The following are Figure 11The structure of the logic output circuit 3111 is illustrated by an example. As described above, the logic output circuit 3111 can output either the first control signal Ctr1 or the second control signal CP2 to the controlled element, such as the first switch S1, after arbitration by the arbitration signal AS according to a preset control protocol. Based on this, as... Figure 12 As shown, the logic output circuit 3111 may include: an inverter 34, at least one first buffer 35, and at least one second buffer 36.

[0125] The input terminal a1 of inverter 34 is coupled to the third decoder 33. Inverter 34 inverts the signal from input terminal a1 and outputs it from output terminal a2. For example, when the arbitration signal AS = 0 (i.e., low level), the input terminal a1 of inverter 34 is 0 (i.e., low level), and the output terminal a2 of inverter 34 is 1 (i.e., high level). Conversely, when the arbitration signal AS = 1 (i.e., high level), the input terminal a1 of inverter 34 is 1 (i.e., high level), and the output terminal a2 of inverter 34 is 0 (i.e., low level).

[0126] Based on this, the input terminal b1 of the first buffer 35 can be coupled to the first decoder 31, and the enable terminal En1 of the first buffer 35 is coupled to the input terminal a1 of the inverter 34. The first buffer 35 is used to be in an active or inactive state based on the signal of the enable terminal En1. When the first buffer 35 is in an active state, it can output a first control signal Ctr1; when the first buffer 35 is in an inactive state, there is no data output. The input terminal c1 of the second buffer 36 is coupled to the second decoder 32, and the enable terminal En2 of the second buffer 36 is coupled to the output terminal a2 of the inverter 34. The second buffer 36 is used to be in an active or inactive state based on the signal of the enable terminal En2. When the second buffer 36 is in an active state, it can output a second control signal Ctr1; when the second buffer 36 is in an inactive state, there is no data output.

[0127] As described above, the enable terminal En1 of the first buffer 35 and the enable terminal En2 of the second buffer 36 are respectively coupled to the input terminal a1 and the output terminal a2 of the inverter 34. Since the level of the arbitration signal AS received at the input terminal a1 of the inverter 34 is opposite to the level of the signal at the output terminal a2 of the inverter 34, when the first buffer 35 is in the working state to output the first control signal Ctr1, the second buffer 36 is in the non-working state and cannot output the second control signal Ctr2. Conversely, when the second buffer 36 is in the working state to output the second control signal Ctr2, the first buffer 35 is in the non-working state and cannot output the first control signal Ctr1. Therefore, by controlling the level of the arbitration signal AS received at the input terminal a1 of the inverter 34, the purpose of controlling the first buffer 35 to output the first control signal Ctr1 or the second buffer 36 to output the second control signal Ctr2 can be achieved.

[0128] Figure 12 This example illustrates the logic output circuit 3111, which includes a first buffer 35 and a second buffer 36. For instance, the output of either the first buffer 35 or the second buffer 36 can output 1 bit of data within a preset unit time. This 1 bit of data can be used as a state to control the controlled element, for example... Figure 11 The first switch S1 is shown. When the number of control states required by the first switch S1 increases, the logic output circuit 3111, as shown... Figure 13 The device may include N first buffers 35 or N second buffers 36, where N ≥ 1 and N is an integer. Each first buffer 35 or second buffer 36 can output 1 bit of data to increase the control state of the controlled element. This application does not limit the number of first buffers 35 and second buffers 36.

[0129] In this case, taking the first switch S1 as an example of the controlled element, in order for the logic output circuit 3111 to output the first control signal Ctr1 or the second control signal CP2 to the first selection terminal ST1 of the first switch S1 according to the arbitration signal AS, as follows: Figure 14 As shown, the first strobe terminal ST1 of the first switch S1 can be coupled to the output terminal b2 of the first buffer 35 and the output terminal c2 of the second buffer 36. The first strobe terminal ST1 is used to receive the first control signal Ctr1 or the second control signal CP2.

[0130] Taking the example that when the enable terminal En1 of the first buffer 35 and the enable terminal En2 of the second buffer 36 receive a high level (e.g., 1), the first buffer 35 and the second buffer 36 are in the above-mentioned working state, and when the above-mentioned enable terminal receives a low level (e.g., 0), they are in the above-mentioned non-working state, the example of the logic output circuit 3111 outputting the first control signal Ctr1 or the second control signal Ctr2 to the selection terminal of the first switch S1 according to the arbitration signal AS is used for illustration.

[0131] For example, continue as Figure 14 As shown, when the arbitration signal AS is high (e.g., 1), the input terminal a1 of the inverter 34 is high, and the enable terminal En1 of the first buffer 35 receives a high level, so the first buffer 35 is in the working state. At this time, the output terminal a2 of the inverter 34 is low (e.g., 0), and the enable terminal En2 of the second buffer 36 receives a low level, so the second buffer 36 is in the non-working state. Therefore, the second buffer 36 cannot output the second control signal Ctr2.

[0132] In this case, the first buffer 35 can decode the first decoder 31 to generate a first control signal Ctr1 (e.g., MIPI), and output it to the first selection terminal ST1 of the first switch S1. Under the control of the first control signal Ctr1, the first switch S1 can select the first radio frequency input terminal RFIN1 to transmit the first radio frequency signal (e.g., cellular communication radio frequency signal) from the first radio frequency input terminal RFIN1, or the third radio frequency signal (e.g., satellite communication radio frequency signal) from the third radio frequency input terminal RFIN3, through the first switch S1 to other circuit structures or components coupled to the first switch S1.

[0133] Or, continue as Figure 14 As shown, when the arbitration signal AS is low (e.g., 0), the input terminal a1 of the inverter 34 is low, the enable terminal En1 of the first buffer 35 receives a low level, and the first buffer 35 is in a non-operating state. At this time, the output terminal a2 of the inverter 34 is high (e.g., 1), the enable terminal En2 of the second buffer 36 receives a high level, the second buffer 36 is in an operating state, and therefore the second buffer 36 can output the second control signal Ctr2.

[0134] The second buffer 36 can decode the second decoder 32 to generate a second control signal Ctr2 (e.g., GPIO) and output it to the first selection terminal ST1 of the first switch S1. Under the control of the second control signal Ctr2, the first switch S1 can select the second RF input terminal RFIN2 to transmit the second RF signal (e.g., short-range communication RF signal or satellite positioning RF signal) from the second RF input terminal RFIN2, or the third RF signal (e.g., satellite communication RF signal) from the third RF input terminal RFIN3, through the first switch S1 to other circuit structures or components coupled to the first switch S1.

[0135] Furthermore, in other embodiments, such as Figure 15 As shown, the first strobe terminal ST1 of the first switch S1 can be coupled to the first decoder 31, and the first strobe terminal ST1 is used to receive the first control signal Ctr1. For example, the first strobe terminal ST1 of the first switch S1 can be directly coupled to the first decoder 31. Alternatively, the signal control circuit 3001 described above can also include at least one third buffer 37, which can be coupled between the first strobe terminal ST1 of the first switch S1 and the first decoder 31. The third buffer 37 can be in an active state, and while connecting the first strobe terminal ST1 and the first decoder 31, the third buffer 37 can reduce the impact of the electrical signal from the first decoder 31 on the first strobe terminal ST1, thereby improving the stability of the signal transmitted to the first strobe terminal ST1. In this case, the logic output circuit 3111 can directly output the first control signal Ctr1 to the first strobe terminal ST1 of the first switch S1 without relying on the arbitration signal AS.

[0136] Table 1

[0137]

[0138] For example, the first control signal Ctr1 is MIPI. For instance, the MIPI address of the first control signal Ctr1 can be Reg04 in the truth table Table 1, and when the 8 address bits in Reg04 (i.e., Reg[0], Reg[1]...Reg[7]) are 00000000, in the case that the first radio frequency signal is a cellular communication radio frequency signal and matches the MIPI signal, the aforementioned first control signal Ctr1 can control the first switch S1 to select the first radio frequency signal input terminal RFIN1, so that the first radio frequency signal (e.g., the cellular communication radio frequency signal) from the first radio frequency input terminal RFIN1 is transmitted through the first switch S1 to other circuit structures or components coupled to the first switch S1. Among them, the various data in Table 1 are only illustrative examples and do not constitute a limitation on the first control signal Ctr1 or the second control signal Ctr2.

[0139] Or, for example, Figure 15 The MIPI address of the first control signal Ctr1 shown can be Reg04 in Table 1. When the 8 address bits in Reg04 (i.e. Reg[0], Reg[1]...Reg[7]) are 00000010, and the third radio frequency signal is a satellite communication radio frequency signal that matches the MIPI signal, the first control signal Ctr1 can control the first switch S1 to select the third radio frequency signal input terminal RFIN3 so that the first radio frequency signal (e.g., satellite communication radio frequency signal) from the third radio frequency input terminal RFIN3 can be transmitted through the first switch S1 to other circuit structures or components coupled to the first switch S1.

[0140] Furthermore, when the second radio frequency signal is a short-range communication radio frequency signal (at least matching the MIPI signal), the aforementioned first control signal Ctr1 can control the first switch S1 to select the second radio frequency signal input terminal RFIN2, so that the second radio frequency signal (e.g., a short-range communication radio frequency signal) from the second radio frequency input terminal RFIN2 is transmitted through the first switch S1 to other circuit structures or components coupled to the first switch S1.

[0141] Alternatively, if the second RF signal is a short-range communication RF signal (matched with a GPIO signal), in order for the first switch S1 to select the second RF signal input terminal RFIN2, the first selection terminal ST1 of the first switch S1 can also be coupled to the processor 40, which can provide the aforementioned first control signal Ctr1 to the first selection terminal ST1 of the first switch S1. For example, the interface circuit 3110 may also include a fourth decoder 304, which can be coupled between the processor 40 and the first selection terminal ST1. The first decoder 31 is used to decode the signal from the processor 40 into the aforementioned first control signal Ctr1. For example, the fourth decoder 304 can be the aforementioned serial-to-parallel state machine.

[0142] Based on this, for example, the MIPI address of the first control signal Ctr1 can be Reg04 in Table 1, and when the 8 address bits in Reg04 (i.e. Reg[0], Reg[1]...Reg[7]) are 00000001, the first control signal Ctr1 can control the first switch S1 to select the second radio frequency signal input terminal RFIN2, so that the second radio frequency signal (e.g., short-range communication radio frequency signal) from the first radio frequency input terminal RFIN2 is transmitted through the first switch S1 to other circuit structures or components coupled to the first switch S1.

[0143] The above explanation uses the first control signal Ctr1 as an example of a MIPI signal. Therefore, based on the MIPI addresses in Table 1, the first control signal Ctr1 can be used to select the first RF signal input terminal RFIN1, the second RF signal input terminal RFIN2, and the third RF signal input terminal RFIN3 of the first switch S1. Since the second control signal Ctr2 is not used during the selection of the first switch S1, and Ctr2 is a GPIO signal, Figure 15 The four GPIO pins of the second decoder 32 shown, such as GPIO1, GPIO2, GPIO3 and GPIO4, are all in an unapplicable (NA) state as shown in Table 1.

[0144] Alternatively, in other embodiments, such as Figure 16 As shown, the first strobe terminal ST1 of the first switch S1 can be coupled to the second decoder 32, and the first strobe terminal ST1 is used to receive the second control signal Ctr2. Similarly, the first strobe terminal ST1 of the first switch S1 can be directly coupled to the second decoder 32. Alternatively, the above logic output circuit 3111 may also include at least one fourth buffer 38, which can be coupled between the first strobe terminal ST1 and the second decoder 32. The technical effect of the fourth buffer 38 is the same as that of the third buffer 37, and will not be described in detail here.

[0145] As described above, the second control signal Ctr2 is a GPIO signal. Therefore, when the second radio frequency signal is a short-range communication radio frequency signal (matched with the GPIO signal) and the third radio frequency signal is a satellite communication radio frequency signal (matched with the GPIO signal), the second control signal Ctr2 can control the first switch S1 to select the second radio frequency signal input terminal RFIN2. Alternatively, the second control signal Ctr2 can control the first switch S1 to select the third radio frequency signal input terminal RFIN3.

[0146] Furthermore, when the first radio frequency signal is a cellular communication radio frequency signal (at least matching a GPIO signal), the aforementioned second control signal Ctr2 can control the first switch S1 to select the first radio frequency signal input terminal RFIN1. Alternatively, when the first radio frequency signal is a cellular communication radio frequency signal (matching a MIPI signal), the process continues as follows: Figure 16As shown, in order for the first switch S1 to select the first radio frequency signal input terminal RFIN1, the first switch S1 can also be coupled to the processor 40, which can provide the aforementioned second control signal Ctr2 to the first selection terminal ST1 of the first switch S1. For example, the aforementioned logic output circuit 3111 can also include a fifth decoder 305, which can be coupled between the processor 40 and the first selection terminal ST1. The fifth decoder 305 is used to decode the signal from the processor 40 into the aforementioned second control signal Ctr2. For example, the fifth decoder 305 can be the aforementioned level-shifting state machine. In this way, the second control signal Ctr2 decoded by the fifth decoder 305 can control the first switch S1 to select the first radio frequency signal input terminal RFIN1.

[0147] Since the second control signal Ctr2 is a GPIO signal, it can be set... Figure 15 The states of the four GPIO pins of the second decoder 32 shown, such as GPIO1, GPIO2, GPIO3 and GPIO4, enable the second control signal Ctr2 to select the first RF signal input terminal RFIN1, the second RF signal input terminal RFIN2 and the third RF signal input terminal RFIN3 of the first switch S1.

[0148] Figure 14 , Figure 15 as well as Figure 16 This example illustrates the concept using M third buffers (37) and S fourth buffers (38). Where M ≥ 1, M is an integer; and S ≥ 1, S is an integer. This application does not limit the number of the third buffers (37) and fourth buffers (38). The example is as follows: Figure 12 As shown, the logic output circuit 3111 may include a third buffer 37 and a fourth buffer 38.

[0149] Furthermore, in some embodiments of this application, such as Figure 17 As shown, the signal control circuit 3001 may further include an RF amplifier 321. A first switch S1 may be coupled to the input terminal of the RF amplifier 321. The first switch S1 can be used to connect the first RF input terminal RFIN1 to the input terminal of the RF amplifier 321 to select the first RF input terminal RFIN1. The RF amplifier 321 is coupled to the controller 311, and the RF amplifier 321 can amplify the first RF signal (e.g., a cellular communication RF signal) under the control of a first control signal Ctr1 or a second control signal Ctr2.

[0150] Alternatively, the first switch S1 can be used to connect the second RF input terminal RFIN2 to the input terminal of the RF amplifier 321, thereby selecting the second RF input terminal RFIN2. The RF amplifier 321 can amplify the second RF signal (e.g., a short-range communication RF signal or a satellite positioning RF signal) under the control of the first control signal Ctr1 or the second control signal Ctr2. Alternatively, if the first switch S1 also includes a third RF input terminal RFIN3, the first switch S1 is used to connect the third RF input terminal RFIN3 to the input terminal of the RF amplifier 321, thereby selecting the third RF input terminal RFIN3. The RF amplifier 321 can amplify the third RF signal (e.g., a satellite communication RF signal) under the control of the first control signal Ctr1 or the second control signal Ctr2.

[0151] The aforementioned radio frequency amplifier 321 may include at least one amplifier. In some embodiments, the amplifier may be, for example, Figure 18 The power amplifier (PA) shown is used to couple to at least one antenna radiator 20. Figure 18 This example illustrates the connection between the output of the RF amplifier 321 and the three antenna radiators 20.

[0152] The aforementioned PA can amplify the power of cellular communication radio frequency signals from the first RF input terminal RFIN1, short-range communication radio frequency signals from the second RF input terminal RFIN2, or satellite communication radio frequency signals from the third RF input terminal RFIN3, respectively, to meet the transmission power requirements of the electronic device 100 and ensure reliable signal transmission over a certain distance. For example, the power of the cellular communication radio frequency signal can be amplified to be sufficient for effective communication with a base station. Alternatively, the power of the short-range communication radio frequency signal can be amplified to be sufficient for effective communication with nearby devices. Or, the power of the satellite communication radio frequency signal can be amplified to be sufficient for effective communication with a satellite.

[0153] For example, the PA may include a bias circuit and an amplifier circuit. The bias circuit may mainly include components such as variable resistors or transistors. The amplifier circuit may mainly include transistors for power amplification. The controller 311 provides a first control signal Ctr1 or a second control signal Ctr2 to the RF amplifier 321. The control signals can control the DC bias provided by the bias circuit in the RF amplifier 321 to the amplifier circuit, so that the transistors in the amplifier circuit operate in the optimal operating state, thereby meeting the performance indicators of the PA such as gain, frequency band, and linearity, and ensuring accurate signal amplification.

[0154] Based on this, in some embodiments, the first RF input terminal RFIN1, the second RF input terminal RFIN2, and the third RF input terminal RFIN3 of the first switch S1 can be coupled to the first baseband circuit 401, the second baseband circuit 402, and the third baseband circuit 403, respectively. When the first switch S1 connects the first RF input terminal RFIN1 to the output terminal of the PA, the first baseband circuit 401 can convert the processed cellular communication baseband signal into a first RF signal, i.e., a cellular communication RF signal, through the transceiver and transmit it to the PA. The PA amplifies the first RF signal and then transmits it through the antenna 20.

[0155] Similarly, when the first switch S1 connects the second RF input terminal RFIN2 to the output terminal of the PA, the second baseband circuit 402 can convert the processed short-range communication baseband signal into a second RF signal via the transceiver, i.e., the short-range communication RF signal is transmitted to the PA. The PA amplifies the second RF signal and then transmits it through the antenna 20. When the first switch S1 connects the third RF input terminal RFIN3 to the output terminal of the PA, the third baseband circuit 403 can convert the processed satellite communication baseband signal into a third RF signal via the transceiver, i.e., the satellite communication RF signal is transmitted to the PA. The PA amplifies the second RF signal and then transmits it through the antenna 20. The above three different RF input terminals can be coupled to different baseband circuits to receive RF signals of different standards, thereby simplifying the control logic of the circuit. Alternatively, in some other embodiments, the above three different RF input terminals can come from two different baseband circuits, which will not be elaborated here.

[0156] Figure 18 This illustration uses an electronic device 100 that includes an antenna 20 as an example. In other embodiments of this application, such as... Figure 19 As shown, the electronic device 100 may include multiple antenna radiators 20, and the electronic device 100 also includes a filtering circuit 330, which may include multiple filters. Different filters can filter signals of different frequency bands (e.g., cellular communication radio frequency signals, short-range communication radio frequency signals, and satellite communication radio frequency signals). In addition, the signal control circuit 3001 may also include a third switch S3 and a fourth switch S4.

[0157] Continue as Figure 19As shown, the third switch S3 can be coupled between the output of the RF amplifier 321 and the filter circuit 330. Furthermore, the third control terminal ST3 of the third switch S3 can be coupled to the controller 311. The third switch S3 is used to connect the output of the RF amplifier 321 to a filter in the filter circuit 330 according to the first control signal Crt1 or the second control signal Ctr2. In this way, the third switch S3 can select different signals from the output of the RF amplifier 321 (e.g., cellular communication RF signals, short-range communication RF signals, and satellite communication RF signals) to the filters in the filter circuit 330 capable of filtering those signals. The third switch S3 can be an SPMT or MPMT switch, or multiple SPST switches.

[0158] Furthermore, a fourth switch S4 can be coupled between the filter circuit 330 and the multiple antenna radiators 20. The fourth selector terminal ST4 of the fourth switch S4 can be coupled to the controller 311 to connect one of the filters in the filter circuit 330 to one of the antenna radiators 20 according to the first control signal Crt1 or the second control signal Ctr2. In this way, the fourth switch S4 can couple different signals from the output of the filter circuit 330 to at least one antenna for transmitting or receiving that signal. The fourth switch S4 can be an MPMT switch or multiple SPST switches.

[0159] The controller 311 outputs a first control signal Crt1 or a second control signal Ctr2 through the third selector terminal ST3 of the third switch S3 or the fourth selector terminal ST4 of the fourth switch S4 to select the path of the control of the third switch S3 or the fourth switch S4. The process of selecting the path of the control of the first switch S1 is the same as that of the control of the first switch S1, and will not be described in detail here.

[0160] The above example uses the amplifier PA in the RF amplifier 321 coupled to the first switch S1 as an example. In other embodiments of this application, such as Figure 20 As shown, the amplifier in the RF amplifier 321 coupled to the first switch S1 can be a low noise amplifier (LNA). Based on this, in some embodiments, the first RF input terminal RFIN1 of the first switch S1 can be coupled to the filter circuit 330. When the first switch S1 connects the filter circuit 330 to the input terminal of the LNA, the LNA can amplify and reduce the noise of the first RF signal (e.g., a cellular communication RF signal) received by the antenna radiator 20 and after being noise-reduced by the filter circuit 330.

[0161] Similarly, the second RF input terminal RFIN2 of the first switch S1 can be coupled to the third switch S3. In this case, the TX and RX filtering paths of the second RF signal (e.g., short-range communication RF signal or satellite positioning RF signal) can be shared. Alternatively, the second RF input terminal RFIN2 of the first switch S1 can be coupled to the filter circuit 330. When the first switch S1 connects the third switch S3 to the input terminal of the LNA, or connects the filter circuit 330 to the input terminal of the LNA, the LNA can amplify and reduce the noise of the second RF signal (e.g., short-range communication RF signal or satellite positioning RF signal) received by the antenna radiator 20 and after being denoised by the filter circuit 330.

[0162] The third RF input terminal RFIN3 of the first switch S1 can be coupled to the fourth switch S4. When the first switch S1 connects the fourth switch S4 to the input terminal of the LNA, the LNA can amplify and reduce the noise of the third RF signal (e.g., satellite communication RF signal) received by the antenna radiator 20, and then filter it through an external filter to reduce the impact on the LNA sensitivity. Alternatively, the third RF input terminal RFIN3 of the first switch S1 can be coupled to the filter circuit 330. When the first switch S1 connects the filter circuit 330 to the input terminal of the LNA, the LNA can amplify and reduce the noise of the third RF signal (e.g., satellite communication RF signal) received by the antenna radiator 20 and after being denoised by the filter circuit 330.

[0163] Similar to a power amplifier (PA), an low-frequency amplifier (LNA) can also include a bias circuit and an amplifier circuit. The controller 311 can provide the LNA with a first control signal Ctr1 or a second control signal Ctr2. These control signals can control the DC bias provided by the bias circuit to the amplifier circuit in the LNA, thereby meeting the LNA's performance specifications such as gain, frequency band, and linearity. Unlike a power amplifier (PA), an LNA can also include a noise reduction circuit.

[0164] The following uses a LAN as an example to illustrate the structure of the RF amplifier 321 and the process by which the controller 311 controls the LAN to amplify the received signal. In some embodiments of this application, such as... Figure 21As shown, when the type of data transmitted at the first control signal input terminal CP1 (e.g., MIPI signal) matches the first radio frequency signal (e.g., cellular communication radio frequency signal), and the type of data transmitted at the second control signal input terminal CP2 (e.g., GPIO signal) matches the second radio frequency signal (e.g., short-range communication radio frequency signal or satellite positioning radio frequency signal) and the third radio frequency signal (e.g., satellite communication radio frequency signal), the radio frequency amplifier 321 may include a first amplifier 3211 and a second amplifier 3212. Both the first amplifier 3211 and the second amplifier 3212 may be LNAs.

[0165] On this basis, continue as Figure 21 As shown, the first switch S1 connects the first RF input terminal RFIN1 and the input terminal of the first amplifier 3211. In this case, the first switch S1 can connect the first RF input terminal RFIN1 and the input terminal of the first amplifier 3211 under the control of the first control signal Ctr1. This allows the first amplifier 3211 to amplify the first RF signal from the first RF input terminal RFIN1, such as a cellular communication RF signal, under the control of the first control signal Ctr1. In this case, the first amplifier 3211 only needs to amplify one type of RF signal, such as a cellular communication RF signal, so the transmit power of the signal targeted by the first amplifier 3211 is the same, which helps to improve the power efficiency of the first amplifier 3211. This power efficiency refers to the ratio of the RF signal power output by the RF amplifier to the DC power input.

[0166] In addition, continue as Figure 21 As shown, the second amplifier 3212 includes a first input terminal IN1 and a second input terminal IN2. A first switch S1 connects the second RF input terminal RFIN2 and the third RF input terminal RFIN3 to the first input terminal IN1 and the second input terminal IN2, respectively. Under the control of a second control signal Ctr2, the first switch S1 can connect the second RF input terminal RFIN2 to the first input terminal IN1 of the second amplifier 3212. This allows the second amplifier 3212 to amplify a second RF signal, such as a short-range communication RF signal, from the second RF input terminal RFIN2 under the control of the second control signal Ctr2.

[0167] Furthermore, under the control of the second control signal Ctr2, the first switch S1 can connect the third RF input terminal RFIN3 to the second input terminal IN2 of the second amplifier 3212. This allows the second amplifier 3212 to amplify the third RF signal, such as a satellite communication RF signal, from the third RF input terminal RFIN3 under the control of the second control signal Ctr2. In this way, a single amplifier, namely the aforementioned second amplifier 3212, can amplify both the second RF signal (e.g., a short-range communication RF signal) and the third RF signal (e.g., a satellite communication RF signal), thereby reducing the number of amplifiers and simplifying the structure.

[0168] In addition, continue as Figure 21 As shown, the electronic device 100 may further include a fifth switch S5. This fifth switch S5 can be coupled to the output of the LNA. The fifth switch S5 may include a first radio frequency output terminal RFO1, a second radio frequency output terminal RFO2, and a third radio frequency output terminal RFO3. The first radio frequency output terminal RFO1, the second radio frequency output terminal RFO2, and the third radio frequency output terminal RFO3 are respectively used to output a first radio frequency signal (e.g., a cellular communication radio frequency signal), a second radio frequency signal (e.g., a short-range communication radio frequency signal or a satellite positioning radio frequency signal), and a third radio frequency signal (e.g., a satellite communication radio frequency signal). The fifth switch S5 can connect the first radio frequency output terminal RFO1, the second radio frequency output terminal RFO2, or the third radio frequency output terminal RFO3 to the output of the LNA.

[0169] The first RF output terminal RFO1, the second RF output terminal RFO2, and the third RF output terminal RFO3 can be coupled to the first baseband circuit 401, the second baseband circuit 402, and the third baseband circuit 403, respectively. In this way, the first RF output terminal RFO1, the second RF output terminal RFO2, and the third RF output terminal RFO3 can convert the noise-reduced first RF signal (e.g., cellular communication RF signal), the second RF signal (e.g., short-range communication RF signal or satellite positioning RF signal), and the third RF signal (e.g., satellite communication RF signal) into baseband signals via a transceiver and output them to the aforementioned different baseband circuits.

[0170] Furthermore, as described above, in order for the RF amplifier 321 to amplify the input RF signal as needed, such as... Figure 22As shown, the signal control circuit 3001 may further include a power switching circuit 340. This power switching circuit 340 may be coupled to the power supply terminal of the RF amplifier 321. Furthermore, the power switching circuit 340 is also coupled to the output terminal b2 of the first buffer 35 and the output terminal c2 of the second buffer 36. A controller 311 is coupled to the power switching circuit 340, and the controller 311 controls the power switching circuit 340 to provide a power supply voltage to the RF amplifier 321 according to a first control signal Ctr1 or a second control signal Ctr2.

[0171] In some embodiments of this application, when the RF amplifier 321 includes a first amplifier 3211 and a second amplifier 3212, the power switching circuit 340 can be coupled to the power supply terminal P1 of the first amplifier 3211 and the power supply terminal P2 of the second amplifier 3212. For example, in... Figure 21 When the first switch S1 connects the first RF input terminal RFIN1 and the input terminal of the first amplifier 3211, Figure 22 The arbitration signal AS shown can control the enable terminal En1 of the first buffer 35 to be high (e.g., 1) and control the enable terminal En2 of the second buffer 36 to be low (e.g., 0). When the first buffer 35 is operational, it can transmit the first control signal Ctr1 from the first decoder 31 to the power switching circuit 340. The power switching circuit 340 is used to provide a supply voltage matching the first control signal Ctr1 to the power supply terminal P1 of the first amplifier 3211.

[0172] Furthermore, when the first control signal Ctr1 used to control the power switching circuit 340 is a MIPI signal, if the MIPI address of the first control signal Ctr1 can be Reg10 in Table 1, and the eight address bits in Reg10 (i.e., Reg[0], Reg[1]...Reg[7]) are 00000000, the power switching circuit 340 provides a power supply voltage of 1.2V to the power supply terminal P1 of the first amplifier 3211 according to the first control signal Ctr1. The first amplifier 3211 can amplify the first radio frequency signal from the first radio frequency input terminal RFIN1, such as a cellular communication radio frequency signal.

[0173] Or, for example, in Figure 21 When the first switch S1 connects the third RF input terminal RFIN3 (or the second RF input terminal RFIN2) to the input terminal of the first amplifier 3211, Figure 22The arbitration signal AS shown can control the enable terminal En2 of the second buffer 36 to be high (e.g., 1) and control the enable terminal En1 of the first buffer 35 to be low (e.g., 0). When the second buffer 36 is operational, it can transmit the second control signal Ctr2 from the second decoder 32 to the power switching circuit 340. The power switching circuit 340 is used to provide a supply voltage matching the second control signal Ctr2 to the power supply terminal P2 of the second amplifier 3212.

[0174] Furthermore, when the second control signal Ctr2 used to control the power switching circuit 340 is GPIO, Figure 22 Of the four GPIO pins of the second decoder 32 shown, such as GPIO1, GPIO2, GPIO3, and GPIO4, as shown in Table 1, only GPIO4 is high (e.g., 1), while the other pins are in a no-level state (indicated by "×") and are in a floating state. At this time, the power switching circuit 340 provides a supply voltage of 2.5V to the power supply terminal P2 of the second amplifier 3212, matching the second control signal Ctr2. The second amplifier 3212 can amplify the third radio frequency signal from the third radio frequency input terminal RFIN3, such as a satellite communication radio frequency signal.

[0175] In this embodiment, the floating state can refer to a state where the pin of a circuit node or component is not connected to any defined potential reference point (such as ground) and is not connected to other nodes or power supplies with defined potentials, thus remaining in a suspended, unfixed potential state. Alternatively, in other embodiments, the power switching circuit 340 can provide a supply voltage (e.g., 1.2V) matching the second control signal Ctr2 to the power supply terminal P1 of the first amplifier 3211. Figure 22 Of the four GPIO pins of the second decoder 32 shown, such as GPIO1, GPIO2, GPIO3, and GPIO4, as shown in Table 1, only GPIO4 is low (e.g., 0), while the other pins are in a no-level state (represented by "×"). Furthermore, the power switching circuit 340 is used to provide a power supply voltage (e.g., 2.5V) matching the first control signal Ctr1 to the power supply terminal P2 of the second amplifier 3212. At this time, the MIPI address of the first control signal Ctr1 can be Reg10 in Table 1, and the eight address bits in Reg10 (i.e., Reg[0], Reg[1]...Reg[7]) are 00000001.

[0176] The power supply voltage provided by the power switching circuit 340 to the first amplifier 3211 and the second amplifier 3212 determines the linearity of the first amplifier 3211 and the second amplifier 3212. Furthermore, when the first amplifier 3211 and the second amplifier 3212 amplify the received radio frequency signal, it is related not only to the aforementioned linearity but also to the gain of the first amplifier 3211 and the second amplifier 3212. Based on this, in order to adjust the gain of the first amplifier 3211 and the second amplifier 3212, the following process continues... Figure 22 As shown, the first amplifier 3211 also has a bias position control terminal B1, and the second amplifier 3212 also has a bias position control terminal B2.

[0177] exist Figure 21 When the first switch S1 connects the first RF input terminal RFIN1 and the input terminal of the first amplifier 3211, as shown, Figure 22 As shown, the bias level control terminal B1 of the first amplifier 3211 can be coupled to the first decoder 31. For example, the bias level control terminal B1 of the first amplifier 3211 can be indirectly coupled to the first decoder 31 through the third buffer 37. The first decoder 31 can convert the signal from the first control signal input terminal CP1 (such as...) Figure 21 The signal (shown) is decoded to generate a first control signal Ctr1, which is directly transmitted to the bias level control terminal B1 of the first amplifier 3211 without going through the arbitration signal AS. Based on this, the first amplifier 3211 can be used to adjust the bias level according to the first control signal Ctr1, so as to achieve the purpose of adjusting the gain of the first amplifier 3211.

[0178] For example, when the first control signal Ctr1 received by the bias level control terminal B1 of the first amplifier 3211 is a MIPI signal, when the MIPI address of the first control signal Ctr1 is Reg05 in Table 1, and the 8 address bits in Reg05 (i.e., Reg[0], Reg[1]...Reg[7]) are 00000000, after the first amplifier 3211 adjusts the bias level according to the first control signal Ctr1, the gain of the first amplifier 3211 can reach the first level Gain0. At this time, the first amplifier 3211 adjusts the bias level from the first RF input terminal RFIN1 (e.g., Gain0) with the gain corresponding to the first level Gain0. Figure 21 The first radio frequency signal (shown) is amplified, such as a cellular communication radio frequency signal.

[0179] Alternatively, when the MIPI address of the first control signal Ctr1 is Reg05 in Table 1, and the 8 address bits in Reg05 (i.e., Reg[0], Reg[1]...Reg[7]) are 00000001, the gain of the first amplifier 3211 reaches the second level Gain1. When the MIPI address of the first control signal Ctr1 is Reg05 in Table 1, and the 8 address bits in Reg05 (i.e., Reg[0], Reg[1]...Reg[7]) are 00000010, the gain of the first amplifier 3211 reaches the third level Gain2. When the MIPI address of the first control signal Ctr1 is Reg05 in Table 1, and the 8 address bits in Reg05 (i.e., Reg[0], Reg[1]...Reg[7]) are 00000011, the gain of the first amplifier 3211 reaches the fourth level Gain3. Alternatively, when the MIPI address of the first control signal Ctr1 is Reg05 in Table 1, and the eight address bits in Reg05 (i.e., Reg[0], Reg[1]...Reg[7]) are 00000100, the gain of the first amplifier 3211 reaches the fifth level Gain4. Similarly, the first amplifier 3211 adjusts the gain corresponding to the second level Gain1, the third level Gain2, the fourth level Gain3, or the fifth level Gain4 from the first RF input terminal RFIN1 (e.g., ...). Figure 21 The first radio frequency signal (shown) is amplified, such as a cellular communication radio frequency signal.

[0180] The gains corresponding to the first gain level (Gain0), second gain level (Gain1), third gain level (Gain2), fourth gain level (Gain3), and fifth gain level (Gain4) mentioned above are different; for example, they can increase or decrease sequentially, and this application does not limit this. The number of gain levels and their corresponding address bits in Table 1 are merely illustrative examples and do not constitute a limitation on this application. Furthermore, during the adjustment of the gain of the first amplifier 3211, the second control signal Ctr2 is not used. The second control signal Ctr2 is a GPIO signal, therefore... Figure 21 The four GPIO pins of the second decoder 32 shown, such as GPIO1, GPIO2, GPIO3 and GPIO4, are all in the NA state as shown in Table 1.

[0181] In addition, Figure 21 When the first switch S1 connects the second RF input terminal RFIN2 and the input terminal of the second amplifier 3212, as shown, Figure 22As shown, the bias level control terminal B2 of the second amplifier 3212 is coupled to the second decoder 32. For example, the bias level control terminal B2 of the second amplifier 3212 can be indirectly coupled to the second decoder 32 through the fourth buffer 38. The second decoder 32 can convert the signal from the second control signal input terminal CP2 (such as...) Figure 21 The signal (shown) is decoded to generate a second control signal Ctr2, which is directly transmitted to the bias level control terminal B2 of the second amplifier 3212 without going through the arbitration signal AS. Based on this, the second amplifier 3212 can be used to adjust the bias level according to the second control signal Ctr2, so as to adjust the gain of the second amplifier 3212.

[0182] For example, when the second control signal Ctr2 received at the bias level control terminal B2 of the second amplifier 3212 is a GPIO signal, when Figure 22 As shown in Table 1, among the four GPIO pins of the second decoder 32, such as GPIO1, GPIO2, GPIO3, and GPIO4, when 000×, the second amplifier 3212 adjusts its bias level according to the second control signal Ctr2, so that the gain of the second amplifier 3212 reaches the first level Gain0. At this time, the second amplifier 3212 uses the gain corresponding to the first level Gain0 to adjust the bias level from the second RF input terminal RFIN2 (e.g., ...). Figure 21 The second radio frequency signal (as shown) is amplified, such as a short-range communication radio frequency signal. In the above "000×", "0" represents a low level, and "×" indicates that the pin is in a no-level state, meaning the pin can be in a floating state.

[0183] Or, when Figure 22 As shown in Table 1, among the four GPIO pins of the second decoder 32, such as GPIO1, GPIO2, GPIO3, and GPIO4, when 001×, the second amplifier 3212 is in Bypass mode. At this time, the signal from the second RF input terminal RFIN2 (e.g., ...) is... Figure 21 The second radio frequency signal (as shown) can pass directly through the second amplifier 3212 without adjusting the amplification gain. This enables direct signal transmission, avoiding the influence of the gain adjustment of the second amplifier 3212 on the signal. This allows for obtaining a relatively pure, unamplified original signal under specific conditions, such as in signal testing, calibration, or scenarios where the original signal characteristics need to be directly obtained for analysis.

[0184] Similarly, in Figure 21 When the first switch S1 connects the third RF input terminal RFIN3 and the input terminal of the second amplifier 3212, as shown, Figure 22 As shown, the bias level control terminal B2 of the second amplifier 3212 is coupled to the second decoder 32, and the second amplifier 3212 adjusts the bias level according to the second control signal Ctr2. For example, when the second control signal Ctr2 received by the bias level control terminal B2 of the second amplifier 3212 is a GPIO signal, when... Figure 22 As shown in Table 1, when the four GPIO pins of the second decoder 32, such as GPIO1, GPIO2, GPIO3, and GPIO4, are 0, 1, 0, or 0 respectively, the second amplifier 3212, after adjusting the bias level according to the second control signal Ctr2, can achieve the first level Gain0. At this time, the second amplifier 3212 uses the gain corresponding to the first level Gain0 to adjust the bias level from the third RF input terminal RFIN3 (e.g., ...). Figure 21 The third radio frequency signal (as shown) is amplified, such as a satellite communication radio frequency signal.

[0185] Or, when Figure 22 The second decoder 32, as shown in Table 1, has four GPIO pins, such as GPIO1, GPIO2, GPIO3, and GPIO4, respectively. When these pins are 0, 1, 1, or 1, the second amplifier 3212 is in Bypass mode. At this time, the signal from the third RF input terminal RFIN2 (e.g., ...) is transmitted through the GPIO pins. Figure 21 The third radio frequency signal (as shown) can be directly passed through the second amplifier 3212 without undergoing amplification gain adjustment.

[0186] As can be seen from the above, the first control signal Ctr1 was not used during the process of adjusting the gain of the second amplifier 3212. The first control signal Ctr1 is a MIPI signal. Therefore, during the process of adjusting the amplification gain of the second radio frequency signal, such as the short-range communication radio frequency signal, and the third radio frequency signal, such as the cellular communication radio frequency signal, in Table 1, the eight address bits (i.e., Reg[0], Reg[1]...Reg[7]) in the MIPI address of the first control signal Ctr1 are all in the NA state.

[0187] The above example illustrates the use of an RF amplifier 321 comprising two amplifiers, a first amplifier 3211 and a second amplifier 3212. The first amplifier 3211 amplifies a first RF signal (e.g., a cellular communication RF signal), and the second amplifier 3212 amplifies a second RF signal (e.g., a short-range communication RF signal or a satellite positioning RF signal) and a third RF signal (e.g., a satellite communication RF signal). In other embodiments of this application, the first amplifier 3211 amplifies the second RF signal (e.g., a short-range communication RF signal or a satellite positioning RF signal), and the second amplifier 3212 amplifies both the first RF signal (e.g., a cellular communication RF signal) and the third RF signal (e.g., a satellite communication RF signal). Alternatively, the first amplifier 3211 amplifies the third RF signal (e.g., a satellite communication RF signal), and the second amplifier 3212 amplifies both the first RF signal (e.g., a cellular communication RF signal) and the second RF signal (e.g., a short-range communication RF signal or a satellite positioning RF signal). This application does not limit the amplification of these embodiments.

[0188] The above example illustrates that the RF amplifier 321 includes two amplifiers, one of which, for example, the first amplifier 3211, can amplify one type of RF signal, and the other amplifier, for example, the second amplifier 3212, can amplify two other different RF signals. In other embodiments of this application, the RF amplifier 321 includes two amplifiers, both of which can amplify different RF signals.

[0189] For example, if the type of data transmitted at the first control signal input CP1 (e.g., MIPI signal) matches a first radio frequency signal (e.g., cellular communication radio frequency signal), the type of data transmitted at the second control signal input CP2 (e.g., GPIO signal) matches a second radio frequency signal (e.g., short-range communication radio frequency signal or satellite positioning radio frequency signal), and the type of data transmitted at either the first control signal input CP1 or the second control signal input CP2 matches a third radio frequency signal (e.g., satellite communication radio frequency signal), then... Figure 23 As shown, the RF amplifier 321 may include a third amplifier 3213 and a fourth amplifier 3214. Both the third amplifier 3213 and the fourth amplifier 3214 may be LNAs.

[0190] Continue as Figure 23As shown, the third amplifier 3213 may include a third input terminal IN3 and a fourth input terminal IN4. The first switch S1 connects the first RF input terminal RFIN1 and the third input terminal IN3 according to the first control signal Ctr1. This allows the third amplifier 3213 to amplify the high-frequency portion of the first RF signal (e.g., a cellular communication RF signal) from the first RF input terminal RFIN1 under the control of the first control signal Ctr1. Furthermore, the first switch S1 connects the second RF input terminal RFIN2 and the fourth input terminal IN4 according to the second control signal Ctr2. This allows the third amplifier 3213 to amplify the second RF signal (e.g., a short-range communication RF signal) from the second RF input terminal RFIN2 under the control of the second control signal Ctr2. Thus, the third amplifier 3213 can amplify both the high-frequency portion of the first RF signal (e.g., a cellular communication RF signal) and the second RF signal (e.g., a short-range communication RF signal). At this time, the high-frequency part of the cellular communication radio frequency signal can be the same as or similar to the frequency of the short-range communication radio frequency signal, which reduces the bandwidth requirement of the third amplifier 3213 and thus reduces the performance requirements of the third amplifier 3213.

[0191] In addition, such as Figure 23 As shown, the fourth amplifier 3214 may include a fifth input terminal IN5 and a sixth input terminal IN6. A first switch S1 is used to connect the first RF input terminal RFIN1 to the fifth input terminal IN5 according to a first control signal Ctr1. This allows the fourth amplifier 3214 to amplify the low-frequency portion of a first RF signal, such as a cellular communication RF signal, from the first RF input terminal RFIN1 under the control of the first control signal Ctr1. Furthermore, the first switch S1 is used to connect the third RF input terminal RFIN3 and the sixth input terminal IN6 according to either the first control signal Ctr1 or the second control signal Ctr2. This allows the fourth amplifier 3214 to amplify the third RF signal, such as a satellite communication RF signal, from the third RF input terminal RFIN3 under the control of either the first control signal Ctr1 or the second control signal Ctr2.

[0192] In this way, the fourth amplifier 3214 can amplify the first radio frequency signal, such as the low-frequency portion of a cellular communication radio frequency signal, and the third radio frequency signal, such as a satellite communication radio frequency signal. In this case, the low-frequency portion of the cellular communication radio frequency signal can be at the same or similar frequency as the satellite communication radio frequency signal, thus reducing the bandwidth requirements for the fourth amplifier 3214. Furthermore, when the satellite communication radio frequency signal is a low-Earth orbit (LEO) satellite communication radio frequency signal, the transmission power of the low-frequency portion of the cellular communication radio frequency signal can be the same or similar to the transmission power of the LEO satellite communication radio frequency signal, thereby reducing the performance requirements for the fourth amplifier 3214.

[0193] As described above, the first switch S1 can connect the first RF input terminal RFIN1 to the third input terminal IN3 of the third amplifier 3213 or the fifth input terminal IN5 of the fourth amplifier 3214. Alternatively, the first switch S1 can connect the second RF input terminal RFIN2 to the fourth input terminal IN4 of the third amplifier 3213, or connect the third RF input terminal RFIN3 to the sixth input terminal IN6 of the fourth amplifier 3214. Therefore, the first switch S1 can be an MTMP switch.

[0194] Similarly, such as Figure 24 As shown, the power switching circuit 340 can be coupled to the power supply terminal P3 of the third amplifier 3213 and the power supply terminal P4 of the fourth amplifier 3214. The power switching circuit 340 provides power supply voltage to the third amplifier 3213 and the fourth amplifier 3214 according to the first control signal Ctr1 or the second control signal Ctr2. The process for determining the linearity of the third amplifier 3213 and the fourth amplifier 3214 is similar and will not be repeated here. Furthermore, in order to adjust the gain of the third amplifier 3213 and the fourth amplifier 3214, the following steps are performed... Figure 24 As shown, the third amplifier 3213 also has a bias range control terminal B3, and the fourth amplifier 3214 also has a bias range control terminal B4.

[0195] like Figure 24 As shown, the bias level control terminal B3 of the third amplifier 3213 is coupled to the output terminal b2 of the first buffer 35 and the output terminal c2 of the second buffer 36. Based on this, in Figure 23 When the first switch S1 connects the first RF input terminal RFIN1 and the third input terminal IN3 of the third amplifier 3213, Figure 24 The arbitration signal AS shown can control the enable terminal En1 of the first buffer 35 to be high (e.g., 1) and control the enable terminal En2 of the second buffer 36 to be low (e.g., 0). When the first buffer 35 is operational, it can transmit the first control signal Ctr1 from the first decoder 31 to the bias level control terminal B3 of the third amplifier 3213. The third amplifier 3213 can be used to adjust the bias level according to the first control signal Ctr1, thereby adjusting the gain of the first amplifier 3211, and further amplifying the high-frequency portion of the cellular communication radio frequency signal from the first RF input terminal RFIN1.

[0196] Or, in Figure 23 When the first switch S1 connects the second RF input terminal RFIN2 and the fourth input terminal IN4 of the third amplifier 3213, Figure 24The arbitration signal AS shown can control the enable terminal En1 of the first buffer 35 to be low (e.g., 0) and control the enable terminal En2 of the second buffer 36 to be high (e.g., 1). The second buffer 36 is in an active state, thereby enabling the transmission of the second control signal Ctr2 from the second decoder 32 to the bias level control terminal B3 of the third amplifier 3213. The third amplifier 3213 can be used to adjust the bias level according to the second control signal Ctr2 to amplify the short-range communication radio frequency signal from the second RF input terminal RFIN2.

[0197] In addition, such as Figure 24 As shown, the bias level control terminal B4 of the fourth amplifier 3214 is coupled to the output terminal b2 of the first buffer 35 and the output terminal c2 of the second buffer 36. Based on this, in Figure 23 When the first switch S1 connects the first RF input terminal RFIN1 and the fifth input terminal IN5 of the fourth amplifier 3214, Figure 24 The arbitration signal AS shown can control the enable terminal En1 of the first buffer 35 to be high (e.g., 1) and control the enable terminal En2 of the second buffer 36 to be low (e.g., 0). When the first buffer 35 is operational, it can transmit the first control signal Ctr1 from the first decoder 31 to the bias level control terminal B4 of the fourth amplifier 3214. The fourth amplifier 3214 can be used to adjust the bias level according to the first control signal Ctr1 to amplify the low-frequency portion of the cellular communication radio frequency signal from the first RF input terminal RFIN1.

[0198] Or, in Figure 23 When the first switch S1 connects the third RF input terminal RFIN3 and the sixth input terminal IN6 of the fourth amplifier 3214, Figure 24 The arbitration signal AS shown can control the enable terminal En1 of the first buffer 35 to be low (e.g., 0) and control the enable terminal En2 of the second buffer 36 to be high (e.g., 1). The second buffer 36 is in an active state, thereby enabling the transmission of the second control signal Ctr2 from the second decoder 32 to the bias level control terminal B3 of the third amplifier 3213. The third amplifier 3213 can be used to adjust the bias level according to the second control signal Ctr2 to amplify the satellite communication radio frequency signal from the third RF input terminal RFIN3.

[0199] or, Figure 24The arbitration signal AS shown can control the enable terminal En1 of the first buffer 35 to be high (e.g., 1) and control the enable terminal En2 of the second buffer 36 to be low (e.g., 0). When the first buffer 35 is operational, it can transmit the first control signal Ctr1 from the first decoder 31 to the bias level control terminal B3 of the third amplifier 3213. The third amplifier 3213 can be used to adjust the bias level according to the first control signal Ctr1 to amplify the satellite communication radio frequency signal from the third RF input terminal RFIN3.

[0200] Figure 21 , Figure 22 , Figure 23 as well as Figure 24 This example illustrates the power supply and bias adjustment of the LNA using an LNA as an example in the RF amplifier 321. In other embodiments of this application, the amplifier in the RF amplifier 321 can be a PA. The process of the power switching circuit 340 supplying power to the PA according to the first control signal Ctr1 or the second control signal Ctr2, and adjusting the bias level of the PA according to the first control signal Ctr1 or the second control signal Ctr2, can be obtained similarly and will not be described again here.

[0201] As can be seen from the above, if Figure 25 As shown, the logic output circuit 3111 of the controller 311 can be coupled to a switch, an RF amplifier 321, and a power switching circuit 340. For example, the switch can be... Figure 19 The first switch S1, the third switch S3, or the fourth switch S4 coupled to PA are shown. As another example, the above switches can also be... Figure 20 The first switch S1, coupled to the LAN, is shown. The logic output circuit 3111 can output either the first control signal Ctr1 (a MIPI signal) from the first decoder 31 or the second control signal Ctr2 (a GPIO signal) from the second decoder 32 to... Figure 25 The switch, RF amplifier 321, and power switching circuit 340 are shown.

[0202] In addition, continue as Figure 25 As shown, the controller 311 can be integrated with at least one of the switch, the RF amplifier 321, and the power switching circuit 340. Figure 5 The controller 311 and at least one of the switches, RF amplifiers 321 and power switching circuits 340 are integrated into the same bare chip 302. Alternatively, the controller 311 and at least one of the switches, RF amplifiers 321 and power switching circuits 340 may be packaged in the same package structure, or they may be located in different packaged chips. This application does not limit this.

[0203] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A signal control circuit, characterized in that, include: The controller includes a first control signal input terminal and a second control signal input terminal; the first control signal input terminal and the second control signal input terminal transmit data of different types. The controller is configured to output a first control signal based on the signal at the first control signal input terminal, or to output a second control signal based on the signal at the second control signal input terminal; and, The first switch includes a first radio frequency (RF) input terminal and a second RF input terminal, which are respectively used to receive different first RF signals and second RF signals; the type of data transmitted by the first control signal input terminal matches the first RF signal, and the type of data transmitted by the second control signal input terminal matches the second RF signal; the first switch is coupled to the controller, and the first switch is used to select the first RF input terminal or the second RF input terminal according to the first control signal or the second control signal.

2. The signal control circuit according to claim 1, characterized in that, The controller also includes: An interface circuit is coupled to the first control signal input terminal and the second control signal input terminal; the interface circuit is used to decode the signal from the first control signal input terminal into the first control signal, and to decode the signal from the second control signal input terminal into the second control signal; and... A logic output circuit is coupled to the interface circuit, and the logic output circuit is used to output the first control signal or the second control signal.

3. The signal control circuit according to claim 2, characterized in that, The interface circuit includes: A first decoder, coupled to the first control signal input terminal, is used to decode the signal from the first control signal input terminal into the first control signal; and The second decoder, coupled to the second control signal input terminal, is used to decode the signal from the second control signal input terminal into the second control signal.

4. The signal control circuit according to claim 3, characterized in that, The controller further includes an arbitration signal terminal, and the interface circuit is also coupled to the arbitration signal terminal. The interface circuit is used to decode the signal from the arbitration signal terminal into an arbitration signal. The logic output circuit is also used to output the first control signal or the second control signal according to the arbitration signal. The interface circuit further includes a third decoder, which is coupled to the arbitration signal terminal and is used to decode the signal from the arbitration signal terminal into an arbitration signal.

5. The signal control circuit according to claim 4, characterized in that, The logic output circuit includes: The inverter has its input coupled to the third decoder; A first buffer, its input terminal coupled to the first decoder, and its enable terminal coupled to the input terminal of the inverter; the first buffer is used to output the first control signal according to the state of the enable terminal; and... The second buffer has its input terminal coupled to the second decoder, and its enable terminal coupled to the output terminal of the inverter; the second buffer is used to output the second control signal according to the state of the enable terminal.

6. The signal control circuit according to any one of claims 3-5, characterized in that, The first switch includes a first selection terminal; The first strobe terminal is coupled to the first decoder, and the first strobe terminal is used to receive the first control signal; or, the first strobe terminal is coupled to the second decoder, and the first strobe terminal is used to receive the second control signal. Alternatively, the first strobe terminal is coupled to the output terminal of the first buffer and the output terminal of the second buffer, and the first strobe terminal is used to receive the first control signal or the second control signal.

7. The signal control circuit according to any one of claims 1-6, characterized in that, The first switch further includes a third radio frequency input terminal, which is used to receive a third radio frequency signal; the third radio frequency signal is different from both the first radio frequency signal and the second radio frequency signal; at least one of the first control signal input terminal or the second control signal input terminal transmits data of a type that matches the third radio frequency signal; The first switch is also used to select the third radio frequency input terminal according to the first control signal or the second control signal.

8. The signal control circuit according to any one of claims 2-7, characterized in that, The signal control circuit also includes: A radio frequency amplifier is coupled to the controller; a first switch is coupled to the input terminal of the radio frequency amplifier; the first switch is used to connect the first radio frequency input terminal to the input terminal of the radio frequency amplifier to select the first radio frequency input terminal, or to connect the second radio frequency input terminal to the input terminal of the radio frequency amplifier to select the second radio frequency input terminal.

9. The signal control circuit according to claim 8, characterized in that, The first switch further includes a third radio frequency input terminal, which is used to receive a third radio frequency signal; the type of data transmitted by the second control signal input terminal is matched with the second radio frequency signal and the third radio frequency signal; The radio frequency amplifier includes: A first amplifier, wherein the first switch is configured to connect the first radio frequency input terminal to the input terminal of the first amplifier according to the first control signal; and, The second amplifier includes a first input terminal and a second input terminal; the first switch is used to connect the second radio frequency input terminal and the third radio frequency input terminal to the first input terminal and the second input terminal respectively according to the second control signal.

10. The signal control circuit according to claim 9, characterized in that, The bias level control terminal of the first amplifier is coupled to the first decoder, and the first amplifier is used to adjust the bias level according to the first control signal. The bias level control terminal of the second amplifier is coupled to the second decoder, and the second amplifier is used to adjust the bias level according to the second control signal.

11. The signal control circuit according to claim 8, characterized in that, The first switch further includes a third radio frequency input terminal, which is used to receive a third radio frequency signal; the type of data transmitted by the first control signal input terminal or the second control signal input terminal is matched with the third radio frequency signal; The radio frequency amplifier includes: A third amplifier includes a third input terminal and a fourth input terminal; a first switch is configured to connect the first radio frequency input terminal to the third input terminal according to the first control signal, and to connect the second radio frequency input terminal to the fourth input terminal according to the second control signal; and, The fourth amplifier includes a fifth input terminal and a sixth input terminal; the first switch is used to connect the first radio frequency input terminal to the fifth input terminal according to the first control signal, and to connect the third radio frequency input terminal to the sixth input terminal according to the first control signal or the second control signal.

12. The signal control circuit according to claim 11, characterized in that, The bias level control terminal of the third amplifier is coupled to the output terminal of the first buffer and the output terminal of the second buffer. The third amplifier is used to adjust the bias level according to the first control signal or the second control signal. The bias level control terminal of the fourth amplifier is coupled to the output terminals of the first buffer and the second buffer. The fourth amplifier is used to adjust the bias level according to the first control signal or the second control signal.

13. The signal control circuit according to any one of claims 8-12, characterized in that, The signal control circuit further includes a power switching circuit; the power switching circuit is coupled to the power supply terminal of the RF amplifier. The power switching circuit is also coupled to the output terminal of the first buffer and the output terminal of the second buffer. The power switching circuit is used to provide a power supply voltage to the RF amplifier according to the first control signal or the second control signal.

14. An electronic device, characterized in that, include: At least one antenna radiator; processor; The signal control circuit as described in any one of claims 1-13; The signal control circuit is coupled to the processor and the antenna radiator.

15. A controller, characterized in that, It includes a first control signal input terminal or a second control signal input terminal; the first control signal input terminal and the second control signal input terminal transmit different types of data; The controller is used to output a first control signal based on the signal at the first control signal input terminal, or to output a second control signal based on the signal at the second control signal input terminal; The first control signal input terminal is used to transmit Mobile Industry Processor Interface (MIPI) signals; The second control signal input terminal is used to transmit general purpose input / output (GPIO) signals.

16. The controller according to claim 15, characterized in that, The controller also includes: An interface circuit is coupled to the first control signal input terminal and the second control signal input terminal; the interface circuit is used to decode the signal from the first control signal input terminal into the first control signal, and to decode the signal from the second control signal input terminal into the second control signal; A logic output circuit is coupled to the interface circuit, and the logic output circuit is used to output the first control signal and the second control signal.

17. The controller according to claim 16, characterized in that, The controller further includes an arbitration signal terminal, and the interface circuit is also coupled to the arbitration signal terminal. The interface circuit is used to decode the signal from the arbitration signal terminal into an arbitration signal. The logic output circuit is also used to output the first control signal or the second control signal according to the arbitration signal.

18. The controller according to any one of claims 16-17, characterized in that, The controller is used to be coupled to the first switch, and the controller is used to control the first switch to select the first radio frequency input terminal of the first switch according to the first control signal, or the controller is used to control the first switch to select the second radio frequency input terminal of the first switch according to the second control signal; The first radio frequency input terminal and the second radio frequency input terminal are respectively used to receive different first radio frequency signals and second radio frequency signals; the type of data transmitted by the first control signal input terminal matches the first radio frequency signal, and the type of data transmitted by the second control signal input terminal matches the second radio frequency signal.

19. The controller according to any one of claims 16-18, characterized in that, The controller is used to couple with the radio frequency amplifier and to adjust the bias level of the radio frequency amplifier. or, The controller is used to couple with the power switching circuit, and the controller is used to control the power supply voltage provided by the power switching circuit to the RF amplifier.

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