A multi-target measurement and control signal processing architecture

Abstract

This invention discloses a multi-target telemetry and control signal processing architecture, belonging to the field of telemetry and control signal processing. It includes a scalable high-speed backplane, an integrated signal processing board, a parallel signal processing board, and a scheduling and control module. The integrated signal processing board samples, digitally down-converts, coarsely acquires, and separates the combined intermediate frequency (IF) signal, generating target data packets carrying target identifiers, sampling time markers, coarse frequency offset, coarse code phase, and baseband in-phase and quadrature data. The scheduling and control module allocates processing resources and generates a data routing table based on the target code rate, spreading parameters, and available processing capabilities of the target processing unit. When the target processing unit's processing capability is insufficient or the high-speed data channel is abnormal, it tracks the processing status at the target data packet boundary migration corresponding to a unified time reference and switches the data route. This architecture is also used to complete the encoding, spreading, modulation, combining, and IF output of multi-target remote control commands, improving the resource utilization and scalability of multi-target telemetry and control tasks.

Description

Technical Field

[0001] This invention belongs to the field of measurement and control signal processing technology, and in particular relates to a multi-target measurement and control signal processing architecture. Background Technology

[0002] With the mass deployment of low-Earth orbit satellite constellations and the increase in multi-spacecraft cluster test missions, a single mission needs to simultaneously complete the telemetry reception and remote control transmission of multiple targets. The signals from multiple targets are usually combined within the same radio frequency front-end or intermediate frequency channel, and the back-end processing equipment needs to complete the acquisition, tracking, despreading, decoding, and remote control command modulation of different target signals under a unified time reference.

[0003] Existing multi-target telemetry and control equipment typically uses independent intermediate frequency (IF) processing boards and baseband processing boards for each individual target. As the number of targets increases, complete IF and baseband processing links are required, leading to an increase in the number of devices, chassis space, power supply capacity, and interfaces. Furthermore, different boards need to switch signals via RF switch matrices or external communication interfaces, making task configuration and field maintenance quite complex.

[0004] Some devices incorporate multiple processing channels on a single programmable logic device (PLD), but the number of processing channels is limited by logic resources, storage resources, and the number of high-speed interfaces. When the target code rate, chip rate, number of related computational branches, and decoding method differ, the processing time and data bandwidth occupied by different targets vary significantly. Simply allocating processing channels evenly according to the number of targets can easily lead to situations where data queues increase on one board while another board still has idle resources.

[0005] In architectures employing multiple parallel processing boards, target signals are typically assigned to a fixed processing channel before the task begins. When processing load changes, high-speed data channels experience errors, or boards need to be decommissioned, existing processing methods often require re-execution of target acquisition and tracking, which can easily lead to telemetry data interruptions. Furthermore, if a unified capability registration, time synchronization, and task migration process is lacking when boards are added online, the newly added processing resources are difficult to directly utilize in the current task.

[0006] Therefore, it is necessary to develop a measurement and control signal processing architecture that can perform hierarchical processing of multiple target signals, allocate parallel processing resources according to the actual processing load, and migrate the target tracking processing status under a unified time reference. Summary of the Invention

[0007] In view of this, the present invention aims to propose a multi-target measurement and control signal processing architecture to at least solve one of the problems in the background art.

[0008] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0009] A multi-target measurement and control signal processing architecture includes a scalable high-speed backplane, an integrated signal processing board, at least one parallel signal processing board, and a scheduling and control module; the scalable high-speed backplane is equipped with a high-speed data channel, a time-frequency bus, and a management and configuration bus.

[0010] In telemetry receiving mode, the integrated signal processing board samples, digitally down-converts, coarsely acquires, and separates the combined intermediate frequency signal formed by multiple targets, and generates a target data packet for each target, carrying target identifier, sampling time marker, coarse frequency offset, coarse code phase, baseband in-phase data, and baseband quadrature data.

[0011] The parallel signal processing board is equipped with multiple target processing channels. Each target processing channel performs fine carrier tracking, fine code tracking, despreading, frame synchronization and decoding according to the corresponding target data packet.

[0012] The scheduling control module determines the correspondence between targets and target processing channels based on the task parameters of each target and the available processing capacity of each target processing channel, and generates a data routing table for the integrated signal processing board to execute.

[0013] When the processing capacity of the current target processing channel is insufficient, the scheduling control module determines the replacement target processing channel and the switching time marker. The switching time marker is aligned to the target data packet boundary according to the unified time reference provided by the time-frequency bus. The current target processing channel sends the tracking processing status of the corresponding target to the replacement target processing channel. The replacement target processing channel loads the tracking processing status and returns loading completion information. The integrated signal processing board sends the corresponding target data packet according to the updated data routing table starting from the switching time marker.

[0014] Furthermore, the scalable high-speed backplane has one integrated board slot and multiple parallel board slots; the integrated signal processing board and each of the parallel signal processing boards have independent high-speed data channels; the time-frequency bus is used to transmit reference clocks and second pulses to the integrated signal processing board and the parallel signal processing boards; the management configuration bus is used to read board identifiers, logic versions, temperature, voltage, current and high-speed data channel status, and to issue logic loading instructions, register configuration parameters and power supply control instructions.

[0015] Furthermore, the scheduling control module establishes a target task parameter table, a target processing channel capability table, and a processing time record table. The target task parameter table records the target's code rate, chip rate, number of related computation branches, decoding type, target data packet generation interval, and task priority. The target processing channel capability table records the number of available related computation branches, available decoding throughput, available storage capacity, and remaining bandwidth of the corresponding high-speed data channel for the target processing channel. The scheduling control module first completes the initial allocation based on the target task parameter table and the target processing channel capability table, and then adjusts the corresponding relationship based on the actual single-packet processing time in the processing time record table.

[0016] Furthermore, the target data packet also includes a data sequence number, a valid data length, and a check field; each routing record in the data routing table includes a target identifier, an output high-speed data channel identifier, a target processing channel identifier, a backup target processing channel identifier, a valid start time marker, and a valid end time marker; the integrated signal processing board matches valid routing records according to the target identifier and the sampling time marker, and checks the continuity and integrity of the target data packet according to the data sequence number and the check field.

[0017] Furthermore, each target processing channel records the entry time, start time, and completion time of the target data packet into the buffer. When the processing time of three consecutive target data packets for the same target is not less than the corresponding target data packet generation interval, and the number of unprocessed target data packets in the buffer increases within the three consecutive target data packet generation intervals, the scheduling control module determines that the corresponding target processing channel has insufficient processing capacity. When the high-speed data channel loses synchronization, the number of consecutive verification errors reaches the error count limit recorded in the link configuration table, the data sequence number is not continuous, or the transmission time is not less than the target data packet generation interval, the scheduling control module determines that the high-speed data channel is abnormal.

[0018] Furthermore, the tracking processing status includes the frequency control word and phase accumulation value of the carrier digitally controlled oscillator, the frequency control word and code phase of the code digitally controlled oscillator, the carrier loop filter status, the code loop filter status, the frame synchronization position, and the decoder internal status. After receiving the target migration instruction, the current target processing channel completes the target data packet being processed and stops reading new target data packets from the input buffer, forming a new status snapshot containing the tracking processing status. The new status snapshot also carries the last processed data sequence number and check field. The replacement target processing channel loads the new status snapshot and returns loading completion information. If the loading completion information is not received before the switching time marker, the scheduling control module postpones the switching time marker to the next target data packet boundary.

[0019] Furthermore, the integrated signal processing board sets up a circular buffer and a state backup area for each target. The circular buffer stores multiple recently received target data packets according to their data sequence numbers, and the state backup area stores state snapshots periodically sent by the target processing channel. When the current target processing channel fails to form and send a new state snapshot during target migration, the replacement target processing channel reads the most recent state snapshot of the corresponding target from the state backup area, and reads the target data packets after the data sequence number corresponding to the most recent state snapshot from the circular buffer, and restores the processing sequentially according to the data sequence number.

[0020] Furthermore, each of the parallel signal processing boards includes multiple programmable logic devices and memories respectively connected to the programmable logic devices; each programmable logic device is provided with multiple target state storage areas, input buffer areas, output buffer areas, correlation operation units, tracking loop operation units, and decoding units. Different target state storage areas respectively store the spreading code, carrier tracking state, code tracking state, frame synchronization state, decoding state, and cache address of the corresponding target; the programmable logic devices call the correlation operation units, the tracking loop operation units, and the decoding units in turn according to the data sequence number of the target data packet to process different targets.

[0021] Furthermore, in remote control transmission mode, the scheduling and control module allocates a target processing channel to each target; the target processing channel sequentially encodes, spreads, and modulates the remote control commands of the corresponding target using binary phase shift keying, generating a target transmission data packet carrying the target identifier, transmission time marker, data sequence number, baseband in-phase data, and baseband quadrature data; the integrated signal processing board performs sampling point alignment and digital combining of multiple target transmission data packets according to the transmission time marker, performs digital up-conversion and digital-to-analog conversion on the digitally combined signal, and outputs the combined intermediate frequency signal.

[0022] Furthermore, when a new parallel signal processing board is connected to the scalable high-speed backplane, the scheduling control module sequentially performs board identification, logic loading, high-speed data channel training, time-frequency synchronization, memory detection, and processing capability registration, and determines an activation time stamp for the new parallel signal processing board; the scheduling control module uses the new state snapshot and the target data packets in the circular buffer to migrate at least one target to the new parallel signal processing board; when a parallel signal processing board is scheduled to exit operation, the scheduling control module migrates the target processed by the corresponding parallel signal processing board to other parallel signal processing boards before shutting down the power supply to the corresponding parallel signal processing board.

[0023] Compared with existing technologies, the multi-target measurement and control signal processing architecture described in this invention has the following advantages:

[0024] (1) In this invention, the sampling, digital down-conversion, coarse acquisition, and target separation of the combined intermediate frequency signal are uniformly completed by the integrated signal processing board, while the fine tracking, despreading, and decoding of each target are completed by the parallel signal processing board. The intermediate frequency interface resources no longer increase with the number of targets, and the parallel signal processing board can be expanded according to the task scale, which is suitable for measurement and control tasks where the number of targets and the target code rate change.

[0025] (2) The present invention allocates processing resources based on the target task parameters, target processing channel capacity and single packet processing time recorded during operation. It can identify tasks with the same number of targets but different processing loads, and reduce idle processing resources or local queuing caused by average allocation. Attached Figure Description

[0026] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0027] Figure 1 This is a schematic diagram of a multi-target measurement and control signal processing architecture according to an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of target processing channel switching and tracking processing state transition according to an embodiment of the present invention.

[0029] Explanation of reference numerals in the attached figures

[0030] 100 - Integrated signal processing board; 110 - Intermediate frequency transceiver module; 120 - Analog-to-digital / digital-to-analog conversion module; 130 - First programmable logic processing module; 140 - Target data packet formation, circular buffer and state backup unit; 200 - Expandable high-speed backplane; 201 - Integrated board slot; 202 - Parallel board slot; 210 - High-speed data channel; 220 - Time and frequency bus; 230 - Management and configuration bus; 300 - Parallel signal processing board; 300-1 - First parallel signal processing board; 300-m - m-th parallel signal processing board; 310 - Target processing channel; 310A - Current target processing channel; 310B - Replacement target processing channel; 320 - Memory; 400 - Scheduling control module; 500 - Main control computer; 600 - External time and frequency source. Detailed Implementation

[0031] The following combination Figure 1 and Figure 2 The multi-target measurement and control signal processing architecture and target processing channel switching process of this embodiment are described.

[0032] The multi-target telemetry and control signal processing architecture of this embodiment includes a scalable high-speed backplane, a comprehensive signal processing board, two parallel signal processing boards, and a main control computer. The scheduling and control module is implemented using a combination of software and programmable logic. Task parameter management, resource allocation, and board status management programs run on the main control computer, while the data routing table execution logic, target data packet cyclic buffering, and time stamp generation logic are located on the comprehensive signal processing board. Figure 1 As shown, the task parameter management, resource allocation, and board status management programs of the scheduling control module 400 can run on the main control computer 500; the data routing table execution logic, target data packet cyclic buffering, and real-time logic for generating and executing switching time markers according to a unified time base are set on the integrated signal processing board 100. The main control computer 500 sends the routing table and switching configuration to the integrated signal processing board 100, and the integrated signal processing board 100 performs switching at the target data packet boundary according to the reference clock and second pulse provided by the time-frequency bus 220. Communication between the main control computer 500 and the board is allowed to have a delay, and the switching time marker reserves the protection time required for status transmission, status loading, and confirmation information transmission; if the loading completion information is not received before the switching time marker, the switching time marker is postponed to the next target data packet boundary.

[0033] exist Figure 1 In the integrated signal processing board 100, there are intermediate frequency transceiver modules 110, analog-to-digital / digital-to-analog converter modules 120, first programmable logic processing modules 130, and target data packet formation, circular buffer, and state backup units 140; the expandable high-speed backplane 200 includes an integrated board slot 201, a parallel board slot 202, a high-speed data channel 210, a time-frequency bus 220, and a management and configuration bus 230; the parallel signal processing board 300 is equipped with multiple target processing channels 310 (the current target processing channel 310A and the successor target processing channel 310B both belong to the target processing channels 310) and a memory 320; the scheduling control module 400 can be implemented by the main control computer 500 in cooperation with the logic on the board, and the external time-frequency source 600 provides a reference clock and second pulse to the time-frequency bus 220.

[0034] The scalable high-speed backplane features one integrated board slot and three parallel board slots. The integrated board slot connects to the integrated signal processing board, and the parallel board slots connect to parallel signal processing boards. Multiple high-speed serial differential channels are arranged between the integrated signal processing board and each parallel board slot; inserting or removing any parallel signal processing board does not alter the channel connections between the other parallel board slots and the integrated signal processing board. The backplane also includes reference clock lines, second pulse lines, management configuration lines, and board power supply lines.

[0035] The integrated signal processing board includes an intermediate frequency (IF) transceiver module, an analog-to-digital (ADC) converter module, a digital-to-analog (DAC) converter module, a first programmable logic processing (PLC) module, a data buffer, and a host communication interface. During telemetry reception, the IF transceiver module receives the combined IF signal output from the RF front-end; the ADC module outputs digital sampled data; and the first PLC module performs digital down-conversion, coarse target acquisition, target separation, and target data packet formation. During remote transmission, the first PLC module receives data packets transmitted from each target, performs sampling point alignment, digital combining, and digital up-conversion; and the ADC module outputs an analog IF signal.

[0036] The intermediate frequency (IF) transceiver module can be equipped with a multi-input combining circuit on the board or connected to an external RF combiner. In this embodiment, an external RF front-end down-converts four RF received signals and combines them into a single 70 MHz IF signal, which is then connected to the integrated signal processing board via an IF input interface. When using the on-board combining method, the multiple IF inputs are each connected to the on-board combining circuit, and the output of the combining circuit is connected to the analog-to-digital converter module. Neither of these connection methods alters the subsequent target coarse acquisition, target separation, and target data packet distribution processes.

[0037] Each parallel signal processing board has four programmable logic devices (PLDs), each connected to external memory. The board contains high-speed data interface logic, an input buffer, a target state storage area, a correlation operation unit, a carrier tracking operation unit, a code tracking operation unit, a frame synchronization unit, a decoding unit, and an output buffer. Each PLD can serve as one or more target processing channels; the number of channels is determined by the loaded logic version and target task parameters.

[0038] The main control computer connects to the integrated signal processing board via Ethernet, PCI bus, or other host interfaces. The main control computer reads the board registration information and task parameters, sends a data routing table to the integrated signal processing board, and sends the target spreading code, nominal carrier frequency, chip rate, code rate, modulation scheme, decoding scheme, and buffer address to the parallel signal processing board. The main control computer receives the decoding results, error statistics, and processing status of each target.

[0039] The time-frequency bus transmits a 10 MHz reference clock and a second pulse to the integrated signal processing board and each parallel signal processing board. Each board uses the reference clock to drive a local counter and corrects its local integer second mark when the second pulse arrives. The integrated signal processing board generates a sampling time stamp based on the sampling clock count value and writes the sampling time stamp into the target data packet. After receiving the target data packet, the parallel signal processing board checks the data packet order and data transmission time according to the sampling time stamp.

[0040] This embodiment uses a 64-bit time stamp. The high-order bits of the time stamp record the number of whole seconds accumulated since the task's start second pulse, while the low-order bits record the sampling clock count value within the current whole second. The integrated signal processing board and the parallel signal processing board read the local count value between two adjacent second pulses before the task begins. When the count value deviation is no greater than one reference clock cycle, the board's time status is marked as available; when the count value deviation exceeds one reference clock cycle, the scheduling control module stops allocating new targets to the corresponding board and re-executes clock locking and second pulse correction.

[0041] The management configuration bus includes a board presence detection line, a low-speed management bus, and a register configuration bus. After a board is inserted, the backplane first provides auxiliary power to the board management circuit. The management circuit then returns the board identifier, board type, logic version, number of programmable logic devices, external storage capacity, number of high-speed data channels, and supported decoding types. The scheduling control module establishes a board capability record based on the above information.

[0042] The board capability record includes board identifier, target processing channel identifier, number of available related computation branches, number of available carrier tracking units, number of available code tracking units, available decoding throughput, available storage capacity, high-speed data channel identifier, channel rated bandwidth, channel currently occupied bandwidth, logic version, and board operating status. Board temperature, voltage, and current are updated according to the management sampling cycle. When the temperature reaches the de-load temperature recorded in the board configuration file, the scheduling control module will no longer assign new targets to the corresponding board; when the temperature reaches the shutdown temperature, the scheduling control module will initiate target migration.

[0043] Before the high-speed data channel is enabled, transceiver reset, reference clock locking, word alignment, channel bonding, and verification data transmission are performed sequentially. The integrated signal processing board sends verification data packets with incrementing data sequence numbers to the parallel signal processing board, which returns the received sequence number and verification result. After receiving a specified number of correct verification data packets consecutively, the high-speed data channel status is marked as available. The specified number and the maximum allowed error count are recorded in the link configuration table, which is saved along with the board's logic version.

[0044] Before the task begins, the scheduling and control module establishes a target task parameter table. Each target corresponds to a task record, which includes the target identifier, nominal intermediate frequency, frequency search range, spreading code, chip rate, code rate, sampling rate, modulation scheme, decoding scheme, frame synchronization word, number of related operation branches, task priority, and output data address. The integrated signal processing board configures the digital down-conversion channel and coarse acquisition search range according to the target task parameter table.

[0045] Before the combined intermediate frequency (IF) signal enters the analog-to-digital (ADC) converter module, the automatic gain control (AGC) circuit adjusts the IF gain based on the amplitude statistics of the ADC output data, ensuring that the peak value of the sampled data is within the effective range of the ADC. The integrated signal processing board performs digitally controlled oscillation mixing and low-pass filtering on the sampled data to obtain combined baseband in-phase and quadrature baseband data. For targets with different nominal IF frequencies, the integrated signal processing board sets the digital down-conversion frequency for each. For targets using the same IF frequency but distinguished by different spreading codes, the integrated signal processing board performs correlation operations on the same digital down-conversion result using different spreading codes.

[0046] For any target, the integrated signal processing board calculates the correlation power at the frequency search point and the code phase search point. The correlation power can be determined according to the following formula:

[0047]

[0048] In the formula, This indicates the relevant power of the corresponding target; Indicates the frequency search point number; Indicates the sequence number of the phase search point; Indicates the first after digital down-conversion A complex number of sampling points; Indicates the number of sampling points involved in a single correlation operation; Indicates the first The frequency offset corresponding to each frequency search point; This indicates the sampling rate after digital down-conversion; Indicates the corresponding target spreading code in the th... The conjugate sequence at each code phase; It represents the imaginary unit.

[0049] The integrated signal processing board selects the location with the highest correlation power within the search region corresponding to each target. The frequency search point corresponding to the highest position is determined as the coarse frequency offset, and the code phase search point corresponding to the highest position is determined as the coarse code phase. The acquisition decision threshold is determined by the no-signal sampling segment before the mission begins. The integrated signal processing board performs the same correlation operation on the no-signal sampling segment, calculates the mean and standard deviation of the correlation power, and divides the no-signal sampling segment into sections with the same correlation integral length as the actual acquisition. A statistical window was used to obtain the relevant power. ; Based on the false alarm probability of the task Choice, make ,For example hour Let the mean of the above-mentioned related power be denoted as . Standard deviation is and will The relevant power values ​​are arranged in ascending order as follows: .make Capture decision threshold The corresponding threshold coefficient Therefore, The above statistics are calculated once before the mission begins; when the capture is re-executed, they are recalculated using a new no-signal sampling segment. The peak-to-peak ratio threshold of the maximum correlation power to the second-largest correlation power is written into the target mission parameter table and can be determined based on the noise sampling and target signal trial run results during the mission preparation phase; in this embodiment, it is set to 2.0.

[0050] Then, select the threshold coefficient according to the false alarm probability required by the task. When the maximum value of the relevant power reaches the acquisition decision threshold and the ratio of the maximum value to the second largest value reaches the peak ratio requirement recorded in the task parameter table, the corresponding target is marked as acquired.

[0051] After a target is marked as acquired, the integrated signal processing board performs carrier de-rotation on the combined baseband data according to the coarse frequency offset and aligns the spreading code according to the coarse code phase to obtain the baseband in-phase data and baseband quadrature data for the corresponding target. For targets using different spreading codes, the target separation result is output from the corresponding spreading code related branch; for targets using different subcarrier frequencies, the target separation result is output from the corresponding digital down-conversion branch. The integrated signal processing board saves the most recent coarse frequency offset and coarse code phase for each target and re-executes the search if the acquisition result fails.

[0052] The integrated signal processing board groups the baseband in-phase data and baseband quadrature data of each target according to a fixed number of sampling points. The target data packet generation interval for any target is determined by the following formula:

[0053]

[0054] In the formula, Indicates the target data packet generation interval for the corresponding target; This indicates the number of complex sampling points contained in a target data packet; This represents the baseband sampling rate of the corresponding target.

[0055] Each target data packet includes a fixed-length header and a variable-length data area. The header sequentially records the frame type, routing table version, target identifier, sampling time stamp, data sequence number, coarse frequency offset, coarse code phase, effective data length, data format, and checksum field. The data area is stored in the order of in-phase data first, followed by quadrature data, or alternatively, in-phase and quadrature data can be arranged alternately. The data format field records the quantization bits and arrangement of each component, enabling target processing channels with different logical versions to parse the same target data packet.

[0056] The data sequence number is reset to zero at the start of processing for each target and incremented sequentially. The sampling time marker corresponds to the first complex sampling point in the data area. After the integrated signal processing board completes the target data packet, it first writes it to the corresponding target's circular buffer, and then sends it to the target processing channel according to the currently valid data routing table. The circular buffer stores at least all target data packets from the data sequence number corresponding to the most recent state snapshot to the current data sequence number, and releases earlier data packets after the new state snapshot passes verification.

[0057] For ease of explanation, the main fields of the target data packet header in this embodiment are shown in the table below.

[0058]

[0059] Before a task begins, the scheduling control module reads the target task parameter table, the target processing channel capability table, and the processing time record table. The initial reference processing time in the processing time record table is generated through board factory testing or trial operation during the task preparation phase. The processing time record table records the reference processing time for a target data packet according to the programmable logic device model, logic version, chip rate range, code rate range, number of related operation branches, and decoding method. The scheduling control module uses the reference processing time to complete the initial allocation and replaces the reference processing time with the actual single-packet processing time after the task starts.

[0060] The processing load of any target under the current processing configuration is determined by the following formula:

[0061]

[0062] In the formula, This indicates the processing load for the corresponding target; This indicates the actual or reference processing time required for the target processing channel to process one target data packet corresponding to the target. This indicates the target data packet generation interval for the corresponding target.

[0063] When a target processing channel handles multiple targets, the total processing load of the target processing channel is determined by the following formula:

[0064]

[0065] In the formula, This indicates the total processing load of the corresponding target processing channel; This represents the set of targets assigned to the corresponding target processing channel; This represents the processing load of any target within the target set.

[0066] The scheduling control module begins allocation to targets with higher processing loads. For each target, the module sequentially checks the relevant computational branches, decoding type, storage capacity, remaining bandwidth of the high-speed data channel, and total processing load of the candidate target's processing channel. The total processing load of the target processing channel after target allocation should not exceed the upper limit of the operating load recorded in the processing capacity table. The upper limit of the operating load is less than the full load value to reserve processing margins required for high-speed data channel jitter, decoding operation fluctuations, and state transitions.

[0067] The total length of the target data packet consists of a fixed-length header and baseband sampled data. In this embodiment, the bandwidth occupied by the corresponding high-speed data channel is determined by the ratio of the total number of bits in the target data packet to the target data packet generation interval. The total number of bits in the target data packet and the occupied bandwidth satisfy the following relationships:

[0068]

[0069]

[0070] In the formula, Indicates the total number of bits in the corresponding target data packet; Indicates the number of bits in the header of the corresponding target data packet; Indicates the number of quantization bits for the in-phase or quadrature components of the corresponding target; This indicates the number of complex sampling points contained in a target data packet; This indicates the high-speed data channel bandwidth occupied by the corresponding target; This indicates the target data packet generation interval for the corresponding target.

[0071] When multiple allocation results meet the requirements for processing load, storage capacity, and high-speed data channel bandwidth, the scheduling control module prioritizes the allocation result with fewer parallel signal processing boards to be put into operation, and reserves at least one backup target processing channel when available resources permit. For targets with higher task priority, the backup target processing channel should be set on different parallel signal processing boards to reduce the impact of a single parallel signal processing board failure on high-priority targets.

[0072] The scheduling and control module generates a data routing table based on the final allocation results. Each routing record includes a target identifier, an output high-speed data channel identifier, a target processing channel identifier, a backup target processing channel identifier, a routing table version, a valid start time marker, and a valid end time marker. The integrated signal processing board simultaneously stores the current routing table and the routing table to be activated. The routing table to be activated does not participate in the distribution of target data packets before its corresponding valid start time marker arrives, preventing different boards from changing processing channels midway for the same target data packet.

[0073] After the integrated signal processing board generates the target data packet, it looks up the routing record based on the target identifier and then compares the sampling timestamp with the valid time range of the routing record. If the sampling timestamp is within the valid time range of the current routing record, the target data packet is sent to the current target processing channel; if the sampling timestamp reaches the valid start timetamp of the routing record to be activated, the target data packet is sent to the succeeding target processing channel. The routing table version is written to the target data packet header, and the target processing channel uses this to check whether the received target data packet uses the correct routing table.

[0074] After receiving a target data packet, the target processing channel first checks the target identifier, data sequence number, valid data length, routing table version, and verification field. If the verification passes, the target data packet is written to the input buffer. If the data sequence number is discontinuous, the target processing channel reports the missing data sequence number to the scheduling control module; if the integrated signal processing board still has the corresponding target data packet in the circular buffer, it retransmits the missing target data packet.

[0075] The target processing channel uses the coarse frequency offset and coarse code phase from the target data packet to set the initial values ​​of the carrier numerically controlled oscillator (CNC oscillator) and the code numerically controlled oscillator (CNC oscillator). For binary phase shift keying (BPSK) signals, carrier tracking can employ a Costas loop, and code tracking can employ a code tracking loop formed by a leading correlation branch and a lagging correlation branch. The correlation operation unit performs despreading based on the spreading code and the number of correlation operation branches in the target task parameter table, and the tracking loop operation unit updates the carrier CNC oscillator and the code CNC oscillator based on the correlation results.

[0076] After despreading, the symbol data enters bit synchronization and frame synchronization processing. The frame synchronization unit searches for the frame synchronization word recorded in the target task parameter table in the despread data, and outputs the frame boundary after the synchronization positions of consecutive frames satisfy the frame length relationship. The decoding unit performs Viterbi decoding, Reed-Solomon decoding, or other channel decoding specified by the task according to the decoding method recorded in the target task parameter table. The decoding result carries the target identifier, the data sequence number range of the corresponding target data packet, the frame time stamp, and the decoding status, and is transmitted back to the integrated signal processing board via the high-speed data channel.

[0077] Each target processing channel has an independent target state storage area for each target it processes. The target state storage area stores the spreading code address, the frequency control word and phase accumulation value of the carrier digitally controlled oscillator, the frequency control word and code phase of the code digitally controlled oscillator, the delay values ​​of each stage of the carrier loop filter, the delay values ​​of each stage of the code loop filter, the frame synchronization position, the current intra-frame position, the decoder internal state, the input buffer read address, the output buffer write address, and the last processed data sequence number.

[0078] When a single programmable logic device (PLD) processes multiple low-code-rate targets, it selects the target to be processed according to the arrival order of the target data packets and the task priority. Before starting to process a target, the PLD loads the tracking state and cache address from the corresponding target state storage area; after completing a target data packet, it writes the updated tracking state and cache address back to the corresponding target state storage area before processing the next target. The correlation operation unit, tracking loop operation unit, and decoding unit are shared among different targets, and the target state storage area maintains the processing state of different targets independently.

[0079] The target processing channel records the time each target data packet enters the input buffer, the start time of processing, and the completion time of processing. The single packet processing time is obtained by subtracting the start time from the completion time, and the queuing time is obtained by subtracting the entry time into the buffer from the start time. After processing each target data packet, the target processing channel sends the single packet processing time, queuing time, number of unprocessed target data packets, remaining input buffer capacity, and the sequence number of the last processed data packet to the scheduling control module.

[0080] The target processing channel sends status snapshots to the integrated signal processing board according to the status backup cycle. The status backup cycle can be determined based on the number of target data packets, for example, a status snapshot is formed every eight target data packets processed; for targets with higher task priority or shorter target data packet generation intervals, the status backup cycle can be shortened. The status snapshot includes the target identifier, status version, data sequence number corresponding to the status, tracking processing status, status data length, and verification field. The integrated signal processing board only updates the status backup area when the verification passes and the data sequence number corresponding to the status is later than the existing backup.

[0081] The scheduling control module checks the operation record of the target processing channel according to the target data packet generation interval. The single-packet processing ratio of any target data packet is determined by the single-packet processing time of the corresponding target data packet and the target data packet generation interval. A single-packet processing ratio of not less than one indicates that the time required for the target processing channel to process one target data packet has reached or exceeded the arrival interval of the next target data packet.

[0082] To avoid frequent migrations caused by fluctuations in a single decoding operation, this embodiment uses both continuous processing time and cache changes to determine insufficient processing capacity. When the processing time of a single packet for three consecutive target data packets of the same target is not less than the target data packet generation interval, and the number of unprocessed target data packets increases within each of the three consecutive target data packet generation intervals, the scheduling control module marks the corresponding target processing channel as having insufficient processing capacity. For targets with long decoding blocks in their tasks, the number of consecutive observations can be increased based on the number of target data packets contained in the decoding block. The number of consecutive observations is recorded in the target task parameter table.

[0083] The status of a high-speed data channel is determined by transceiver synchronization status, parity error count, data sequence number continuity, and transmission time. A high-speed data channel is immediately marked as abnormal when it loses word alignment or channel bonding. It is also marked as abnormal when the number of consecutive parity errors reaches the error count limit recorded in the link configuration table, even if the high-speed data channel remains synchronized. Furthermore, if the integrated signal processing board has sent a target data packet but the target processing channel fails to acknowledge receipt within one target data packet generation interval, or if the data sequence number reported by the target processing channel is inconsistent with the sent sequence number, the corresponding high-speed data channel will also be marked as abnormal.

[0084] The scheduling control module selects a replacement target processing channel from the target processing channel capability table. The replacement target processing channel should support the same modulation scheme and decoding method, and have sufficient related computation branches, storage capacity, and remaining bandwidth in the high-speed data channel. The scheduling control module also compares the temperature and power supply status of the parallel signal processing board where the replacement target processing channel is located. If multiple candidate channels meet the requirements, the candidate channel located on a different parallel signal processing board than the current target processing channel and with a lower total processing load is preferentially selected.

[0085] After determining the target processing channel to be replaced, the scheduling control module determines the switching time marker based on a unified time base. The time difference between the switching time marker and the task start time should be an integer multiple of the target data packet generation interval, satisfying the following formula:

[0086]

[0087] In the formula, Indicates the switching time marker for the corresponding target; Indicates the start time of the target data packet for the corresponding target in the current task; Represents a non-negative integer; This indicates the target data packet generation interval for the corresponding target.

[0088] The switching time stamp should also reserve time for status transmission, status loading, and acknowledgment information transmission.

[0089]

[0090] In the formula, This indicates the time taken to complete the target parameter configuration and input buffer allocation after taking over the target processing channel; This indicates the protection time required for status transmission, status loading, and acknowledgment information transmission. The protection time is determined based on the high-speed data channel transmission time and the board's internal status loading time, and is recorded in the board capability table.

[0091] The scheduling control module generates a route record to be activated and sends it to the integrated signal processing board, the current target processing channel, and the successor target processing channel. The valid end time stamp of the current route record is set to the switching time stamp, and the valid start time stamp of the route record to be activated is set to the same switching time stamp. The integrated signal processing board continues to send target data packets to the current target processing channel until the switching time stamp arrives.

[0092] like Figure 2 As shown, after receiving the target migration command, the current target processing channel completes the target data packet it is currently processing and stops reading new target data packets from the input buffer. It then uses the sequence number of the completed target data packet as the last processed data sequence number to form a state snapshot. Unprocessed target data packets in the input buffer with sequence numbers greater than this last processed data sequence number are no longer processed by the current target processing channel. Instead, the integrated signal processing board retransmits them to the succeeding target processing channel according to the data sequence number in the circular buffer. It then stops reading new data from the input buffer and reads the tracking processing status from the target state storage area. The current target processing channel encapsulates the target identifier, state version, last processed data sequence number, carrier tracking status, code tracking status, frame synchronization status, decoder internal status, and check field into a state snapshot, which is then sent to the succeeding target processing channel via the high-speed data channel.

[0093] After receiving the status snapshot, the replacement target processing channel first checks the target identifier, status version, last processed data sequence number, and verification field, then writes each status field to the corresponding target status storage area. The replacement target processing channel sets the next expected data sequence number to the last processed data sequence number recorded in the status snapshot plus one, and returns loading completion information. Based on this last processed data sequence number, the integrated signal processing board retransmits subsequent target data packets from the circular buffer according to their data sequence numbers. The retransmission range includes target data packets sent to the current target processing channel before the switching time stamp but not yet processed. The replacement target processing channel writes the retransmitted data packets and the switched real-time data packets into the input buffer according to their data sequence numbers; if the same data sequence number arrives repeatedly, only one copy is retained, and data packets with consecutive sequence numbers are processed sequentially. The loading completion information includes the target identifier, status version, last processed data sequence number, and replacement target processing channel identifier.

[0094] When the integrated signal processing board receives a loading completion message before the switching time marker, it maintains the record of routes to be enabled. If it does not receive a loading completion message before the switching time marker, the scheduling control module postpones the switching time marker to the next target data packet boundary and synchronously updates the current route record and the record of routes to be enabled. After the number of consecutive postponements reaches the allowed number recorded in the task parameter table, the scheduling control module cancels the current target processing channel to be replaced and selects another target processing channel.

[0095] When further verification of the status of the replacement target processing channel is required, the integrated signal processing board can copy a verification target data packet to the replacement target processing channel before the formal handover. The replacement target processing channel processes the verification target data packet according to the loaded status, but does not output the decoding result; it only returns the carrier error, code phase error, frame synchronization position, and processing completion time. The scheduling control module compares the above results with the processing results of the current target processing channel for the same target data packet. If the error is within the allowable range recorded in the target task parameter table, the handover time stamp is retained; if the error exceeds the allowable range, a status snapshot is resent or a new replacement target processing channel is selected.

[0096] Upon arrival of the switching time marker, the integrated signal processing board sends target data packets with sampling time markers no earlier than the switching time marker to the replacement target processing channel, and no longer sends such target data packets to the current target processing channel. The replacement target processing channel begins processing data packets starting from the data sequence number corresponding to the state snapshot. After the current target processing channel completes the remaining results in the output buffer, it releases the corresponding target state storage area. The entire switching position is located between two target data packets, without changing the processing channel of the sampling point within a single target data packet. After forming a state snapshot, the current target processing channel only outputs completed processing results for data sequence numbers no greater than the last processed data sequence number in the state snapshot; for unprocessed target data packets with larger data sequence numbers, no processing results are generated. The replacement target processing channel deduplicates data according to the data sequence number and processes them continuously, thus using the last processed data sequence number in the state snapshot as the unique processing boundary.

[0097] If the current target processing channel suddenly loses power, the high-speed data channel loses synchronization, or the programmable logic device stops responding, the current target processing channel may be unable to form a new state snapshot. After receiving each periodic state snapshot, the integrated signal processing board records the data sequence number corresponding to the state snapshot and continues to save subsequent target data packets in the circular buffer. The storage depth of the circular buffer should be greater than the number of target data packets covered by the state backup cycle and the fault detection time.

[0098] After confirming the failure of the current target processing channel, the scheduling control module selects a replacement target processing channel and sends the target task parameters and the most recent state snapshot from the state backup area to the replacement target processing channel. After completing the state loading, the replacement target processing channel requests the integrated signal processing board to retransmit the target data packet starting from the data sequence number corresponding to the state snapshot. The integrated signal processing board reads the target data packet from the circular buffer according to the data sequence number and transmits it at a rate not exceeding the input bandwidth of the replacement target processing channel.

[0099] During the recovery phase, the target replacement processing channel prioritizes processing retransmitted target data packets. When the processing capacity of the target replacement processing channel exceeds the real-time generation rate of the target data packets, the sequence number difference between the retransmitted data and the real-time data gradually decreases; once the sequence number difference decreases to zero, the target replacement processing channel switches to normal real-time processing. When the processing capacity of the target replacement processing channel can only meet the real-time processing requirements, the integrated signal processing board suspends the output of the latest decoding result of the corresponding target to the main control computer, first completes the recovery of the buffered data, and then resumes real-time output.

[0100] If the circular buffer fails to save all target data packets after the state snapshot, the target processing channel loads the most recent state snapshot and begins processing from the earliest data sequence number in the circular buffer. It then reconverges the carrier tracking loop and code tracking loop based on the coarse frequency offset and coarse code phase in the target data packets. The decoding results during the reconvergence period are marked as recovered data, and the master computer decides whether to use this data based on its continuity markings. This processing method is used when the circular buffer depth is insufficient or the fault duration exceeds the designed recovery time.

[0101] After a new parallel signal processing board is inserted into the parallel board slot, the backplane presence detection line first reports the board insertion status to the scheduling control module. The scheduling control module then turns on the auxiliary power and reads the board identifier and logic version. After the board identifier matches the slot type, the scheduling control module selects and loads the corresponding baseband processing logic according to the task requirements. After the logic loading is complete, the scheduling control module turns on the main power and performs memory read / write checks.

[0102] After the memory test passes, the integrated signal processing board and the newly added parallel signal processing board perform high-speed data channel training. Once the high-speed data channel training is complete, the newly added parallel signal processing board locks onto the reference clock and receives the second pulse. The scheduling control module compares the local time of the newly added parallel signal processing board with the time stamp of the integrated signal processing board. After the time deviation meets the synchronization requirements recorded in the board capability table, the newly added parallel signal processing board reports the target number of processing channels, supported decoding types, available storage capacity, and channel bandwidth.

[0103] After completing capability registration, the scheduling control module determines an activation timestamp for the newly added parallel signal processing board. This timestamp is located after the second pulse and aligned to the target data packet boundary of the target to be migrated. The scheduling control module selects the target to be migrated from the parallel signal processing boards with the highest current total processing load, and the state transition process transfers the target to be migrated to the newly added parallel signal processing board. After migration is complete, the scheduling control module updates the board capability table and data routing table.

[0104] When a parallel signal processing board requires maintenance or is planned to be decommissioned, the scheduling control module first stops assigning new targets to the corresponding parallel signal processing board, and then selects a replacement target processing channel for each existing target on the board. After all targets have completed state transitions and the results in the output buffer have been returned, the scheduling control module shuts down the high-speed data channel, saves the board's operation record, and then shuts down the main power supply and auxiliary power supply through the management configuration bus.

[0105] When the parallel signal processing board needs to exit due to abnormal temperature, current, or voltage, the scheduling control module selects between planned exit and immediate shutdown based on the severity of the abnormality. If the operating state still allows for the continued processing of several target data packets, a planned exit is adopted and a state transition is completed; if the operating state may damage the board or affect the backplane power supply, it is immediately shut down and the corresponding target is restored using the state backup area and the circular buffer area.

[0106] This embodiment uses one integrated signal processing board and two parallel signal processing boards to process twelve low code rate targets. The integrated signal processing board can employ two programmable logic devices (PLDs), a 14-bit analog-to-digital converter (ADC) with 250 Mbps sampling rate, and a 16-bit digital-to-analog converter (DAC). Each parallel signal processing board can employ four PLDs, each connected to an external dynamic random access memory (DRAM). The PLDs can be XC7K325T, the ADCs can be AD9680, and the DACs can be AD9144; alternatively, devices with comparable processing and interface capabilities can be used.

[0107] The RF front-end receives spread spectrum signals from twelve targets and forms a single 70 MHz combined intermediate frequency (IF) signal. The integrated signal processing board samples the combined IF signal and performs digital down-conversion and coarse acquisition according to the twelve target task records. After successful coarse acquisition of each target, the integrated signal processing board generates the corresponding target data packet and writes it into the corresponding target's circular buffer.

[0108] Before the task begins, the scheduling control module calculates the processing load of the twelve targets based on the processing time log. Assuming the first six targets use the same code rate and decoding method, and the last six targets use a different set of the same code rate and decoding method, the scheduling control module can allocate the first six targets to the first parallel signal processing board and the last six targets to the second parallel signal processing board. When the target processing loads are different, the scheduling control module allocates them alternately from high to low processing load, making the total processing load of the two parallel signal processing boards similar, and registers a backup target processing channel located on another board for targets with higher task priority.

[0109] The first and second parallel signal processing boards perform fine carrier tracking, fine code tracking, despreading, frame synchronization, and decoding on the received target data packets, respectively. The processing results are transmitted back to the integrated signal processing board via a high-speed data channel, and then sent to the main control computer according to the target identifier and frame time stamp. The main control computer stores the telemetry frames for each of the twelve targets and displays the carrier lock status, code ring lock status, frame synchronization status, error statistics, and processing load for each target.

[0110] In one operational example, the target data packet generation interval for a certain target is one millisecond. The processing times for three consecutive target data packets on the corresponding target processing channel are 1.05 milliseconds, 1.08 milliseconds, and 1.12 milliseconds, respectively. Simultaneously, the number of unprocessed target data packets increases from two to three and then to four. Based on this, the scheduling control module determines that the target processing channel's processing capacity is insufficient and selects an idle target processing channel on another parallel signal processing board as the replacement target processing channel.

[0111] The scheduling control module sets the handover time marker at the boundary of subsequent target data packets. After the current target processing channel completes the processing of the last target data packet before the handover, it creates a state snapshot, recording the sequence number of the last processed data. The succeeding target processing channel loads the state snapshot and returns a loading completion message. The integrated signal processing board sends the target data packets for that target to the succeeding target processing channel, starting from the data sequence number corresponding to the handover time marker. The routing of other data for the current target remains unchanged, while the other eleven targets continue to be processed in their original target processing channels.

[0112] When the first parallel signal processing board suddenly loses power, the scheduling control module reads the most recent state snapshot of each target processed by that board and retrieves the corresponding subsequent target data packets from the circular buffer of the integrated signal processing board. If the second parallel signal processing board has sufficient backup processing capacity, targets with higher task priority are preferentially migrated to the second parallel signal processing board. Remaining targets can be resumed after the newly added parallel signal processing board is enabled, or low-priority targets can be paused according to task priority to ensure the data continuity of high-priority targets.

[0113] When all four targets are high code rate targets, a single integrated signal processing board and a parallel signal processing board can be used, and the four targets can be assigned to four programmable logic devices (PLDs). Each PLD has only one target processing channel, and the correlation operation unit, tracking loop operation unit, and decoding unit are not time-division multiplexed among multiple targets to ensure the data processing time of a single target.

[0114] When a task contains both high-code-rate targets and low-code-rate targets, the scheduling control module allocates the high-code-rate targets first. High-code-rate targets preferentially occupy independent programmable logic devices, while low-code-rate targets are then allocated to the remaining programmable logic devices. Multiple low-code-rate targets can have independent target state storage areas set up on the same programmable logic device and share related arithmetic units, tracking loop arithmetic units, and decoding units.

[0115] During task execution, the scheduling control module updates the processing time record table based on the actual single-packet processing time. If the decoding method of a low-code-rate target changes or the number of related computation branches increases, the actual single-packet processing time may increase. The scheduling control module recalculates the total processing load of the corresponding target processing channel and proactively migrates other low-code-rate targets on the same programmable logic device to the backup target processing channel before reaching insufficient processing capacity, thereby freeing up processing time for targets with increased processing load.

[0116] Before the remote transmission mission begins, the main control computer establishes twelve remote transmission mission records. Each remote transmission mission record includes the target identifier, remote transmission command data, command encoding method, spreading code, chip rate, modulation method, transmission time stamp, baseband sampling rate, and target output gain. The scheduling and control module allocates target processing channels according to the command encoding and spreading processing load of each target.

[0117] The target processing channel reads the remote control command for the corresponding target, and sequentially completes command encoding, spread spectrum, and binary phase shift keying modulation to form baseband in-phase data and baseband quadrature data. The target processing channel then generates target transmission data packets according to the same data sequence number and verification rules as the telemetry-received target data packets. The header of the target transmission data packet records the target identifier, transmission time stamp, data sequence number, effective data length, baseband sampling rate, target output gain, and a verification field.

[0118] After receiving data packets transmitted from each target, the integrated signal processing board aligns the first valid sampling point of different targets to a unified sampling time according to the transmission time marker. When the baseband sampling rates are different, the integrated signal processing board first performs interpolation or decimation according to the task parameters to ensure that the data to be combined uses the same combining sampling rate. If the target's transmitted data packet does not arrive before the corresponding transmission time marker, the integrated signal processing board suspends the combining of the corresponding target and reports the late data sequence number to the scheduling control module, without using missing data to replace valid remote control commands.

[0119] After completing the sampling point alignment, the integrated signal processing board adjusts the amplitude of the baseband in-phase and baseband quadrature data according to the output gain of each target, and then accumulates the complex baseband data of the twelve targets point by point. The integrated signal processing board checks whether the accumulation result exceeds the digital up-conversion input bit width. When the accumulation result approaches the upper limit of the bit width, the integrated signal processing board reduces the amplitude of each target according to the uniform scaling factor recorded in the mission parameter table, and writes the scaling factor into the transmission status record.

[0120] The complex baseband data after digital combining is digitally up-converted to form digital intermediate frequency (IF) data, and then the analog IF signal is output by the digital-to-analog converter module. The analog IF signal is converted into a radio frequency (RF) signal by an external up-converter and power amplifier and transmitted by the antenna. The scheduling and control module records the data sequence number range, actual transmission time stamp, output gain, and digital combining scaling status of each target's transmitted data packet, so that the main control computer can verify the remote control command transmission results.

[0121] When a target processing channel needs to be migrated during remote transmission, the scheduling and control module switches at the boundary of the target transmission data packet after a remote control command or a complete coding block ends. The current target processing channel writes the spreading code position, encoder internal state, current command position, and last generated data sequence number into a state snapshot. The next target processing channel loads the state snapshot and continues to generate subsequent target transmission data packets. The integrated signal processing board combines the data according to the transmission time marker, without changing the data already in the transmission buffer.

[0122] In one specific hardware configuration, the scalable high-speed backplane employs a multi-layer printed circuit board. High-speed serial differential traces between the integrated signal processing board slot and the parallel signal processing board slot are designed with a 100-ohm differential impedance, and the trace length difference within the same differential pair is controlled. Eight high-speed serial channels are provided between the integrated signal processing board and each parallel signal processing board, with a single-channel transmission rate of 2.5 gigabits per second. The backplane can also reserve high-speed channels for use between parallel signal processing boards or between programmable logic devices within parallel signal processing boards.

[0123] The integrated signal processing board can use two XC7K325T programmable logic devices. One device connects to the intermediate frequency (IF) receiver link and the analog-to-digital converter (ADC) module, performing telemetry reception sampling, digital down-conversion, coarse acquisition, target separation, and target data packet formation. The other device connects to the digital-to-analog converter (DAC) module and the IF transmitter link, performing remote control transmission data reception, digital combining, digital up-conversion, and transmitter buffer management. The ADC module can be an AD9680, and the DAC module can be an AD9144.

[0124] The parallel signal processing board can employ four XC7K325T programmable logic devices (PLDs), each connected to two gigabytes of external memory. Each PLD can independently process one high code rate target, or time-divisionally process multiple low code rate targets when the processing load allows. The actual number of targets that can be processed is determined by the target code rate, chip rate, number of related operation branches, decoding method, and target data packet generation interval, and is not solely determined by the number of targets.

[0125] The backplane can input 12V DC power and provide the required multiple operating voltages for each board. The management configuration bus monitors the voltage, current, and board temperature of each circuit and controls the main power supply for each slot. The entire unit can be housed in a standard four-unit height chassis. Chassis size, number of boards, programmable logic device models, and number of high-speed data channels can be adjusted according to mission scale.

[0126] The above embodiments describe the target data packet formation, resource allocation, tracking processing status saving, target processing channel switching, fault recovery, parallel signal processing board expansion, and remote control transmission process. Those skilled in the art can adjust the intermediate frequency, sampling rate, spreading scheme, decoding method, high-speed serial interface type, and number of boards while maintaining the above processing relationships.

Claims

1. A multi-target measurement and control signal processing architecture, characterized in that, It includes a scalable high-speed backplane, an integrated signal processing board, at least one parallel signal processing board, and a scheduling and control module; the scalable high-speed backplane is equipped with a high-speed data channel, a time-frequency bus, and a management and configuration bus. In telemetry receiving mode, the integrated signal processing board samples, digitally down-converts, coarsely acquires, and separates the combined intermediate frequency signal formed by multiple targets, and generates a target data packet for each target, carrying target identifier, sampling time marker, coarse frequency offset, coarse code phase, baseband in-phase data, and baseband quadrature data. The parallel signal processing board is equipped with multiple target processing channels. Each target processing channel performs fine carrier tracking, fine code tracking, despreading, frame synchronization and decoding according to the corresponding target data packet. The scheduling control module determines the correspondence between targets and target processing channels based on the task parameters of each target and the available processing capacity of each target processing channel, and generates a data routing table for the integrated signal processing board to execute. When the processing capacity of the current target processing channel is insufficient, the scheduling control module determines the target processing channel to be replaced and the switching time marker. The switching time marker is aligned to the target data packet boundary according to the unified time reference provided by the time-frequency bus. The current target processing channel sends the tracking processing status of the corresponding target to the replacement target processing channel. The replacement target processing channel loads the tracking processing status and returns loading completion information. The integrated signal processing board sends the corresponding target data packet according to the updated data routing table starting from the switching time mark.

2. The multi-target measurement and control signal processing architecture according to claim 1, characterized in that, The scalable high-speed backplane has one integrated board slot and multiple parallel board slots; the integrated signal processing board and each of the parallel signal processing boards have independent high-speed data channels; the time-frequency bus is used to transmit reference clocks and second pulses to the integrated signal processing board and the parallel signal processing boards; the management configuration bus is used to read board identifiers, logic versions, temperature, voltage, current and high-speed data channel status, and to issue logic loading instructions, register configuration parameters and power supply control instructions.

3. The multi-target measurement and control signal processing architecture according to claim 1, characterized in that, The scheduling and control module establishes a target task parameter table, a target processing channel capability table, and a processing time record table; the target task parameter table records the target's code rate, chip rate, number of related computation branches, decoding type, target data packet generation interval, and task priority; The target processing channel capability table records the number of available related computation branches, available decoding throughput, available storage capacity, and remaining bandwidth of the corresponding high-speed data channel for the target processing channel. The scheduling control module first completes the initial allocation based on the target task parameter table and the target processing channel capacity table, and then adjusts the corresponding relationship based on the actual single-packet processing time in the processing time record table.

4. The multi-target measurement and control signal processing architecture according to claim 1, characterized in that, The target data packet also includes a data sequence number, a valid data length, and a check field; each routing record in the data routing table includes a target identifier, an output high-speed data channel identifier, a target processing channel identifier, a backup target processing channel identifier, a valid start time marker, and a valid end time marker; the integrated signal processing board matches valid routing records according to the target identifier and the sampling time marker, and checks the continuity and integrity of the target data packet according to the data sequence number and the check field.

5. The multi-target measurement and control signal processing architecture according to claim 4, characterized in that, Each target processing channel records the entry time, start time, and completion time of the target data packet into the buffer. When the processing time of three consecutive target data packets for the same target is not less than the corresponding target data packet generation interval, and the number of unprocessed target data packets in the buffer increases within the three consecutive target data packet generation intervals, the scheduling control module determines that the corresponding target processing channel has insufficient processing capacity. When the high-speed data channel loses synchronization, the number of consecutive verification errors reaches the error count limit recorded in the link configuration table, the data sequence number is not continuous, or the transmission time is not less than the target data packet generation interval, the scheduling control module determines that the high-speed data channel is abnormal.

6. The multi-target measurement and control signal processing architecture according to claim 5, characterized in that, The tracking processing status includes the frequency control word and phase accumulation value of the carrier digitally controlled oscillator, the frequency control word and code phase of the code digitally controlled oscillator, the carrier loop filter status, the code loop filter status, the frame synchronization position, and the decoder internal status. After receiving the target migration instruction, the current target processing channel completes the target data packet being processed and stops reading new target data packets from the input buffer, forming a new status snapshot containing the tracking processing status. The new status snapshot also carries the last processed data sequence number and check field. The replacement target processing channel loads the new status snapshot and returns loading completion information. If the loading completion information is not received before the switching time mark, the scheduling control module postpones the switching time mark to the next target data packet boundary.

7. The multi-target measurement and control signal processing architecture according to claim 6, characterized in that, The integrated signal processing board sets up a circular buffer and a state backup area for each target. The circular buffer stores multiple recently received target data packets according to their data sequence numbers. The state backup area stores state snapshots periodically sent by the target processing channel. When the current target processing channel fails to form and send a new state snapshot during target migration, the replacement target processing channel reads the most recent state snapshot of the corresponding target from the state backup area, and reads the target data packets after the data sequence number corresponding to the most recent state snapshot from the circular buffer, and restores the processing in sequence according to the data sequence number.

8. The multi-target measurement and control signal processing architecture according to claim 1, characterized in that, Each of the parallel signal processing boards includes multiple programmable logic devices and memories respectively connected to the programmable logic devices; each programmable logic device is provided with multiple target state storage areas, input buffer areas, output buffer areas, correlation operation units, tracking loop operation units, and decoding units. Different target state storage areas respectively store the spreading code, carrier tracking state, code tracking state, frame synchronization state, decoding state, and buffer address of the corresponding target; the programmable logic devices call the correlation operation units, the tracking loop operation units, and the decoding units in turn according to the data sequence number of the target data packet to process different targets.

9. The multi-target measurement and control signal processing architecture according to claim 1, characterized in that, In remote control transmission mode, the scheduling and control module allocates a target processing channel to each target; the target processing channel sequentially encodes, spreads, and modulates the remote control commands of the corresponding target using two-phase phase shift keying to generate a target transmission data packet carrying the target identifier, transmission time marker, data sequence number, baseband in-phase data, and baseband quadrature data; The integrated signal processing board performs sampling point alignment and digital combining of multiple target transmitted data packets according to the transmission time mark, performs digital up-conversion and digital-to-analog conversion on the digitally combined signal, and outputs the combined intermediate frequency signal.

10. The multi-target measurement and control signal processing architecture according to claim 7, characterized in that, When a new parallel signal processing board is connected to the scalable high-speed backplane, the scheduling control module sequentially performs board identification, logic loading, high-speed data channel training, time-frequency synchronization, memory detection, and processing capability registration, and determines an activation time stamp for the new parallel signal processing board. The scheduling control module uses the new state snapshot and the target data packets in the circular buffer to migrate at least one target to the newly added parallel signal processing board; when the parallel signal processing board is scheduled to shut down, the scheduling control module migrates the target processed by the corresponding parallel signal processing board to other parallel signal processing boards before shutting down the power supply to the corresponding parallel signal processing board.

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