Chip transceiver delay test method and device, terminal equipment and storage medium
Patent Information
- Application Number
- CN202510447157.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-10
- Publication Date
- 2026-10-20
AI Technical Summary
[0004]本发明提供了一种芯片收发器延迟测试方法、装置、终端设备及存储介质，能够解决现有技术中直接在FPGA芯片内部使用并行位宽的计数器做延迟统计，存在并行时钟周期的跨时钟域不确定性误差，导致收发器延迟测试的准确性较低的技术问题
[0037]本发明通过控制信号脉冲触发测试数据跳变为标记数据，并记录跳变时间，能够将延迟测试的延迟测试事件限制在同一时钟域内，避免并行位宽计数器在跨时钟同步时，因相位偏差等不确定误差而导致收发器延迟测试的准确性较低的问题，能够有效提高收发器延迟测试的准确性。
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Abstract
Description
Technical Field
[0001] This invention relates to the field of communication technology, and in particular to a method, apparatus, terminal device, and storage medium for testing the latency of a chip transceiver. Background Technology
[0002] Communication and network equipment typically require rapid development, easy upgrades, rich high-speed data transmission interfaces, and flexible usage during research and development. Therefore, FPGA chips are widely used as one of the core chips, and SERDES circuits, as an important hard-core component of FPGAs, are also widely used in communication, networking, and storage fields. SERDES stands for Serializer / Deserializer. At the transmitting end, it converts low-speed parallel data into a high-speed serial data stream for transmission. At the receiving end, it restores the received high-speed serial data stream back to the original low-speed parallel data. This technology is widely used in high-speed serial data transmission. The SERDES transmission delay is the time required for parallel data to be converted into serial data by SERDES and sent to the TX port. The SERDES reception delay is the time required for RX serial data to be converted into parallel user data. Transmission and reception delays are collectively referred to as SERDES delay. With more and more high-precision devices using SERDES circuits, delay performance is crucial to the overall system performance.
[0003] Existing methods for testing transceiver latency typically use parallel bit-width counters within the FPGA chip to perform latency statistics. This introduces cross-clock domain uncertainty errors in the parallel clock cycle, resulting in low accuracy of transceiver latency testing. Summary of the Invention
[0004] This invention provides a method, apparatus, terminal device, and storage medium for testing the delay of a chip transceiver. It can solve the technical problem that the prior art uses a parallel bit-width counter directly inside the FPGA chip to perform delay statistics, which has cross-clock domain uncertainty error of the parallel clock cycle, resulting in low accuracy of transceiver delay testing.
[0005] This invention provides a method for testing the latency of a chip transceiver, comprising:
[0006] Test data is sent to the target chip transceiver. When the target chip transceiver receives the data control signal pulse, the test data is changed to marker data and a start pulse is triggered.
[0007] The time when the test data transitions to the marked data is determined as the transition time, and the transmission delay of the target chip transceiver is determined based on the transition time and the start pulse trigger time.
[0008] Furthermore, after determining the time when the test data transitions to the marked data as the transition time, and determining the transmission delay of the target chip transceiver based on the transition time and the start pulse trigger time, the method further includes:
[0009] Determine the parallel data output by the receiving end of the target chip transceiver, wherein the parallel data is generated based on the data sent by the transmitting end of the target chip transceiver;
[0010] The parallel data is compared bit by bit with the labeled data to determine the offset value of the parallel data.
[0011] When the marker data is obtained based on the offset value of the parallel data and the parallel data, an alignment pulse is triggered;
[0012] The total delay of the target chip transceiver is determined based on the trigger time of the start pulse and the trigger time of the alignment pulse.
[0013] Furthermore, the step of performing a bit-by-bit comparison between the parallel data and the marked data to determine the offset value of the parallel data includes:
[0014] The parallel data is delayed by one clock cycle to obtain delayed data, and the parallel data and the delayed data are concatenated to obtain concatenated data.
[0015] The spliced data and the marked data are compared bit by bit to determine the offset value of the parallel data.
[0016] Furthermore, the step of performing a bit-by-bit comparison between the spliced data and the marked data to determine the offset value of the parallel data includes:
[0017] The data length of the marked data is determined to be n;
[0018] Starting from the 0th position of the spliced data, slide one data position at a time and extract data of length n as comparison data;
[0019] The comparison data is compared with the marker data. If the comparison data matches the marker data, the alignment start position of the current spliced data is recorded.
[0020] The offset value of the parallel data is determined based on the alignment start position.
[0021] Furthermore, after determining the total delay of the target chip transceiver based on the trigger time of the start pulse and the trigger time of the alignment pulse, the method further includes:
[0022] The receive delay of the target chip transceiver is determined based on the total delay of the target chip transceiver, the offset value of the parallel data, and the transmit delay of the target chip transceiver.
[0023] Furthermore, determining the receive delay of the target chip transceiver based on the total delay of the target chip transceiver, the offset value of the parallel data, and the transmit delay of the target chip transceiver includes:
[0024] The offset values of the parallel data are converted into time data to obtain the offset time.
[0025] The formula for calculating the receiving delay of the target chip transceiver is determined as follows:
[0026] The receive delay of the target chip transceiver = the total delay of the target chip transceiver - the transmit delay of the target chip transceiver - the offset time.
[0027] The present invention also provides a chip transceiver delay testing device, comprising:
[0028] The start pulse triggering module is used to send test data to the target chip transceiver. When the target chip transceiver receives the data control signal pulse, it changes the test data to marker data and triggers the start pulse.
[0029] The transmission delay determination module is used to determine the time when the test data transitions to the marked data as the transition time, and to determine the transmission delay of the target chip transceiver based on the transition time and the start pulse trigger time.
[0030] Furthermore, the chip transceiver delay testing device also includes a total delay determination module, used for:
[0031] Determine the parallel data output by the receiving end of the target chip transceiver, wherein the parallel data is generated based on the data sent by the transmitting end of the target chip transceiver;
[0032] The parallel data is compared bit by bit with the labeled data to determine the offset value of the parallel data.
[0033] When the marker data is obtained based on the offset value of the parallel data and the parallel data, an alignment pulse is triggered;
[0034] The total delay of the target chip transceiver is determined based on the trigger time of the start pulse and the trigger time of the alignment pulse.
[0035] The present invention also provides a terminal device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, it implements the chip transceiver delay testing method as described above.
[0036] The present invention also provides a computer-readable storage medium, comprising: a stored computer program, wherein, when the computer program is executed, it controls the device in which the computer-readable storage medium is located to perform the chip transceiver delay test method as described above.
[0037] This invention controls the transition of test data to marker data by controlling signal pulses and recording the transition time. This restricts the delay test events of the delay test to the same clock domain, avoiding the problem of low accuracy of transceiver delay test caused by uncertain errors such as phase deviation when parallel bit-width counters are synchronized across clocks. This effectively improves the accuracy of transceiver delay test.
[0038] Furthermore, this invention compares the marked data bit by bit through a sliding window (sliding 1 bit each time) and extracts a comparison data of length n. This allows direct location of the starting position in the parallel data that perfectly matches the marked data. Compared with the multi-bit synchronization mechanism of traditional parallel counters, this avoids bit slip and metastability propagation problems caused by clock phase deviation when crossing clock domains (CDC), effectively improving the accuracy of transceiver delay testing. Attached Figure Description
[0039] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0040] Figure 1 This is a flowchart illustrating a chip transceiver delay testing method provided in an embodiment of the present invention;
[0041] Figure 2 This is a schematic diagram of the structure of a chip transceiver delay testing system provided in an embodiment of the present invention;
[0042] Figure 3 This is another flowchart illustrating a chip transceiver delay testing method provided in an embodiment of the present invention;
[0043] Figure 4 This is a schematic diagram of the structure of a chip transceiver delay testing device provided in an embodiment of the present invention. Detailed Implementation
[0044] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.
[0046] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.
[0047] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0048] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0049] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).
[0050] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.
[0051] See Figure 1 To address the technical problem of low accuracy in transceiver delay testing caused by cross-clock domain uncertainty errors in parallel clock cycles when using parallel bit-width counters directly within the FPGA chip for delay statistics, this invention provides a chip transceiver delay testing method, comprising:
[0052] S1. Send test data to the target chip transceiver. When the target chip transceiver receives the data control signal pulse, change the test data to marker data and trigger the start pulse.
[0053] The chip transceiver latency testing method provided in this embodiment of the invention can be executed in a chip transceiver latency testing system.
[0054] Please see Figure 2 This invention provides a chip transceiver latency testing system, comprising a host computer, a high-speed oscilloscope, and an FPGA chip. The FPGA chip is the target chip, and the host computer can be a computer. The target chip is connected to both the host computer and the high-speed oscilloscope, with the high-speed oscilloscope also connected to the host computer. The target chip includes a SERDES module, a bus interface module, a data_gen module, a data_align module, and a data_chk module. The SERDES module functions as the transceiver for the target chip.
[0055] In this embodiment of the invention, the transceiver interface can be initialized. When the initialization is completed, it is recorded as time A. Test data A1 is sent to the transceiver through the data_gen module. The test data A1 can be composed of any data. In this embodiment of the invention, 16-bit wide PRBS data is used as the test data. PRBS0, PRBS1, PRBS2 and PRBS3 data are seen sequentially on the high-speed differential serial data line output by the transceiver.
[0056] The moment the data_gen module receives the data control signal pulse transmitted by the bus interface module is designated as time B. At time B, the test data A1 sent by the data_gen module is changed to marker data B1, where marker data B1 can be composed of any data that is different from the test data A1. The data control signal pulse is a control signal used in the FPGA's internal logic to trigger data switching. The data control signal pulse can be generated by the user sending a test mode switching command via a computer or host computer and transmitted to the data_gen module. For example, if the user clicks "Start sending marker data" on the software interface, the computer sends the command through the FPGA control bus, and the bus interface module parses it and generates the data control signal pulse. The data control signal pulse can also be triggered by a timed task scheduling method, such as triggering the pulse when the FPGA's internal timer overflows to meet periodic testing requirements. The data control signal pulse can also be triggered by an abnormal event response method. For example, when the data_chk module reports an error three times consecutively, the bus interface module sends this pulse to force resynchronization.
[0057] For example, the marker data B1 in this embodiment of the invention can be hexadecimal data:
[0058] F0F0_46EA_F0F0_46EA_F0F0_46EA_F0F0_46EA, at this time the data seen on the differential data line output by the transceiver is: 1111000011110000_0100011011101010_1111000011110000_0100011011101010.
[0059] In this embodiment of the invention, as the transmitted data is changed from test data A1 to marker data B1, a counter starts counting sequentially, and the start pulse S is set to a high level to trigger the start pulse. When the counter counts to K (K can be any period; in this embodiment, K is 100), the start pulse S is set to a low level. At this time, the data_gen module changes the transmitted data from marker data B1 to test data A1.
[0060] S2. Determine the time when the test data transitions to the marked data as the transition time. Based on the transition time and the start pulse trigger time, determine the transmission delay of the target chip transceiver.
[0061] In this embodiment of the invention, after the transmitted data is changed from marker data B1 to test data A1, the oscilloscope outputs data composed of test data A1 and marker data B1. The format of this data is: ...PRBS data_1111000011110000... When the oscilloscope outputs the data composed of test data A1 and marker data B1, it is the test data that jumps to marker data. At this time, the current time point is recorded as the jump time. The duration from the start pulse trigger time to this jump time is determined as the transmission delay of the target chip transceiver.
[0062] In this embodiment of the invention, the transceiver can be set to a line rate of 10.3125Gbps, a user data bit width of 64bit, and a near-end PMA loopback configuration, while the output TX differential signal is connected to an oscilloscope.
[0063] This invention, through a control signal pulse triggering the test data to transition to marker data and recording the transition time, can limit the delay test events of the delay test to the same clock domain. This avoids the problem of low accuracy of transceiver delay test due to uncertain errors such as phase deviation when the parallel bit-width counter is synchronized across clocks, and can effectively improve the accuracy of transceiver delay test.
[0064] In one embodiment, after determining the transition time from test data to marker data in step S2, and determining the transmission delay of the target chip transceiver based on the transition time and the start pulse trigger time, the method further includes:
[0065] S3. Determine the parallel data output by the receiving end of the target chip transceiver. The parallel data is generated based on the data sent by the transmitting end of the target chip transceiver. For example, the transmitting end sends marker data B1 and generates the corresponding parallel data.
[0066] In this embodiment of the invention, the data_align module sets the marker word used for alignment to marker data B1.
[0067] In this embodiment of the invention, the transceiver's data transmission process is uninterrupted, and therefore the transmitted serial bit data is not lost. Due to the characteristics of the serial-to-parallel conversion circuit, the parallel data received by the receiving end is converted from any serial bit to parallel data. Therefore, in this embodiment of the invention, the parallel data is denoted as rx_data_in. This parallel data is obtained by bit shifting 1 / B1 and needs to be aligned and the original marker data B1 data needs to be found.
[0068] S4. Perform bit-by-bit comparison between the parallel data and the labeled data to determine the offset value of the parallel data.
[0069] In this embodiment of the invention, the parallel data is obtained by shifting the marker data B1. By comparing the parallel data with the original marker data B1 bit by bit, the offset of the parallel data relative to the original marker data B1 can be determined, thereby determining the offset value of the parallel data.
[0070] S5. When the offset value of the parallel data and the marked data are obtained from the parallel data, the alignment pulse is triggered;
[0071] In this embodiment of the invention, the alignment start position in the parallel data can be located by bit-by-bit comparison processing. The alignment start position is the starting data bit of the original marker data B1 in the parallel data. The offset value of the parallel data is determined according to the position of the alignment start position. For example, if the alignment start position is the 3rd bit of the parallel data, the offset value of the parallel data is 3 bits to the right.
[0072] In this embodiment of the invention, after determining the offset value in the parallel data, n bits of data are taken upwards from the alignment start bit to obtain the original marker data B1, where n bits represent the data length of the original marker data B1. Simultaneously with obtaining the original marker data B1, the alignment pulse S1 is pulled high to trigger the alignment pulse S1.
[0073] In this embodiment of the invention, the obtained original marker data B1 can also be denoted as B2. The data_chk module serves as a data verification module, verifying whether B2 becomes A1 after S consecutive cycles. If the condition is met, the data is considered normal; otherwise, if there is a data error in the test environment, the verification result is output for debugging.
[0074] S6. Determine the total delay of the target chip transceiver based on the trigger time of the start pulse and the trigger time of the alignment pulse.
[0075] In this embodiment of the invention, by comparing parallel data with marked data bit by bit, the offset value of the parallel data can be accurately determined, thereby effectively improving the accuracy of transceiver delay testing.
[0076] In one embodiment, step S4, performing a bit-by-bit comparison between the parallel data and the marked data to determine the offset value of the parallel data, includes:
[0077] S41. Delay the parallel data by one clock cycle to obtain delayed data, and then concatenate the parallel data and the delayed data to obtain concatenated data.
[0078] In this embodiment of the invention, the parallel data rx_data_in is delayed by one clock cycle to obtain delayed data rx_data_in_ff1, and the data before and after the delay are concatenated to obtain concatenated data data_in_comb, that is:
[0079] data_in_comb={rx_data_in_ff1, rx_data_in}.
[0080] S42. Perform bit-by-bit comparison between the spliced data and the marked data to determine the offset value of the parallel data.
[0081] In this embodiment of the invention, the parallel data is delayed by one clock cycle to obtain delayed data, resulting in concatenated data with double the width. This ensures that the concatenated data covers all possible shift situations, guaranteeing that the complete code of the marker data B1 from the transmitting end exists in the concatenated data, which can effectively improve the accuracy of transceiver delay testing.
[0082] In one embodiment, step S42, comparing the concatenated data and the marked data bit by bit to determine the offset value of the parallel data, includes:
[0083] S421. Determine the length of the marked data as n;
[0084] In this embodiment of the invention, n can be 64.
[0085] S422. Starting from the 0th position of the concatenated data, slide one data position at a time and extract data of length n as comparison data.
[0086] S423. Compare the comparison data with the marker data. If the comparison data matches the marker data, record the alignment start position of the current spliced data.
[0087] In this embodiment of the invention, the ata_in_comb data bit Taking 64 upwards is denoted as:
[0088] data_i n_comb[i+:63];
[0089] Where i takes values from 0 to 63. First, the concatenated data data_i n_comb[0+:64] (i.e. the 0th bit of the concatenated data) is compared with the marker data B1. If they are equal, the alignment information recording signal match_pos[0] is set to 1; otherwise, it is set to 0.
[0090] In this embodiment of the invention, i is set sequentially from 0 to 63, the above steps are repeated, and the position where bit 1 is found in the alignment information recording signal is determined. The offset value de lta_phase of the parallel data is determined by this position.
[0091] S424. Determine the offset value of the parallel data based on the alignment start position.
[0092] This invention, through a sliding window, compares the marked data bit by bit (sliding 1 bit at a time) and extracts a comparison data of length n. This allows direct location of the starting position in the parallel data that perfectly matches the marked data. Compared to the multi-bit synchronization mechanism of traditional parallel counters, this avoids bit slip and metastability propagation problems caused by clock phase deviation when crossing clock domains (CDC), effectively improving the accuracy of transceiver delay testing.
[0093] In one embodiment, after determining the total delay of the target chip transceiver based on the trigger time of the start pulse and the trigger time of the alignment pulse in step S6, the method further includes:
[0094] S7. Determine the receiving delay of the target chip transceiver based on the total delay of the target chip transceiver, the offset value of the parallel data, and the transmission delay of the target chip transceiver.
[0095] In one embodiment, step S7, determining the receive delay of the target chip transceiver based on the total delay of the target chip transceiver, the offset value of the parallel data, and the transmit delay of the target chip transceiver, includes:
[0096] S71. Convert the offset values of parallel data into time data to obtain the offset time;
[0097] In this embodiment of the invention, the units of offset value, total delay, and transmission delay can be converted to UI to obtain the corresponding time data.
[0098] S72. The formula for calculating the receiving delay of the target chip transceiver is determined as follows:
[0099] The receiving delay of the target chip transceiver = the total delay of the target chip transceiver - the sending delay of the target chip transceiver - the offset time.
[0100] The embodiments of the present invention can repeat the above delay test steps to obtain multiple sets of delay test values.
[0101] In one embodiment, in Figure 2 In the transceiver delay test shown, before starting the test, the start pulse S can be connected to oscilloscope channel 1, the alignment pulse S1 to oscilloscope channel 2, and the SERDES high-speed differential data line TX_P to oscilloscope channel 3. The oscilloscope is set to automatically trigger from the first rising edge of channel 1 to the first rising edge of channel 2. When the host computer issues a reset command, the entire circuit environment is reset, and then a start test command is issued to begin the test.
[0102] Please see Figure 3 This is another flowchart illustrating a chip transceiver delay testing method according to an embodiment of the present invention.
[0103] Implementing the embodiments of the present invention has the following beneficial effects:
[0104] This invention, through a control signal pulse triggering the test data to transition to marker data and recording the transition time, can limit the delay test events of the delay test to the same clock domain. This avoids the problem of low accuracy of transceiver delay test due to uncertain errors such as phase deviation when the parallel bit-width counter is synchronized across clocks, and can effectively improve the accuracy of transceiver delay test.
[0105] Furthermore, this embodiment of the invention compares the marked data bit by bit through a sliding window (sliding 1 bit each time) and extracts the comparison data of length n. This can directly locate the starting position in the parallel data that completely matches the marked data. Compared with the multi-bit synchronization mechanism of the traditional parallel counter, this avoids bit slip and metastability propagation problems caused by clock phase deviation when crossing clock domains (CDC), effectively improving the accuracy of transceiver delay testing.
[0106] like Figure 4 As shown, based on the above method embodiments, corresponding apparatus embodiments are provided;
[0107] An embodiment of the present invention provides a chip transceiver delay testing device, comprising:
[0108] The start pulse triggering module 10 is used to send test data to the target chip transceiver. When the target chip transceiver receives the data control signal pulse, it changes the test data to marker data and triggers the start pulse.
[0109] The transmission delay determination module 20 is used to determine the time when the test data changes into the marker data as the transition time, and to determine the transmission delay of the target chip transceiver based on the transition time and the start pulse trigger time.
[0110] In one embodiment, the chip transceiver delay testing apparatus further includes a total delay determination module:
[0111] Determine the parallel data output from the receiver of the target chip transceiver, wherein the parallel data is generated based on the data sent by the transmitter of the target chip transceiver;
[0112] The offset value of the parallel data is determined by comparing the parallel data with the labeled data bit by bit.
[0113] An alignment pulse is triggered when the offset value of the parallel data and the marked data are obtained from the parallel data.
[0114] The total delay of the target chip transceiver is determined based on the trigger time of the start pulse and the trigger time of the alignment pulse.
[0115] In one embodiment, performing a bit-by-bit comparison between the parallel data and the labeled data to determine the offset value of the parallel data includes:
[0116] The parallel data is delayed by one clock cycle to obtain the delayed data, and the parallel data and the delayed data are concatenated to obtain the concatenated data.
[0117] The spliced data and the labeled data are compared bit by bit to determine the offset value of the parallel data.
[0118] In one embodiment, the concatenated data and the marked data are compared bit by bit to determine the offset value of the parallel data, including:
[0119] The length of the labeled data is determined to be n;
[0120] Starting from the 0th position of the concatenated data, slide one data position at a time and extract data of length n as comparison data;
[0121] The comparison data is compared with the marker data. If the comparison data matches the marker data, the alignment start position of the current spliced data is recorded.
[0122] The offset value of the parallel data is determined based on the alignment start position.
[0123] In one embodiment, the chip transceiver delay testing apparatus further includes a receive delay determination module, used for:
[0124] The receive delay of the target chip transceiver is determined based on the total delay of the target chip transceiver, the offset of the parallel data, and the transmit delay of the target chip transceiver.
[0125] In one embodiment, determining the receive delay of the target chip transceiver based on the total delay of the target chip transceiver, the offset of the parallel data, and the transmit delay of the target chip transceiver includes:
[0126] Convert the offset values of parallel data into time data to obtain the offset time;
[0127] The formula for calculating the receive delay of the target chip transceiver is determined as follows:
[0128] The receiving delay of the target chip transceiver = the total delay of the target chip transceiver - the sending delay of the target chip transceiver - the offset time.
[0129] It is understood that the above-described device embodiments correspond to the method embodiments of the present invention, and can implement the chip transceiver delay testing method provided by any of the above-described method embodiments of the present invention.
[0130] It should be noted that the device embodiments described above are merely illustrative, and some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can specifically be implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.
[0131] Based on the above embodiments of the chip transceiver latency testing method, another embodiment of the present invention provides a terminal device, which includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the chip transceiver latency testing method of any embodiment of the present invention.
[0132] For example, in this embodiment, the computer program can be divided into one or more modules, one or more modules are stored in memory and executed by a processor to complete the present invention. One or more module elements can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in a terminal device.
[0133] Terminal devices can be computing devices such as desktop computers, laptops, handheld computers, and cloud servers. Terminal devices may include, but are not limited to, processors and memory.
[0134] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting all parts of the terminal device through various interfaces and lines.
[0135] Based on the above-described method embodiments, another embodiment of the present invention provides a computer-readable storage medium including a stored computer program, wherein, when the computer program is running, it controls the device where the computer-readable storage medium is located to execute the chip transceiver delay test method of any of the above-described method embodiments of the present invention.
[0136] The modules / units integrated into the device / terminal equipment, if implemented as software functional units and sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.
[0137] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.
Claims
1. A method for testing the delay of a chip transceiver, characterized in that, include: Test data is sent to the target chip transceiver. When the target chip transceiver receives the data control signal pulse, the test data is changed to marker data and a start pulse is triggered. The time when the test data transitions to the marked data is determined as the transition time, and the transmission delay of the target chip transceiver is determined based on the transition time and the start pulse trigger time.
2. The chip transceiver delay testing method as described in claim 1, characterized in that, After determining the transition time as the time when the test data transitions to the marked data, and determining the transmission delay of the target chip transceiver based on the transition time and the start pulse trigger time, the method further includes: Determine the parallel data output by the receiving end of the target chip transceiver, wherein the parallel data is generated based on the data sent by the transmitting end of the target chip transceiver; The parallel data is compared bit by bit with the labeled data to determine the offset value of the parallel data. When the marker data is obtained based on the offset value of the parallel data and the parallel data, an alignment pulse is triggered; The total delay of the target chip transceiver is determined based on the trigger time of the start pulse and the trigger time of the alignment pulse.
3. The chip transceiver delay testing method as described in claim 2, characterized in that, The step of performing a bit-by-bit comparison between the parallel data and the marked data to determine the offset value of the parallel data includes: The parallel data is delayed by one clock cycle to obtain delayed data, and the parallel data and the delayed data are concatenated to obtain concatenated data. The spliced data and the marked data are compared bit by bit to determine the offset value of the parallel data.
4. The chip transceiver delay testing method as described in claim 3, characterized in that, The step of performing a bit-by-bit comparison between the concatenated data and the marked data to determine the offset value of the parallel data includes: The data length of the marked data is determined to be n; Starting from the 0th position of the spliced data, slide one data position at a time and extract data of length n as comparison data; The comparison data is compared with the marker data. If the comparison data matches the marker data, the alignment start position of the current spliced data is recorded. The offset value of the parallel data is determined based on the alignment start position.
5. The chip transceiver delay testing method as described in claim 2, characterized in that, After determining the total delay of the target chip transceiver based on the trigger time of the start pulse and the trigger time of the alignment pulse, the method further includes: The receive delay of the target chip transceiver is determined based on the total delay of the target chip transceiver, the offset value of the parallel data, and the transmit delay of the target chip transceiver.
6. The chip transceiver delay testing method as described in claim 5, characterized in that, The step of determining the receive delay of the target chip transceiver based on the total delay of the target chip transceiver, the offset value of the parallel data, and the transmit delay of the target chip transceiver includes: The offset values of the parallel data are converted into time data to obtain the offset time. The formula for calculating the receiving delay of the target chip transceiver is determined as follows: The receive delay of the target chip transceiver = the total delay of the target chip transceiver - the transmit delay of the target chip transceiver - the offset time.
7. A chip transceiver delay testing device, characterized in that, include: The start pulse triggering module is used to send test data to the target chip transceiver. When the target chip transceiver receives the data control signal pulse, it changes the test data to marker data and triggers the start pulse. The transmission delay determination module is used to determine the time when the test data transitions to the marked data as the transition time, and to determine the transmission delay of the target chip transceiver based on the transition time and the start pulse trigger time.
8. The chip transceiver delay testing apparatus as described in claim 7, characterized in that, It also includes a total delay determination module, used for: Determine the parallel data output by the receiving end of the target chip transceiver, wherein the parallel data is generated based on the data sent by the transmitting end of the target chip transceiver; The parallel data is compared bit by bit with the labeled data to determine the offset value of the parallel data. When the marker data is obtained based on the offset value of the parallel data and the parallel data, an alignment pulse is triggered; The total delay of the target chip transceiver is determined based on the trigger time of the start pulse and the trigger time of the alignment pulse.
9. A terminal device, characterized in that, The device includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, it implements the chip transceiver delay testing method as described in any one of claims 1-6.
10. A computer-readable storage medium, characterized in that, include: A stored computer program, wherein, when the computer program is executed, it controls the device containing the computer-readable storage medium to perform the chip transceiver delay test method as described in any one of claims 1-6.