Distributed clock synchronization methods, devices, equipment, media, and software products

Abstract

This application relates to the field of industrial Ethernet technology and provides a distributed clock synchronization method, apparatus, device, medium, and program product. The method includes: obtaining the arrival timestamp of a first synchronization frame received by a first slave station; calculating a target compensation amount based on the arrival timestamp and superimposing the target compensation amount onto the first synchronization frame to be forwarded to a second slave station to obtain a second synchronization frame; adjusting the frequency of a first local clock to obtain a second local clock; arbitrating a second clock source node from multiple first clock source nodes; obtaining a target clock signal and determining a third local clock; calculating a synchronization deviation statistic based on the arrival timestamp, the third local clock, and the target clock signal; and outputting a fault type and fault location when the synchronization deviation statistic exceeds a preset threshold. This invention ensures that the frequency of the local clock changes continuously during the switching process, solving the technical problem of phase jump at the moment of master clock switching in the prior art.

Description

Technical Field

[0001] This invention relates to the field of industrial Ethernet technology, and in particular to a distributed clock synchronization method, apparatus, device, medium, and program product. Background Technology

[0002] In industrial real-time Ethernet systems, the master station periodically sends synchronization frames to the slave stations. The slave stations calculate the transmission delay based on the received synchronization frames and adjust their local clocks to achieve distributed clock synchronization. In existing technologies, synchronization frames need to be forwarded by multiple slave stations before reaching the network's end node. The jitter components introduced by each slave station cannot be pre-emptively removed but are passed and accumulated with the synchronization frames. The more cascaded hops in the network, the greater the accumulated synchronization error at the end slave station. This leads to problems in existing technologies, such as a fixed and delayed arbitration basis and discontinuous phase during the clock source switching process. Summary of the Invention

[0003] This invention provides a distributed clock synchronization method, apparatus, device, medium, and program product. This invention enables the frequency pull of the local clock to change continuously during the switching process, solving the technical problem of phase jump at the moment of master clock switching in the prior art.

[0004] In a first aspect, embodiments of this application provide a distributed clock synchronization method, including: The arrival timestamp of the first synchronization frame received by the first slave station is obtained, and a state space model is established to calculate the target compensation amount, covariance matrix and innovation sequence. The target compensation amount is superimposed on the first synchronization frame to be forwarded to the second slave station to obtain the second synchronization frame. The frequency of the first local clock is adjusted to obtain the second local clock. Based on the covariance matrix and the innovation sequence, a second clock source node is arbitrated from a plurality of first clock source nodes, the target clock signal of the second clock source node is obtained, and a third local clock is determined based on the second local clock and the target clock signal. Based on the arrival timestamp, the third local clock, and the target clock signal, a synchronization deviation statistic is calculated. When the synchronization deviation statistic exceeds a preset threshold, the fault type and fault location are output.

[0005] Optionally, in a first implementation of the first aspect of the present invention, the step of obtaining the arrival timestamp of the first synchronization frame received by the first slave station, establishing a state-space model to calculate the target compensation amount, covariance matrix, and innovation sequence, superimposing the target compensation amount onto the first synchronization frame to be forwarded to the second slave station to obtain the second synchronization frame, and performing frequency pulling adjustment on the first local clock to obtain the second local clock includes: Obtain the arrival timestamp of the first synchronization frame received from the first slave station; The process noise is inverted on the free operating frequency data of the local crystal oscillator in the first slave station to obtain the process noise matrix. The link transmission delay is calculated based on the port transmit and receive timestamp register group of the first slave station. A state space model is established based on the process noise matrix, the link transmission delay, the clock deviation and the frequency offset. Kalman filtering recursive operation is performed on the state-space model to obtain the target compensation amount, covariance matrix and innovation sequence; The target compensation amount is written into the system time field of the first synchronization frame to be forwarded to the second slave station to obtain the second synchronization frame. The rate count register of the first local clock is adjusted according to the target compensation amount to obtain the second local clock.

[0006] Optionally, in a second implementation of the first aspect of the present invention, the step of performing Kalman filtering recursive operations on the state-space model to obtain the target compensation amount, covariance matrix, and innovation sequence includes: The state space model is predicted in one step according to the state transition equation to obtain the prior state and the prior covariance matrix, and the observation residual is calculated based on the arrival timestamp and the prior state. The timestamp quantization noise, physical layer elastic buffer jitter, and transmit / receive path asymmetry error are superimposed to obtain the observation noise matrix. Based on the prior covariance matrix and the observation noise matrix, the gain of the observation residual is calculated to obtain the Kalman gain. The clock skew prediction, link transmission delay prediction, and innovation sequence are calculated based on the observation residuals and the Kalman gain, and the prior covariance matrix is ​​updated to obtain the covariance matrix. The target compensation amount is obtained by extrapolating the predicted clock deviation and the predicted link transmission delay to the next synchronization cycle based on the state transition equation.

[0007] Optionally, in a third implementation of the first aspect of the present invention, the step of performing a one-step prediction on the state-space model based on the state transition equation to obtain the prior state and the prior covariance matrix, and calculating the observation residual based on the arrival timestamp and the prior state, includes: The state variables of the state-space model are converted into fixed-point number format to obtain fixed-point state variables; The fixed-point state variables are extrapolated based on the state transition equation and the process noise matrix to obtain the prior state and the prior covariance matrix. The observation residual is calculated based on the arrival timestamp and the prior state.

[0008] Optionally, in a fourth implementation of the first aspect of the present invention, the step of arbitrating a second clock source node from a plurality of first clock source nodes based on the covariance matrix and the innovation sequence, obtaining a target clock signal of the second clock source node, and determining a third local clock based on the second local clock and the target clock signal includes: The clock bias variance and frequency offset variance are calculated based on the covariance matrix, and the normalized residual sum of squares of the innovation sequence is calculated. The clock bias variance, the frequency offset variance, the normalized residual sum of squares, the node hop count, and the node temperature are used as dynamic clock quality parameters for each first clock source node. According to the dynamic clock quality parameters, an inverse backoff time is set for each of the first clock source nodes, and a second clock source node is arbitrated from multiple first clock source nodes according to the inverse backoff time, and the target clock signal of the second clock source node is obtained. The system time offset of the target clock signal is inherited and written into the time offset register of the second local clock to obtain the phase difference. The phase difference is then processed by S-curve allocation according to a preset number of cycles to obtain a phased frequency offset. The phased frequency offset is then input into the rate count register of the second local clock for traction adjustment to obtain the third local clock.

[0009] Optionally, in a fifth implementation of the first aspect of the present invention, the step of calculating a synchronization deviation statistic based on the arrival timestamp, the third local clock, and the target clock signal, and outputting the fault type and fault location when the synchronization deviation statistic exceeds a preset threshold, includes: Based on the arrival timestamp, a synchronization deviation statistic is calculated between the third local clock and the target clock signal; When the synchronization deviation statistic exceeds a preset threshold, the deviation spectrum is calculated and a change point test is performed on the innovation sequence to obtain the sudden anomaly point; The fault type and fault location are determined and output based on the deviation spectrum, the sudden anomaly point, the reception error count of the second slave station, and the link loss count.

[0010] Secondly, embodiments of this application provide a distributed clock synchronization device, comprising: The acquisition module is used to acquire the arrival timestamp of the first synchronization frame received by the first slave station, and to establish a state space model to calculate the target compensation amount, covariance matrix and innovation sequence. The target compensation amount is superimposed on the first synchronization frame to be forwarded to the second slave station to obtain the second synchronization frame. The first local clock is then frequency-adjusted to obtain the second local clock. The arbitration module is used to arbitrate a second clock source node from a plurality of first clock source nodes based on the covariance matrix and the innovation sequence, obtain the target clock signal of the second clock source node, and determine a third local clock based on the second local clock and the target clock signal. The output module is used to calculate the synchronization deviation statistic based on the arrival timestamp, the third local clock, and the target clock signal. When the synchronization deviation statistic exceeds a preset threshold, the module outputs the fault type and fault location.

[0011] Thirdly, embodiments of this application provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described distributed clock synchronization method.

[0012] Fourthly, embodiments of this application provide a readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described distributed clock synchronization method.

[0013] Fifthly, embodiments of this application provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the above-described distributed clock synchronization method.

[0014] In one scheme provided by the aforementioned distributed clock synchronization method, apparatus, device, medium, and program products, a state-space model is established with clock deviation and frequency offset as state variables and link transmission delay as the observable. Kalman filtering recursive calculations are then performed on the state-space model to obtain predicted clock deviation and link transmission delay values ​​for the next synchronization cycle. These predicted values ​​are then fed forward and superimposed at the forwarding exit point of the synchronization frame from the slave station to the downstream slave station. This ensures that predictable jitter components are removed before the synchronization frame is forwarded, preventing the jitter components introduced at each stage of the multi-level cascaded forwarding process from accumulating linearly with the number of hops. This allows the distributed clock synchronization method to maintain the synchronization accuracy of the end slave station even in large-scale multi-level cascaded topologies. Furthermore, the covariance matrix and innovation sequence generated by the Kalman filtering recursive calculations are not discarded after feedforward compensation but are reused for dynamic clock quality quantification of candidate clock source nodes. This transforms the clock source arbitration criteria from a fixed priority list or static dataset in existing technologies into dynamic parameters that reflect the confidence level of the current clock state of each candidate node in real time, ensuring that the arbitration result matches the actual state of network operation. This invention digests the phase difference between the local clock and the new reference clock node in stages according to a preset number of cycles, ensuring that the frequency pull of the local clock remains continuously changing during the switching process. This solves the technical problem of phase jumps during master clock switching in existing technologies. The innovation sequence in this invention is also reused for burst detection in online monitoring, and correlated with the spectral analysis results of the deviation statistics and the slave station's own reception error count and link loss count. This solves the technical problem of existing technologies that can only rely on dedicated instruments for offline detection after shutdown. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a distributed clock synchronization system according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating a distributed clock synchronization method according to an embodiment of the present invention; Figure 3 yes Figure 2 A schematic diagram of the implementation process of step S100; Figure 4 yes Figure 3 A schematic diagram of the implementation process of step S103; Figure 5 yes Figure 2 A schematic diagram of the implementation process of step S200; Figure 6 yes Figure 2 A schematic diagram of the implementation process of step S300; Figure 7 This is a schematic diagram of a distributed clock synchronization device according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. It should also be understood that, as used in this specification and the appended claims, the term "and / or" refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0019] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0020] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0021] It should be understood that the sequence number of each step in the following embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0022] To illustrate the technical solution of the present invention, specific embodiments are described below.

[0023] To address the problems mentioned above in the background art, embodiments of this application propose a distributed clock synchronization method, apparatus, device, medium, and program product. The distributed clock synchronization method provided by the embodiments of this invention can be applied to, for example... Figure 1 The distributed clock synchronization system shown includes an active master clock node, an industrial real-time communication network, multiple slave nodes connected in sequence, and a master station. The active master clock node periodically sends synchronization frames through the industrial real-time communication network. Each slave node receives synchronization frames sent by the upstream node, captures the hardware timestamp of the arrival time of the synchronization frame, processes the synchronization frame, and forwards it to the downstream slave node. Each slave node includes a hardware timestamp capture unit, a local clock unit, a state-space model construction unit, a Kalman filter unit, a forwarding output feedforward compensation unit, and a synchronization accuracy monitoring and anomaly diagnosis unit. The Kalman filter unit recursively estimates the clock deviation and frequency offset based on the timestamp sequence; the forwarding output feedforward compensation unit compensates for the forwarding delay before the synchronization frame is forwarded to the downstream slave node based on the estimation results, thereby suppressing the accumulation of synchronization jitter among multiple slave nodes. At least some slave nodes also include redundant clock sources and a distributed arbitration unit. The distributed arbitration unit determines a new active master clock node based on the dynamic clock quality and priority information of each candidate node when the active master clock node fails or the synchronization frame reception times out. Each slave node switches to the new reference clock using a phase transition method to avoid phase jumps in the local clock. The synchronization accuracy monitoring and anomaly diagnosis unit calculates the deviation statistics between the local clock and the reference clock. When the deviation statistics exceed a preset threshold, it identifies the fault type and fault location and reports the synchronization status and diagnosis results to the master station.

[0024] In one embodiment, such as Figure 2 As shown, a distributed clock synchronization method is provided, which is applied to... Figure 1 Taking a distributed clock synchronization system as an example, the following steps are included: S100: Obtain the arrival timestamp of the first synchronization frame received by the first slave station, establish a state space model to calculate the target compensation amount, covariance matrix and innovation sequence, superimpose the target compensation amount onto the first synchronization frame to be forwarded to the second slave station to obtain the second synchronization frame, and perform frequency pulling adjustment on the first local clock to obtain the second local clock. S200: Based on the covariance matrix and the innovation sequence, arbitrate the second clock source node from multiple first clock source nodes, obtain the target clock signal of the second clock source node, and determine the third local clock based on the second local clock and the target clock signal. S300: Calculate the synchronization deviation statistic based on the arrival timestamp, the third local clock, and the target clock signal. When the synchronization deviation statistic exceeds the preset threshold, output the fault type and fault location.

[0025] In this embodiment, a state-space model is established with clock skew and frequency offset as state variables and link transmission delay as the observable. Kalman filtering recursive operations are then performed on the state-space model to obtain the predicted clock skew and link transmission delay values ​​for the next synchronization cycle. These predicted values ​​are then fed forward and superimposed at the forwarding exit point of the synchronization frame from the slave station to the downstream slave station. This ensures that predictable jitter components are removed before the synchronization frame is forwarded, preventing the jitter components introduced at each stage of the multi-level cascaded forwarding process from accumulating linearly with the number of hops. This allows the distributed clock synchronization method to maintain the synchronization accuracy of the end slave station even in large-scale multi-level cascaded topologies. The covariance matrix and innovation sequence generated by the Kalman filtering recursive operation are not discarded after feedforward compensation but are reused for dynamic clock quality quantification of candidate clock source nodes. This transforms the clock source arbitration criteria from a fixed priority list or static dataset in existing technologies into dynamic parameters that reflect the confidence level of the current clock state of each candidate node in real time, ensuring that the arbitration result matches the actual state of network operation. This invention digests the phase difference between the local clock and the new reference clock node in stages according to a preset number of cycles, ensuring that the frequency pull of the local clock remains continuously changing during the switching process. This solves the technical problem of phase jumps during master clock switching in existing technologies. The innovation sequence in this invention is also reused for burst detection in online monitoring, and correlated with the spectral analysis results of the deviation statistics and the slave station's own reception error count and link loss count. This solves the technical problem of existing technologies that can only rely on dedicated instruments for offline detection after shutdown.

[0026] In one embodiment, such as Figure 3 As shown, step S100 specifically includes the following steps: S101: Obtain the arrival timestamp of the first synchronization frame received by the first slave station; S102: Perform process noise inversion on the free operating frequency data of the local crystal oscillator in the first slave station to obtain the process noise matrix. Calculate the link transmission delay based on the port transmit and receive timestamp register group of the first slave station. Establish a state space model based on the process noise matrix, link transmission delay, clock deviation, and frequency offset. S103: Perform Kalman filtering recursive calculations on the state-space model to obtain the target compensation amount, covariance matrix, and innovation sequence; S104: Write the target compensation amount into the system time field of the first synchronization frame to be forwarded to the second slave station to obtain the second synchronization frame. Adjust the rate count register of the first local clock according to the target compensation amount to obtain the second local clock.

[0027] In this embodiment, the first slave station monitors the MII or RMII physical interface through the hardware timestamp capture unit in the slave station controller. When the start of frame (SOF) bit of the first synchronization frame is detected to arrive, the current count value of the local distributed clock counter is immediately latched into the receive timestamp register. The latched value is then associated with and stored with the sequence number, receive port number, and synchronization cycle number of the first synchronization frame to form the arrival timestamp of the first synchronization frame. The timestamp acquisition process does not use the method of reading the software timer after the microcontroller interrupts to avoid microsecond-level interrupt response jitter from mixing into the synchronization measurement results. For example, in the first slave station using a standard ESC chip, the arrival timestamp can be recorded with a time quantization granularity of 10 nanoseconds. After the capture is completed, the corresponding hardware latch flag is read. Only when the latch flag is valid and the synchronization frame sequence number is continuous will the arrival timestamp be sent to subsequent calculations.

[0028] In this embodiment, during the initialization or maintenance calibration phase of the first slave station, the external clock pull is released, allowing the local crystal oscillator to operate freely. The offset data of the local crystal oscillator frequency relative to the nominal frequency is continuously recorded according to the synchronization cycle. Then, Allan variance analysis is performed on the frequency offset data to separate the white frequency noise figure. flicker frequency noise figure and frequency random walk noise figure and in accordance with , The mapping relationship determines the corresponding noise intensity in the process noise matrix, so that the process noise matrix is ​​obtained by inversion from the actual stability data of the local crystal oscillator, rather than directly using fixed empirical values. Simultaneously, the first slave station reads the port transmit / receive timestamp register group. In EtherCAT applications, it can read the port receive and transmit timestamps within the address range 0x0900 to 0x090C. The link transmission delay between the first slave station and the previous node is calculated using the transmit / receive time difference of the corresponding ports and the uplink / downlink path relationship, and known fixed forwarding dwell times are eliminated. For Profinet applications, the link transmission delay can be calculated based on the round-trip timestamps carried in the DELAY_REQ and DELAY_RES messages of the PTCP protocol. After completing the above processing, the clock offset is used as the basis for the calculation. Frequency offset and frequency drift rate Constructing a state vector , and according to , Establish state transition relationships, where, The synchronization period between adjacent first synchronization frames, and simultaneously according to Establish observation relationships, among which, For the first Timestamp observations obtained from each synchronization period For link transmission delay, To measure the noise of timestamps, when determining the observation noise matrix, the timestamp quantization noise, PHY elastic buffer jitter, and transmit / receive path asymmetry error are uniformly converted into variances before being superimposed. For example, the elastic buffer jitter of 8 nanoseconds under the 100-megabit physical layer is used as the standard deviation parameter and squared to avoid directly adding the jitter amplitude in nanoseconds to the quantization noise variance in square nanoseconds, thereby ensuring the consistency of the dimensions of the observation noise matrix.

[0029] In this embodiment, the arrival timestamp, state transition relationship, process noise matrix, link transmission delay, and observation noise matrix are input into the Kalman filter operation module. Based on the state estimate of the previous synchronization cycle, a one-step prediction is performed. Then, the current arrival timestamp is used to form the observation residual and complete the state update. This yields the clock deviation prediction value, the link transmission delay prediction value, the covariance matrix, and the innovation sequence. The clock deviation prediction value and the link transmission delay prediction value are extrapolated to the next synchronization cycle to form the target compensation amount. The covariance matrix is ​​used to characterize the uncertainty of the current state estimate, and the innovation sequence is used to characterize the difference between the actual timestamp and the predicted timestamp. After the current compensation is completed, both are passed on to the subsequent clock source quality assessment and anomaly diagnosis process. In this embodiment, before the first synchronization frame enters the forwarding exit, the target compensation amount is converted into a field write value according to the data format, byte order, and sign direction specified in the system time field, and superimposed on the system time field of the first synchronization frame to be forwarded to obtain the second synchronization frame. This ensures that the system time received by the second slave station has already deducted the compensable clock deviation and link jitter components predicted by the first slave station. Simultaneously, the same target compensation result is converted into an adjustment value for the rate count register according to the local clock pull direction. When the first local clock runs faster than the reference clock, the rate count increment is reduced; when the first local clock runs slower than the reference clock, the rate count increment is increased. The second local clock is formed through frequency pull of multiple consecutive synchronization cycles, without directly implementing instantaneous jumps to the local clock count value. The system time field compensation acts on the second synchronization frame sent to the second slave station, while the local rate count register adjustment acts on the first slave station's own clock. Since the two have different objects of action, they do not constitute repeated compensation for the same clock deviation, and can simultaneously block the accumulation of jitter to downstream nodes and gradually correct the local frequency of the first slave station.

[0030] In one embodiment, such as Figure 4 As shown, step S103 specifically includes the following steps: S1031: Perform a one-step prediction on the state-space model based on the state transition equation to obtain the prior state and prior covariance matrix, and calculate the observation residual based on the arrival timestamp and prior state; S1032: The timestamp quantization noise, physical layer elastic buffer jitter and transmit / receive path asymmetry error are superimposed to obtain the observation noise matrix. Based on the prior covariance matrix and the observation noise matrix, the gain of the observation residual is calculated to obtain the Kalman gain. S1033: Calculate the predicted clock skew, predicted link transmission delay, and innovation sequence based on the observation residuals and Kalman gain, and update the prior covariance matrix to obtain the covariance matrix; S1034: Extrapolate the predicted clock deviation and link transmission delay values ​​according to the state transition equation for the next synchronization cycle to obtain the target compensation amount.

[0031] In this embodiment, the first slave station can read the posterior state, posterior covariance matrix, process noise matrix, and arrival timestamp of the current first synchronization frame saved in the previous synchronization cycle after each SYNC0 synchronization interruption. It then converts state variables such as clock offset, frequency offset, and frequency drift rate into Q31 fixed-point format, and extrapolates the posterior state of the previous synchronization cycle to the current synchronization cycle according to the established state transition equation to obtain the prior state. Simultaneously, it follows... Calculate the prior covariance matrix, where, Here is the state transition matrix. The process noise matrix is ​​obtained by inversion based on the local crystal oscillator's free-running frequency data. It is used to characterize the uncertainty of the current cycle prediction result; the prior state is mapped to the timestamp observation space, and the predicted arrival time corresponding to the prior state is subtracted from the current arrival timestamp to obtain the observation residual of the current synchronization cycle.

[0032] In this embodiment, the timestamp quantization error, physical layer elastic buffer jitter, and transmit / receive path asymmetry error are converted into variances and then superimposed to obtain the observation noise matrix. The timestamp quantization noise is adopted Determine, for example: hardware timestamp quantization granularity If the amplitude is 10 nanoseconds, the corresponding quantization noise variance is approximately 8.33 square nanoseconds. For a 100-megabit physical layer, the measured or calibrated 8-nanosecond elastic buffer jitter can be included in the observation noise. When 8 nanoseconds represents the standard deviation, it is first squared to 64 square nanoseconds and then added to other variances. When the standard deviation of the transmit / receive path asymmetry error after calibration is 4 nanoseconds, its variance is 16 square nanoseconds. In this case, the observation noise variance can be set to approximately 88.33 square nanoseconds, and the three amplitudes of 10 nanoseconds, 8 nanoseconds, and 4 nanoseconds cannot be directly added together. After determining the observation noise matrix in this embodiment, according to... Calculate the Kalman gain, where, This is the mapping matrix from state to timestamp observations. It increases the correction weight of the current arrival timestamp when the prior covariance is large, and decreases the correction weight of the current observation when the observation noise is large. According to... The prior state is updated, and the updated clock skew component is used as the predicted clock skew value for the current period. Based on the link transmission delay calculated from the port transmit / receive timestamp register, the predicted link transmission delay value is corrected using the component in the observation residual corresponding to the link delay change. The observation residual within square brackets is simultaneously written into the innovation sequence as the k-th innovation value. Therefore, the observation residual and the current period's innovation are not two independent data points, but rather different uses of the same difference in state updates and continuous quality analysis. After the state update, the prior covariance matrix is ​​updated using either the Josephus stable form or UD decomposition form to obtain the covariance matrix for the current period. This prevents rounding errors from Q31 fixed-point operations from compromising the symmetry and positive definiteness of the covariance matrix. Simultaneously, the covariance matrix and the innovation sequence are saved and passed to the subsequent dynamic clock quality assessment process. Substitute the current cycle's updated predicted clock offset, frequency offset, and link transmission delay into the state transition equation, and extrapolate over one synchronization cycle to obtain the expected clock offset and link transmission delay when the next synchronization frame arrives. Then, perform symbol conversion and fixed-point quantization according to the compensation direction adopted by the system time field of the first synchronization frame to form the target compensation amount, so that the target compensation amount reflects the clock offset and link delay changes that are expected to be eliminated in advance in the next synchronization cycle.

[0033] In one embodiment, a one-step prediction is performed on the state-space model based on the state transition equation to obtain the prior state and the prior covariance matrix, and the observation residuals are calculated based on the arrival timestamps and the prior state, including: The state variables of the state-space model are converted into fixed-point number format to obtain fixed-point state variables; The fixed-point state variables are extrapolated based on the state transition equation and the process noise matrix to obtain the prior state and the prior covariance matrix. The observation residuals are calculated based on the arrival timestamp and prior state.

[0034] In this embodiment, after the first slave station enters the Kalman filter prediction stage in each synchronization cycle, it reads the clock skew, frequency offset, and frequency drift rate saved in the previous synchronization cycle, normalizes them according to preset ranges, and then converts them into 32-bit signed Q31 fixed-point numbers. Since the dimensions and numerical ranges of clock skew, frequency offset, and frequency drift rate are different, the three original values ​​cannot be directly written into the Q31 variable using the same ratio. For example, the full scale of clock skew is set to ±1 millisecond, the full scale of frequency offset is set to ±100 ppm, and the full scale of frequency drift rate is set to ±1 ppm / s, so that each state component is mapped to the range of -1 to close to positive 1 that Q31 can represent. For state components that exceed the full scale, saturation limiting is performed and an overflow flag is set. The absolute arrival timestamp of the first synchronization frame is still saved as a 64-bit nanosecond count value and is not directly converted to Q31 format to avoid fixed-point overflow caused by excessively large absolute time values.

[0035] In this embodiment, the first slave station follows and Extrapolate the fixed-point state variables over a synchronization period, where, The period value between actual adjacent synchronization frames is used. When the synchronization frame period is configured to 1 millisecond, 1 millisecond can be used as the initial period parameter for this extrapolation, and it is updated according to the interval between two consecutive hardware timestamps. The frequency drift rate retains the previous period estimate during one prediction step, and its random changes are reflected by process noise, thus obtaining the prior clock offset, prior frequency offset, and prior frequency drift rate of the current synchronization period. Fixed-point multiplication uses a 64-bit intermediate register to store the product, and after completing the corresponding shift and rounding, it is written back to the 32-bit Q31 variable, and the relevant parameters are also considered. The calculation first unifies the periodic units to prevent directly substituting millisecond values ​​into the state transition equation established in seconds. Simultaneously, it reads the posterior covariance matrix of the previous synchronization cycle and follows... Extrapolate from the state transition matrix. The uncertainties of each state component from the previous cycle are propagated, and then superimposed with the process noise matrix obtained by inversion from the Allan variance data of the local crystal oscillator. The prior covariance matrix is ​​obtained. Matrix multiplication also uses 64-bit intermediate results, and after each matrix update, it is checked whether the elements at symmetrical positions are consistent. For small differences caused by fixed-point rounding, the average result of the corresponding elements can be taken to maintain the symmetry of the prior covariance matrix.

[0036] In this embodiment, the first slave station generates a timestamp observation value based on the arrival timestamp of the current first synchronization frame, maps the clock deviation in the prior state to the timestamp observation space, and then combines it with the link transmission delay of the current cycle calculated by the port transmit / receive timestamp register group to determine the predicted arrival time of the synchronization frame. The difference between the actual arrival timestamp and the predicted arrival time is then used as the observation residual. Since the state vector consists of clock deviation, frequency offset, and frequency drift rate, and the link transmission delay is not included as an independent state variable in the state vector, it is not sufficient to simply subtract the prior clock deviation from the arrival timestamp; the link transmission delay should also be subtracted simultaneously. Alternatively, it can be based on the observation equation... Subtracting the link transmission delay from the arrival timestamp observation and comparing it with the prior clock deviation, the two processing methods should yield the same observation residual. A range check is performed on the observation residual; for example, the normal residual range can be set to ±10 microseconds. When the observation residual exceeds this range, it is not directly used for state correction but is marked as a timestamp anomaly or a synchronization frame burst delay. The observation residual that meets the range requirement, along with the prior state and the prior covariance matrix, is then fed into the Kalman gain calculation process, thereby avoiding unreasonable jumps in the filter state caused by a single abnormal timestamp.

[0037] In one embodiment, such as Figure 5 As shown, step S200 specifically includes the following steps: S201: Calculate the clock deviation variance and frequency offset variance based on the covariance matrix, and calculate the normalized residual sum of squares of the innovation sequence. Use the clock deviation variance, frequency offset variance, normalized residual sum of squares, node hop count, and node temperature as dynamic clock quality parameters for each first clock source node. S202: Set an inverse backoff time for each first clock source node according to the dynamic clock quality parameters, and arbitrate a second clock source node from multiple first clock source nodes according to the inverse backoff time, and obtain the target clock signal of the second clock source node. S203: The system time offset of the target clock signal is inherited and written into the time offset register of the second local clock to obtain the phase difference. The phase difference is distributed by S-curve according to the preset number of cycles to obtain the staged frequency offset. The staged frequency offset is input into the rate count register of the second local clock for traction adjustment to obtain the third local clock.

[0038] In this embodiment, each first clock source node with clock source capability reads the diagonal elements corresponding to clock deviation and frequency offset from the posterior covariance matrix obtained by the most recent Kalman filter recursion of this node. The diagonal elements corresponding to clock deviation are used as clock deviation variance, and the diagonal elements corresponding to frequency offset are used as frequency offset variance. The smaller the clock deviation variance, the lower the uncertainty of the time phase estimation of this node; the smaller the frequency offset variance, the more stable the local crystal oscillator rate estimation. At the same time, a sliding window with a length of 32 synchronization cycles can be established, and the innovation values ​​within the window can be read sequentially. The normalized residual sum of squares is obtained by normalizing the covariance of each new information value and summing its squares. This allows the new information amplitudes generated by different nodes due to differences in timestamp quantization accuracy, link noise, and observation noise matrices to be compared on the same scale. The smaller the normalized residual sum of squares, the better the consistency between the actual timestamp and the predicted timestamp. Since clock deviation variance, frequency offset variance, normalized residual sum of squares, node hop count, and node temperature have different dimensions, they are converted into quality levels according to preset ranges. For example, each parameter is quantized into an 8-bit level value from 0 to 255. The variance and normalized residual sum of squares are encoded in the direction that the smaller the value, the higher the quality level. The node hop count is encoded in the direction that the fewer the hop count, the higher the quality level. The node temperature is encoded according to its deviation from the nominal operating temperature of the crystal oscillator. For example, with 25 degrees Celsius as the temperature reference, the closer the temperature is to 25 degrees Celsius, the higher the temperature quality level. The five level values ​​are then combined into a fixed-length dynamic clock quality word in the order of clock deviation variance, frequency offset variance, normalized residual sum of squares, node hop count, and node temperature.

[0039] In this embodiment, each candidate node continuously listens for synchronization frames emitted by the currently active clock source. When no valid synchronization frame is received for three consecutive synchronization cycles, and the ESC watchdog register simultaneously indicates a synchronization communication timeout, the node switches its state from listening to candidate state. It then queries the inverse backoff duration table based on the dynamic clock quality word, ensuring that nodes with higher dynamic clock quality receive shorter backoff durations. For example, the backoff duration can be set between 1 and 16 synchronization cycles. The candidate node with the highest quality level backoffs for 1 synchronization cycle, the candidate node with the lowest quality level backoffs for 16 synchronization cycles, and the remaining candidate nodes obtain their corresponding backoff durations based on the range their quality level falls into. After entering the candidate state, each candidate node writes its dynamic clock quality word, node identifier, current clock state, backoff start cycle, and backoff duration into its arbitration status register or mailbox buffer. The master station reads the arbitration status of each candidate node in each synchronization cycle and writes the dynamic clock quality word and node identifier of the candidate node with the best dynamic clock quality among the currently reported candidate nodes into the arbitration notification information, which is then sent to each candidate node. During the backoff period, each candidate node continuously reads the arbitration notification information. If a candidate node reads information about a candidate node with a better dynamic clock quality than itself before its own backoff timer expires, or reads information about a candidate node with the same dynamic clock quality but a smaller node identifier value, then the backoff is canceled and the node returns to the listening state. When the backoff time of a candidate node expires, the node sets its clock source request flag to valid. After the main station reads the clock source request flag, it continues to read the arbitration status of each candidate node within a confirmation period. If no candidate node with a better dynamic clock quality is found within the confirmation period, and no candidate node with the same dynamic clock quality but a smaller node identifier value is found, then the candidate node with a valid clock source request flag is determined as the second clock source node, and the node identifier of the second clock source node is written into the clock source switching instruction and sent to each candidate node. After receiving the clock source switching instruction, the remaining candidate nodes return to the listening state, and the second clock source node enters the active clock source state. When the backoff time of multiple candidate nodes expires within the same synchronization period, the master station first compares the dynamic clock quality words of each candidate node. Then, if the dynamic clock quality words are the same, it compares the node identifiers and selects the candidate node with the smaller node identifier value. This ensures that only one second clock source node is formed in any arbitration period. After the second clock source node is determined, its output system time, system time offset, and synchronization period information together constitute the target clock signal, which is latched by the remaining slave stations during the reception of subsequent synchronization frames.

[0040] In this embodiment, each slave station first latches the current count value of the second local clock at the switching boundary to avoid directly rewriting the local system time to the absolute time of the target clock signal when the reference source changes. Then, the system time offset carried by the target clock signal is loaded into the time offset register of the second local clock, and the current continuous running time value of the second local clock is used as the inheritance basis of the new offset relationship. In this way, the residual phase difference between the second local clock and the target clock signal that still needs to be digested is calculated. Distribute the residual phase difference to a preset value. Each synchronization cycle, average frequency offset according to It is confirmed that, among them, For example, when the synchronization period is 1 millisecond, the residual phase difference is 5 microseconds, and the preset number of transition periods is 100, the average frequency offset is 50 ppm. Based on this, instead of writing 50 ppm as a constant step value into the rate count register all at once, 100 normalized S-curve coefficients are pre-stored. The frequency offset is gradually increased in the first 20 synchronization periods, the main phase digestion is completed in the middle 60 synchronization periods, and the frequency offset is gradually decreased in the last 20 synchronization periods, so that the frequency offset of the first period and the last period is close to zero. At the same time, it is ensured that the cumulative phase correction formed by the frequency offset of each stage in the 100 periods is equal to the residual phase difference. The phased frequency offset of each cycle is written to the rate count register of the second local clock at the SYNC0 boundary. When the second local clock lags behind the target clock signal, the counting rate is increased; when the second local clock leads the target clock signal, the counting rate is decreased. The frequency offset amplitude can be limited to within ±100 ppm. If the frequency offset calculated based on the residual phase difference exceeds this upper limit, the upper limit of the frequency offset is maintained and the number of transition cycles is automatically increased without truncating the phase difference to be corrected. After all transition cycles, the residual phase difference of the second local clock gradually converges to a preset range, such as within ±10 nanoseconds. At this time, the additional frequency offset is removed and normal Kalman filtering is maintained, resulting in a third local clock with continuous time phase, smooth frequency change, and alignment with the target clock signal of the second clock source node. This avoids time count jumps, control speed steps, or multi-axis interpolation shocks during reference clock switching.

[0041] In one embodiment, such as Figure 6 As shown, step S300 specifically includes the following steps: S301: Calculate the synchronization deviation statistics between the third local clock and the target clock signal based on the arrival timestamp; S302: When the synchronization deviation statistic exceeds the preset threshold, calculate the deviation spectrum and perform a change point test on the innovation sequence to obtain the sudden anomaly point; S303: Determine the fault type and fault location based on the deviation spectrum, sudden anomaly points, the reception error count of the second slave station, and the link loss count, and output them.

[0042] In this embodiment, when the second slave station arrives at the frame start bit of the physical interface in each first or second synchronization frame, it simultaneously latches the current count value of the third local clock through the hardware timestamp capture unit, and reads the target clock signal, system time offset, and link delay compensation information carried in the synchronization frame, thereby unifying the third local clock reading and the target clock signal to the same frame arrival time for comparison. When calculating a single synchronization deviation, the synchronization period number corresponding to this synchronization frame is determined using the arrival timestamp, and then the reference system time of the synchronization period is extracted from the target clock signal. The determined link transmission delay and fixed forwarding dwell time are deducted to obtain the reference time corresponding to the synchronization frame arriving at the second slave station. Subsequently, the latched value of the third local clock at the same time is subtracted from the reference time to form a synchronization deviation sample of the synchronization period, so as to avoid directly comparing the absolute times of two non-simultaneously read values ​​and introducing software reading delay. The synchronization accuracy monitoring module can establish a circular buffer with a length of 1024 synchronization cycles. When the synchronization cycle is 1 millisecond, a statistical window corresponds to 1.024 seconds. The mean and standard deviation of the synchronization deviation are calculated sample by sample using the Welford online update method. At the same time, the difference between the maximum and minimum synchronization deviation within the window is recorded as the peak jitter. Thus, a synchronization deviation statistic including the mean deviation, standard deviation deviation, and peak jitter is obtained. For example, the absolute value of the mean deviation of 100 nanoseconds, the standard deviation of 50 nanoseconds, and the peak jitter of 300 nanoseconds can be set as the warning threshold. When any statistic exceeds the warning threshold, only a warning record is generated. The absolute value of the mean deviation of 300 nanoseconds, the standard deviation of 150 nanoseconds, and the peak jitter of 1 microsecond can be set as the alarm threshold. When any statistic exceeds the alarm threshold for two consecutive statistical windows, S302 is executed. This avoids the fault diagnosis being mistakenly triggered by a single abnormal timestamp or the brief convergence process after the master-slave clock switch.

[0043] In this embodiment, the most recent 1024 synchronization deviation samples are extracted from the circular buffer, the mean deviation is removed, a Hanning window is applied, and then a real-number fast Fourier transform is performed to obtain the amplitude and dominant frequency position of each frequency component. When the synchronization period is 1 millisecond, the frequency resolution of the obtained deviation spectrum is approximately 0.9766 Hz. If a stable narrowband peak with an amplitude significantly higher than that of a neighboring frequency appears in the spectrum, the frequency point is recorded as a candidate frequency for periodic interference. If multiple consecutive frequency bands show an increase in energy at the same time, it is recorded as a broadband noise feature. In order to prevent the synchronization sampling frequency from aliasing with interference frequencies such as switching power supply and pulse width modulation driver, the synchronization sampling interval can be finely adjusted from 1 millisecond to 0.98 milliseconds in the next statistical window and the deviation spectrum can be calculated again. The actual interference frequency is determined by comparing the peak positions of the two spectra. Meanwhile, the diagnostic module reads the continuously output innovation sequence of the Kalman filter process, normalizes each innovation value according to the corresponding innovation covariance, and then uses the Page-Hinkley test or cumulative sum test to detect whether there are sudden changes in the mean and fluctuation level of each sample. For example, the test threshold can be calibrated according to a window false alarm rate of 0.1%. When the cumulative statistic first crosses the threshold, the timestamp, node identifier, innovation amplitude and the direction of the cross-limit of the corresponding synchronization period are recorded as a sudden anomaly point, and the data of 32 synchronization periods before and after the anomaly point are saved to distinguish different burst modes caused by single timestamp spikes, continuous link jitter and synchronization frame loss.

[0044] In this embodiment, a unified target clock signal is used as the time reference. The deviation spectrum, sudden anomaly points, second slave station receive error count register, link loss count register, and frame check error count register are time-aligned. The fault type is determined according to the consistency of multiple evidences. When the deviation spectrum has a narrowband peak corresponding to the switching power supply or pulse width modulation frequency, and the receive error count or frame check error count increases in the same time period while the link loss count does not increase significantly, the fault type is determined to be electromagnetic interference. When the deviation spectrum shows an overall increase in broadband energy, a continuous increase in the receive error count and frame check error count, and an intermittent increase in the link loss count, the fault type is determined to be link physical layer degradation. When the sudden anomaly point is consistent with the synchronization period of the increase in the link loss count, and several consecutive synchronization frames fail to arrive normally after the anomaly occurs, the fault type is determined to be connector looseness, instantaneous cable disconnection, or port unlocking. When the deviation spectrum mainly shows a slow drift close to zero frequency, with no obvious frame check errors or link loss, and the mean and standard deviation of the deviation increase slowly and monotonically with node temperature or running time, the fault type is determined to be local crystal oscillator temperature drift or crystal oscillator aging. When determining the fault location, each slave station reports the synchronization deviation statistics, spectrum characteristics, sudden anomaly points, and register increments according to a unified time label. If the anomaly first appears at the k-th hop node in the network topology, and multiple nodes downstream of the k-th hop node inherit the same spectrum peak or sudden anomaly characteristics from the same time, while the upstream node of the k-th hop node remains normal, then the fault location is determined to be the link between the k-th hop node and its upstream node. If only the second slave station itself experiences a synchronization deviation anomaly, and its upstream and downstream nodes do not exhibit the same characteristics, then the fault location is determined to be the crystal oscillator, timestamp capture unit, or port transceiver circuit inside the second slave station. In this embodiment, the diagnostic module generates a diagnostic result data packet including fault type, fault node identifier, fault link segment, first abnormal time, duration period, deviation peak, spectrum main peak, receive error count increment and link loss count increment, and reports it to the master station or management system. At the same time, when the fault is determined to be a continuous abnormality of the current clock source, the clock source arbitration is retried. When the fault is determined to be a transient interference of a specific link, the value of the corresponding link observation noise matrix is ​​increased to reduce the Kalman filter's trust in the interfered timestamp.

[0045] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0046] In one embodiment, a distributed clock synchronization device is provided, which corresponds one-to-one with the distributed clock synchronization method described in the above embodiments. For example... Figure 7As shown, the distributed clock synchronization device includes: The acquisition module 701 is used to acquire the arrival timestamp of the first synchronization frame received by the first slave station, and to establish a state space model to calculate the target compensation amount, covariance matrix and innovation sequence. The target compensation amount is superimposed on the first synchronization frame to be forwarded to the second slave station to obtain the second synchronization frame. The first local clock is frequency-pulling adjustment to obtain the second local clock. Arbitration module 702 is used to arbitrate a second clock source node from multiple first clock source nodes based on the covariance matrix and the innovation sequence, obtain the target clock signal of the second clock source node, and determine a third local clock based on the second local clock and the target clock signal. The output module 703 is used to calculate the synchronization deviation statistics based on the arrival timestamp, the third local clock and the target clock signal. When the synchronization deviation statistics exceed the preset threshold, the fault type and fault location are output.

[0047] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0048] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0049] This application also provides a computer device, such as... Figure 8 As shown, the computer device includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor. When the processor executes the computer program, it implements the steps in any of the above method embodiments, or when the processor executes the computer program, it implements the functions of each module / unit in the above device embodiments.

[0050] For example, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete this application. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the computer device.

[0051] Those skilled in the art will understand that Figure 8 The computer device described is merely an example and does not constitute a limitation on the computer device. It may include more or fewer components than shown, or combine certain components, or different components. For example, the computer device may also include input / output devices, network access devices, buses, etc.

[0052] The aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0053] The memory can be an internal storage unit of the computer device, such as a hard drive or RAM. The memory can also be an external storage device of the computer device, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory can include both internal and external storage units of the computer device.

[0054] This application also provides a readable storage medium storing a computer program, which, when executed by a processor, can implement the steps in the above-described method embodiments.

[0055] This application provides a computer program product that, when run on an electronic device, enables the electronic device to implement the steps described in the various method embodiments above.

[0056] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a photographing device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0057] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0058] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0059] In the embodiments provided in this application, it should be understood that the disclosed apparatus / devices and methods can be implemented in other ways. For example, the apparatus / device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0060] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0061] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A distributed clock synchronization method, characterized in that, include: The process involves: obtaining the arrival timestamp of the first synchronization frame received by the first slave station; establishing a state-space model to calculate the target compensation amount, covariance matrix, and innovation sequence; superimposing the target compensation amount onto the first synchronization frame to be forwarded to the second slave station to obtain the second synchronization frame; and adjusting the frequency of the first local clock to obtain the second local clock. Specifically, this includes: obtaining the arrival timestamp of the first synchronization frame received by the first slave station; performing process noise inversion on the free-running frequency data of the local crystal oscillator in the first slave station to obtain the process noise matrix; calculating the link transmission delay based on the port transmit / receive timestamp register group of the first slave station; establishing a state-space model based on the process noise matrix, the link transmission delay, clock deviation, and frequency offset; performing Kalman filtering recursive operations on the state-space model to obtain the target compensation amount, covariance matrix, and innovation sequence; writing the target compensation amount into the system time field of the first synchronization frame to be forwarded to the second slave station to obtain the second synchronization frame; and adjusting the rate counter register of the first local clock according to the target compensation amount to obtain the second local clock. Based on the covariance matrix and the innovation sequence, a second clock source node is arbitrated from multiple first clock source nodes. A target clock signal from the second clock source node is obtained, and a third local clock is determined based on the second local clock and the target clock signal. Specifically, this includes: calculating the clock deviation variance and frequency offset variance based on the covariance matrix, and calculating the normalized sum of squared residuals of the innovation sequence; using the clock deviation variance, frequency offset variance, and normalized sum of squared residuals along with the node hop count and node temperature as dynamic clock quality parameters for each first clock source node; setting an inverse backoff duration for each first clock source node based on the dynamic clock quality parameters, and arbitrating a second clock source node from multiple first clock source nodes based on the inverse backoff duration; obtaining the target clock signal from the second clock source node; inheriting the system time offset of the target clock signal into the time offset register of the second local clock to obtain the phase difference; performing S-curve allocation processing on the phase difference according to a preset number of cycles to obtain a phased frequency offset; inputting the phased frequency offset into the rate counter register of the second local clock for traction adjustment to obtain the third local clock. Based on the arrival timestamp, the third local clock, and the target clock signal, a synchronization deviation statistic is calculated. When the synchronization deviation statistic exceeds a preset threshold, the fault type and fault location are output.

2. The distributed clock synchronization method as described in claim 1, characterized in that, The step of performing Kalman filtering recursive operations on the state-space model to obtain the target compensation amount, covariance matrix, and innovation sequence includes: The state space model is predicted in one step according to the state transition equation to obtain the prior state and the prior covariance matrix, and the observation residual is calculated based on the arrival timestamp and the prior state. The timestamp quantization noise, physical layer elastic buffer jitter, and transmit / receive path asymmetry error are superimposed to obtain the observation noise matrix. Based on the prior covariance matrix and the observation noise matrix, the gain of the observation residual is calculated to obtain the Kalman gain. The clock skew prediction, link transmission delay prediction, and innovation sequence are calculated based on the observation residuals and the Kalman gain, and the prior covariance matrix is ​​updated to obtain the covariance matrix. The target compensation amount is obtained by extrapolating the predicted clock deviation and the predicted link transmission delay to the next synchronization cycle based on the state transition equation.

3. The distributed clock synchronization method as described in claim 2, characterized in that, The step of performing a one-step prediction on the state-space model based on the state transition equation to obtain the prior state and the prior covariance matrix, and calculating the observation residual based on the arrival timestamp and the prior state, includes: The state variables of the state-space model are converted into fixed-point number format to obtain fixed-point state variables; The fixed-point state variables are extrapolated based on the state transition equation and the process noise matrix to obtain the prior state and the prior covariance matrix. The observation residual is calculated based on the arrival timestamp and the prior state.

4. The distributed clock synchronization method as described in claim 1, characterized in that, The step involves calculating a synchronization deviation statistic based on the arrival timestamp, the third local clock, and the target clock signal. When the synchronization deviation statistic exceeds a preset threshold, the fault type and fault location are output, including: Based on the arrival timestamp, a synchronization deviation statistic is calculated between the third local clock and the target clock signal; When the synchronization deviation statistic exceeds a preset threshold, the deviation spectrum is calculated and a change point test is performed on the innovation sequence to obtain the sudden anomaly point; The fault type and fault location are determined and output based on the deviation spectrum, the sudden anomaly point, the reception error count of the second slave station, and the link loss count.

5. A distributed clock synchronization device, characterized in that, The steps for implementing the distributed clock synchronization method as described in any one of claims 1 to 4 include: The acquisition module is used to acquire the arrival timestamp of the first synchronization frame received by the first slave station, and to establish a state space model to calculate the target compensation amount, covariance matrix and innovation sequence. The target compensation amount is superimposed on the first synchronization frame to be forwarded to the second slave station to obtain the second synchronization frame. The first local clock is then frequency-adjusted to obtain the second local clock. The arbitration module is used to arbitrate a second clock source node from a plurality of first clock source nodes based on the covariance matrix and the innovation sequence, obtain the target clock signal of the second clock source node, and determine a third local clock based on the second local clock and the target clock signal. The output module is used to calculate the synchronization deviation statistic based on the arrival timestamp, the third local clock, and the target clock signal. When the synchronization deviation statistic exceeds a preset threshold, the module outputs the fault type and fault location.

6. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the distributed clock synchronization method as described in any one of claims 1 to 4.

7. A readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the distributed clock synchronization method as described in any one of claims 1 to 4.

8. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the distributed clock synchronization method as described in any one of claims 1 to 4.

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