Ethernet interface rate degradation control method and system, storage medium

Abstract

This invention discloses an Ethernet interface rate degradation control method, system, and storage medium. The method includes: acquiring real-time detected quality parameters of the SerDes link between the MAC controller and the PHY chip; statistically analyzing the quality parameters within a preset evaluation period to determine whether the link quality meets the degradation trigger condition; if so, acquiring the minimum guaranteed bandwidth requirement for the currently carried service; determining whether the bandwidth of the preset target degradation mode meets the minimum guaranteed bandwidth requirement; if so, performing a degradation switching operation to switch the SerDes link from high-speed mode to the low-speed mode corresponding to the preset target degradation mode; continuously monitoring the link quality under the preset target degradation mode; and automatically performing a switchback to high-speed mode when the link quality meets the preset back-switch conditions. This application achieves automatic back-switchback of link quality through an adaptive recovery mechanism and a hysteresis comparison strategy, maximizing bandwidth utilization while ensuring stability.

Description

Technical Field

[0001] This invention relates to the field of Ethernet communication technology, and in particular to an Ethernet interface rate degradation control method, system, and storage medium. Background Technology

[0002] High-speed Ethernet interfaces (such as 10GE / 5GE / 2.5GE) are widely used in high-speed communication scenarios such as 5G fronthaul, data center interconnection, and AI intelligent computing clusters. Currently, the physical layer of high-speed Ethernet interfaces such as 10GE, 5GE, and 2.5GE generally uses high-speed SerDes serializers to achieve high-speed data transmission and reception. Taking the 10GE interface as an example, the SerDes channel between the MAC media access controller and the PHY physical layer transceiver operates in SFI (SerDes Framer Interface) mode, achieving a transmission rate of 10.3125Gbps and employing a 64B / 66B encoding mechanism. Currently, the main existing technical solutions for Ethernet link quality control and rate adjustment are as follows: Option 1 is the IEEE 802.3 standard automatic negotiation mechanism. This mechanism only negotiates and matches the rate during link initialization, and the rate remains fixed after the link is established. During link operation, the link is prone to sudden degradation due to factors such as temperature drift, electromagnetic interference, optical module aging, and poor connector contact, resulting in high bit error rates and frequent link interruptions. This mechanism cannot monitor and intervene in link failures in real time, and can only renegotiate after the link is broken, which can easily cause service interruptions and is difficult to meet the requirements of high-reliability transmission.

[0003] Option 2 is a speed reduction scheme based on bit error rate detection. This scheme calculates the bit error rate by statistically analyzing FCS frame errors, and reduces the speed to the standard Ethernet rate level when the bit error rate exceeds the standard. However, it has several drawbacks: the rate levels only include 10M / 100M / 1G / 10G, without intermediate transitional rates of 2.5G and 5G; a direct reduction from 10G to 1G can easily cause bandwidth-sensitive services to fail; it only adjusts the MAC layer rate and does not switch the SerDes underlying working mode, resulting in poor control stability; the speed reduction does not match the minimum bandwidth and QoS requirements of the service, which can easily lead to service interruption while maintaining the link; and it cannot automatically increase the speed after the link quality is repaired, resulting in long-term waste of bandwidth resources.

[0004] Option 3 is the LACP link aggregation redundancy scheme, which relies on dual-link hardware redundancy to achieve fault traffic switching. This scheme doubles the hardware cost, and the fault switching latency reaches the second level, making it unsuitable for low-latency services; moreover, it can only passively offload traffic after a fault and cannot improve the transmission quality of a single link itself.

[0005] In summary, existing link rate control schemes have the following problems: they cannot detect quality changes in high-speed Ethernet SerDes links in real time; they cannot downgrade the SerDes mode from high-speed mode to a suitable low-speed mode when the link quality deteriorates; and they cannot automatically switch back to high-speed mode after the link quality recovers. Summary of the Invention

[0006] This invention aims to provide an Ethernet interface rate degradation control method, system, and storage medium, which addresses the problems of existing link rate management schemes being unable to detect quality changes in high-speed Ethernet SerDes links in real time, being unable to downgrade the SerDes mode from high-speed mode to a suitable low-speed mode when link quality deteriorates, and being unable to automatically switch back to high-speed mode after link quality recovers.

[0007] To address the aforementioned technical problems, a first aspect of the present invention provides an Ethernet interface rate degradation control method, the method comprising: Obtain the quality parameters of the SerDes link between the MAC controller and the PHY chip detected in real time; Within a preset evaluation period, the quality parameters are statistically analyzed to obtain the link quality evaluation results, and based on the link quality evaluation results, it is determined whether the link quality meets the degradation triggering conditions. When the link quality meets the degradation triggering condition, obtain the minimum guaranteed bandwidth requirement for the currently carried service; Determine whether the preset target degradation mode bandwidth meets the minimum guaranteed bandwidth requirement; If the preset target degradation mode meets the minimum guaranteed bandwidth requirement, a degradation switching operation is performed to switch the SerDes link from the current high-speed mode to the low-speed mode corresponding to the preset target degradation mode; the high-speed mode and the low-speed mode are different working modes of the SerDes physical layer. The link quality is continuously monitored under the preset target degradation mode. When the link quality meets the preset back-switch conditions, the back-switch is automatically executed to switch the SerDes link from the low-speed mode back to the high-speed mode.

[0008] Accordingly, a second aspect of the present invention provides an Ethernet interface rate degradation control system, applied to the Ethernet interface rate degradation control method described in the first aspect of the present invention, the system comprising: The link quality monitoring module is used to continuously and in real time detect the quality parameters of the SerDes link between the MAC controller and the PHY chip; The health assessment module is used to collect the above quality parameters within a preset assessment period, obtain the link quality assessment results, and determine whether the link quality meets the degradation triggering conditions based on the link quality assessment results. The service awareness module is used to obtain the minimum guaranteed bandwidth requirement of the currently carried service when the degradation trigger condition is met. The strategy decision module is used to determine whether the preset target degradation mode bandwidth meets the minimum guaranteed bandwidth requirement; The mode switching execution module is used to perform a degradation switching operation if the preset target degradation mode meets the minimum guaranteed bandwidth requirement, and switch the SerDes link from the current high-speed mode to the low-speed mode corresponding to the preset target degradation mode; the high-speed mode and the low-speed mode are different working modes of the SerDes physical layer. The strategy decision module is also used to determine whether the preset back-switch conditions are met based on the continuously obtained link quality assessment results. When the continuously obtained link quality assessment results meet the preset back-switch conditions, the back-switch process is triggered. The mode switching execution module is also used to automatically execute the back-switch process to switch the SerDes link from low-speed mode back to high-speed mode.

[0009] Accordingly, a third aspect of the present invention provides a computer storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, cause the processor to execute the Ethernet interface rate degradation control method described in the first aspect of the present invention.

[0010] Compared with existing technologies, the present invention provides an Ethernet interface rate degradation control method, system, and storage medium. This method acquires the quality parameters of the SerDes link between the MAC controller and the PHY chip detected in real time, statistically analyzes these quality parameters within a preset evaluation period, and obtains a link quality evaluation result to monitor link quality in real time. Based on the link quality evaluation result, it determines whether the link quality meets the degradation triggering conditions. When the link quality meets the degradation triggering conditions, it acquires the minimum guaranteed bandwidth requirement of the currently carried service and determines whether the bandwidth of the preset target degradation mode meets this minimum guaranteed bandwidth requirement. This introduces a service QoS awareness mechanism to ensure that the degradation switching operation is only performed when the bandwidth meets the minimum service requirement, avoiding service damage due to blind speed reduction. The degradation switching is performed when the preset target degradation mode meets the minimum guaranteed bandwidth requirement. The process involves switching the SerDes link from its current high-speed mode to the low-speed mode corresponding to the preset target degradation mode. This allows for a SerDes mode downgrade from SFI (5G) to 2500BASE-X (2.5G) when link quality deteriorates, achieving fine-grained 2.5G rate degradation. This avoids the excessive bandwidth jump caused by directly downgrading from 10G to 1G. Furthermore, the 8B / 10B encoding used in 2500BASE-X offers stronger clock recovery and anti-interference capabilities compared to SFI's 64B / 66B encoding, effectively reducing the quality requirements of the physical channel. It significantly suppresses link interruptions and bit errors, ensuring zero service interruption and better adapting to application scenarios with precise bandwidth requirements, such as 5G fronthaul. By continuously monitoring link quality under the preset target degradation mode, an automatic switchback is executed when the link quality meets the preset switchback conditions, transferring the SerDes link to 2500BASE-X (2.5G). The link switches from low-speed mode back to high-speed mode, thereby achieving automatic link quality recovery through adaptive recovery mechanisms and hysteresis comparison strategies, maximizing bandwidth utilization while ensuring stability.

[0011] This application addresses the problems of existing link rate control schemes being unable to detect quality changes in high-speed Ethernet SerDes links in real time, being unable to downgrade the SerDes mode from high-speed mode to a suitable low-speed mode when the link quality deteriorates, and being unable to automatically switch back to high-speed mode after the link quality recovers. Attached Figure Description

[0012] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0013] Figure 1A schematic diagram of an Ethernet interface rate degradation control system based on link quality assessment provided by the present invention; Figure 2 This is a flowchart illustrating an Ethernet interface rate degradation control method based on link quality assessment provided by the present invention. Figure 3 This is a detailed flowchart illustrating an Ethernet interface rate degradation control method based on link quality assessment provided by the present invention. Figure 4 This is another schematic diagram of an Ethernet interface rate degradation control system based on link quality assessment provided by the present invention. Detailed Implementation

[0014] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0015] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0016] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0017] High-speed Ethernet interfaces (such as 10GE / 5GE / 2.5GE) are widely used in high-speed communication scenarios such as 5G fronthaul, data center interconnection, and AI intelligent computing clusters. Currently, the physical layer of high-speed Ethernet interfaces such as 10GE, 5GE, and 2.5GE generally adopts high-speed SerDes serializers to achieve high-speed data transmission and reception. Taking the 10GE interface as an example, the SerDes channel between the MAC media access controller and the PHY physical layer transceiver operates in SFI mode, with a transmission rate of up to 10.3125Gbps, and uses a 64B / 66B encoding mechanism.

[0018] Currently, the industry mainly has the following existing technical solutions for Ethernet link quality control and rate adjustment: Option 1 is the automatic negotiation mechanism specified in the IEEE 802.3 standard. This mechanism only executes during the physical layer initialization phase of the link. The two ends of the communication device determine the optimal operating rate that the link can support through interactive negotiation messages. After the link is established, the rate is locked and no longer dynamically adjusted. This mechanism can only complete the rate matching in the initial stage of link establishment, and cannot detect the link transmission status in real time during link operation. When problems such as ambient temperature drift, external electromagnetic interference, attenuation of transmitted optical power due to long-term operation of optical modules, and increased contact impedance due to connector aging occur in the field, the link quality will suddenly deteriorate, resulting in frequent link interruptions, a sharp increase in bit error rate, and other faults. The existing automatic negotiation mechanism cannot predict and intervene in link degradation in advance, and can only re-initiate negotiation after the link is disconnected, which can easily cause short-term interruption of communication services and cannot meet the high-reliability continuous transmission service requirements of 5G fronthaul and other services.

[0019] Option 2 is a link speed reduction scheme based on bit error rate detection, such as the scheme disclosed in US Patent US6529957B1. This scheme calculates the link bit error rate by counting the number of FCS frame check error frames at the receiving end. When the bit error rate exceeds a preset threshold, the interface rate is switched down to the next standard Ethernet rate level. This solution has several limitations: First, the rate adjustment granularity is coarse, supporting only standard rate levels of 10M, 100M, 1G, and 10G, and not supporting intermediate transitional rates such as 2.5G and 5G. If a 10G link is directly downgraded to 1G, bandwidth-sensitive services such as eCPRI will experience insufficient bandwidth supply, leading to performance degradation or even service interruption. Second, the rate adjustment only stays at the MAC layer parameter configuration level and does not involve the switching of the underlying SerDes physical mode. The SerDes working mode includes underlying core parameters such as encoding format (64B / 66B, 8B / 10B), clock recovery circuit, and equalization algorithm. Adjusting only the MAC rate is far less stable and compatible than the overall switching of the physical layer SerDes mode. Third, the rate reduction decision does not incorporate service-aware logic and does not distinguish between the minimum bandwidth and QoS of the currently carried service. The first problem is that the solution is prone to problems such as blindly reducing speed to maintain link connectivity, which may lead to the inability of core services to operate normally. The second problem is that the solution only has the ability to reduce speed in one direction and does not have the logic to automatically increase speed and switch back after the link quality is restored. Even if the external environment improves and the link error rate returns to the normal range, the link will still operate at a low speed for a long time, resulting in a continuous waste of transmission bandwidth resources.

[0020] Option 3 is the Link Aggregation LACP Redundancy Switching scheme, which is mostly used in high-reliability communication scenarios. This scheme adopts a dual-link hardware redundancy architecture. When the primary link fails, service traffic is switched to the backup link via the LACP protocol. This scheme has obvious drawbacks: First, the hardware cost increases significantly, requiring two sets of PHY chips, optical modules, and transmission media; second, the traffic switching latency can reach the second level, making it unsuitable for application scenarios with stringent requirements for service interruption latency, such as 5G fronthaul; third, this scheme is only a passive traffic backup measure after a failure and cannot fundamentally solve the problem of transmission quality degradation of a single link itself.

[0021] In summary, existing link rate control schemes cannot detect quality changes in high-speed Ethernet SerDes links in real time, cannot downgrade the SerDes mode from high-speed mode to a suitable low-speed mode when the link quality deteriorates, and cannot automatically switch back to high-speed mode after the link quality recovers.

[0022] Please see Figure 1 , Figure 1 This invention provides a schematic diagram of an Ethernet interface rate degradation control system based on link quality assessment.

[0023] exist Figure 1 In the Ethernet interface rate degradation control system 10 based on link quality assessment, there is an electronic device 500. The electronic device 500 includes one or more processors 501, a MAC controller 503, a PHY chip 504, an optical module 505, a memory 502, and one or more computer programs stored in the memory 502 and executable on the processor 501. The memory 502 and the processor 501 are coupled together through a bus system 503. The one or more computer programs are executed by the processor 501 to perform the corresponding functions in the methods described in the following method embodiments.

[0024] Among them, electronic device 500 can be a server, edge computing device, cloud computing node or intelligent network device (such as intelligent router) with information processing and communication capabilities, etc., and is not limited to one specific device.

[0025] Processor 501 is used to run intelligent degradation control strategy software. Processor 501 can be a Central Processing Unit (CPU), a Network Processor (NP), a hardware chip, or any combination thereof. The aforementioned hardware chip can be an Application Specific Integrated Circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The aforementioned PLD can be a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a Generic Array Logic (GAL), or any combination thereof.

[0026] Memory 502 is used to store program code, etc. Memory 502 may include volatile memory (VM), such as random access memory (RAM); memory 502 may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); memory 502 may also include combinations of the above types of memory.

[0027] The memory 502 can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the methods in the embodiments of the present invention. The processor 501 executes various functional applications and data processing of the method and apparatus by running the non-volatile software programs, instructions, and modules stored in the memory 502, that is, it implements the functions of each module or unit of the method and apparatus provided in the above method embodiments.

[0028] The memory 502 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function. The data storage area may store data created based on the use of the device.

[0029] The one or more modules are stored in the memory 502. When executed by the one or more processors 501, they execute the methods in any of the above method embodiments. For example, they execute the method steps described in the above method embodiments to realize the functions of the modules described in the above device embodiments.

[0030] The MAC controller 503 implements Ethernet data link layer functions and supports SerDes interface mode configuration.

[0031] The PHY chip 504 implements physical layer functions and supports configurable switching between SerDes modes such as SFI and 2500BASE-X.

[0032] Optical module 505 connects to an external transmission medium.

[0033] The link quality monitoring module 506 is integrated into the MAC controller 503 or the PHY chip 504 or exists independently, and is used to detect the quality parameters of the SerDes link between the MAC controller and the PHY chip in real time.

[0034] The processor 501 directly controls the register configuration of the PHY chip 504 through the MDIO bus, and interacts with the MAC controller 503 through the data bus. The MAC controller 503 and the PHY chip 504 are connected through the SerDes link, and the PHY chip 504 and the optical module 505 are connected through electrical / optical signals.

[0035] Please see Figure 2 , Figure 2 This invention provides a flowchart illustrating an Ethernet interface rate degradation control method based on link quality assessment. The method includes: S1. Obtain the quality parameters of the SerDes link between the MAC controller and the PHY chip detected in real time; S2. Within the preset evaluation period, the above quality parameters are statistically analyzed to obtain the link quality evaluation results, and based on the link quality evaluation results, it is determined whether the link quality meets the degradation triggering conditions. S3. When the link quality meets the degradation triggering conditions, obtain the minimum guaranteed bandwidth requirement of the currently carried service; S4. Determine whether the preset target degradation mode bandwidth meets the minimum guaranteed bandwidth requirement; S5. If the preset target degradation mode meets the minimum guaranteed bandwidth requirement, then perform a degradation switching operation to switch the SerDes link from the current high-speed mode to the low-speed mode corresponding to the preset target degradation mode; the high-speed mode and the low-speed mode are different working modes of the SerDes physical layer. S6. Continuously monitor the link quality under the preset target degradation mode. When the link quality meets the preset back-switch conditions, automatically perform back-switch to switch the SerDes link from the low-speed mode back to the high-speed mode.

[0036] This embodiment provides an Ethernet interface rate degradation control method based on link quality assessment. It acquires the quality parameters of the SerDes link between the MAC controller and the PHY chip in real time, statistically analyzes these parameters within a preset assessment period, and obtains the link quality assessment result to monitor link quality in real time. Based on the link quality assessment result, it determines whether the link quality meets the degradation trigger condition. When the link quality meets the degradation trigger condition, it acquires the minimum guaranteed bandwidth requirement of the currently carried service and determines whether the preset target degradation mode bandwidth meets this minimum guaranteed bandwidth requirement. This introduces a service QoS awareness mechanism to ensure that the degradation switching operation is only performed when the bandwidth meets the minimum service requirement, avoiding service damage caused by blindly reducing speed. By performing the degradation switching operation when the preset target degradation mode meets the minimum guaranteed bandwidth requirement, the SerDes link... The path switches from the current high-speed mode to the low-speed mode corresponding to the preset target degradation mode. This allows the SerDes mode to be downgraded from SFI (5G) to 2500BASE-X (2.5G) when the link quality deteriorates, achieving fine-grained rate degradation at 2.5G. This avoids the problem of excessive bandwidth jump caused by directly downgrading from 10G to 1G. Furthermore, the 8B / 10B encoding used in 2500BASE-X has stronger clock recovery and anti-interference capabilities compared to the 64B / 66B encoding of SFI, effectively reducing the quality requirements of the physical channel. It can significantly suppress link interruptions and bit errors, ensuring zero service interruption, and better adapting to application scenarios with precise bandwidth requirements, such as 5G fronthaul. By continuously monitoring the link quality under the preset target degradation mode, when the link quality meets the preset back-switch conditions, a back-switch is automatically executed, switching the SerDes link from low-speed mode back to high-speed mode. Through adaptive recovery mechanisms and hysteresis comparison strategies, automatic back-switch of link quality is achieved, maximizing bandwidth utilization while ensuring stability.

[0037] This invention provides an Ethernet interface rate degradation control method based on link quality assessment. This method can detect quality changes in high-speed Ethernet SerDes links in real time, and when link quality deteriorates, it can finely and smoothly degrade the SerDes mode from high-speed mode to a suitable low-speed mode. Simultaneously, it can sense service bandwidth requirements to ensure the operation of core services, and automatically switch back to high-speed mode after link quality recovers. This solves the problems of existing link rate control schemes that cannot detect quality changes in high-speed Ethernet SerDes links in real time, cannot degrade the SerDes mode from high-speed mode to a suitable low-speed mode when link quality deteriorates, and cannot automatically switch back to high-speed mode after link quality recovers.

[0038] In one embodiment, in step S1, the quality parameters of the SerDes link between the MAC controller and the PHY chip are obtained in real time.

[0039] Specifically, please refer to Figure 2 , Figure 3 and Figure 4 The electronic device 500 is equipped with a link quality monitoring module 506. This link quality monitoring module 506 is integrated into the MAC controller 503 or the PHY chip 504 or exists independently. It is used to collect the physical layer quality parameters of the SerDes link according to a preset sampling period T_s (e.g., 100ms) and monitor the link quality in real time. Among them, the quality parameters include, but are not limited to, bit error rate (BER), flicker frequency (i.e., the number of times the link flickers per unit time), and clock data recovery lock status.

[0040] The link quality monitoring module 506 reads the link status register and symbol error counter (e.g., the Frame Check Sequence (FCS) error counter defined in IEEE 802.3 Clause 45) of the PHY chip at a preset sampling period T_s via the MDIO (Management Data Input / Output) bus. At the same time, it reads the FCS error statistics counter of the MAC controller and records the sampled data to obtain the quality parameters of the SerDes link between the MAC controller and the PHY chip in real time and monitor the link quality in real time.

[0041] MDIO is a serial communication bus defined by the IEEE 802.3 standard for management data transmission between the MAC controller and the PHY chip in Gigabit Ethernet. This interface is implemented using a two-wire structure of MDC (clock line) and MDIO (bidirectional data line), supporting register configuration and status monitoring between master and slave devices, including parameter settings such as link status, rate adjustment, and power consumption mode. Its protocol frames cover a preamble, operator, address field, and data field, supporting sharing among multiple devices and addressing via a unique address. The MDIO protocol initially used the Clause22 frame format, suitable for 100Mbps / 1Gbps networks, and was later extended to the Clause45 standard to adapt to higher speed scenarios. The protocol design follows low power consumption and high compatibility characteristics, and is widely used in embedded systems, switches, and routers. Linux systems can directly read and write PHY registers using MDIO tools to achieve network parameter configuration and diagnostics.

[0042] In one embodiment, in step S2, the above quality parameters are statistically analyzed within a preset evaluation period to obtain the link quality evaluation result, and the link quality is determined based on the link quality evaluation result to determine whether the link quality meets the degradation triggering condition.

[0043] Specifically, please refer to Figure 2 , Figure 3 and Figure 4The electronic device 500 is equipped with a health assessment module 507. This module is used to perform statistical analysis on the collected quality parameters at the end of a preset assessment period T_p (e.g., 60s), calculate key quality indicators (KQIs), obtain link quality assessment results, and determine whether the link quality meets the degradation triggering conditions based on the link quality assessment results. The key quality indicators KQIs include the bit error rate (BER) and the flashover frequency (Flap_Rate). The degradation triggering conditions include the BER exceeding the preset degradation triggering high threshold TH_ber, or the flashover frequency exceeding the flashover threshold TH_flap.

[0044] Among them, the key quality indicators calculated by statistical analysis based on quality parameters can be obtained using existing methods, which will not be elaborated here.

[0045] Specifically, determining whether the link quality meets the degradation triggering conditions based on the link quality assessment results includes: calculating the bit error rate (BER) and the flashover frequency (Flap_Rate) within the preset assessment period T_p, and determining whether the BER exceeds the preset degradation triggering high threshold TH_ber (e.g., 1E-6), or whether the flashover frequency (Flap_Rate) exceeds the flashover threshold TH_flap (e.g., 3 times / minute). When the BER exceeds the preset degradation triggering high threshold TH_ber, or the flashover frequency (Flap_Rate) exceeds the flashover threshold TH_flap, the link quality is determined to meet the degradation triggering conditions.

[0046] In one embodiment, in step S3, when the link quality meets the degradation triggering condition, the minimum guaranteed bandwidth requirement of the currently carried service is obtained.

[0047] Specifically, please refer to Figure 2 , Figure 3 and Figure 4 The electronic device 500 is equipped with a service awareness module 508. This module communicates with the upper-layer protocol stack or service management plane to obtain service awareness information, including the type of the currently carried service and the corresponding Quality of Service (QoS) parameters, in order to obtain the minimum guaranteed bandwidth requirement for the currently carried service. The type of the currently carried service includes, but is not limited to, eCPRI, RoCE, and ordinary data; the QoS parameters include, but are not limited to, Guaranteed Bit Rate (GBR) and maximum latency. In other words, the service awareness module obtains the type of the currently carried service and the corresponding QoS parameters, including the guaranteed bit rate, and uses the guaranteed bit rate as the minimum guaranteed bandwidth requirement.

[0048] In this invention, the minimum guaranteed bandwidth requirement includes the guaranteed bit rate. Guaranteed bit rate (GBR) is a Quality of Service (QoS) parameter in mobile communication networks, applicable to services with high real-time requirements such as voice and video calls. It guarantees the minimum bit rate that can be carried, ensuring that the corresponding bit rate is maintained even under conditions of limited network resources.

[0049] In this embodiment, when the link quality meets the degradation triggering condition, the minimum guaranteed bandwidth requirement of the currently carried service is obtained, and it is determined whether the preset target degradation mode meets the minimum guaranteed bandwidth requirement. This introduces a service QoS awareness mechanism to realize intelligent decision-making that prioritizes service experience, ensuring that the degradation switching operation is only executed when the bandwidth meets the minimum service requirement, ensuring that the degradation switching operation will not lead to insufficient service bandwidth, and avoiding service damage caused by blind speed reduction.

[0050] In one embodiment, in step S4, it is determined whether the preset target degradation mode bandwidth meets the minimum guaranteed bandwidth requirement.

[0051] Specifically, please refer to Figure 2 , Figure 3 and Figure 4 The electronic device 500 is equipped with a policy decision module 509. This policy decision module is used to determine whether to switch and the preset target degradation mode to switch to, based on the link quality assessment results and service awareness information, according to a preset degradation decision mechanism. When the available bandwidth of the preset target degradation mode is greater than or equal to the minimum guaranteed bandwidth requirement, a degradation switching operation is triggered; when the available bandwidth of the preset target degradation mode is less than the minimum guaranteed bandwidth requirement, the current high-speed mode is maintained and an alarm is reported. The preset degradation decision mechanism includes degradation trigger condition judgment and service bandwidth guarantee judgment.

[0052] The preset target degradation mode is a low-speed mode operating at 2500BASE-X with a bandwidth of 2.5G, using 8B / 10B encoding.

[0053] In this invention, a service QoS-aware preset degradation decision mechanism is adopted, specifically: degradation trigger condition judgment and service bandwidth guarantee judgment are introduced into the degradation decision process. When the degradation trigger condition is met, the policy decision module queries the service awareness module for the guaranteed bit rate (GBR) requirement of the currently carried service; when the available bandwidth of the preset target degradation mode is greater than or equal to GBR, the trigger mode switching execution module performs a degradation switching operation; otherwise, the current high-speed mode is maintained and an alarm is reported.

[0054] Since existing technologies do not consider the needs of the service layer and adopt a "one-size-fits-all" speed reduction strategy, this invention introduces a service QoS awareness mechanism to achieve intelligent decision-making that prioritizes service experience. This ensures that degradation switching operations are only performed when the bandwidth meets the minimum service requirements, and that degradation switching operations do not lead to insufficient service bandwidth, thus avoiding service damage caused by blind speed reduction. It unifies "link quality assurance" and "service experience assurance" within the same decision-making framework, elevating "speed reduction" from a purely link-layer behavior to a system-level behavior of "joint optimization of link quality and service experience," reflecting the design concept of system-level intelligent control.

[0055] In one embodiment, in step S5, if the preset target degradation mode meets the minimum guaranteed bandwidth requirement, a degradation switching operation is performed to switch the SerDes link from the current high-speed mode to the low-speed mode corresponding to the preset target degradation mode; the high-speed mode and the low-speed mode are different working modes of the SerDes physical layer.

[0056] Specifically, the high-speed mode is when the SerDes link operates in SFI mode and uses 64B / 66B encoding; the low-speed mode is when the SerDes link operates in the preset target degradation mode of 2500BASE-X and uses 8B / 10B encoding; the degradation switching operation includes switching the encoding method of the SerDes physical layer from 64B / 66B to 8B / 10B.

[0057] Please see Figure 2 , Figure 3 and Figure 4 The electronic device 500 is equipped with a mode switching execution module 510. This module configures the SerDes interface mode registers of the PHY chip and MAC controller through a preset management interface, and executes a smooth degradation switching process to switch the SerDes link from the current high-speed mode to the low-speed mode corresponding to the preset target degradation mode. The degradation switching process includes sub-steps such as traffic pause, buffer emptying, soft reset, register configuration, link verification, and traffic recovery. The preset management interface includes MDIO, I2C, or SPI.

[0058] More specifically, the degradation handover process includes: sending an IEEE 802.3x Pause flow control frame to pause traffic → waiting for the transmission queue to empty → performing a soft reset on the PHY chip → configuring the PHY chip's SerDes control register to the low-speed mode corresponding to the preset target degradation mode → configuring the MAC controller's SerDes interface mode to match the PHY chip → releasing the PHY chip reset and waiting for link training to complete → verifying the link status (Link Up, CDR Lock, BER normal) → resuming data traffic after the link status is normal. This achieves a fine-grained degradation mechanism based on SerDes physical layer mode switching, directly controlling the SerDes interface mode registers of the PHY chip and MAC controller to achieve a precise and smooth degradation handover from SFI high-speed mode to 2500BASE-X low-speed mode.

[0059] Because existing technologies typically reinitialize the link directly during rate switching, leading to brief service interruptions, this invention defines a standardized mode switching execution process. This process includes complete steps such as traffic backpressure (sending a Pause frame or disabling TX enable), emptying the transmission queue, soft reset of the PHY chip, register configuration, link status verification, and traffic recovery. This allows for smooth, lossless switching when link quality deteriorates, achieved through flow control frames and buffer emptying mechanisms. It downgrades the SerDes mode from SFI (5G) to 2500BASE-X (2.5G), enabling fine-grained 2.5G rate degradation. This avoids the excessive bandwidth jump caused by directly downgrading from 10G to 1G. Furthermore, the 8B / 10B encoding used in 2500BASE-X offers stronger clock recovery and anti-interference capabilities compared to the 64B / 66B encoding of SFI, effectively reducing the quality requirements of the physical channel. It significantly suppresses link interruptions and bit errors, ensuring zero data loss and zero service interruption during the switching process, thus better adapting to application scenarios with precise bandwidth requirements, such as 5G fronthaul.

[0060] In one embodiment, see Figure 2 and Figure 3 In step S6, the link quality is continuously monitored under the preset target degradation mode. When the link quality meets the preset switchback conditions, a switchback is automatically executed to switch the SerDes link from the low-speed mode back to the high-speed mode. Specifically, this includes: S61. Under the preset target degradation mode, continuously monitor the quality parameters of the SerDes link between the MAC controller and the PHY chip in real time for N preset evaluation cycles, and continuously obtain the link quality evaluation results within N preset evaluation cycles, where N is a positive integer.

[0061] The implementation process of real-time detection of the quality parameters of the SerDes link between the MAC controller and the PHY chip in each preset evaluation cycle is similar to the implementation process of step S1 above, and will not be repeated here.

[0062] The implementation process for obtaining the link quality assessment results within each preset assessment period is similar to the implementation process for obtaining the link quality assessment results in step S2 above, and will not be repeated here.

[0063] For example, N=3. Under the preset target degradation mode, the quality parameters of the SerDes link between the MAC controller and the PHY chip are continuously monitored in real time for 3 preset evaluation cycles, and the continuous evaluation results of the link quality within the 3 preset evaluation cycles are obtained.

[0064] S62. Based on the continuously obtained link quality assessment results, determine whether the preset back-switch conditions are met. When the bit error rate in the consecutive N preset assessment periods is lower than the preset recovery trigger low threshold (e.g., 1E-9) and no flashover event occurs, determine that the link quality meets the preset back-switch conditions and trigger the back-switch process.

[0065] Specifically, the strategy decision module determines whether preset handover conditions are met based on continuously obtained link quality assessment results. When the bit error rate (BER) is lower than the preset recovery trigger low threshold (TL_ber) for N consecutive preset assessment periods and no intermittent interruption events occur, the link quality is determined to meet the preset handover conditions, and the handover process is triggered. The preset handover conditions include a BER continuously lower than the preset recovery trigger low threshold (TL_ber) for multiple consecutive preset assessment periods and no intermittent interruption events.

[0066] S63. Automatically execute the back-switch process to switch the SerDes link from low-speed mode back to high-speed mode.

[0067] Specifically, the mode switching execution module automatically executes the back-switch process, switching the SerDes link from low-speed mode back to high-speed mode.

[0068] The back-switch process is symmetrical to the downgrade process. This mode switching execution module is used to configure the SerDes interface mode register of the PHY chip and MAC controller through the preset management interface, and execute the smooth back-switch process operation to switch the SerDes link from the current low-speed mode back to the high-speed mode. The back-switch process operation includes sub-steps such as traffic pause, buffer emptying, soft reset, register configuration, link verification, and traffic recovery.

[0069] More specifically, the handover process includes: sending an IEEE 802.3x Pause flow control frame to pause traffic → waiting for the transmission queue to empty → performing a soft reset on the PHY chip → configuring the SerDes control register of the PHY chip to target mode → configuring the SerDes interface mode of the MAC controller to match the PHY chip → releasing the PHY chip reset and waiting for the link training to complete → verifying the link status (Link Up, CDR Lock, BER normal) → resuming data traffic after the link status is normal.

[0070] This enables an adaptive back-switch recovery mechanism based on hysteresis comparison. Specifically, a preset recovery trigger low threshold TL_ber (far lower than the preset degradation trigger high threshold TH_ber) is set. The back-switch operation is only triggered after the link bit error rate has been continuously lower than the preset recovery trigger low threshold TL_ber for N consecutive preset evaluation cycles and there are no intermittent events. This directly controls the SerDes interface mode register of the PHY chip and MAC controller, enabling precise and smooth back-switch switching of the physical layer mode from 2500BASE-X low-speed mode to SFI high-speed mode.

[0071] In this invention, the high and low thresholds include a preset degradation trigger high threshold TH_ber and a preset recovery trigger low threshold TL_ber. A hysteresis interval is formed when the preset recovery trigger low threshold TL_ber < the preset degradation trigger high threshold TH_ber. The hysteresis comparison strategy includes that the bit error rate is continuously lower than the preset recovery trigger low threshold TL_ber for multiple consecutive preset evaluation periods without any interruption events.

[0072] In this embodiment, by employing a dual-threshold strategy of preset recovery trigger low threshold TL_ber and preset degradation trigger high threshold TH_ber, along with a hysteresis comparison strategy of continuous periodic verification (i.e., the bit error rate is continuously lower than the preset recovery trigger low threshold TL_ber for multiple consecutive preset evaluation periods without any interruption events), automatic link quality back-switching is achieved. This maximizes bandwidth utilization while ensuring stability, and effectively prevents frequent ping-pong switching (i.e., the oscillation phenomenon of degradation → back-switching → further degradation) caused by fluctuations in link quality near the threshold values, thereby improving system stability.

[0073] Based on the same inventive concept, please refer to Figure 4 , Figure 4 This is a schematic diagram of an Ethernet interface rate degradation control system based on link quality assessment provided in an embodiment of the present invention.

[0074] exist Figure 4 In the above embodiment, the Ethernet interface rate degradation control system 10 based on link quality assessment is applied to the Ethernet interface rate degradation control method based on link quality assessment, including: Link quality monitoring module 506 is used to continuously and in real time monitor the quality parameters of the SerDes link between the MAC controller and the PHY chip; The health assessment module 507 is used to collect the above quality parameters within a preset assessment period, obtain the link quality assessment results, and determine whether the link quality meets the degradation triggering conditions based on the link quality assessment results. The service awareness module 508 is used to obtain the minimum guaranteed bandwidth requirement of the currently carried service when the degradation trigger condition is met. The strategy decision module 509 is used to determine whether the preset target degradation mode bandwidth meets the minimum guaranteed bandwidth requirement. The mode switching execution module 510 is used to perform a degradation switching operation if the preset target degradation mode meets the minimum guaranteed bandwidth requirement, and switch the SerDes link from the current high-speed mode to the low-speed mode corresponding to the preset target degradation mode; the high-speed mode and the low-speed mode are different working modes of the SerDes physical layer. The strategy decision module 509 is also used to determine whether the preset back-switch conditions are met based on the continuously obtained link quality assessment results. When the continuously obtained link quality assessment results meet the preset back-switch conditions, the back-switch process is triggered. The mode switching execution module 510 is also used to automatically execute the back-switch process, switching the SerDes link from low-speed mode back to high-speed mode.

[0075] In this embodiment, an Ethernet interface rate degradation control system based on link quality assessment is provided. A link quality monitoring module monitors the quality parameters of the SerDes link between the MAC controller and the PHY chip in real time. A health assessment module statistically analyzes these quality parameters within a preset assessment period to obtain link quality assessment results, thereby monitoring link quality in real time. Based on the link quality assessment results, it determines whether the link quality meets the degradation trigger conditions. When the link quality meets the degradation trigger conditions, a service awareness module obtains the minimum guaranteed bandwidth requirement for the currently carried service. A policy decision module determines whether the bandwidth of the preset target degradation mode meets this minimum guaranteed bandwidth requirement, thus introducing a service QoS awareness mechanism to ensure that the degradation switching operation is only performed when the bandwidth meets the minimum service requirement, avoiding service damage due to blind speed reduction. A mode switching execution module performs a degradation switching operation when the preset target degradation mode meets the minimum guaranteed bandwidth requirement, switching the SerDes link from the current high-speed mode to the low-speed mode defined by the preset target degradation mode. When link quality deteriorates, the SerDes mode is downgraded from SFI (5G) to 2500BASE-X (2.5G), achieving fine-grained rate degradation at 2.5G. This avoids the excessive bandwidth jump caused by directly downgrading from 10G to 1G. Furthermore, the 8B / 10B encoding used in 2500BASE-X has stronger clock recovery and anti-interference capabilities compared to the 64B / 66B encoding of SFI, effectively reducing the quality requirements of the physical channel. It can significantly suppress link interruptions and bit errors, ensuring zero service interruption, and better adapting to application scenarios with precise bandwidth requirements, such as 5G fronthaul. The policy decision module continuously monitors the link quality under the preset target degradation mode. When the link quality meets the preset back-switch conditions, the back-switch process is triggered. The mode switching execution module automatically executes the back-switch process, switching the SerDes link from low-speed mode back to high-speed mode. Thus, through adaptive recovery mechanisms and hysteresis comparison strategies, automatic back-switch of link quality is achieved, maximizing bandwidth utilization while ensuring stability.

[0076] This invention provides an Ethernet interface rate degradation control system based on link quality assessment. This system can detect quality changes in high-speed Ethernet SerDes links in real time. When link quality deteriorates, it can finely and smoothly degrade the SerDes mode from high-speed mode to a suitable low-speed mode. Simultaneously, it can sense service bandwidth requirements to ensure the operation of core services and automatically switch back to high-speed mode after link quality recovers. This solves the problems of existing link rate control schemes that cannot detect quality changes in high-speed Ethernet SerDes links in real time, cannot degrade the SerDes mode from high-speed mode to a suitable low-speed mode when link quality deteriorates, and cannot automatically switch back to high-speed mode after link quality recovers.

[0077] It is understood that the link quality monitoring module 506, health assessment module 507, service awareness module 508, policy decision module 509, and mode switching execution module 510 in the Ethernet interface rate degradation control system based on link quality assessment can be implemented as hardware modules or as software modules, and the present invention does not impose any restrictions.

[0078] When implemented using hardware modules, the link quality monitoring module 506 can be integrated into the MAC controller 503 or the PHY chip 504 or exist independently. The health assessment module 507, the service awareness module 508, the policy decision module 509, and the mode switching execution module 510 can be integrated into the processor 501 as one of the hardware modules of the processor 501.

[0079] When implemented using software modules, the link quality monitoring module 506 can be a functional module within the MAC controller 503 or the PHY chip 504. The link quality monitoring module, health assessment module 507, service awareness module 508, policy decision module 509, and mode switching execution module 510 can be functional modules within the processor 501.

[0080] It should be noted that the above system embodiments and the above method embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments. Furthermore, the technical features in the method embodiments are all applicable to the above device embodiments, and will not be repeated here.

[0081] This invention provides an Ethernet interface rate degradation control method and system based on link quality assessment. It can detect changes in the quality of high-speed Ethernet SerDes links in real time; when link quality deteriorates, it can finely and smoothly degrade the SerDes mode from high-speed mode to a suitable intermediate rate (such as 2.5G / 5G) mode, rather than being limited to the standard tier; simultaneously, it can sense service bandwidth requirements to ensure the operation of core services; after link quality recovers, it can automatically switch back to high-speed mode; and based on physical layer mode switching, it ensures stability and compatibility after rate reduction. Ultimately, it achieves the goal of not interrupting critical services when link quality deteriorates and automatically returning to high-speed transmission after quality recovery. The specific technical effects achieved are as follows: (i) Fine-grained degradation. This invention achieves fine-grained degradation from 10G (SFI) to 2.5G (2500BASE-X), filling the gap in the existing technology where 5G directly jumps to 1G, and can more accurately adapt to the service needs of scenarios such as 5G fronthaul (approximately 2.5G bandwidth requirement).

[0082] (ii) Enhanced link stability assurance. By switching the SerDes physical layer mode (SFI→2500BASE-X), this invention not only reduces the rate but also changes the physical layer coding method and clock recovery mechanism (64B / 66B→8B / 10B), significantly improving the link's tolerance to the physical channel and providing better suppression of link intermittent interruptions than simple MAC layer rate limiting.

[0083] (III) Intelligent Decision-Making Prioritizing Service Experience. This invention introduces a service QoS awareness mechanism to ensure that downgrade switching operations do not lead to insufficient service bandwidth. It unifies "link quality assurance" and "service experience assurance" within the same decision-making framework, reflecting the design concept of system-level intelligent control.

[0084] (iv) Adaptive lossless back-switching capability. This invention adopts a high and low dual-threshold hysteresis comparison strategy, combined with a continuous periodic verification mechanism, to achieve automatic back-switching after link quality recovery, maximizing bandwidth utilization while ensuring switching stability.

[0085] (v) Smooth switching with zero interruption. This invention ensures zero data loss and zero service interruption during mode switching through a complete switching process design including traffic backpressure, buffer emptying, and link verification. It is suitable for scenarios with strict requirements on interruption time, such as 5G fronthaul.

[0086] (vi) Significant cost advantage. This invention is implemented entirely through software / firmware upgrades, without the need for any additional hardware. It only requires the PHY chip to support SFI and 2500BASE-X mode switching, which is almost zero cost compared to link aggregation redundancy solutions.

[0087] The present invention provides an Ethernet interface rate degradation control method and system based on link quality assessment, which can be widely used in high-speed communication scenarios such as 5G fronthaul, data center interconnection and AI intelligent computing clusters.

[0088] The following description uses the 5G fronthaul eCPRI interface scenario and the data center switch copper cable interconnection scenario as examples, but it is not limited to the scenarios mentioned above. The Ethernet interface rate degradation control method and system based on link quality assessment provided by this invention can be applied to any high-speed communication scenario using high-speed Ethernet interfaces (such as 10GE / 5GE / 2.5GE).

[0089] Application Implementation Method 1: Applied to 5G fronthaul eCPRI interface scenario.

[0090] In 5G base stations, the RRU (Remote Radio Unit) and DU (Distributed Unit) are connected via the eCPRI interface, and the physical layer uses a 10GE optical link (SFI mode) and an SFP+ optical module.

[0091] When the optical module's transmitted optical power decreases due to increased temperature or aging, the received signal amplitude weakens, and the bit error rate in SFI mode increases from the normal value of 1E-12 to over 1E-6.

[0092] Upon detecting an excessive BER (Bit Error Rate), this invention queries the eCPRI service's GBR (Bit Error Rate of 2.4576 Gbps) and determines that the 2.5 Gbps bandwidth of 2500BASE-X meets the requirements. It then performs a downgrade handover operation from SFI to 2500BASE-X. After the handover, the eCPRI link operates stably at 2.5 Gbps without any further interruptions. Once the optical module is replaced and the link quality remains stable for 180 seconds, it automatically switches back to SFI mode.

[0093] Application Implementation Method 2: Applied to copper cable interconnection scenarios for data center switches.

[0094] Within the data center, ToR switches are interconnected via 10G DACs (direct copper cables) over a distance of approximately 5 meters. Due to rack vibrations causing loose DAC connector contacts, the links frequently experience physical layer up / down interruptions. Although the instantaneous bit error rate may not have exceeded the standard, services have already been severely impaired.

[0095] The link quality monitoring module of this invention detects that the flicker frequency (Flap_Rate) exceeds the threshold of 3 times / minute, directly triggering degradation and switching SerDes to 2500BASE-X mode. Because the low-speed mode has a higher tolerance for connector contact impedance, the link returns to stability after degradation.

[0096] This invention also provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a computer processor, cause the processor to perform the method described in the foregoing embodiments.

[0097] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0098] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; under the concept of the present invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the present invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for controlling Ethernet interface rate degradation, characterized in that, The method includes: Obtain the quality parameters of the SerDes link between the MAC controller and the PHY chip detected in real time; Within a preset evaluation period, the quality parameters are statistically analyzed to obtain the link quality evaluation results, and based on the link quality evaluation results, it is determined whether the link quality meets the degradation triggering conditions. When the link quality meets the degradation triggering condition, obtain the minimum guaranteed bandwidth requirement for the currently carried service; Determine whether the preset target degradation mode bandwidth meets the minimum guaranteed bandwidth requirement; If the preset target degradation mode meets the minimum guaranteed bandwidth requirement, a degradation switching operation is performed to switch the SerDes link from the current high-speed mode to the low-speed mode corresponding to the preset target degradation mode; the high-speed mode and the low-speed mode are different working modes of the SerDes physical layer. The link quality is continuously monitored under the preset target degradation mode. When the link quality meets the preset back-switch conditions, the back-switch is automatically executed to switch the SerDes link from the low-speed mode back to the high-speed mode.

2. The method according to claim 1, characterized in that, The quality parameters of the SerDes link between the MAC controller and the PHY chip detected in real time include: The link status register and symbol error counter of the PHY chip are read at a preset sampling period, and the frame check sequence error statistics counter of the MAC controller is read at the same time. The sampled data is recorded to obtain the quality parameters.

3. The method according to claim 1, characterized in that, The high-speed mode is SFI mode, using 64B / 66B encoding; the low-speed mode is 2500BASE-X mode, using 8B / 10B encoding; the downgrade switching operation includes switching the encoding method of the SerDes physical layer from 64B / 66B to 8B / 10B.

4. The method according to claim 1, characterized in that, The step of determining whether the link quality meets the degradation triggering conditions based on the link quality assessment result includes: Calculate the bit error rate and interruption frequency within the preset evaluation period; Determine whether the bit error rate exceeds the preset degradation trigger high threshold, or whether the interruption frequency exceeds the interruption threshold; When the bit error rate exceeds the preset degradation trigger high threshold, or the intermittent disconnection frequency exceeds the intermittent disconnection threshold, the link quality is determined to meet the degradation triggering condition.

5. The method according to claim 1, characterized in that, When the link quality meets the degradation triggering condition, obtaining the minimum guaranteed bandwidth requirement for the currently carried service includes: Obtain the type of the currently carried service and the corresponding quality of service parameters, wherein the quality of service parameters include the guaranteed bit rate, and the guaranteed bit rate is used as the minimum guaranteed bandwidth requirement.

6. The method according to claim 1, characterized in that, The step of determining whether the preset target degradation mode bandwidth meets the minimum guaranteed bandwidth requirement includes: Based on the link quality assessment results and service awareness information, the decision on whether to switch and the preset target degradation mode for switching are determined according to the preset degradation decision mechanism. When the available bandwidth of the preset target degradation mode is greater than or equal to the minimum guaranteed bandwidth requirement, a degradation switching operation is triggered. When the available bandwidth of the preset target degradation mode is less than the minimum guaranteed bandwidth requirement, maintain the current high-speed mode and report an alarm.

7. The method according to claim 1, characterized in that, If the preset target degradation mode meets the minimum guaranteed bandwidth requirement, then a degradation switching operation is performed to switch the SerDes link from the current high-speed mode to the low-speed mode corresponding to the preset target degradation mode, including: By configuring the SerDes interface mode registers of the PHY chip and MAC controller, a smooth degradation switching process is executed to switch the SerDes link from the current high-speed mode to the low-speed mode corresponding to the preset target degradation mode. The degradation switching process includes: Send an IEEE 802.3x Pause flow control frame to pause data traffic; Waiting for the send queue to empty; Perform a soft reset on the PHY chip; Configure the SerDes control register of the PHY chip to the low-speed mode; Configure the SerDes interface mode of the MAC controller to match the PHY chip; Release the PHY chip reset and wait for the link training to complete; Data traffic was restored after verifying that the link status was normal.

8. The method according to claim 1, characterized in that, The process involves continuously monitoring link quality under the preset target degradation mode. When the link quality meets the preset switchback conditions, a switchback is automatically executed to switch the SerDes link from the low-speed mode back to the high-speed mode, including: Under the preset target degradation mode, the quality parameters of the SerDes link between the MAC controller and the PHY chip are continuously monitored in real time for N preset evaluation cycles, and the link quality evaluation results within N preset evaluation cycles are continuously obtained, where N is a positive integer. Based on the continuously obtained link quality assessment results, it is determined whether the preset back-switch conditions are met. When the bit error rate is lower than the preset recovery trigger low threshold and no flashover event occurs within the N consecutive preset assessment periods, it is determined that the link quality meets the preset back-switch conditions and the back-switch process is triggered. The automatic switchback process is executed to switch the SerDes link from the low-speed mode back to the high-speed mode.

9. An Ethernet interface rate degradation control system, characterized in that, The system, applied to the Ethernet interface rate degradation control method according to any one of claims 1 to 8, comprises: The link quality monitoring module is used to continuously and in real time detect the quality parameters of the SerDes link between the MAC controller and the PHY chip; The health assessment module is used to collect the above quality parameters within a preset assessment period, obtain the link quality assessment results, and determine whether the link quality meets the degradation triggering conditions based on the link quality assessment results. The service awareness module is used to obtain the minimum guaranteed bandwidth requirement of the currently carried service when the degradation trigger condition is met. The strategy decision module is used to determine whether the preset target degradation mode bandwidth meets the minimum guaranteed bandwidth requirement; The mode switching execution module is used to perform a degradation switching operation if the preset target degradation mode meets the minimum guaranteed bandwidth requirement, and switch the SerDes link from the current high-speed mode to the low-speed mode corresponding to the preset target degradation mode; the high-speed mode and the low-speed mode are different working modes of the SerDes physical layer. The strategy decision module is also used to determine whether the preset back-switch conditions are met based on the continuously obtained link quality assessment results. When the continuously obtained link quality assessment results meet the preset back-switch conditions, the back-switch process is triggered. The mode switching execution module is used to automatically execute the back-switch process to switch the SerDes link from low-speed mode back to high-speed mode.

10. A computer storage medium, characterized in that, The computer storage medium stores a computer program, which includes program instructions. When executed by a processor, the program instructions cause the processor to perform the Ethernet interface rate degradation control method according to any one of claims 1 to 8.

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