Low latency linear layer implementation optimization method and system based on multiple-input xors

Abstract

This invention relates to the field of cryptographic algorithm hardware optimization technology, and provides a method and system for optimizing low-latency linear layer implementations based on multi-input XOR gates. The method includes: initializing a target node set, a unit node set, a working set, and a predecessor node set; calculating the target node depth and determining the initial operation depth; executing a reverse search strategy based on the initial operation depth, prioritizing nodes according to node splitting rules, performing splitting operations on nodes in the working set according to the splitting rules, and dynamically adjusting the working set and predecessor node set based on the splitting results, and dynamically adjusting the operation depth; determining whether all nodes in the working set have been split into unit nodes of the unit node set; if so, proceeding to the next step; generating a linear layer implementation circuit with the minimum depth based on the splitting results, statistically analyzing resource utilization and latency indicators, and outputting the optimal implementation scheme if the conditions are met. This invention effectively solves the problem that the circuit depth is limited by the logarithmic growth of Hamming weight in traditional methods.

Description

Technical Field

[0001] This invention relates to the field of cryptographic algorithm hardware optimization technology, and in particular to a low-latency linear layer implementation optimization method and system based on multi-input XOR gates. Background Technology

[0002] With the rapid development of emerging applications such as the Internet of Things (IoT), wireless sensor networks, and embedded systems, the security requirements of lightweight cryptographic algorithms in resource-constrained environments are becoming increasingly prominent, making it one of the hot topics in cryptographic research. In symmetric cryptosystems, block ciphers are widely used in data encryption, identity authentication, and message authentication due to their fast encryption / decryption speed and high degree of standardization. However, traditional block cipher algorithms face problems such as low hardware resource utilization efficiency, slow computation speed, and resistance to side-channel attacks during implementation. Particularly in the implementation of linear components, the existing 2-input XOR gate implementation results in circuit depth being limited by the logarithmic growth of the Hamming weight, affecting the overall performance and security of the algorithm.

[0003] To address these issues, researchers began exploring new technical solutions. Introducing multi-input XOR gates (such as 3-input XOR gates, 3-XOR) is an effective method, but existing reverse search algorithms only support 2-XOR gates, making it difficult to fully utilize the advantages of multi-input gates. Furthermore, traditional algorithms also have shortcomings in node splitting rules and priority ordering, failing to effectively achieve global optimization goals. These problems make it difficult for existing cryptographic algorithms to simultaneously achieve low latency and small footprint in hardware implementation, especially in high-speed communication and real-time systems where latency-sensitive requirements are increasingly stringent.

[0004] Therefore, how to reduce latency and improve efficiency by optimizing the implementation of linear layers while ensuring the security of cryptographic algorithms has become an urgent problem to be solved in the fields of cryptography and hardware design. Especially on resource-constrained platforms, achieving efficient encryption and decryption functions while maintaining low hardware overhead has become a technical challenge for cryptographic algorithm optimization. Developing a low-latency linear layer implementation optimization method based on multi-input XOR gates can effectively solve these problems and provide new ideas for the hardware implementation of cryptographic algorithms.

[0005] Regarding the issues of latency and depth in linear layer implementations of cryptographic algorithms, some invention patents and related academic papers have been published, proposing heuristic algorithms for optimizing the hardware implementation of linear layers in cryptographic algorithms. However, existing technologies have the following drawbacks: 1. Traditional block cipher algorithms suffer from low hardware resource utilization efficiency, slow computation speed, and poor resistance to side-channel attacks, especially in the implementation of the linear layer. Existing 2-input XOR gate implementations limit circuit depth to the logarithmic growth of the Hamming weight, impacting the overall algorithm's performance and security.

[0006] 2. Existing reverse search algorithms only support 2-XOR gates, making it difficult to fully utilize the advantages of multi-input gates and creating a significant bottleneck in the implementation of linear layers. This makes it difficult to simultaneously achieve low latency and small area in hardware implementation, especially in high-speed communication and real-time systems where latency-sensitive requirements are increasingly stringent.

[0007] 3. Existing technologies lack effective methods to fully utilize the potential of multi-input XOR gates (such as 3-XOR) in reducing circuit depth and latency. This makes it difficult to implement lower-latency linear layer circuits in hardware, affecting the overall performance and applicability of cryptographic algorithms. Summary of the Invention

[0008] The purpose of this invention is to solve at least one technical problem in the background art and to provide a method and system for optimizing the implementation of a low-delay linear layer based on a multi-input XOR gate.

[0009] To achieve the above objectives, the present invention provides an optimization method for low-delay linear layer implementation based on multi-input XOR gates, characterized by comprising: S1. Set the input parameters as an m×n binary matrix, obtain the target node set, unit node set, working set and predecessor node set based on the input parameters, initialize the target node set, unit node set, working set and predecessor node set, calculate the depth of each target node based on the target node set, and select the maximum value of the target node depth as the initial operation depth; S2. Execute a reverse search strategy based on the initial operation depth, sort the nodes according to the priority of the node splitting rules, perform splitting operations on the nodes in the working set according to the splitting rules, and dynamically adjust the working set and the predecessor node set based on the splitting results, and dynamically adjust the operation depth; S3. Determine whether all nodes in the working set have been split into unit nodes in the unit node set. If not, return to step S2 to continue the splitting operation. If yes, proceed to step S4. S4. Generate a linear layer with the minimum depth based on the splitting results to implement the circuit, calculate resource utilization and latency indicators, and output the optimal implementation scheme if the conditions are met.

[0010] According to one aspect of the present invention, the initialization of the target node set, unit node set, working set, and predecessor node set, and the calculation of the target node depth and determination of the initial operation depth include: The working set is initialized as the row vectors of the input binary matrix. ,in, These are the row vectors of the input binary linear layer matrix; Initialize the unit node set to each input unit vector ,in Indicates the first Unit nodes with bit set to 1; Initialize the predecessor node set ; Calculate the minimum depth of each target node The depth of the binary matrix is ​​obtained. Determine the initial operation depth .

[0011] According to one aspect of the present invention, the step of executing a reverse search strategy based on an initial operation depth, prioritizing nodes according to node splitting rules, performing splitting operations on nodes in the working set according to splitting rules, and dynamically adjusting the working set and the predecessor node set based on the splitting results, and dynamically adjusting the operation depth, includes: Based on the current initial operation depth, each node in the working set is split using 2-XOR and 3-XOR rules. Select the splitting rule based on the set priority sorting rules; Perform node splitting according to the splitting rules, and update the working set and the predecessor node set; The current node's operation depth is dynamically adjusted, and high-priority splitting rules are prioritized for matching.

[0012] According to one aspect of the invention, the 3-XOR rule includes: For 3-XOR gates, the following splitting rules are defined: Rule 1: If it exists Satisfy node depth Then remove it from the working set Move to the precursor set ; Rule 2: for like Make Then from Remove ; Rule 3: like and Make Then from Remove from and in Add to ,in This represents a node with a minimum depth of k; Rule 4: like and Make Then from Remove from And in Add to ; Rule 5: This is the default partitioning rule, which randomly splits the data into three predecessor nodes, satisfying the following conditions: , Then from Remove from And in Add to ; The 2-XOR rule includes: For 2-XOR gates, the following splitting rule is defined: Rule 1: If it exists satisfy Then from Move to ; Rule 2: If ,have satisfy Then from delete ; Rule 3: If ,have , satisfy So from Remove from and in Add to ,in This represents a node with a minimum depth of k; Rule 4: If , satisfy , So from Remove from and in Add to ; Rule 5: This is the default splitting rule, which will randomly split the node into 2 predecessor nodes; The priority order of node splitting rules is as follows: rule 1 > rule 2 > rule 2 > rule 3 > rule 3 > rule 4 > rule 5, and other splitting rules are not considered.

[0013] According to one aspect of the present invention, the circuit that generates a linear layer of minimum depth based on the splitting result, calculates resource utilization and latency indicators, and outputs the optimal implementation scheme if certain conditions are met, includes: If the resource utilization rate and latency indicators meet the requirements, the optimal solution is output; if the resource utilization rate and latency indicators do not meet the requirements, the process returns to step S1 for re-optimization.

[0014] To achieve the above objectives, the present invention also provides a low-delay linear layer implementation optimization system based on a multi-input XOR gate, comprising: The parameter initialization module sets the input parameters to an m×n binary matrix, obtains the target node set, unit node set, working set, and predecessor node set based on the input parameters, initializes the target node set, unit node set, working set, and predecessor node set, calculates the depth of each target node based on the target node set, and selects the maximum value among the target node depths as the initial operation depth. The node splitting and adjustment module executes a reverse search strategy based on the initial operation depth, sorts nodes according to the priority of the node splitting rules, performs splitting operations on the nodes in the working set according to the splitting rules, and dynamically adjusts the working set and the predecessor node set based on the splitting results, and dynamically adjusts the operation depth. The node splitting result judgment module determines whether all nodes in the working set have been split into unit nodes in the unit node set. If not, it returns to step S2 to continue the splitting operation; if so, it executes step S4. The linear layer implementation circuit generation and output module generates the minimum depth linear layer implementation circuit based on the splitting results, calculates resource utilization and latency indicators, and outputs the optimal implementation scheme if the conditions are met.

[0015] To achieve the above objectives, the present invention also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, it implements the low-latency linear layer implementation optimization method based on multi-input XOR gates as described above.

[0016] To achieve the above objectives, the present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the low-latency linear layer implementation optimization method based on a multi-input XOR gate as described above.

[0017] According to the present invention, by introducing a 3-XOR gate in the reverse search algorithm and improving the node splitting rule, the present invention breaks through the depth limitation of the traditional 2-XOR implementation, reduces the minimum circuit depth of the 4×4MDS matrix to 2, and effectively solves the problem that the circuit depth is limited by the logarithmic growth of Hamming weight in the traditional method. By introducing 3-XOR gates, this invention significantly reduces the number of XOR operations compared to the traditional 2-XOR implementation, thereby reducing the complexity of hardware implementation and lowering latency. This effectively solves the problem of unclear area-latency trade-offs in the prior art. This invention employs a dynamic depth adjustment mechanism, combining the priority ordering of 2-XOR and 3-XOR rules, to achieve a global optimization goal. It is suitable for resource-constrained scenarios such as the Internet of Things, effectively balancing the latency and hardware overhead of cryptographic components, and providing a better linear layer implementation scheme for lightweight block ciphers and hash functions. Attached Figure Description

[0018] Figure 1 The flowchart schematically illustrates an optimization method for low-latency linear layer implementation based on a multi-input XOR gate according to an embodiment of the present invention. Figure 2 This diagram illustrates different partitioning rules for a 3-XOR gate according to one embodiment of the present invention. Figure 3 The diagram illustrates different partitioning rules for a 2-XOR gate according to one embodiment of the present invention. Detailed Implementation

[0019] The invention will now be discussed with reference to exemplary embodiments. It should be understood that the described embodiments are merely intended to enable those skilled in the art to better understand and thus implement the invention, and are not intended to imply any limitation on the scope of the invention.

[0020] As used herein, the term "comprising" and its variations are to be interpreted as open-ended terms meaning "including but not limited to". The term "based on" is to be interpreted as "at least partially based on". The terms "one embodiment" and "an embodiment" are to be interpreted as "at least one embodiment".

[0021] Figure 1 The flowchart schematically illustrates an optimization method for low-latency linear layer implementation based on a multi-input XOR gate according to an embodiment of the present invention. Figure 1 As shown, in this embodiment, the optimization method for low-latency linear layers based on multi-input XOR gates includes: S1. Set the input parameters as an m×n binary matrix, obtain the target node set, unit node set, working set and predecessor node set based on the input parameters, initialize the target node set, unit node set, working set and predecessor node set (predecessor set), calculate the depth of each target node based on the target node set, and select the maximum value of the target node depth as the initial operation depth; S2. Execute a reverse search strategy based on the initial operation depth, sort the nodes according to the priority of the node splitting rules, perform splitting operations on the nodes in the working set according to the splitting rules, and dynamically adjust the working set and the predecessor node set based on the splitting results, and dynamically adjust the operation depth; split the nodes in the working set according to the splitting rules, which can be divided into two (corresponding to 2 input XOR) or three predecessor nodes (corresponding to 3 input XOR), and put the predecessor nodes into the predecessor node set. S3. Determine whether all nodes in the working set have been split into unit nodes in the unit node set. If not, return to step S2 to continue the splitting operation. If yes, proceed to step S4. S4. Based on the splitting results, generate the linear layer implementation circuit with the minimum depth, statistically analyze resource utilization and latency indicators, and output the optimal implementation scheme if the conditions are met. The linear layer implementation circuit actually reflects the splitting results of the nodes in the working set. For example, in S2, the splitting operation splits node a in the working set into b and c, and the corresponding circuit is a = b + c. At this time, a 2-input XOR gate circuit is added to the circuit set. .

[0022] Further, according to one embodiment of the present invention, initializing the target node set, unit node set, working set, and predecessor node set, calculating the target node depth, and determining the initial operation depth includes: The working set is initialized as the row vectors of the input binary matrix. ,in, The input binary linear layer matrix consists of row vectors, which are the target vectors. Initialize the unit node set to each input unit vector ,in Indicates the first Unit nodes with bit set to 1; Initialize the predecessor node set , Indicates the empty set; Calculate the minimum depth of each target node The depth of the binary matrix is ​​obtained. Determine the initial operation depth .

[0023] Furthermore, according to one embodiment of the present invention, a reverse search strategy is executed based on the initial operation depth, and the nodes in the working set are sorted by priority according to the node splitting rules. Splitting operations are then performed on the nodes according to the splitting rules, and the working set and the predecessor node set are dynamically adjusted based on the splitting results, thereby dynamically adjusting the operation depth. This includes: Based on the current initial operation depth, each node in the working set is split using 2-XOR and 3-XOR rules. Select the splitting rule based on the set priority sorting rules; Perform node splitting according to the splitting rules, and update the working set and the predecessor node set; The operation depth of the current node is dynamically adjusted (the initial operation depth is set to the maximum target node depth. First, the working set and predecessor node set are initialized. Then, the nodes in the working set are split according to the splitting rules, and the resulting predecessor nodes are added to the predecessor node set. Finally, the nodes in the working set are split, at which point the working set is empty, and the predecessor node set contains the resulting predecessor nodes. Then, the depth is decremented by one: s = s - 1, working set ← predecessor node set, predecessor node set ← ∅, and the predecessor node set is set to empty. This completes the dynamic adjustment of the node operation depth.), and high-priority splitting rules are matched first.

[0024] Further, according to one embodiment of the present invention, it is determined whether all nodes in the working set have been split into unit nodes in the unit node set. If not, the process returns to step S2 to continue the splitting operation; if so, step S4 is executed, including: Determine if it satisfies ; If the above conditions are met, return to step S2 to continue the iteration; otherwise, proceed to step S4.

[0025] Furthermore, according to one embodiment of the present invention, the 3-XOR rule includes: like Figure 2 As shown, for a 3-XOR gate, the following splitting rule is defined: Rule 1 (Direct Migration Rule): like Figure 2 As shown in a, if it exists Satisfy node depth Then remove it from the working set Move to the precursor set ; Rule 2 (Three-Precursor Elimination Rule): like Figure 2 As shown in b, for like Make Then from Remove ; Rule 3` (Hybrid Precursor Generation Rule): like Figure 2 As shown in c, if and Make Then from Remove from and in Add to ,in This represents a node with a minimum depth of k; Rule 4 (Partial Precursor Generation Rule): like Figure 2 As shown in d, if and Make Then from Remove from And in Add to ; Rule 5 (default splitting rule): like Figure 2 As shown in e, this is the default partitioning rule, which randomly splits the node into three predecessor nodes, satisfying... , Then from Remove from And in Add to ; like Figure 3 As shown, the 2-XOR rule includes: For 2-XOR gates, the following splitting rule is defined: Rule 1: For example Figure 3 As shown in a, if it exists satisfy Then from Move to ; Rule 2: such as Figure 3 As shown in b, if ,have satisfy Then from delete ; Rule 3: For example Figure 3 As shown in c, if ,have , satisfy So from Remove from and in Add to ,in This represents a node with a minimum depth of k; Rule 4: For example Figure 3 As shown in d, if , satisfy , So from Remove from and in Add to ; Rule 5: For example Figure 3 As shown in e, this is the default splitting rule, which randomly splits the node into two predecessor nodes. The priority order of node splitting rules is as follows: rule 1 > rule 2 > rule 2 > rule 3 > rule 3 > rule 4 > rule 5, and other splitting rules are not considered.

[0026] In this implementation, the priority of node splitting rules is based on minimizing the number of newly added predecessors versus maximizing predecessor reuse. When splitting nodes using 3-XOR, rule 1' will match first because it reduces one node in the working set and adds one node to the predecessor set without requiring an additional XOR operation. Next is rule 2'. In rule 2', all three predecessor nodes are in the predecessor set, so no new predecessor node is generated; only a 3-XOR gate is needed to remove one node from the working set. Rule 3' splits a node where two of its predecessor nodes can be found in the predecessor set, generating a new predecessor node. Rule 4' splits a node where only one of its predecessor nodes can be found in the predecessor set, generating two new predecessor nodes. Therefore, if both can match, rule 3' is preferred over rule 4'. Rule 5' corresponds to the default node splitting method and can be considered the worst-case scenario, where a node will be split into three intermediate nodes. Therefore, when splitting nodes using 3-XOR, the priority relationship of the rules is: rule 1' > rule 2' > rule 3' > rule 4' > rule 5'. For the splitting rules corresponding to 2-XOR, the original reverse search method can be referenced: Rule 1 > Rule 2 > Rule 3 > Rule 4 > Rule 5. Considering all the above situations, the following priority order can be obtained: Rule 1 > Rule 2 > Rule 2 > Rule 3 > Rule 3 > Rule 4 > Rule 5. Other rules can be included in the above rules and are not considered.

[0027] Furthermore, according to one embodiment of the present invention, a linear layer with minimum depth is generated based on the splitting result to implement the circuit, and resource utilization and latency indicators are statistically analyzed. If the conditions are met, the optimal implementation scheme is output, including: If the resource utilization rate and latency indicators meet the requirements, the optimal solution is output; if the resource utilization rate and latency indicators do not meet the requirements, the process returns to step S1 for re-optimization.

[0028] In this embodiment, step S4 specifically includes: Step S41. Generate linear layers to implement the circuit based on the final split. For example, for a matrix... Based on output circuit assembly This results in a decision tree with, for example, 7 leaf nodes connected by 3-XOR or 2-XOR gates.

[0029] Step S42. Analyze the circuit resource utilization and delay performance. For example, at this time, the circuit set... The XOR gate count is 8, and the measurement circuit delay is 0.33µs on the UMC 55nm process hardware library.

[0030] Step S43. If the resource utilization and latency performance meet the requirements, output the optimal solution; otherwise, return to step S1 for re-optimization. For example, if the number of XOR gates is less than 10 and the latency is less than 0.5μs, it is determined to be the optimal solution. The resulting circuit meets the conditions, and the output circuit set is used. .

[0031] According to the above-described scheme of the present invention, by introducing a 3-XOR gate in the reverse search algorithm and improving the node splitting rule, the present invention breaks through the depth limitation of the traditional 2-XOR implementation, reduces the minimum circuit depth of the 4×4MDS matrix to 2, and effectively solves the problem that the circuit depth is limited by the logarithmic growth of Hamming weight in the traditional method. By introducing 3-XOR gates, this invention significantly reduces the number of XOR operations compared to the traditional 2-XOR implementation, thereby reducing the complexity of hardware implementation and lowering latency. This effectively solves the problem of unclear area-latency trade-offs in the prior art. This invention employs a dynamic depth adjustment mechanism, combining the priority ordering of 2-XOR and 3-XOR rules, to achieve a global optimization goal. It is suitable for resource-constrained scenarios such as the Internet of Things, effectively balancing the latency and hardware overhead of cryptographic components, and providing a better linear layer implementation scheme for lightweight block ciphers and hash functions.

[0032] Furthermore, to achieve the above objectives, the present invention also provides a low-delay linear layer implementation optimization system based on a multi-input XOR gate, comprising: The parameter initialization module sets the input parameters as a binary matrix, obtains the target node set, unit node set, working set, and predecessor node set based on the input parameters, initializes the target node set, unit node set, working set, and predecessor node set, calculates the depth of each target node based on the target node set, and selects the maximum value among the target node depths as the initial operation depth. The node splitting and adjustment module executes a reverse search strategy based on the initial operation depth, sorts nodes according to the priority of the node splitting rules, performs splitting operations on the nodes in the working set according to the splitting rules, and dynamically adjusts the working set and the predecessor node set based on the splitting results, and dynamically adjusts the operation depth. The node splitting result judgment module determines whether all nodes in the working set have been split into unit nodes in the unit node set. If not, it returns to step S2 to continue the splitting operation; if so, it executes step S4. The linear layer implementation circuit generation and output module generates the minimum depth linear layer implementation circuit based on the splitting results, calculates resource utilization and latency indicators, and outputs the optimal implementation scheme if the conditions are met.

[0033] The low-latency linear layer implementation optimization system based on multi-input XOR gates according to the present invention can realize the low-latency linear layer implementation optimization method based on multi-input XOR gates. The specific process steps are as described above and will not be repeated here.

[0034] Furthermore, to achieve the above objectives, the present invention also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, it implements the low-latency linear layer implementation optimization method based on multi-input XOR gates as described above.

[0035] Furthermore, to achieve the above objectives, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the optimization method for low-latency linear layer implementation based on multi-input XOR gates as described above.

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely one preferred embodiment of the invention and are only used to explain the invention. They do not limit the scope of protection of the invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0037] Example 1 This embodiment provides an optimization method for implementing a low-latency linear layer based on a multi-input XOR gate. The specific implementation steps are as follows: Step S1: Assume the input matrix is Its binary matrix representation is as follows: ; Based on the input matrix, the target node set, unit node set, working set, and predecessor node set are obtained. The target node set, unit node set, working set, and predecessor node set are initialized. The target node depth is calculated and the initial operation depth is determined. Step S11, for The initial working set is the row vectors of the linear layer matrix to be optimized. The unit node set is ; Step S12: Initialize the predecessor node set Circuit set ; Step S13: Calculate the minimum depth of each target node. , , obtain the matrix depth Initialize the current operation depth. The reverse processing starts from the maximum depth.

[0038] Step S2: Execute the reverse search algorithm to iteratively optimize the implementation scheme of the linear layer; Step S21: In this example, for the current operation depth... Matching rule 1: For ,if The minimum depth satisfies We will take it from Put .therefore, , ; Step S22, Next, segmentation Other nodes .if The nodes in the data can be split. If a node is selected from the list of nodes, no new node will be generated. First, use... To divide A new node must be generated. and ,available , Place it in the circuit set ; Step S23 It can split into , and No new nodes were added. Placed in circuit set ; Step S24: Continue splitting Generate new nodes and , can be obtained , Place it in the circuit set Update the collection , ; Step S25: Because Reset collection , , Matching rule 1, set , ; Step S26: Generate new unit nodes To split .final, , ; Step S27: Since at this time ,set up , , .

[0039] Step S3: Determine if all nodes have been split into unit nodes. If not, return to step S2; otherwise, execute step S4. For example, after step S2, at this point... All target nodes have been divided into unit nodes. The search process is now complete.

[0040] Step S4: Generate the optimal linear layer implementation circuit; Step S41: Generate a linear layer implementation circuit based on the final target node set; for example, for a matrix Based on output circuit assembly The final result is a decision tree constructed from 7 leaf nodes, which are connected by 3-XOR or 2-XOR gates. Step S42: Statistically analyze circuit resource utilization and delay performance; as shown in Table 1 below, the circuit set at this time... The XOR gate count is 8, and the measurement circuit delay is 0.33µs on the UMC 55 nm process hardware library. Table 1 Optimized circuit implementation of the matrix (8 XOR gates, depth 2) Step S43: If the resource utilization and latency performance meet the requirements, output the optimal solution; otherwise, return to step S1 for re-optimization. For example, if the number of XOR gates is less than 10 and the latency is less than 0.5μs, it is determined to be the optimal solution. The resulting circuit meets the conditions, and the output circuit set is used. .

[0041] This embodiment's low-latency linear layer implementation optimization method based on multi-input XOR gates is tested on linear layer matrices of a large number of cryptographic algorithms. The results show that for any linear layer matrix, the method of this embodiment can achieve its optimal circuit depth, and compared to scenarios using only 2-XOR gates, most matrices can achieve implementations with lower depths. Specifically, applying this embodiment's method to the MixColumns matrix of the most widely used cryptographic algorithm—AES—results shown in Table 2: only 68 XOR gates (59 3-XOR gates and 9 2-XOR gates) are needed to implement this matrix at a depth of 2.

[0042] Table 2 Optimized circuit implementation of AES MixColumns matrix (68 XOR gates, depth 2) Those skilled in the art will recognize that the modules and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0043] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described apparatus and equipment can be referred to the corresponding process in the foregoing method implementation, and will not be repeated here.

[0044] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or modules may be electrical, mechanical, or other forms.

[0045] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of the embodiments of the present invention, depending on actual needs.

[0046] In addition, the functional modules in the embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0047] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the sending / receiving methods of various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0048] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

[0049] It should be understood that the sequence number of each step in the invention and its embodiments does not absolutely imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

Claims

1. A low-delay linear layer implementation optimization method based on multi-input XOR gates, characterized in that, include: S1. Set the input parameters as an m×n binary matrix, obtain the target node set, unit node set, working set and predecessor node set based on the input parameters, initialize the target node set, unit node set, working set and predecessor node set, calculate the depth of each target node based on the target node set, and select the maximum value of the target node depth as the initial operation depth; S2. Execute a reverse search strategy based on the initial operation depth, prioritize nodes according to the node splitting rules, perform splitting operations on nodes in the working set according to the splitting rules, and dynamically adjust the working set and the predecessor node set based on the splitting results, and dynamically adjust the operation depth. S3. Determine whether all nodes in the working set have been split into unit nodes in the unit node set. If not, return to step S2 to continue the splitting operation. If yes, proceed to step S4. S4. Generate a linear layer with the minimum depth based on the splitting results to implement the circuit, calculate resource utilization and latency indicators, and output the optimal implementation scheme if the conditions are met.

2. The low-delay linear layer implementation optimization method based on multi-input XOR gates according to claim 1, characterized in that, The initialization of the target node set, unit node set, working set, and predecessor node set, and the calculation of the target node depth and determination of the initial operation depth include: The working set is initialized as the row vectors of the input binary matrix. ,in, These are the row vectors of the input binary linear layer matrix; Initialize the unit node set to each input unit vector ,in, Indicates the first Unit nodes with bit set to 1; Initialize the predecessor node set ; Calculate the minimum depth of each target node The depth of the binary matrix is ​​obtained. Determine the initial operation depth .

3. The low-delay linear layer implementation optimization method based on multi-input XOR gates according to claim 2, characterized in that, The reverse search strategy based on the initial operation depth, prioritizing nodes according to the node splitting rules, performing splitting operations on nodes in the working set according to the splitting rules, and dynamically adjusting the working set and predecessor node set based on the splitting results, and dynamically adjusting the operation depth, includes: Based on the current initial operation depth, each node in the working set is split using 2-XOR and 3-XOR rules. Select the splitting rule based on the set priority sorting rules; Perform node splitting according to the splitting rules, and update the working set and the predecessor node set; The current node's operation depth is dynamically adjusted, and high-priority splitting rules are prioritized for matching.

4. The low-delay linear layer implementation optimization method based on multi-input XOR gates according to claim 3, characterized in that, The 3-XOR rule includes: For 3-XOR gates, the following splitting rules are defined: Rule 1: If it exists Satisfy node depth Then remove it from the working set Move to the precursor set ; Rule 2: for like Make Then from Remove ; Rule 3: like and Make Then from Remove from and in Add to ,in This represents a node with a minimum depth of k; Rule 4: like and Make Then from Remove from And in Add to ; Rule 5: This is the default partitioning rule, which randomly splits the data into three predecessor nodes, satisfying the following conditions: , Then from Remove from And in Add to ; The 2-XOR rule includes: For 2-XOR gates, the following splitting rule is defined: Rule 1: If it exists satisfy Then from Move to ; Rule 2: If ,have satisfy Then from delete ; Rule 3: If ,have , satisfy So from Remove from and in Add to ,in This represents a node with a minimum depth of k; Rule 4: If , satisfy , So from Remove from and in Add to ; Rule 5: This is the default splitting rule, which will randomly split the node into 2 predecessor nodes; The priority order of node splitting rules is as follows: rule 1 > rule 2 > rule 2 > rule 3 > rule 3 > rule 4 > rule 5, and other splitting rules are not considered.

5. The low-delay linear layer implementation optimization method based on multi-input XOR gates according to claim 1, characterized in that, The circuit that generates a linear layer with minimum depth based on the splitting result, calculates resource utilization and latency metrics, and outputs the optimal implementation scheme if certain conditions are met, including: If the resource utilization rate and latency indicators meet the requirements, the optimal solution is output; if the resource utilization rate and latency indicators do not meet the requirements, the process returns to step S1 for re-optimization.

6. An optimized system based on a low-delay linear layer using multi-input XOR gates, characterized in that: include: The parameter initialization module sets the input parameters to an m×n binary matrix, obtains the target node set, unit node set, working set, and predecessor node set based on the input parameters, initializes the target node set, unit node set, working set, and predecessor node set, calculates the depth of each target node based on the target node set, and selects the maximum value among the target node depths as the initial operation depth. The node splitting and adjustment module executes a reverse search strategy based on the initial operation depth, sorts nodes according to the priority of the node splitting rules, performs splitting operations on the nodes in the working set according to the splitting rules, and dynamically adjusts the working set and the predecessor node set based on the splitting results, and dynamically adjusts the operation depth. The node splitting result judgment module determines whether all nodes in the working set have been split into unit nodes in the unit node set. If not, it returns to step S2 to continue the splitting operation; if so, it executes step S4. The linear layer implementation circuit generation and output module generates the minimum depth linear layer implementation circuit based on the splitting results, calculates resource utilization and latency indicators, and outputs the optimal implementation scheme if the conditions are met.

7. An electronic device, characterized in that, The system includes a processor, a memory, and a computer program stored in the memory and executable on the processor. When executed by the processor, the computer program implements the low-latency linear layer implementation optimization method based on a multi-input XOR gate as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, which, when executed by a processor, implements the low-latency linear layer implementation optimization method based on a multi-input XOR gate as described in any one of claims 1-5.

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