Aes side channel protection method based on neural network and random dual mode switching

Abstract

This invention discloses an AES side-channel protection method based on neural networks and random dual-mode switching, relating to the field of information security technology. For AES round key addition and column hybrid operations, a GF2Net neural network is established over a finite field GF(2), the connection weight matrix is ​​trained, and mode bias is configured only at the output layer. For S-box mapping, a fused row-shift position index-based original code bit string substitution matrix and inverse code bit string substitution matrix are pre-generated offline. Random control bits are generated round by round, and the output layer bias of the linear module and the lookup matrix of the nonlinear module are selected synchronously, causing the round key addition output and the nonlinear operation output to randomly switch between original code and inverse code representations. The column hybrid combination output is restored to the original code, and the ciphertext is output in the original code mode in the last round. Under the condition that the random control bits are approximately uniform, the expected Hamming weight of the intermediate results tends to half the bit width, thereby reducing the correlation between side-channel leakage and sensitive data.

Description

Technical Field

[0001] This invention relates to the field of information security and cryptographic chip protection technology, specifically to an AES side-channel protection method based on neural network and random dual-mode switching. Background Technology

[0002] Advanced Encryption Standard (AES) is one of the most widely used block cipher algorithms, deployed extensively in smart cards, IoT terminals, security chips, and embedded devices to protect data confidentiality. However, when the AES algorithm runs on physical devices, physical quantities such as power consumption, electromagnetic radiation, and runtime during the encryption process become correlated with sensitive intermediate data processed internally. Attackers do not need to crack the algorithm itself; they can recover the key using side-channel attacks such as differential power analysis and correlation power analysis simply by collecting and analyzing this physically leaked information, posing a serious threat to the actual security of the cryptographic implementation.

[0003] For side-channel attacks, existing protection technologies are mainly divided into two categories: masking and hiding. Masking technology introduces random numbers to randomly split sensitive intermediate variables, making the physical leakage decorrelated with the real data. However, it requires designing masking schemes for the linear and nonlinear components of the algorithm separately. In particular, the masking of S-boxes is complex, resource-intensive, and has limited protection capabilities against high-order attacks. Hiding technology reduces the leakage signal-to-noise ratio by balancing power consumption or inserting random delays, but it is difficult to fundamentally eliminate data correlation and often relies on specialized hardware circuits, resulting in poor versatility and portability.

[0004] Furthermore, the aforementioned methods typically implement AES linear and nonlinear operations separately. Operations such as byte substitution, row shifting, column mixing, and round key addition are passed between different components using explicit intermediate registers. The steady-state storage and transmission of intermediate variables can still generate physical leaks strongly correlated with the data, becoming a breakthrough point for side-channel attacks. Therefore, how to construct an AES side-channel protection method that is structurally unified, easy to implement, and can effectively balance physical leaks while maintaining the correctness of the AES encryption result is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The purpose of this invention is to provide an AES side-channel protection method based on neural networks and random dual-mode switching, to solve the problems of inconsistent implementation structures of linear and nonlinear components, complex S-box mask implementation, and difficulty in balancing physical leakage of intermediate variables in existing AES side-channel protection methods. While maintaining the correctness of the AES logic operation results and approximately uniform random control bits, the round key addition output and the nonlinear operation output are randomly switched between sign-magnitude and inverse-magnitude representations, making the expected Hamming weight approach half the bit width, thereby reducing the correlation between side-channel leakage and sensitive data.

[0006] To solve the above problems, the technical solution of the present invention is implemented as follows: A side-channel protection method for AES based on neural networks and random dual-mode switching includes the following steps: S1. Establish a finite field GF(2) neural network for implementing AES round key addition and column hybrid operations, train it to obtain the connection weight matrix, and configure the output layer bias; S2. Construct a bit string substitution matrix that integrates AES S-box mapping and row shifting position transposition to form a non-linear operation module; S3. Connect the linear module composed of the neural network and the nonlinear operation module according to the execution order of the AES round function to form a unified encrypted execution architecture; S4. Represent the state data and round key as bit strings, and establish a sign-magnitude mode and a one's complement mode to represent the same logical value. The bits of the one's complement mode are the bit-inverted values ​​of the corresponding sign-magnitude bits. S5. Perform dual-mode adaptation on the unified encryption execution architecture: keep the connection weight matrix of the neural network unchanged, only configure and select the original code mode bias or the inverse code mode bias in the output layer; generate the original code bit string replacement matrix LUT1 and the inverse code bit string replacement matrix LUT2 offline before encryption operation, and form a dual-channel bit string lookup matrix. S6. Generate random control bits for each round of control. Use the random control bits of the same round to synchronously select the output layer bias and search channel. Make the round key plus output and nonlinear operation output of this round use the original code representation or the inverse code representation. Make the column mixing module of non-last round restore the original code representation after XOR combination of two bytes. In the last round, select the original code mode and output the original code ciphertext.

[0007] Further, in step S1, the GF2Net neural network includes an input layer and an output layer, and the column-mixed GF2Net neural network also includes at least one hidden layer; each neuron in each layer is represented by a binary representation, and the connection weight matrix of each layer is a binary matrix over the finite field GF(2); the forward propagation of each layer is:

[0008] In the formula, For the first Layer output vector, For the first -1 layer output vector For the first -1st floor to the The connection weight matrix of the layer, The corresponding bias vector is used; multiplication and addition are performed according to the AND and XOR operations of the finite field GF(2), respectively; the bias vector corresponding to the hidden layer is fixed as an all-zero vector, and the bias of the output layer is selected according to the original code mode or the inverse code mode; the number of neurons in the input layer and the output layer is configured according to the data bit width of the AES linear operation to be implemented, and the connection weight matrix is ​​initialized with all zeros, all ones, or random initialization.

[0009] Furthermore, the training of this GF2Net neural network includes: constructing a training sample set, initializing the connection weight matrix of each layer, and fixing the output layer bias to an all-zero vector during the training phase; performing forward propagation, constructing an error function based on the network output and the target output, and calculating the output error; for training samples that generate errors, determining the voting intention value of each connection according to whether flipping the corresponding connection helps to correct the output error, and filtering valid votes based on the output state of the previous layer nodes; aggregating the valid votes of each connection to obtain the net vote count, flipping the weights corresponding to the connection with the largest net vote count and generating a weight flipping mask matrix M, and determining the connection to be updated through random perturbation when multiple connections have the same net vote count; updating the connection weight matrix according to W←W⊕M, and adopting a layer-by-layer update strategy from the output layer to the input layer, re-performing forward propagation after each update until the network reaches zero error.

[0010] Furthermore, the GF2Net neural network implements AES linear operations including round key addition and column hybrid operations. Specifically, in implementing round key addition, single-byte data from the AES state matrix and the corresponding single-byte round key are used as training sample inputs, and the XOR result of these two input bytes is used as the training sample target output. This trains the connection weight matrix for single-byte round key addition and maintains this connection weight matrix unchanged during AES encryption. In implementing column hybrid operations, the finite field corresponding to the AES column hybrid matrix is ​​used... The operation relationship is as follows: the four-byte operation of each column of the state matrix is ​​divided into two groups of two consecutive two-byte operations. Each group of two-byte inputs corresponds to the matrix coefficients (02, 03), (01, 01), (03, 01), and (01, 02), respectively. The two consecutive two-byte input data is used as input samples, and the corresponding finite field multiplication and XOR operation results are used as target outputs. Four types of GF2Net column hybrid computing units corresponding to the above matrix coefficients are established and trained respectively. During the AES encryption process, according to the positional relationship of the AES column hybrid matrix, the four types of GF2Net column hybrid computing units are reused and arranged in each output byte and column of the state matrix. The state matrix is ​​divided into two consecutive two-byte inputs by column and input into the corresponding GF2Net column hybrid computing units respectively. After obtaining the two-byte calculation results, they are rearranged according to the positional relationship of the AES column hybrid matrix and XOR combination is performed to obtain the column hybrid output of each column.

[0011] Further, step S2 includes: constructing the original code bit string substitution matrix LUT1 according to the input-output mapping relationship of the AES S-box, using 8-bit input bit data as the search index and the corresponding 8-bit S-box output bits as the search result; rearranging the output positions of the bit string substitution matrix according to the AES row shifting and transposition rules, so that the output result of the bit string substitution matrix simultaneously satisfies the requirements of byte substitution and row shifting; and using the bit string substitution matrix after the output position rearrangement as an AES nonlinear operation module to realize the integrated search calculation of byte substitution and row shifting.

[0012] Further, step S3 includes: constructing a round key addition module and a column mixing module based on the GF2Net neural network, as well as a nonlinear operation module based on the bit string substitution matrix and permutation index; connecting the round key addition module, the nonlinear operation module, and the column mixing module with a unified bit-level data interface according to the execution order of the AES round function to form a unified round function structure; in this unified round function structure, the round key addition module first performs round key addition operation on the input state matrix, then the nonlinear operation module performs byte substitution and row shifting integrated operation on the result of the round key addition operation, and finally... The column mixing module performs a column mixing operation on the result of the byte substitution and row shifting integrated operation, and uses the result of the column mixing operation as the input state matrix for the next round. During the AES encryption process, all rounds except the last round are executed according to this unified round function structure. In the last round, the round key addition module first performs a round key addition operation on the input state matrix, then the nonlinear operation module performs a byte substitution and row shifting integrated operation on the result of the round key addition operation, and finally the round key addition module performs a round key addition operation on the result of the byte substitution and row shifting integrated operation to obtain the encrypted output.

[0013] Further, step S4 includes: converting the state data involved in the AES encryption process into a unified bit-level representation; establishing two data representation methods, namely, the original code mode and the inverse code mode, wherein the original code mode uses the original bit representation and the inverse code mode uses the representation after inverting the corresponding bits; establishing a data mapping relationship between the original code mode and the inverse code mode so that the two data representation methods correspond to the same logical operation results; and establishing a dual-mode control interface for receiving random control signals and controlling the data representation mode of each operation module in the unified encryption execution architecture.

[0014] Further, in step S5, biases are set only at the output layers of each GF2Net neural network, and the connection weight matrices of each layer remain unchanged in dual mode; the original code mode bias is a vector of all zeros with the corresponding output bit width, and the round key plus GF2Net neural network's inverse code mode bias is an 8-bit vector of all one; for the q-th column hybrid GF2Net computation unit with 16-bit input and 8-bit output, Wq is the equivalent connection weight matrix from input to output of the computation unit, and its inverse code mode bias is the XOR result of the 16-bit vector of all one mapped by Wq and modulo 2 and the 8-bit vector of all one, so that the inverse code input yields a two-byte computation result in inverse code form; the original code bit string substitution matrix LUT1 and the inverse code bit string substitution matrix LUT2 are both pre-generated offline before encryption operation. LUT1 is a 256×8 bit matrix, with each row storing the S-box output bits corresponding to the 8-bit input index, and each bit element of LUT2 satisfies the following formula:

[0015] In the formula, i is the 8-bit input index of LUT1, the overscore of i indicates its bit-inverted index, j is the bit position, j=0,1,...,7; during the encryption stage, the offline fixed LUT1 or LUT2 address is selected only according to the random control bit m.

[0016] Further, in step S6, a random control bit sequence M=(m1, m2, ..., m10) corresponding to ten rounds of operation is generated for AES-128, where m1 to m9 are randomly selected as 0 or 1, and m10 is fixed as 0; at the beginning of each round, the input state matrix and the round key are both represented in original code; when mr=0, the round key of the r-th round is added to the GF2Net neural network with an all-zero output layer bias and the original code result is output, the nonlinear operation module selects LUT1 and outputs the original code result, and the column mixing GF2Net computing unit selects an all-zero output layer bias; when mr=1, the round key is added to the GF2Net neural network The network selects an 8-bit all-1 output layer bias and outputs the inverse code result. The nonlinear operation module selects LUT2 and outputs the inverse code result. Each column of the GF2Net hybrid computation unit selects the corresponding inverse code mode output layer bias, so that the two computation units constituting the same output byte output the inverse code of the corresponding part of the result respectively. The two inverse code results are XORed to restore the original code result of the output byte. From the first to the ninth round, the round key addition operation, byte substitution and row shift integrated operation and column hybrid operation are performed in sequence. In the tenth round, the round key addition operation, byte substitution and row shift integrated operation and the final round key addition operation are performed in sequence and the original code ciphertext is output.

[0017] Furthermore, the random control bit sequence is obtained by continuously sampling the original random sequence from the physical noise source, and then by debiasing and state expansion of the pseudo-random number generator; mode equalization is performed on the control bits that can take random values ​​so that the frequency of occurrence of 0 and 1 tends to be equal.

[0018] The AES side-channel protection method based on neural network and random dual-mode switching of the present invention has the following beneficial effects: This invention unifies linear operations such as round key addition and column mixing in AES into forward propagation of a GF2Net neural network over a finite field GF(2), and unifies nonlinear operations such as byte substitution and row shifting into a bit string lookup matrix that integrates row shifting. This forms a unified encryption execution architecture that uses table lookup operations to implement nonlinear operations and neural network forward propagation to implement linear operations. This reduces the transfer of intermediate registers between different components in traditional implementations and reduces the leakage of stable storage of sensitive intermediate variables.

[0019] This invention configures mode bias only in the output layer of the GF2Net neural network and keeps the connection weight matrix unchanged during dual-mode switching; the nonlinear module completes mode adaptation by selecting a pre-built LUT1 or LUT2, without configuring bias in the hidden layer or setting up online masking for the S-box, which is convenient to implement in a unified structure.

[0020] This invention uses the same random control bit to control the linear and nonlinear modules within a round, allowing the round key addition output and the nonlinear operation output to randomly switch between the original code representation and the inverse code representation. When the original code and the inverse code appear with approximately equal probability, the sum of the Hamming weights of the two representations of the same logic value equals the data bit width. Therefore, under the Hamming weight leakage model, its conditional expectation tends to half the bit width, which can reduce the correlation between leakage and sensitive data.

[0021] This invention employs a discrete error backpropagation mechanism based on voting rules to train the GF2Net neural network, using zero error as the convergence criterion. After training, the connection weight matrix is ​​fixed, and the AES logical operation results in each mode are kept consistent through determined bias and lookup table relationships. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the overall architecture of AES encryption based on neural network and random dual-mode switching of the present invention; Figure 2 This is a schematic diagram of the GF2Net neural network of the present invention implementing AES linear operation in the finite field GF(2); Figure 3 This is a schematic diagram of the integrated byte replacement and row shifting of the present invention, wherein (a) is the schematic diagram of the traditional step-by-step implementation, and (b) is the schematic diagram of the improved integrated implementation of the present invention. Figure 4 This is a schematic diagram illustrating the principle of generating the voting-based discrete error backpropagation weight flipping mask of the present invention. Figure 5 This is a schematic diagram of the original code / inverse code dual-mode representation and side channel leakage equalization of the present invention, wherein (a) is a schematic diagram of the Hamming weight complementary representation of the original code and inverse code, and (b) is a comparison curve of the instantaneous power consumption of intermediate variables before and after protection as a function of sample number. Figure 6 This is a comparison curve of the correlation coefficient of the power consumption analysis before and after protection of the present invention as a function of the number of power consumption curves; Figure 7 This is a convergence curve of the backpropagation training of the discrete error of the GF2Net neural network in this invention; Detailed Implementation

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0024] This embodiment uses AES-128 as an example, refer to... Figure 1 The overall encryption process of this invention is described below. Both the plaintext length and key length of AES-128 are 128 bits. The encryption process consists of ten rounds, with the states involved in the computation described below. byte matrix This means it consists of 16 bytes arranged in columns. For example... Figure 1 As shown, this invention reorganizes the AES-128 encryption process into a unified round function structure. Specifically, in one round of encryption, round key addition, byte substitution and row shifting combined operations, and column mixing operations are executed sequentially. The round key addition module and column mixing module are implemented using a GF2Net neural network, and the nonlinear operation module is implemented using a dual-channel bit string lookup matrix LUT1 / LUT2 that integrates row shifting. The random bit sequence generation unit obtains a random control bit sequence from a physical noise source through continuous sampling, bias removal, and pseudo-random number generator state expansion. ,in Used to control the The data representation mode of each module.

[0025] Specifically, the input consists of 128-bit plaintext, the round keys (RoundKey) obtained from key expansion, and a random control bit sequence M. Rounds one through nine sequentially perform round key addition, byte substitution and row shifting, and column mixing; the resulting original code temp_MC after column mixing is used as the input for the next round. Round ten sequentially performs round key addition, byte substitution and row shifting, and the final round key addition. Taking the standard test vector as an example, the plaintext is 0x3243F6A8885A308D313198A2E0370734, the key is 0x2B7E151628AED2A6ABF7158809CF4F3C, and the random control bit sequence is M=(1,0,1,1,0,1,0,0,1,0), where m10 is fixed at 0; the resulting original code ciphertext is 0x3925841D02DC09FBDC118597196A0B32, which is consistent with the standard AES-128 result.

[0026] In this embodiment, a unified bit-level data interface is used between the modules. The round key addition module takes the status byte bits and the round key byte bits as input and outputs an 8-bit bit string. The nonlinear operation module uses this 8-bit bit string as a lookup index and outputs an 8-bit replacement bit string. The column mixing module takes two consecutive byte bit strings as input and outputs a column-mixed byte bit string. This allows the output of the previous module to be directly used as the input of the next module, eliminating the need for explicit intermediate registers for data format conversion between modules. Furthermore, the method of this invention is based on the general structure of the AES round function and is also applicable to AES-192 and AES-256. In this case, it is only necessary to adjust the number of encryption rounds to 12 or 14 rounds and the length of the random control bit sequence to 12 or 14, while keeping the random control bit corresponding to the last round 0.

[0027] The construction and voting-based training of the GF2Net neural network are as follows. Figure 2 As shown, the GF2Net neural network is defined over the finite field GF(2). All neurons and connection weights are represented using binary values. Connections with weights of 1 participate in the XOR operation, while connections with weights of 0 do not. The round key addition GF2Net neural network uses an input layer and an output layer. The input layer has 16 neurons, corresponding to 8 bits of single-byte state data and 8 bits of single-byte round key, respectively. The output layer has 8 neurons. The column mixing GF2Net neural network sets up four types of computation units for coefficient pairs (02, 03), (01, 01), (03, 01), and (01, 02). Each type of computation unit has 16 neurons in the input layer, 16 neurons in the hidden layer, and 8 neurons in the output layer. Mode bias is only set in the output layer of each network.

[0028] The forward propagation of each layer uses the expressions in the technical disclosure document:

[0029] In the formula, For the first Layer output vector, For the first -1 layer output vector For the first -1st floor to the The connection weight matrix of the layer, The corresponding bias vector is used; each neuron performs an XOR operation on the effective connection input. The hidden layer bias is fixed as an all-zero vector; the output layer selects the corresponding bias according to the current mode, so mode switching does not change the connection weight matrix that has been trained and fixed.

[0030] During training, the connection weight matrix is ​​initialized with all zeros, and the output layer bias is fixed as an all-zero vector. The training sample set covers all combinations of values ​​in the input space. For a round key-adding network with a 16-bit input width, the total number of input combinations is... The system uses all 65,536 samples for training. During training, forward propagation is first performed and the results are calculated based on the error function. Calculate the output error, where For sample labels, For the current output layer's output, this error, for a binary output, is equivalent to a bitwise XOR operation between the two; subsequently, for each training sample that generates an error, the error is calculated from the previous layer's... The neurons in the next layer Voting intention value of each neuron connection When flipping the connection helps correct the output error of the sample, take... Otherwise take ; then, valid votes are selected based on the output state of the preceding layer source neurons, i.e., valid votes are the product of the output of the preceding layer source neurons and the voting intention value. When the source neuron outputs When the output is 0, the connection has an impact on the output of the subsequent layer and is counted as valid votes; when the output is 0, the connection has no impact on the output of the subsequent layer and is not counted. The net vote count for the connection is obtained by summing the valid votes of all training samples that generated errors. .like Figure 4 As shown in the figure, the first... The three neurons in the layer and the first The connections between two neurons in the first layer and their voting behavior, for the first layer Each neuron in the layer selects the input connection with the largest net vote count for flipping: when the first neuron... The maximum net voting connection of the first neuron in layer 1 is from the first neuron in layer 2. When connecting the first neuron in a layer, the weights are flipped through the mask matrix elements. Set 1, and Set to 0; when the first The maximum net vote connection of the second neuron in layer 2 is from the first neuron. When connecting the second neuron in the layer, Set 1, and Set to 0; generate a weighted inversion mask matrix accordingly. , and according to The weight matrix is ​​updated by performing an XOR flip, and a random perturbation is introduced to determine the connection to be updated when multiple connections have the same net vote count.

[0031] A layer-by-layer update strategy is adopted. First, the connection weights of the output layer are updated. Then, the updated error is backpropagated layer by layer to the hidden layers for sequential updates. After each update, the forward propagation calculation is re-executed, and the voting, flipping, and updating process is repeated until the network output is completely consistent with the target output, that is, the network converges to zero error. Figure 7 As shown, under the above training mechanism, the round key plus GF2Net neural network reaches zero error in the 33rd training iteration, and the calculation units of the corresponding coefficient pairs (02, 03), (03, 01), (01, 01), and (01, 02) in the column hybrid GF2Net neural network all reach zero error in the range of the 70th to 90th training iterations. Since the training is carried out in a discrete flipping manner on the finite field GF(2) and the convergence criterion is zero error, the network after training can accurately and error-free perform the corresponding AES linear operation, thereby ensuring that the encryption result is completely consistent with the standard AES.

[0032] The process of implementing round key addition and column hybrid operations in the GF2Net neural network is as follows. For round key addition, this operation is a bitwise XOR of the state byte and the round key byte, which is a linear operation on the GF(2) field. Therefore, it uses single-byte data from the state matrix. With the corresponding single-byte round key The training samples are constructed using the input and the XOR result of the two as the target output. The trained network makes each output bit... That is, each column of the equivalent connection weight matrix from the input layer to the output layer of the network contains exactly two elements with a value of 1, corresponding to... and The connection weight matrix is ​​fixed in the round key plus GF2Net neural network after training and remains unchanged throughout the encryption process.

[0033] The nonlinear operation module integrating byte substitution and row shifting is constructed as follows. Based on the AES S-box mapping relationship, a 256×8 two-dimensional lookup table, LUT1, is constructed, using 8-bit input bits as the lookup index and the corresponding 8-bit S-box output bits as the lookup result. For example... According to the AES row shifting rule, the 0th row of the state matrix is ​​not shifted, the 1st row is circularly shifted left by 1 byte, the 2nd row is circularly shifted left by 2 bytes, and the 3rd row is circularly shifted left by 3 bytes. That is, the 0th row is shifted left by 3 bytes. Circularly shift all bytes of the row to the left 1 byte.

[0034] like Figure 3 As shown in (a), in the traditional step-by-step implementation, the output of byte substitution needs to be written to an intermediate register first. The intermediate register is stored in a steady state, and then read and rearranged by the subsequent row shift module. This steady-state storage and data transfer can cause side-channel leakage that is strongly correlated with sensitive data; for example... Figure 3 As shown in (b), this invention pre-integrates the row shift position permutation relationship into the output position of the bit string substitution matrix. That is, during table lookup, the 8-bit substitution result is directly written to the target position after row shift, so that byte substitution and row shift are completed simultaneously in one table lookup operation. For example, the byte located in the 1st row and 0th column of the state matrix, after obtaining the S-box substitution result through LUT table lookup, is directly written to the 1st row and 3rd column position after row shift, without needing to be temporarily stored in a separate intermediate register. Thus, this invention completes byte substitution and row shift in one step by combining the bit string substitution matrix with the permutation index, avoiding explicit storage and transmission of intermediate registers between the two, reducing side-channel leakage points, and reducing the storage and timing overhead of nonlinear operations.

[0035] The unified encryption execution architecture is constructed as follows. First, a round key addition module and a column mixing module based on the GF2Net neural network are constructed, as well as a nonlinear operation module based on bit string substitution matrix and permutation index. Each module adopts a unified bit-level data interface, so that the output of the GF2Net linear module can be directly used as the lookup index of the nonlinear module, and the output of the nonlinear module can be directly used as the input of the GF2Net linear module. Thus, all intermediate data in the entire encryption process flows in the form of a unified bit string.

[0036] like Figure 1As shown, the modules described above are integrated according to the execution order of the AES round functions, reorganizing the AES encryption process into a unified round function structure: In one round of encryption, the round key addition module first performs a round key addition operation on the input state matrix, then the nonlinear operation module performs a byte substitution and row shift operation on the result of the round key addition operation, and finally the column mixing module performs a column mixing operation on the result of the byte substitution and row shift operation, using the result of the column mixing operation as the input state matrix for the next round. For AES-128, the first nine rounds are executed according to the unified round function structure described above; in the tenth round, since standard AES does not contain column mixing operations, after sequentially performing the round key addition operation and the byte substitution and row shift operation, a round key addition operation is performed again and the result is output. The above reorganization only changes the group boundaries of the operations without altering the order of operations: the standard AES-128 operation sequence is an initial round key addition, followed by nine rounds of byte substitution, row shifting, column mixing, and round key addition, with the final round being byte substitution, row shifting, and round key addition. This operation sequence, starting from the initial round key addition, is reorganized into groups of one round key addition, one byte substitution and row shift, and one column mixing, resulting in the unified round function structure for the first nine rounds of this invention. The remaining one round key addition, one byte substitution and row shift, and the final round key addition constitute the tenth round of this invention. Therefore, the reorganized unified architecture is logically completely equivalent to standard AES, and the encryption results remain consistent. Simultaneously, AES linear operations are uniformly implemented as the forward propagation of a GF2Net neural network, and nonlinear operations are uniformly implemented as a lookup table for a bit string lookup matrix, providing a consistent operation object and control interface for subsequent unified dual-mode adaptation and random switching of all operation modules.

[0037] The dual-mode adaptation of the unified encryption execution architecture is as follows. First, the data involved in the computation is uniformly converted into a bit-level representation, and a sign-magnitude mode and a one's complement mode are established. The bits in the one's complement mode are the bitwise inverses of the bits in the sign-magnitude mode. For example... Figure 5 As shown in (a), for 8-bit data, the sum of the Hamming weights of the original code and its inverse code is always equal to the data bit width, i.e. In the formula For source code, for The inverse code obtained by bitwise negation compensates for the Hamming weights of the same logical value in the two modes; for example, the original code. =0xA2 has a Hamming weight of 3, and its inverse code is 3. =0x5D has a Hamming weight of 5, and the sum of the two is 8. To achieve mode switching, a dual-mode control interface is established to receive random control signals and uniformly control the data representation mode of each arithmetic module.

[0038] In the GF2Net linear module, the connection weight matrices of each layer remain unchanged in both original code and inverse code modes, and only the output layer has a bias set. The input to the round key plus GF2Net neural network is the original code state byte and the original code round key byte; when m=0, the output layer uses an 8-bit all-zero bias and outputs the original code of a⊕k; when m=1, the output layer uses an 8-bit all-one bias and outputs NOT8(a⊕k), thus selecting the output representation only through the bias of the last layer. For the q-th class two-byte column hybrid GF2Net computation unit, the output layer bias in original code mode is an 8-bit all-zero vector; the output layer bias in inverse code mode is (1_16×Wq) mod 2⊕1_8, where 1_16 and 1_8 are 16-bit and 8-bit all-one vectors, respectively. Thus, the two-byte input in inverse code form, after passing through this computation unit, yields the inverse code of the corresponding part of the result. Each column of the state matrix is ​​a mixed output byte obtained by XORing the 8-bit results of two two-byte calculation units. When m=1, both calculation units output the partial result in one's complement form. The XOR of the two one's complements is equal to the XOR value of the partial results of the two original codes. Therefore, the column mixed combination output is restored to the original code.

[0039] In the nonlinear module, both the original code bit string substitution matrix LUT1 and the inverse code bit string substitution matrix LUT2 are pre-generated and solidified offline before the encryption operation. LUT1 stores 256 groups of 8-bit output bit strings according to the AES S-box mapping, and each bit element of LUT2 satisfies the following formula:

[0040] In original code mode, the input 8-bit string is written bit-by-bit to the corresponding position of the lookup index, forming an 8-bit index for matrix addressing. For example, when the input encoded value is 0x53, the corresponding row of LUT1 is located, and the 8 bits of that row are read as the output string, with an encoded value of 0xED. In inverse code mode, the input 8-bit string is written bit-by-bit to the corresponding position of the lookup index, forming an 8-bit index for matrix addressing. For example, when the input encoded value is 0xAC, the corresponding row of LUT2 is located, and the 8 bits of that row are read as the output string, with an encoded value of 0x12, where 0x12 and 0xED satisfy a bit-complementary relationship. The addressing and reading processes are the same in both modes, only the offline matrix data selected differs; during the encryption operation stage, LUT1 or LUT2 is directly selected based on the random control bit m, without performing bit-by-bit inversion to generate the lookup result online. The output positions of LUT1 and LUT2 are pre-arranged according to the row shift target position, and directly output to the corresponding position after looking up the table.

[0041] The random dual-mode switching process is as follows. At the beginning of each round, both the input state matrix and the current round key are represented in their original code form. When mr=0, the round key addition module selects an all-zero output layer bias to obtain the original code result temp_AddKey; the nonlinear module selects LUT1 to obtain the original code result temp_SR; the column mixing calculation unit selects an all-zero output layer bias, and the two partial results are XORed to obtain the original code result temp_MC. When mr=1, the round key addition module selects an 8-bit all-one output layer bias to obtain the inverse code result temp_AddKey; the nonlinear module selects LUT2 to obtain the inverse code result temp_SR; the column mixing calculation unit selects the corresponding inverse code mode output layer bias, making both partial results inverse codes, and the two are XORed to restore the original code result temp_MC. Therefore, the original code state is provided to the next round at the end of the first to ninth rounds.

[0042] The random dual-mode control module outputs `mr` according to the round, and uses this control bit to uniformly select the mode parameters of each module in the current round. Mode selection only changes the physical representation of the round key addition output and the nonlinear operation output, without changing their logical values. The column mixing module selects the output layer compensation bias according to the same control bit, and outputs the standard AES column mixing result after XORing the results of the two computation units. In the tenth round, `m10` is fixed to 0. Therefore, the first round key addition, byte substitution and row shift integrated operation, and the final round key addition in the tenth round all adopt the original code mode, directly outputting the original code ciphertext.

[0043] The random control bit sequence is generated as follows. For example... Figure 1 As shown on the right, physical random sources such as internal chip thermal noise and oscillator frequency jitter are used as entropy sources. The original random sequence is obtained through analog-to-digital conversion sampling, oscillator counting sampling, or other digital methods. The sampling rate is configured according to the chip process, the characteristics of the random source, and system security requirements. Since the original output of physical noise sources often has statistical bias, the von Neumann debiasing method is used to debias the original random sequence. That is, adjacent bits are paired, and when the bit pair is 01, 0 is output, when it is 10, 1 is output, and when it is 00 or 11, no output is output, thereby eliminating sampling bias and improving the uniformity of the random sequence.

[0044] The debiased random bits are then used as the seed for a pseudo-random number generator to expand the state, outputting a random control bit sequence with a length corresponding to the number of encryption rounds. The control bit corresponding to the last round is fixed at 0 according to the aforementioned rules. A mode equalization process is performed on this random control bit sequence to make the frequencies of occurrence of the original code mode and the inverse code mode during the encryption process approximately equal. That is, statistically, the probability of each randomly selected control bit being 0 or 1 is approximately one-half, thus achieving a better leakage equalization effect in the flipping of the intermediate variable between the original code and the inverse code, and improving side-channel protection capabilities.

[0045] This embodiment verifies the protection effect under the Hamming weight leakage model, calculating simulated leakage with and without dual-mode protection, and comparing the Pearson correlation coefficients corresponding to correct and incorrect key assumptions using correlation power analysis. This verification illustrates the balancing effect of dual-mode representation on first-order Hamming weight-related leakage.

[0046] like Figure 5 As shown in (b), without protection, the simulated leakage varies with the Hamming weight of the sensitive intermediate variable; after dual-mode switching, when the probability of the random control bit being 0 and 1 is 50%, the Hamming weights corresponding to the same logic value are HW and n-HW respectively, with a conditional expectation of n / 2. For an 8-bit intermediate result, this expectation is 4. Figure 6 As shown, in the unprotected implementation, the correlation coefficient of the correct key assumption clearly separates from the incorrect key assumption after approximately 1200 power consumption curves, and gradually stabilizes at approximately 0.58. Both the dual-mode protection curve and the incorrect key curve fluctuate around zero, failing to form a consistently stable separation as the number of curves increases. Local sampling points may exceed the empirical noise limit of ±4 / √N, but this is not persistent; within the range of 5000 curves shown, the correct key could not be stably identified based on this.

[0047] like Figure 7 As shown, the round-key addition GF2Net neural network achieved zero error in the 33rd training iteration, and the four types of two-byte column hybrid GF2Net computation units all achieved zero error within the 70-90th training iteration range. The zero-error training results demonstrate that the solidified connection weight matrix can achieve the corresponding AES linear mapping. By combining the output layer mode bias and the dual-channel bit string lookup relationship, the physical representation of the round-key addition output and the nonlinear operation output can be randomly switched while maintaining the consistency of the AES logical operation results, thereby reducing the correlation between first-order Hamming weight leakage and sensitive data.

[0048] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A side-channel protection method for AES based on neural networks and random dual-mode switching, characterized in that, Includes the following steps: S1. Establish a finite field GF(2) neural network for implementing AES round key addition and column hybrid operations, train it to obtain the connection weight matrix, and configure the output layer bias; S2. Construct a bit string substitution matrix that integrates AES S-box mapping and row shifting position transposition to form a non-linear operation module; S3. Connect the linear module composed of the neural network and the nonlinear operation module according to the execution order of the AES round function to form a unified encrypted execution architecture; S4. Represent the state data and round key as bit strings, and establish a sign-magnitude mode and a one's complement mode to represent the same logical value. The bits of the one's complement mode are the bit-inverted values ​​of the corresponding sign-magnitude bits. S5. Perform dual-mode adaptation on the unified encryption execution architecture: keep the connection weight matrix of the neural network unchanged, only configure and select the original code mode bias or the inverse code mode bias in the output layer; generate the original code bit string replacement matrix LUT1 and the inverse code bit string replacement matrix LUT2 offline before encryption operation, and form a dual-channel bit string lookup matrix. S6. Generate random control bits for each round of control. Use the random control bits of the same round to synchronously select the output layer bias and search channel. Make the round key plus output and nonlinear operation output of this round use the original code representation or the inverse code representation. Make the column mixing module of non-last round restore the original code representation after XOR combination of two bytes. In the last round, select the original code mode and output the original code ciphertext.

2. The AES side-channel protection method based on neural network and random dual-mode switching according to claim 1, characterized in that, In step S1, the GF2Net neural network includes an input layer and an output layer, and the column-mixed GF2Net neural network also includes at least one hidden layer; each neuron in each layer is represented by a binary value, and the connection weight matrix of each layer is a binary matrix over the finite field GF(2); the forward propagation of each layer is as follows: In the formula, For the first Layer output vector, For the first -1 layer output vector For the first -1st floor to the The connection weight matrix of the layer, The corresponding bias vector is used; multiplication and addition are performed according to the AND and XOR operations of the finite field GF(2), respectively; the bias vector corresponding to the hidden layer is fixed as an all-zero vector, and the bias of the output layer is selected according to the original code mode or the inverse code mode; the number of neurons in the input layer and the output layer is configured according to the data bit width of the AES linear operation to be implemented, and the connection weight matrix is ​​initialized with all zeros, all ones, or random initialization.

3. The AES side-channel protection method based on neural network and random dual-mode switching according to claim 2, characterized in that, The training of the GF2Net neural network includes: constructing a training sample set, initializing the connection weight matrix of each layer, and fixing the output layer bias to an all-zero vector during the training phase; performing forward propagation, constructing an error function based on the network output and the target output, and calculating the output error; for training samples that generate errors, determining the voting intention value of each connection based on whether flipping the corresponding connection helps to correct the output error, and filtering valid votes based on the output state of the previous layer nodes; aggregating the valid votes of each connection to obtain the net vote count, flipping the weights corresponding to the connection with the largest net vote count and generating a weight flip mask matrix M, and determining the connection to be updated by random perturbation when multiple connections have the same net vote count; updating the connection weight matrix according to W←W⊕M, and adopting a layer-by-layer update strategy from the output layer to the input layer, re-performing forward propagation after each update until the network reaches zero error.

4. The AES side-channel protection method based on neural network and random dual-mode switching according to claim 3, characterized in that, The GF2Net neural network implements AES linear operations, including round key addition and column hybrid operations. For round key addition, single-byte data from the AES state matrix and the corresponding single-byte round key are used as training sample inputs, and the XOR result of the two input bytes is used as the target output. This trains the connection weight matrix for single-byte round key addition and maintains the connection weight matrix unchanged during AES encryption. For column hybrid operations, the finite field corresponding to the AES column hybrid matrix is ​​used... The operation relationship is as follows: the four-byte operation of each column of the state matrix is ​​divided into two groups of two consecutive two-byte operations. The two-byte input of each group corresponds to the matrix coefficients (02, 03), (01, 01), (03, 01) and (01, 02), respectively. The two consecutive two-byte input data is used as input samples, and the corresponding finite field multiplication and XOR operation results are used as target outputs. Four types of GF2Net column hybrid computing units corresponding to the matrix coefficients are established and trained respectively. During the AES encryption process, according to the positional relationship of the AES column hybrid matrix, the four types of GF2Net column hybrid computing units are reused and arranged in each output byte and column of the state matrix. The state matrix is ​​divided into two consecutive two-byte inputs according to the columns and input to the corresponding GF2Net column hybrid computing units respectively. After obtaining the two-byte calculation results, they are rearranged according to the positional relationship of the AES column hybrid matrix and XOR combination is performed to obtain the column hybrid output of each column.

5. The AES side-channel protection method based on neural network and random dual-mode switching according to claim 1, characterized in that, Step S2 includes: constructing the original code bit string substitution matrix LUT1 according to the input-output mapping relationship of the AES S-box, using 8-bit input bit data as the search index and the corresponding 8-bit S-box output bits as the search result; rearranging the output positions of the bit string substitution matrix according to the AES row shifting and transposition rules, so that the output result of the bit string substitution matrix simultaneously satisfies the requirements of byte substitution and row shifting; and using the bit string substitution matrix after the output position rearrangement as an AES nonlinear operation module to realize the integrated search calculation of byte substitution and row shifting.

6. The AES side-channel protection method based on neural network and random dual-mode switching according to claim 1, characterized in that, Step S3 includes: constructing a round key addition module and a column mixing module based on the GF2Net neural network, as well as a nonlinear operation module based on the bit string substitution matrix and permutation index; connecting the round key addition module, the nonlinear operation module, and the column mixing module with a unified bit-level data interface according to the execution order of the AES round function to form a unified round function structure; in the unified round function structure, the round key addition module first performs round key addition operation on the input state matrix, then the nonlinear operation module performs byte substitution and row shifting operation on the result of the round key addition operation, and finally the column mixing module performs column mixing operation on the result of the byte substitution and row shifting operation, and uses the result of the column mixing operation as the input state matrix for the next round; during the AES encryption process, all rounds except the last round are executed according to the unified round function structure; in the last round, the round key addition module first performs round key addition operation on the input state matrix, then the nonlinear operation module performs byte substitution and row shifting operation on the result of the round key addition operation, and finally the round key addition module performs round key addition operation again on the result of the byte substitution and row shifting operation to obtain the encrypted output.

7. The AES side-channel protection method based on neural network and random dual-mode switching according to claim 1, characterized in that, Step S4 includes: converting the state data involved in the AES encryption process into a unified bit-level representation; establishing two data representation methods, namely, the original code mode and the inverse code mode, wherein the original code mode uses the original bit representation and the inverse code mode uses the representation after inverting the corresponding bits; establishing a data mapping relationship between the original code mode and the inverse code mode so that the two data representation methods correspond to the same logical operation results; and establishing a dual-mode control interface for receiving random control signals and controlling the data representation mode of each operation module in the unified encryption execution architecture.

8. The AES side-channel protection method based on neural network and random dual-mode switching according to claim 7, characterized in that, In step S5, biases are set only at the output layers of each GF2Net neural network, and the connection weight matrices of each layer remain unchanged in dual mode. The original code mode bias is a vector of all zeros with the corresponding output bit width, and the round key plus GF2Net neural network in inverse code mode bias is an 8-bit vector of all one. For the q-th column hybrid GF2Net computation unit with 16-bit input and 8-bit output, Wq is the equivalent connection weight matrix from input to output of the computation unit, and its inverse code mode bias is the XOR result of the 16-bit vector of all one and the vector obtained by mapping Wq and modulo 2 with the 8-bit vector of all one, so that the inverse code input yields a two-byte computation result in inverse code form. The original code bit string substitution matrix LUT1 and the inverse code bit string substitution matrix LUT2 are both pre-generated offline before encryption. LUT1 is a 256×8 bit matrix, with each row storing the S-box output bits corresponding to the 8-bit input index. Each bit element of LUT2 satisfies the following formula: In the formula, i is the 8-bit input index of LUT1, the overscore of i indicates its bit-inverted index, j is the bit position, j=0,1,...,7; during the encryption stage, the offline fixed LUT1 or LUT2 address is selected only according to the random control bit m.

9. The AES side-channel protection method based on neural network and random dual-mode switching according to claim 8, characterized in that, In step S6, a random control bit sequence M = (m1, m2, ..., m10) corresponding to ten rounds of operation is generated for AES-128, where m1 to m9 are randomly selected as 0 or 1, and m10 is fixed as 0. At the beginning of each round, the input state matrix and the round key are both represented in original code. When mr = 0, the round key of the r-th round is added to the GF2Net neural network with an all-zero output layer bias and the original code result is output. The nonlinear operation module selects LUT1 and outputs the original code result. The column mixing GF2Net computing unit selects an all-zero output layer bias. When mr = 1, the round key is added to the GF2Net neural network with an all-zero output layer bias. The output layer bias is set to 8 bits all 1 and the inverse code result is output. The nonlinear operation module selects LUT2 and outputs the inverse code result. The column-mixed GF2Net computing unit selects the corresponding inverse code mode output layer bias, so that the two computing units constituting the same output byte output the inverse code of the corresponding part of the result respectively. The two inverse code results are XORed to restore the original code result of the output byte. The first to ninth rounds are performed sequentially, including round key addition, byte substitution and row shift integrated operation and column mixing operation. The tenth round is performed sequentially, including round key addition, byte substitution and row shift integrated operation and final round key addition and outputting the original code ciphertext.

10. The AES side-channel protection method based on neural network and random dual-mode switching according to claim 9, characterized in that, The random control bit sequence is obtained by continuously sampling the original random sequence from the physical noise source, and then by debiasing and state expansion of the pseudo-random number generator. The control bits that can take random values ​​are subjected to mode equalization so that the frequency of occurrence of 0 and 1 tends to be equal.

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