IPSec acceleration scheme

Abstract

This invention discloses an IPSec acceleration scheme, relating to the field of data encryption and communication acceleration technology. The scheme includes: initializing a data area and a flag area, the flag area being used to identify the state of the data area, including three states: idle, data placement, and computation completed; the application organizes the data, writing encrypted authentication information, block number (BN), and encrypted authentication data into the data area according to a predetermined format; the data area content is moved to a designated memory space of the security chip via a DMA channel, and after the move is complete, the corresponding flag area state is set to data placement; the main process of the security chip continuously monitors the flag area state, and when the data placement flag is detected, it initiates the corresponding cryptographic calculation task to perform encryption and / or authentication operations on the encrypted authentication data in the data area, and after the operation is complete, the flag area state is set to computation completed; the security chip performs cryptographic calculations during data transfer or communication gaps, realizing parallel pipelined computation and communication; when the computation completed flag is detected, the corresponding block number and encrypted authentication data are returned to the application, and the application completes the data packet transmission and reception confirmation by matching the block number. This invention utilizes DMA migration and fixed cryptographic computation space to avoid data migration overhead. Combined with flag area status polling and block number matching mechanisms, it achieves pipelined parallelism of encryption / decryption processing and data communication, significantly improving the processing throughput and communication efficiency of the IPSec protocol.

Description

Technical Field

[0001] This invention relates to the field of data encryption and communication acceleration technology, specifically to an IPSec acceleration scheme, which is particularly suitable for application scenarios in security chips that improve the efficiency of IPSec protocol encryption and decryption processing through DMA transfer and pipelined parallel processing. Background Technology

[0002] IPSec (Internet Protocol Security) is a suite of protocols used to ensure the security of IP network communications. It provides encryption and authentication services at the network layer to ensure the confidentiality, integrity, and authenticity of data transmission. With the continuous growth of network bandwidth and the increasing demands for information security, IPSec protocols are widely used in network devices such as VPN gateways, security routers, and firewalls.

[0003] However, in traditional IPSec implementations, data encryption and decryption are typically performed serially by a general-purpose processor or a dedicated encryption engine. Specifically, when a data packet arrives, the system first copies the data from the receive buffer to the encryption / decryption processing space. After encryption and decryption are completed, the processed data is then copied to the send buffer for forwarding. This process involves multiple data transfer operations, consuming significant processor computing resources and memory bandwidth, and introducing additional processing latency. Especially in high-throughput scenarios, frequent data copying and context switching significantly degrade system performance, becoming a bottleneck restricting IPSec processing capabilities.

[0004] Existing improvement solutions sometimes attempt to accelerate encryption and decryption operations by adding dedicated encryption hardware coprocessors. However, data migration overhead remains, and the lack of an effective pipelined parallel mechanism between encryption computation and data communication results in low hardware resource utilization and limited overall throughput improvement. Furthermore, existing solutions lack flexible block number matching and state management mechanisms during packet processing, making it difficult to efficiently handle concurrent sending, receiving, and acknowledgment of multiple data packets, thus failing to fully leverage hardware acceleration capabilities.

[0005] Therefore, how to design an IPSec acceleration solution that can effectively reduce data migration overhead, enable parallel pipeline operation of encryption / decryption processing and data communication, and support flexible packet management has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] The purpose of this invention is to provide an IPSec acceleration solution to solve the technical problems in the prior art, such as high processing latency due to multiple data transfers, inability to perform encryption / decryption operations and data communication in parallel pipelined operation, and insufficient utilization of hardware resources.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] An IPSec acceleration scheme first initializes the data area and flag area by setting all contents to 0xFF. Each flag bit in the flag area identifies the status of the corresponding data area, including three states: idle, data placed, and computation completed. The size of the data area is set based on the maximum length of received data and password processing, and the number of data blocks received and sent is flexibly configured according to actual application requirements. This scheme is not limited to a specific communication interface and can adapt to various interface types.

[0009] During the data organization phase, the application organizes the data to be processed according to a predetermined format. Each data area consists of three parts: encrypted authentication information, block number (BN), and encrypted authentication data. The encrypted authentication information contains all the parameters required for cryptographic calculation, including the key, initialization vector (N), type, mode, encrypted data offset, and padding fields. The block number is specified by the application and used for matching and confirming subsequent data packets. The encrypted authentication data is the actual payload data to be encrypted and / or authenticated; the starting address of the authentication data plus the offset gives the starting position of the encrypted data.

[0010] After data organization is complete, the data is sent to the security chip via the interface channel. The security chip's internal firmware receives the data through an interrupt subroutine, specifically establishing a DMA channel between the interface and the data area. Upon arrival, the data is directly moved to the designated memory space of the security chip via DMA, without processor intervention in the data copying. After the move is complete, the interrupt subroutine sets the corresponding flag area status to "data placed" (e.g., 0x55), indicating that the data area has data to be processed and awaits password calculation. Subsequently, the security chip's interrupt subroutine or main process searches the flag area to determine if a data area marked as completed has existed. If it exists, the content of the corresponding data area starting from the block number is returned to the application, and the flag area and data area content are restored to the idle state (0xFF). If it does not exist, a status indication that the chip is busy calculating is returned.

[0011] During the execution of the main program, the security chip continuously monitors the status of each flag area. When a flag area is detected to have changed to "Data Placement" (0x55), the corresponding data area is immediately activated to perform the specified cryptographic calculation task. This involves using the encrypted authentication information in that data area to perform encryption and / or authentication operations on the encrypted authentication data, including but not limited to symmetric encryption algorithms such as AES and SM4, and authentication algorithms such as HMAC. During the cryptographic calculation process, the security chip fully utilizes the gaps in data transfer or communication interruptions to perform calculations, allowing the calculation task and data transmission task to form a pipeline in parallel, avoiding idle waiting by the calculation unit. Once all cryptographic calculations are completed, the status of the corresponding flag area is set to "Calculation Completed" (e.g., 0xAA).

[0012] During the data return phase, the application continuously monitors the security chip's return channel. When the security chip detects a completion flag, it returns the corresponding block number and the encrypted / authenticated data after encryption / authentication processing to the application. Upon receiving the response, the application matches the block number in the response with the block number specified during transmission. If a match is found, the application confirms that the transmission, reception, and processing of the data packet are complete and finally returns the result to the client. If no data block has been fully computed, a "device busy" indication is returned, and the application can continue to retrieve processed data in subsequent polling.

[0013] Through the above mechanism, the four stages of data reception, DMA transfer, cryptographic calculation, and data return are performed in overlapping time, achieving fully pipelined IPSec accelerated processing. The state of each data block is clearly identified by a flag area, the state transition is clear and controllable, multiple data blocks do not interfere with each other, and multiple data packets can be processed concurrently, significantly improving the system's parallel processing capability and resource utilization.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] Eliminating data migration overhead: By fixing the address of the cryptographic computing space and using DMA direct migration, data goes directly from the receiving interface to the computing space without the need for processor-intervention data copying operations, reducing CPU utilization and memory bandwidth consumption, and lowering processing latency.

[0016] Achieving a parallel pipeline for computation and communication: Utilizing communication gaps and DMA transfer time to perform cryptographic computation tasks, the four stages of data reception, DMA transfer, cryptographic computation, and data return overlap, keeping the computing resources of the security chip constantly busy and significantly improving the overall system throughput.

[0017] Flexible state management and block number matching mechanism: The processing progress of each data block is precisely managed through three states of the flag area (idle, data placed, and calculation completed). Combined with the block number matching mechanism, it supports out-of-order processing and accurate confirmation of multiple data packets. The next data packet can be processed without waiting for the previous data packet to be completely processed, which is suitable for high-concurrency network traffic scenarios.

[0018] Interface independence: This solution does not depend on a specific communication interface and can be flexibly adapted to various interfaces such as PCIe, USB, SPI, and Ethernet. It has good versatility and portability, making it easy to integrate into security devices with different architectures. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the storage structure of the data area and the flag area of ​​the present invention;

[0021] Figure 2 This is a schematic diagram of the data flow and state transitions in the IPSec accelerated processing of this invention;

[0022] Figure 3 This is the overall flowchart of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0024] The following example, using a specific IPSec packet acceleration process, illustrates the detailed implementation of this invention. This embodiment is based on a security chip integrating a DMA controller and a hardware encryption engine. This chip supports symmetric encryption algorithms such as AES and SM4, as well as authentication algorithms such as HMAC-SHA256. The communication interface uses a PCIe interface, but this invention is not limited thereto.

[0025] First, system initialization is performed. After the main program powers on and starts, it divides the designated memory space of the security chip into a flag area and a data area according to the preset number of data blocks (8 data blocks in this embodiment). The size of the data area is set according to the maximum length of data received and password processing in a single instance. In this embodiment, each data block is 2KB in size, of which the encrypted authentication information occupies 64 bytes, the block number (BN) occupies 8 bytes, and the encrypted authentication data occupies the remaining space. The specific length of each field can be flexibly adjusted according to the actual application. Each flag bit in the flag area is 4 bytes, used to identify the current state of the corresponding data area. During initialization, the entire contents of the flag area are set to 0xFFFFFFFF (i.e., idle state), and the entire contents of the data area are also filled with 0xFF. It should be noted that the specific values ​​of the status indicators can be selected according to the actual design. In this embodiment, 0xFFFFFFFF represents idle, 0x55555555 represents data placement, and 0xAAAAAAAA represents calculation completion, which is only used as an example.

[0026] After initialization, the application begins to organize the data to be processed. The application writes the encrypted authentication information, block number, and encrypted authentication data sequentially into the corresponding data area according to a predetermined format. Taking a specific data packet in this embodiment as an example, the encrypted authentication information is configured as follows: the key (KEY) is 16 bytes long with the values ​​0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0D 0x0E 0x0F 0x10; the initialization vector (Ⅳ) also has the same 16-byte value; the type (TYPE) is set to 0x01 to indicate the encryption type; the mode (MODE) is set to 0x01 to indicate CBC mode; the encrypted data offset (OFFSET) is set to 0x10 to indicate that encryption starts 16 bytes off the starting address of the authentication data; and the padding field (PADDING) is 4 bytes long with the value 0x00. The block number (BN) is specified by the application as 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 (i.e., block number 1). The encrypted authentication data is the actual payload to be encrypted, which in this embodiment is 32 bytes of test data. The first 16 bytes are 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0D 0x0E 0x0F 0x10, and the last 16 bytes contain the same content. The application writes all the above data sequentially into the first data area. At this time, the corresponding flag area is still 0xFFFFFFFF, indicating that the data area is currently in an idle state and has not yet been notified to the security chip for processing.

[0027] The application sends the organized data to the security chip via the PCIe interface. The security chip's internal firmware pre-configures a DMA channel between the interface and the data area. When data arrives, the security chip's interrupt subroutine is triggered, directly initiating the DMA transfer operation to move the received data from the interface buffer to the designated data area memory space. The entire transfer process is completed independently by the DMA controller, without processor involvement in data copying, effectively reducing CPU load. After the DMA transfer is complete, the interrupt subroutine updates the corresponding flag area status from 0xFFFFFFFF to 0x55555555 (data placement status) to indicate that the data area contains valid data awaiting password calculation. Subsequently, the interrupt subroutine or main process immediately searches all flag areas to determine if a data area with a flag of 0xAAAAAAAA (calculation completed status) exists. If it exists, the content of that data area starting from the block number (i.e., the block number and encrypted authentication data) is returned to the application via the interface. After sending, the flag area corresponding to that data area is restored to 0xFFFFFFFF, and the data area content is refilled with 0xFF to clear the data. If no data block has been completed at present, a status indication that the chip is busy calculating is returned to the application, and the application can continue to query later.

[0028] During the execution of the main program of the security chip, the status of each flag area is continuously checked in a loop. When a flag area with a value of 0x55555555 (data placement status) is detected, the cryptographic calculation task for the corresponding data area is immediately initiated. Specifically, the cryptographic calculation task involves the main program reading the encryption authentication information in the data area, parsing out parameters such as the key, initialization vector, type, mode, encrypted data offset, and padding fields, and calling the corresponding hardware encryption engine or software algorithm library based on the parsed type and mode to perform the specified encryption and / or authentication operations on the encrypted authentication data. In this embodiment, the type is 0x01 and the mode is 0x01, meaning the encryption operation is performed in CBC mode using the AES-128 algorithm. The encryption engine starts reading the data to be encrypted from the starting address of the encrypted authentication data plus an offset (0x10), uses the parsed 16-byte key and initialization vector to complete the CBC mode encryption, and outputs the ciphertext data, writing it back to the encrypted authentication data portion in the original data area, overwriting the plaintext data. If authentication is enabled simultaneously (such as HMAC-SHA256), an authentication code is calculated for the encrypted data and appended to the end of the data or stored separately. Throughout the password calculation process, the security chip's encryption engine remains operational, while the DMA channel may be moving subsequent data blocks, achieving pipelined parallelism of computation and communication. Once the password calculation is complete, the main program updates the status of the corresponding flag area from 0x55555555 to 0xAAAAAAAA (computation complete status), indicating that the data area has completed password processing and awaits the application to retrieve the result.

[0029] The application continuously monitors the security chip's return channel via polling or interruption. When the main process detects 0xAAAAAAAA (calculation complete status) in the flag area, it reads the content starting from the block number in the corresponding data area, i.e., the block number and the encrypted / authenticated data (ciphertext) after encryption / authentication processing, and returns it to the application through the interface. After receiving the response, the application extracts the block number from the response and matches it with the block number specified when sending data. In this embodiment, the response block number is 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01, which matches the block number specified when sending. The match is successful, confirming that the transmission and processing of the data packet are complete. The application then returns the final processing result to the client application and restores the corresponding flag area and data area to an idle state, preparing to receive new data tasks. If the block number in the response does not match the block number specified when sending, the response is discarded or a retransmission mechanism is triggered to ensure reliable processing of the data packet.

[0030] In the above process, the four stages of data reception, DMA transfer, cryptographic calculation, and data return overlap in time. Specifically, while the first data block is undergoing cryptographic calculation, the DMA channel can simultaneously transfer the data of the second data block, and the application can simultaneously send the content of the third data block. The main process of the security chip monitors the status of all data blocks simultaneously in a loop. This multi-stage pipeline mechanism keeps the computing resources of the security chip constantly busy, fully utilizes the bandwidth of the communication interface, and improves the overall system throughput by about 3 to 4 times compared to traditional serial processing schemes. Taking the configuration of 8 data blocks in this embodiment as an example, when processing high-throughput network traffic, multiple data blocks are in different processing stages (data waiting, cryptographic calculation in progress, calculation completed and awaiting return), with each stage overlapping and running in parallel, achieving a processing efficiency close to the theoretical peak.

[0031] Optionally, the number of data areas and flag areas can be set according to actual application requirements, and is not limited to the eight in this embodiment. In low-latency scenarios, fewer blocks can be set to reduce resource consumption, while in high-throughput scenarios, the number of blocks can be increased to accommodate more pipeline depth. Each data block is independent of the others and does not interfere with each other.

[0032] Optionally, the status indicator value of the flag area can be flexibly selected according to the actual design, and is not limited to 0xFFFFFFFF, 0x55555555 and 0xAAAAAAAA in this embodiment. Any value that can clearly distinguish the three states and is not prone to misjudgment can be used.

[0033] Optionally, the communication interface of the security chip is not limited to a PCIe interface, but can also be a USB interface, SPI interface, Ethernet interface, UART interface or other custom parallel / serial interface. The acceleration solution provided by the present invention is independent of the communication interface type and has good versatility and portability.

[0034] Optionally, the cryptographic computation task is not limited to AES-CBC encryption mode, but can also be AES-GCM, AES-CCM, or other authenticated encryption modes, or other symmetric encryption algorithms such as SM4 and 3DES, as well as authentication algorithms such as HMAC and CMAC. The type and mode fields in the encryption authentication information are configured according to the actual algorithm used, and the cryptographic computation logic dynamically calls the corresponding hardware engine or software algorithm according to the configuration.

[0035] Optionally, the length and format of the block number can be flexibly set according to application requirements. It is not limited to the 8-byte fixed-length integer in this embodiment. It can also adopt a variable-length or combined format that includes a session identifier to meet the data packet matching requirements of different protocol stacks.

[0036] Through the description of this specific embodiment, those skilled in the art can clearly understand that the present invention, by separating the management of the data area and the flag area and combining DMA direct transfer and status polling mechanisms, realizes deep pipeline parallelism in each stage of IPSec accelerated processing, effectively solving the problems of high data transfer overhead, high processing latency, and insufficient resource utilization in traditional solutions. It can be widely applied in IPSec acceleration modules of network devices such as VPN gateways, security routers, and firewalls.

Claims

1. An IPSec acceleration scheme, characterized in that, include: Initialize the data area and the flag area. The flag area is used to identify the state of the data area, which includes three states: idle, data placed, and calculation completed. The application organizes the data, writing the encrypted authentication information, block number, and encrypted authentication data into the data area according to a predetermined format; The contents of the data area are moved to the designated memory space of the security chip via the DMA channel. After the move is completed, the corresponding flag area is set to the state of data placement. The main process of the security chip continuously detects the status of the flag area. When a data flag is detected, the corresponding password calculation task is started to perform encryption and / or authentication operations on the encrypted authentication data in the data area. After the operation is completed, the flag area status is set to "calculation completed". When the completion flag is detected, the corresponding block number and encrypted authentication data are returned to the application. The application confirms the sending and receiving of data packets by matching the block number.

2. The IPSec acceleration scheme according to claim 1, characterized in that, The data format of the data area consists of three parts: encryption authentication information, block number, and encryption authentication data; the encryption authentication information includes key, initialization vector, type, mode, and encryption data offset.

3. The IPSec acceleration scheme according to claim 1, characterized in that, The status indicators of the flag area are distinguished by specific values: 0xFF for idle state, 0x55 for data placement state, and 0xAA for calculation completion state.

4. The IPSec acceleration scheme according to claim 1, characterized in that, During the initialization process, all contents of the data area and the flag area are initialized to 0xFF, that is, all are set to an idle state.

5. The IPSec acceleration scheme according to claim 1, characterized in that, The process of moving the data area content to the designated memory space of the security chip via the DMA channel involves: establishing a DMA channel between the interface and the data area space; after the data is received, the interrupt subroutine inside the security chip initiates the DMA transfer, directly moving the data to the designated memory space; and after the transfer is completed, setting the flag area status to "data placed".

6. The IPSec acceleration scheme according to claim 1, characterized in that, The main process of the security chip continuously detects the status of the flag area, including: when a flag area is detected to be in the state of placing data, starting the password calculation task of the corresponding data area; when a flag area is detected to be in the state of completed calculation, returning the content of the corresponding data area starting from the block number, and restoring the corresponding flag area and data area to the idle state; when no valid flag is detected, returning "device busy" or continuing to poll.

7. The IPSec acceleration scheme according to claim 1, characterized in that, The application terminal completes the confirmation of data packet transmission and reception by matching the block number, including: after receiving the response information returned by the security chip, the application terminal matches the block number in the response information with the block number specified when sending. After a successful match, it confirms that the data packet transmission and reception is completed and returns the result to the client.

8. The IPSec acceleration scheme according to claim 1, characterized in that, The cryptographic computation task is executed during data transfer or communication gaps, realizing parallel pipelined processing of cryptographic computation and data communication.

9. The IPSec acceleration scheme according to claim 1, characterized in that, The size of the data area and the flag area is set according to the maximum length of data reception and password processing, and the number of data blocks to be received and sent is set according to actual needs.

10. The IPSec acceleration scheme according to claim 1, characterized in that, The proposed solution is not limited to a specific communication interface.

Images