Substation ipv6 white box network deterministic bearer communication method

Abstract

This application relates to the field of power communication technology, specifically disclosing a deterministic bearer communication method for IPv6 white-box networks in substations. It embeds end-to-end delay budget signaling into the IPv6 hop-by-hop option extension header, enabling packets to carry a deterministic delay countdown state. White-box switches along the route calculate dwell time hop-by-hop through the programmable data plane and deduct the budget, transforming static gated scheduling into dynamic scheduling based on the relative delay state at the packet level, eliminating the strong dependence on global high-precision clock synchronization. Each node's inherent intelligent agent integrates the remaining budget urgency and the micro-burst characteristics of the egress port for reasoning, driving the push into the first-out queue to achieve skip-level insertion and reshaping. Simultaneously, a deadline-coupled feasibility check is introduced, performing a reverse search for safe ranking before each insertion to ensure that existing packets do not time out due to cascading pressure, balancing scheduling aggressiveness with the deterministic boundary protection of the entire queue.

Description

Technical Field

[0001] This application relates to the field of power communication technology, and more specifically, to a deterministic bearer communication method for IPv6 white-box networks in substations. Background Technology

[0002] With the large-scale deployment of intelligent devices and sensing terminals in smart substations, production control services such as GOOSE trip messages and SV sampled value messages place stringent requirements on communication networks for end-to-end microsecond-level deterministic latency. Traditional IPv4 networks have limited address capacity and insufficient protocol scalability, making it difficult to support the ever-increasing demands for control interaction within the substation. This is driving the evolution of substation communication infrastructure towards IPv6 and a white-box open architecture. White-box switches, built on general-purpose commercial programmable chips, provide the hardware foundation for flexible deterministic bearer implementation. Therefore, constructing a deterministic bearer communication method for IPv6 white-box networks in substations has urgent engineering value.

[0003] Existing deterministic protection schemes primarily rely on a gating scheduling mechanism driven by a high-precision absolute clock synchronization across the entire network, requiring each node to maintain nanosecond-level time phase consistency. However, in a white-box heterogeneous hardware environment, the clock compensation accuracy of chips from different manufacturers varies considerably. Furthermore, strong electromagnetic interference in substations leads to the accumulation of phase differences across multiple hops in synchronization messages, easily causing misalignment between the gating window and message arrival time, resulting in instantaneous failure of deterministic protection. Moreover, even if the global clock dependency is eliminated and a dynamic queue scheduling strategy based on message-level delay budget is adopted, in concurrent fault scenarios, when multiple high-priority messages simultaneously compete for the front of the queue, each message independently positions itself based on its own weight, ignoring the coupling effect on the deadline of existing messages. This will cause deadline reversal, meaning that existing protection messages with more pressing remaining budgets will time out due to cascading pressure, leading to maloperation or failure of differential protection.

[0004] Therefore, an optimized deterministic bearer communication scheme for substation IPv6 white-box networks is desired. Summary of the Invention

[0005] To address the aforementioned technical problems, this application is proposed. Embodiments of this application provide a deterministic bearer communication method for a substation IPv6 white-box network, comprising: Step 1: Based on the delay tolerance constraints of substation control services, the end-to-end delay budget is encoded and embedded into the IPv6 hop-by-hop option extension header, and the substation source service packet payload is protocol encapsulated to generate IPv6 service packets carrying the delay budget. Step 2: Parse the IPv6 service packets carrying the latency budget and calculate the single-hop dwell time through the programmable data face of the white-box switch, extract the service payload and egress port identifier, and subtract the dynamic dwell time of the current hop from the latency budget in the hop-by-hop extension header to obtain the characteristic value of the remaining latency budget. Step 3: Based on the egress port identifier, perform micro-burst traffic status acquisition and structured tensor mapping on the queue of the target sending port to generate the micro-burst feature matrix of the egress queue. Step 4: Using a lightweight, intrinsically intelligent scheduling agent deployed on a white-box switch, multi-dimensional feature fusion and forward reasoning are performed on the remaining latency budget feature value and the micro-burst feature matrix of the egress queue to obtain the dynamic scheduling priority weight. Step 5: Based on the dynamic scheduling priority weight, the service payload is dynamically reshaped by skipping levels in the programmable push-in first-out queue, and the remaining delay budget feature value is written back to the IPv6 hop-by-hop extension header. The updated delay budget outbound IPv6 packet is sent through the physical port corresponding to the egress port identifier.

[0006] Compared with existing technologies, this application proposes a deterministic bearer communication method for IPv6 white-box networks in substations. By embedding end-to-end delay budget signaling into the IPv6 hop-by-hop option extension header, each service packet carries a quantifiable deterministic delay countdown state. Each white-box switch node along the route uses a programmable data plane to calculate the single-hop dwell time in real time and deduct the budget hop-by-hop. This transforms the traditional static gating scheduling, which relies on the absolute time phase of the entire network, into a dynamic adaptive scheduling based on the relative delay state of the packet, completely eliminating the strong dependence on global high-precision clock synchronization. Based on this, each node's intrinsic intelligent scheduling agent performs multi-dimensional fusion reasoning by integrating the urgency of the remaining delay budget of the packet with the micro-burst congestion characteristics of the egress port, generating dynamic scheduling priority weights to drive programmable push-in-first-out queues to achieve microsecond-level skip-level insertion and reshaping. Meanwhile, to address the issue of cascading and timeout of existing packets that may be caused by multiple packets competing for the front of the queue under concurrent flood conditions, a deadline coupling feasibility verification mechanism is introduced. Before each insertion, the remaining budget of existing packets is traversed and a safe ranking is searched to ensure that no insertion operation will cause the protected packets already in the queue to exceed their deadline constraints. This achieves strict protection of the deterministic latency boundary of the entire queue while maintaining the aggressiveness of dynamic scheduling. Attached Figure Description

[0007] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0008] Figure 1 This is a flowchart illustrating a deterministic bearer communication method for a substation IPv6 white-box network according to an embodiment of this application. Figure 2 This is a schematic diagram of data flow in a deterministic bearer communication method for a substation IPv6 white-box network according to an embodiment of this application. Figure 3 The flowchart illustrates a method for deterministic bearer communication in a substation IPv6 white-box network based on the delay tolerance constraints of substation control services, according to an embodiment of this application. It involves embedding the end-to-end delay budget amount encoding into the IPv6 hop-by-hop option extension header and performing protocol encapsulation on the substation source-end service packet payload to generate an IPv6 service packet carrying the delay budget. Figure 4 This is a flowchart illustrating a deterministic bearer communication method for a substation IPv6 white-box network according to an embodiment of this application. The method involves parsing IPv6 service packets carrying delay budgets and calculating single-hop dwell time through a programmable data surface of a white-box switch, extracting service payloads and egress port identifiers, and subtracting the dynamic dwell time of the current hop from the delay budget in the hop-by-hop extension header to obtain the characteristic value of the remaining delay budget. Figure 5 This is a flowchart illustrating a deterministic bearer communication method for a substation IPv6 white-box network according to an embodiment of this application. The method involves using a lightweight, endogenous intelligent scheduling agent deployed on a white-box switch to perform multi-dimensional feature fusion and forward reasoning on the remaining delay budget feature value and the micro-burst feature matrix of the egress queue to obtain dynamic scheduling priority weights. Figure 6 This is a flowchart illustrating a deterministic bearer communication method for a substation IPv6 white-box network based on dynamic scheduling priority weights. The method involves dynamically inserting and reshaping the service payload in a programmable push-in-first-out queue, writing back the remaining delay budget feature value to the IPv6 hop-by-hop extension header, and sending an outbound IPv6 message with updated delay budget through the physical port corresponding to the outbound port identifier. Figure 7 This document describes a method for deterministic bearer communication in a substation IPv6 white-box network, based on the maximum bearer depth constant of the queue and the safety margin of the queue offset. It involves calculating the absolute index position of a dynamic scheduling priority weight scalar and then reshaping the service load by inserting it into a programmable push-in-first-out queue according to this index to obtain the reshaped service load. Detailed Implementation

[0009] Hereinafter, exemplary embodiments according to this application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0010] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0011] While this application makes various references to certain modules of the systems according to embodiments of this application, any number of different modules can be used and run on user terminals and / or servers. The modules described are merely illustrative, and different aspects of the systems and methods may use different modules.

[0012] Flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0013] Existing deterministic bearer solutions in substations heavily rely on gating scheduling mechanisms driven by high-precision absolute clock synchronization across the entire network. In white-box heterogeneous hardware environments and under conditions of strong electromagnetic interference, clock drift can easily cause gating misalignment, leading to the failure of deterministic guarantees. Furthermore, even with dynamic queue scheduling strategies, in scenarios of concurrent fault surges, when multiple high-priority packets simultaneously compete for the front of the queue, each packet independently positions itself based on its own weight, ignoring the coupling relationship of existing packet deadlines. This can lead to the risk of cascading timeouts and deadline reversals. Therefore, this application proposes a deterministic bearer communication method for substation IPv6 white-box networks. This method shifts the scheduling benchmark for deterministic guarantees from the global absolute time phase to the relative delay state carried by the packet itself, and combines node-level intelligent decision-making and full queue deadline security verification to achieve end-to-end determinism. Specifically, firstly, at the source end, end-to-end delay budget signaling encoding is embedded into the IPv6 hop-by-hop option extension header, enabling each service packet to carry a quantifiable delay countdown state. Secondly, each white-box switch along the route calculates the single-hop dwell time in real time through the programmable data plane and deducts the budget hop-by-hop to obtain the true remaining delay urgency. Then, micro-burst traffic status perception and structured feature extraction are performed on the egress port queue. Subsequently, the endogenous intelligent scheduling agent integrates the remaining budget and micro-burst features to perform forward inference to generate dynamic scheduling weights, driving programmable push-in into the first-out queue to achieve leapfrog insertion reshaping. Finally, before the insertion is executed, a deadline coupling feasibility inversion verification is introduced to ensure that each insertion does not cause the existing packets to exceed their respective deadline constraints, maintaining the aggressiveness of scheduling while strictly adhering to the deterministic boundary of the entire queue.

[0014] Figure 1 This is a flowchart of a deterministic bearer communication method for a substation IPv6 white-box network according to an embodiment of this application. Figure 2 This is a schematic diagram of data flow in a deterministic bearer communication method for a substation IPv6 white-box network according to an embodiment of this application. Figure 1 and Figure 2As shown, a deterministic bearer communication method for a substation IPv6 white-box network according to an embodiment of this application includes: S1, based on the delay tolerance constraints of substation control services, embedding the end-to-end delay budget amount encoding into the IPv6 hop-by-hop option extension header, and encapsulating the substation source-end service packet payload to generate an IPv6 service packet carrying the delay budget; S2, parsing and calculating the single-hop dwell time of the IPv6 service packet carrying the delay budget through the programmable data surface of the white-box switch, extracting the service payload and egress port identifier, and subtracting the current hop dynamic dwell time from the delay budget in the hop-by-hop extension header to obtain the remaining delay budget characteristic value; S3, based on... The process involves: S4, collecting micro-burst traffic status data and performing structured tensor mapping on the queue of the target sending port to generate a micro-burst feature matrix for the egress queue; S5, using a lightweight, intrinsically intelligent scheduling agent deployed on a white-box switch to perform multi-dimensional feature fusion and forward inference on the remaining delay budget feature value and the micro-burst feature matrix of the egress queue to obtain dynamic scheduling priority weights; S6, based on the dynamic scheduling priority weights, dynamically reshaping the service payload in the programmable push-in-first-out queue by inserting it into a higher priority queue, writing the remaining delay budget feature value back to the IPv6 hop-by-hop extension header, and sending an outbound IPv6 packet with the updated delay budget through the physical port corresponding to the egress port identifier.

[0015] Specifically, in step S1, based on the delay tolerance constraints of substation control services, the end-to-end delay budget is encoded and embedded in the IPv6 hop-by-hop option extension header. The substation source-end service message payload is then protocol-encapsulated to generate an IPv6 service message carrying the delay budget. It should be noted that, given that substation differential protection and other control services require end-to-end delay control within microseconds to milliseconds, existing deterministic bearer schemes rely on the network-wide IEEE 1588v2 high-precision absolute clock synchronization to drive gating scheduling. Under white-box heterogeneous hardware clock drift and strong electromagnetic interference, the accumulated phase difference of multiple hops in the synchronization messages easily leads to gating window misalignment, lacking a deterministic state-carrying mechanism decoupled from absolute time phase. Therefore, the technical solution of this application first, based on the delay tolerance constraints of substation control services, embeds the end-to-end delay budget encoding into the IPv6 hop-by-hop option extension header and then protocol-encapsulates the substation source-end service message payload to generate an IPv6 service message carrying the delay budget. Through the above processing, each GOOSE trip message or SV sample value message can carry quantifiable delay countdown status signaling before entering the white-box network, providing a dynamic scheduling criterion basis for each hop node along the way that is independent of the global clock.

[0016] Figure 3This document describes a flowchart illustrating a deterministic bearer communication method for substation IPv6 white-box networks, based on delay tolerance constraints for substation control services. The method embeds end-to-end delay budget encoding into the IPv6 hop-by-hop option extension header and performs protocol encapsulation on the substation source-end service packet payload to generate an IPv6 service packet carrying the delay budget. Figure 3 As shown, step S1 includes: S11, based on the protocol stack encapsulation overhead coefficient and the fixed equipment processing compensation amount, statically deducting the preset end-to-end delay scalar to obtain the service delay budget feature value; S12, based on the IPv6 hop-by-hop option protocol specification, encoding the service delay budget feature value into network byte order and writing it into a specific type length value field to generate a delay budget extension header structure; S13, through protocol layer topology splicing rules, performing multi-layer encapsulation, assembly, verification, and recalculation of the destination IPv6 address, the delay budget extension header structure, and the substation source-end service packet payload to generate an IPv6 service packet carrying the delay budget.

[0017] In step S11, based on the protocol stack encapsulation overhead coefficient and the fixed equipment processing compensation amount, a static overhead deduction is performed on the preset end-to-end delay scalar to obtain the service delay budget characteristic value. It should be noted that since the substation source-end equipment inevitably consumes a certain amount of processing time when performing IPv6 protocol stack encapsulation, if the preset end-to-end delay quota is written in full into the extension header, subsequent hop nodes will make scheduling decisions based on an artificially inflated budget value, resulting in the differential protection delay constraint not being met when the actual message arrives at the terminal. Therefore, the technical solution of this application first performs a static overhead deduction on the preset end-to-end delay scalar based on the protocol stack encapsulation overhead coefficient and the fixed equipment processing compensation amount to obtain the service delay budget characteristic value. Through the above processing, it is effectively ensured that the delay budget value written into the extension header reflects the net effective quota that can actually be consumed by each hop queue after the packet enters the white-box network.

[0018] More specifically, in a specific example of this application, before the substation relay protection device sends a GOOSE trip message, it first reads the preset end-to-end delay scalar corresponding to the differential protection service. This scalar is pre-configured during the substation communication engineering planning phase based on the bus differential protection operation time limit requirements. Then, it retrieves the locally stored protocol stack encapsulation overhead coefficient and fixed equipment processing compensation amount. The protocol stack encapsulation overhead coefficient represents the proportion of dynamic fluctuation time generated by the source device's operating system kernel during IPv6 header assembly, memory copying, and checksum calculation. The fixed equipment processing compensation amount represents the noise floor dwell time constant of the network card driver and hardware circuitry on a single data packet. The service delay budget characteristic value is calculated by subtracting the product of the protocol stack encapsulation overhead coefficient and the fixed equipment processing compensation amount from the preset end-to-end delay scalar. The calculation expression is as follows:

[0019] in, This is a characteristic value for service latency budget, representing the net effective latency allowance that can be consumed by queuing and forwarding at each hop node after a packet actually enters the white-box network link. This is a preset end-to-end delay allowance scalar, representing the maximum absolute transmission delay tolerance limit set by the substation for a specific control service. The protocol stack encapsulation overhead coefficient represents the dynamic fluctuation coefficient when the source device kernel protocol stack performs encapsulation operations. For fixed equipment processing compensation, it represents the noise floor dwell time constant of the source network card hardware circuit on a unit data packet.

[0020] In step S12, based on the IPv6 hop-by-hop options protocol specification, the service delay budget characteristic value is encoded in network byte order and written into a specific type length value field to generate a delay budget extension header structure. It should be noted that since the service delay budget characteristic value exists as a pure numerical value in local memory, it cannot be directly recognized and extracted by the programmable data plane parsing engine of the white-box switches along the route. It must be encapsulated into a network-transmittable structured field according to a standardized protocol format. Based on this, the technical solution of this application further encodes the service delay budget characteristic value in network byte order and writes it into a specific type length value field to generate a delay budget extension header structure based on the IPv6 hop-by-hop options protocol specification. Through the above processing, the delay budget signaling is effectively embedded in the packet header in a protocol-compatible manner, ensuring that each hop node along the route can directly read the budget value through the standard parsing pipeline.

[0021] More specifically, in a concrete example of this application, based on the IPv6 hop-by-hop options extension header format defined in RFC 8200, a hop-by-hop options header space is allocated in memory. This space contains a next header field and an extension header length field. A type length value field is allocated within this header space, where the type field is set to a custom latency budget identifier encoding, and the length field is filled with the number of bytes occupied by the service latency budget characteristic value. Subsequently, a big-endian conversion from host byte order to network byte order is performed on the service latency budget characteristic value, and the converted binary data is written into the value field of the type length value field. After writing, the next header field is set to point to the protocol type number of the subsequent payload, and the extension header length field is updated according to the actual total length of the options filled. This forms a latency budget extension header structure conforming to the IPv6 protocol stack specification, for use in subsequent multi-layer encapsulation and assembly stages.

[0022] In step S13, the destination IPv6 address, delay budget extension header structure, and substation source service packet payload are multi-layered encapsulation, assembly, verification, and recalculation based on protocol layer topology splicing rules to generate an IPv6 service packet carrying the delay budget. It should be noted that since the destination IPv6 address, delay budget extension header structure, and substation source service packet payload are located at different protocol layers and exist in memory as discrete data blocks, if splicing and verification are not performed according to a strict protocol topology order, white-box switches along the route will not be able to correctly locate the extension header boundary and extract the delay budget field. Based on this, the technical solution of this application further uses protocol layer topology splicing rules to multi-layered encapsulation, assembly, verification, and recalculation based on the destination IPv6 address, delay budget extension header structure, and substation source service packet payload to generate an IPv6 service packet carrying the delay budget. Through the above processing, a complete IPv6 data packet with a complete protocol format and self-carrying delay budget state is effectively formed and can be correctly parsed and forwarded by all nodes in the entire link.

[0023] More specifically, in a specific example of this application, the substation source-side service message payload includes a GOOSE message payload and an SV sampled value message payload. The GOOSE message payload carries emergency control information such as relay protection trip commands, while the SV sampled value message payload carries instantaneous current and voltage sampling data required by the bus differential protection. First, an IPv6 basic header is constructed. The local IPv6 address of the source-side relay protection device is filled into the source address field, and the destination IPv6 address is filled into the destination address field. The protocol type number of the hop-by-hop options extension header is written into the next header field to indicate that a hop-by-hop options header exists immediately following the basic header. The payload length field is filled in according to the delay budget extension header structure and the total byte length of the substation source-side service message payload. Then, following the protocol layer topology order from the outside in, the IPv6 basic header, the delay budget extension header structure, and the substation source-side service message payload are sequentially concatenated in a contiguous memory area, with the delay budget extension header structure immediately following the basic header and the substation source-side service message payload located at the innermost layer. After the concatenation is completed, the checksum field of the upper-layer transport protocol is recalculated based on the IPv6 pseudo-header, and the updated checksum value is written back to the corresponding position, thereby generating an IPv6 service packet carrying a delay budget and pushing it into the underlying network card's transmission queue.

[0024] Specifically, in step S2, the programmable data interface of the white-box switch parses the IPv6 service packets carrying the latency budget and calculates the single-hop dwell time, extracts the service payload and egress port identifier, and deducts the dynamic dwell time of the current hop from the latency budget in the hop-by-hop extension header to obtain the remaining latency budget characteristic value. It should be noted that since the budget value in the extension header of the IPv6 service packets carrying the latency budget arrives at the white-box switch, it is still a static value written upstream and does not yet reflect the actual dwell time consumed by the pipeline processing and switching matrix traversal within the current hop node. If it is not calculated and deducted in real time at each hop, the intrinsic intelligent scheduling agent of subsequent nodes will make decisions based on distorted budget values, and will be unable to accurately determine the true latency urgency of the packet. Based on this, the technical solution of this application further parses the IPv6 service packets carrying the latency budget and calculates the single-hop dwell time through the programmable data interface of the white-box switch, extracts the service payload and egress port identifier, and deducts the dynamic dwell time of the current hop from the latency budget in the hop-by-hop extension header to obtain the remaining latency budget characteristic value. Through the above processing, the budget value in the extended header of the message after each hop of the white-box node can accurately reflect the current real remaining available latency, providing a reliable real-time status input for subsequent micro-burst perception and intelligent scheduling reasoning.

[0025] Figure 4 This document describes a method for deterministic bearer communication in a substation IPv6 white-box network, based on an embodiment of this application. It involves parsing IPv6 service packets carrying a delay budget and calculating single-hop dwell time via a programmable data plane on a white-box switch. The method extracts the service payload and egress port identifier, and subtracts the current hop's dynamic dwell time from the delay budget in the hop-by-hop extension header to obtain the characteristic value of the remaining delay budget. Figure 4 As shown, step S2 includes: S21, performing inbound stamping at the moment the first bit of the packet arrives via a hardware clock synchronization unit, and performing programmable decapsulation and parsing of the IPv6 service packet carrying the delay budget to extract the service payload, target IPv6 address, current hop delay budget, and packet inbound timestamp; S22, performing hardware route lookup table addressing on the target IPv6 address to generate an egress port identifier; S23, capturing the packet egress timestamp via the outbound side hardware clock and combining it with hardware processing compensation constants to dynamically deduct the dwell time from the current hop delay budget to obtain the remaining delay budget characteristic value.

[0026] In step S21, an inbound stamp is performed at the moment the first bit of the packet arrives via a hardware clock synchronization unit. The IPv6 service packet carrying the delay budget is then programmably decapsulated and parsed to extract the service payload, target IPv6 address, current hop delay budget, and inbound timestamp. It should be noted that since the packet undergoes multiple pipeline processes within the white-box switch, including parsing, table lookup, and queuing, all of which consume time, and the accurate calculation of dwell time depends on capturing the time base at the moment the packet arrives, delaying the stamping process to the software layer would introduce uncontrollable interrupt response jitter. Therefore, the technical solution of this application further utilizes a hardware clock synchronization unit to perform inbound stamping at the moment the first bit of the packet arrives, and programmably decapsulates and parses the IPv6 service packet carrying the delay budget to extract the service payload, target IPv6 address, current hop delay budget, and inbound timestamp. Through the above processing, accurate time base and various protocol fields within the packet can be simultaneously obtained at the start of the data plane pipeline, providing complete input data for subsequent dwell time calculation and routing.

[0027] More specifically, in a concrete example of this application, when an IPv6 service packet carrying a delay budget arrives at the inbound physical port of a white-box switch via a fiber optic link, the hardware clock synchronization unit on the port side triggers a register latch operation the instant the first bit signal of the packet changes, capturing the current hardware clock count value as the packet's inbound timestamp, with an accuracy of nanoseconds. The packet then enters the parsing pipeline of the programmable data plane, where, according to the pre-loaded IPv6 protocol parser, each protocol layer field is identified and stripped layer by layer. First, the target IPv6 address and the next header type identifier are extracted from the IPv6 basic header. Based on the next header type identifier, the hop-by-hop options extension header area that follows is located, and the current hop delay budget encoded in the type length value field is read. After the extension header is parsed, the inner-layer service payload, i.e., the GOOSE packet payload or the SV sampled value packet payload, is located and separated based on the payload length field. At this point, the four data items—service payload, target IPv6 address, current hop latency budget, and packet inbound timestamp—have all been extracted into the pipeline metadata register for use in subsequent route lookup and dwell time deduction processes.

[0028] In step S22, a hardware route lookup is performed on the target IPv6 address to generate an egress port identifier. It should be noted that since the service payload needs to be forwarded to a specific peer protection device within the substation, and the packet only obtains the logical identifier of the target IPv6 address after parsing in the programmable data plane, it is not yet determined which physical port of the white-box switch the packet should be sent from. Subsequent micro-burst state acquisition and queue insertion operations all depend on a clearly defined egress port. Based on this, the technical solution of this application further performs a hardware route lookup on the target IPv6 address to generate an egress port identifier. Through the above processing, the logical layer target address can be mapped to a definite outbound path in the physical layer, providing accurate hardware location basis for subsequent queue status awareness and dynamic scheduling for this port.

[0029] More specifically, in a concrete example of this application, the programmable data plane uses the target IPv6 address extracted from the parsing pipeline as a lookup key to input into the hardware forwarding table built into the white-box switch. This forwarding table is implemented based on TCAM and is pre-deployed by the control plane according to the substation's network topology and routing policies. Each entry contains the IPv6 address prefix and its corresponding egress port number. The hardware lookup engine performs longest prefix matching on the target IPv6 address, completing the addressing within a single clock cycle and returning the matched entry. The corresponding physical egress port number is read from this entry, encapsulated as an egress port identifier, and written to the packet metadata register. This identifier, along with the service payload, current hop delay budget, and packet inbound timestamp, is then transferred to the subsequent dwell time deduction stage.

[0030] In step S23, the outbound timestamp of the message is captured by the outbound hardware clock and combined with the hardware processing compensation constant to dynamically deduct the dwell time from the current hop delay budget to obtain the characteristic value of the remaining delay budget. It should be noted that the dwell time consumed by the message during the multi-stage pipeline processing (parsing, table lookup, and switching matrix traversal) within the white-box switch varies dynamically with the load status. Furthermore, the chip has an inherent nanosecond-level dead zone error when reading the timestamp register. Without real-time calculation and compensation calibration, the budget value in the extended header will not reflect the true remaining allowance when the message leaves the current hop node. Therefore, the technical solution of this application further captures the outbound timestamp of the message by the outbound hardware clock and combines it with the hardware processing compensation constant to dynamically deduct the dwell time from the current hop delay budget to obtain the characteristic value of the remaining delay budget. Through the above processing, it is effectively ensured that the budget value accurately reflects the current remaining available delay allowance of the message at each hop departure time, providing a reliable quantitative basis for the subsequent urgency judgment of the intrinsic intelligent scheduling agent.

[0031] More specifically, in a specific example of this application, when the packet metadata is transmitted with the switching matrix to the flow management unit on the egress port side and is ready to enter the transmission queue, the outbound hardware clock triggers a register latch operation at that moment, capturing the current clock count value as the packet outbound timestamp. Subsequently, a hardware processing compensation constant is read from the locally fixed configuration register. This constant, obtained from the factory calibration or online calibration of the white-box switch, is used to correct the inherent micro-delay deviation between the internal clock read and operation pipeline of the chip. After obtaining the above parameters, a dynamic dwell time deduction calculation is performed, subtracting the difference between the packet outbound timestamp and the packet inbound timestamp from the current hop delay budget, and then subtracting the hardware processing compensation constant. The calculation expression is as follows:

[0032] in, The remaining latency budget characteristic value represents the actual remaining effective latency allowance that can be consumed by subsequent network paths when the packet leaves the current white-box node. The current hop delay budget represents the initial budget value carried in the extension header when the packet enters this node, which has not yet been consumed by this hop. This is the message outbound timestamp, representing the absolute time point captured by the hardware when the message arrives at the outbound traffic management unit. This is the inbound timestamp of the message, representing the absolute time point captured by the hardware when the first bit of the message arrived at the inbound physical port. This is a hardware processing compensation constant, representing the inherent nanosecond-level dead-time calibration amount during timestamp register reading and addition / subtraction operations. After calculation, the resulting remaining delay budget characteristic value is written to the message metadata register and output along with the service payload and egress port identifier to the subsequent micro-burst state sensing stage.

[0033] Specifically, in step S3, based on the egress port identifier, the queuing queue of the target sending port is subjected to micro-burst traffic state acquisition and structured tensor mapping to generate an egress queue micro-burst feature matrix. It should be noted that due to the massive influx of GOOSE trip messages and SV sampled value messages into the white-box switch during a substation fault, the queuing state of the egress port fluctuates drastically within a microsecond timescale. The remaining delay budget feature value alone cannot fully reflect the actual queuing competition situation that the messages will face. The intrinsic intelligent scheduling agent needs to simultaneously perceive the current port's congestion intensity and deterioration trend to make reasonable scheduling decisions. Based on this, the technical solution of this application further performs micro-burst traffic state acquisition and structured tensor mapping on the queuing queue of the target sending port based on the egress port identifier to generate an egress queue micro-burst feature matrix. Through the above processing, the transient congestion state hidden in the hardware queue memory is effectively transformed into a structured mathematical representation that can be directly read by the AI ​​inference engine.

[0034] More specifically, in a concrete example of this application, after locking the corresponding target physical transmission port on the hardware resource plane based on the egress port identifier, a status scan is performed on the queuing queue storage area under that port at a frequency of microseconds. In each acquisition cycle, the total number of actual backlogged packets or data blocks in the queue buffer is read and recorded as the absolute queue backlog depth index. Simultaneously, the backlog depth of this cycle is differentially calculated with the historical value of the previous cycle to obtain the rate of change of queue growth or decline per unit microsecond, which is recorded as the queuing rate increment parameter. The absolute queue backlog depth index reflects the current static congestion level of the port, while the queuing rate increment parameter reflects the dynamic trend of congestion worsening or mitigation; together, they constitute the basic physical quantities describing micro-burst states.

[0035] After obtaining the two original indicators mentioned above, a pre-calibrated baseline state mapping row vector is retrieved from the local configuration storage of the white-box switch. This vector, calibrated during the offline training phase based on typical substation load conditions, is used to project indicators of different physical dimensions onto a unified feature space. The absolute queue stacking depth indicator and the queueing rate increment parameter are arranged vertically in the spatial domain to form a two-dimensional column vector. Subsequently, a matrix outer product operation is performed between this two-dimensional column vector and the baseline state mapping row vector. The calculation expression is as follows:

[0036] in, The real-time micro-burst feature matrix for the exit queue represents a two-dimensional structured matrix that, after tensor mapping, can be directly read by downstream AI inference models, describing the overall picture of micro-burst congestion at the port. This is an indicator of the absolute backlog depth of the queue, representing the total number of packets actually backed up in the port buffer at the sampling time. The queuing rate increment parameter represents the rate of change of queue growth in the current sampling period relative to the previous period. Let be the baseline state mapping row vector, and let represent the projection weight vector used to expand the low-dimensional physical index to a unified feature space. Through this outer product operation, the original two-dimensional scalar index is upgraded to a structured feature matrix that can fully characterize the port congestion intensity and deterioration direction.

[0037] After the feature matrix is ​​successfully generated, the hardware readiness status of the physical port pointed to by the egress port identifier is further verified to confirm that the physical link of the port is active and the sending queue manager is not in an abnormal locked state. After the verification is passed, a readiness flag is attached to the port identifier and it is output as the verified message egress port identifier. This prevents the subsequent scheduling calculation results from failing to be implemented due to port failure or link interruption, and ensures that the port information used by the downstream intelligent scheduling and physical sending links are reliable identifiers that have been verified.

[0038] Specifically, in step S4, a lightweight, intrinsically intelligent scheduling agent deployed on a white-box switch performs multi-dimensional feature fusion and forward inference on the remaining delay budget feature value and the egress queue micro-burst feature matrix to obtain dynamic scheduling priority weights. It should be noted that, given that the remaining delay budget feature value reflects the delay urgency of a single packet, while the egress queue micro-burst feature matrix reflects the current environmental congestion status of the port, and these two belong to different dimensions and have different scales, traditional static priority or fixed weight mapping cannot dynamically generate the optimal queuing decision based on their real-time coupling relationship. Intelligent inference is needed to jointly perceive and non-linearly decide on packet-level urgency and environmental-level congestion. Based on this, the technical solution of this application further utilizes a lightweight, intrinsically intelligent scheduling agent deployed on a white-box switch to perform multi-dimensional feature fusion and forward inference on the remaining delay budget feature value and the egress queue micro-burst feature matrix to obtain dynamic scheduling priority weights. Through the above processing, personalized scheduling weights adapted to the current network transient conditions can be generated in real time for each inbound packet, driving subsequent programmable push-in into the first-out queue to achieve precise skip-level insertion and reshaping.

[0039] Figure 5 This document presents a flowchart illustrating a deterministic bearer communication method for a substation IPv6 white-box network, based on an embodiment of this application. The method utilizes a lightweight, intrinsically intelligent scheduling agent deployed on a white-box switch to perform multi-dimensional feature fusion and forward inference on the remaining delay budget characteristic values ​​and the micro-burst characteristic matrix of the egress queue to obtain dynamic scheduling priority weights. Figure 5 As shown, step S4 includes: S41, based on the global latency lower limit threshold and the global latency upper limit threshold, performing latency dimension extremum normalization on the remaining latency budget feature values ​​to obtain normalized latency budget feature values; S42, performing multi-dimensional state fusion and splicing on the real-time micro-burst feature matrix of the exit queue and the normalized latency budget feature values ​​to obtain a comprehensive multi-dimensional state vector; S43, based on the pre-trained model weight matrix and the bias term constant vector, performing AI forward inference and weight generation on the comprehensive multi-dimensional state vector to obtain a dynamic scheduling priority weight scalar.

[0040] In step S41, based on the global latency lower limit threshold and the global latency upper limit threshold, the remaining latency budget feature values ​​are normalized by latency dimension extrema to obtain normalized latency budget feature values. It should be noted that since the remaining latency budget feature values ​​are absolute time quantities at the nanosecond level, while the elements in the exit queue micro-burst feature matrix are dimensionless congestion feature values, there is an order of magnitude difference between the two in terms of numerical scale. Directly concatenating them into the neural network would lead to an unbalanced gradient distribution, causing the inference result to favor the larger latency dimension while ignoring the contribution of the congestion dimension. Therefore, the technical solution of this application further normalizes the remaining latency budget feature values ​​by latency dimension extrema based on the global latency lower limit threshold and the global latency upper limit threshold to obtain normalized latency budget feature values. Through the above processing, the latency features are effectively constrained to the same standard interval as the congestion features, eliminating the interference of dimensional differences on the accuracy of subsequent multi-dimensional fusion inference.

[0041] More specifically, in a specific example of this application, the global latency lower limit threshold and the global latency upper limit threshold are read from the local configuration register of the built-in intelligent scheduling agent of the white-box switch. The global latency lower limit threshold is obtained by calibrating the sum of the light propagation time of the shortest physical path in the substation network topology and the minimum processing time of the chip. The global latency upper limit threshold is obtained by calibrating the maximum safe queuing delay boundary of the entire network. Subsequently, a minimum-maximum normalization calculation is performed on the remaining latency budget characteristic value. Subtracting the global latency lower limit threshold from it and dividing by the range between the global latency upper limit threshold and the global latency lower limit threshold, the calculation expression is as follows:

[0042] in, The normalized delay budget eigenvalue represents a delay urgency parameter mapped to a continuous interval of 0 to 1. The closer the value is to 0, the more urgent the remaining available queuing time for the message. The remaining delay budget characteristic value represents the actual remaining effective delay allowance of the message after deducting the current hop dwell time. This is the global latency lower limit threshold, representing the minimum budget baseline value that a packet can hold under extreme network conditions. This represents the global latency upper limit threshold, indicating the maximum safe latency boundary that packets are allowed to accumulate in the network. After calculation, the obtained normalized latency budget feature value is output to the subsequent multi-dimensional state fusion and splicing stage.

[0043] In step S42, the real-time micro-burst feature matrix of the exit queue and the normalized delay budget feature value are multi-dimensionally fused and concatenated to obtain a comprehensive multi-dimensional state vector. It should be noted that since the normalized delay budget feature value is in scalar form while the real-time micro-burst feature matrix of the exit queue is in two-dimensional matrix form, they are inconsistent in data structure dimension and cannot be directly used as a unified input tensor for the neural network. They need to be integrated into a one-dimensional vector with a consistent shape to adapt to the input perception format of the fully connected layer. Based on this, the technical solution of this application further performs multi-dimensionally fused and concatenated multi-dimensional state fusion on the real-time micro-burst feature matrix of the exit queue and the normalized delay budget feature value to obtain a comprehensive multi-dimensional state vector. Through the above processing, a unified input body that simultaneously carries environmental congestion features and message urgency features is effectively formed, allowing subsequent forward inference stages to read and generate scheduling decisions in one go.

[0044] More specifically, in a concrete example of this application, the real-time micro-burst feature matrix of the egress queue is first flattened row by row, arranging the elements in its two-dimensional structure into a continuous one-dimensional sequence according to row priority. This sequence retains all information about the port congestion intensity and deterioration trend. Then, the normalized delay budget feature value is appended as a single-element scalar to the end of the aforementioned one-dimensional sequence, so that the last component of the sequence represents the delay urgency of the current packet. The resulting one-dimensional ordered array is the comprehensive multi-dimensional state vector. Its first component encodes the overall micro-burst congestion situation of the egress port, and its last component encodes the urgency of the current packet relative to the global delay boundary. These two types of information are seamlessly integrated within the same vector space, allowing for direct consumption by the subsequent forward inference computation of the endogenous intelligent scheduling agent.

[0045] In step S43, based on the pre-trained model weight matrix and bias term constant vector, AI forward inference and weight generation are performed on the comprehensive multidimensional state vector to obtain a dynamic scheduling priority weight scalar. It should be noted that, due to the complex nonlinear coupling relationship between the congestion features and urgency features encoded in the comprehensive multidimensional state vector, traditional linear weighting or rule engines cannot accurately capture the optimal scheduling mapping under different combinations of operating conditions. Therefore, a pre-trained neural network is needed to fit and output the decision regarding this nonlinear relationship. Based on this, the technical solution of this application further performs AI forward inference and weight generation on the comprehensive multidimensional state vector based on the pre-trained model weight matrix and bias term constant vector to obtain a dynamic scheduling priority weight scalar. Through the above processing, multidimensional environmental perception and message urgency information are effectively mapped into a single scheduling weight value through nonlinear decision-making, directly driving the subsequent programmable insertion position calculation for the first-out queue.

[0046] More specifically, in a concrete example of this application, the endogenous intelligent scheduling agent loads frozen model parameters, pre-trained through offline reinforcement learning, from local flash memory. These parameters include a pre-trained model weight matrix and a bias term constant vector. The pre-trained model weight matrix is ​​obtained through flow adversarial game training under simulated typical fault conditions in a substation, and the bias term constant vector is used to maintain the basic activation state of neurons with zero input. A vector-matrix multiplication operation is performed between the integrated multidimensional state vector and the pre-trained model weight matrix. The multiplication result is then added element-wise to the bias term constant vector and fed into a nonlinear activation function for bounded mapping. The calculation expression is as follows:

[0047] in, This is a dynamic scheduling priority weight scalar, representing a continuous value between 0 and 1. A larger value indicates that the current message requires a higher queuing priority privilege. It is a non-linear activation function that maps the result of a linear combination to a bounded output space. To synthesize the multi-dimensional state vector, a unified input volume is formed that integrates environmental congestion features and message urgency features. This is the pre-trained model weight matrix, representing the neuron connection strength parameters accumulated during the offline training phase. This is a constant vector of bias terms, representing the inherent bias parameters that maintain the stability of network layer activation. After forward inference, the resulting dynamic scheduling priority weight scalar is output to the subsequent queue insertion position calculation and skip-level reshaping stages.

[0048] Specifically, in a preferred embodiment of this application, the lightweight endogenous intelligent scheduling agent is implemented using a single hidden layer fully connected feedforward neural network structure. The input layer dimension is equal to the total number of elements in the flattened real-time micro-burst feature matrix of the exit queue plus 1 (the added normalized delay budget feature value). For example, when the length of the baseline state mapping row vector is 4, the 2×4 outer product matrix flattened is 8-dimensional. Adding the 1-dimensional delay feature, the input layer dimension is 9. The hidden layer contains 16 neurons and the activation function is the ReLU function. The output layer is a single neuron and the activation function is the Sigmoid function, mapping the output to the (0,1) interval, i.e., the dynamic scheduling priority weight scalar. The training of this model is performed in an offline simulation environment using a proximal policy optimization reinforcement learning algorithm. The simulation environment simulates the white-box network topology within a substation. The state space is defined as a concatenated vector of the normalized delay budget feature value and the micro-burst feature matrix. The action space is defined as continuous scheduling weight values. The reward function is designed as follows: A positive reward is given when a message is successfully delivered within the end-to-end latency constraint, and the reward value is positively correlated with the remaining budget. A significant negative penalty is given when a message times out. An additional negative penalty is given when queue jumping causes existing messages to time out. The training process uses traffic models generated from typical substation operating conditions, including normal load, N-1 fault, and bus short circuit concurrent flood peak scenarios, to generate simulation data. After training until the policy converges, the model parameters are frozen, exported as a weight matrix and bias vector, and written to the local flash memory of the white-box switch. The model inference process involves only one matrix-vector multiplication, one vector addition, and two element-wise activation function calculations. The total computation is in the hundreds of floating-point operations. A single forward inference can be completed within 100ns by the lightweight inference acceleration unit embedded in the white-box switch, ensuring that the inference latency is much less than the microsecond-level message processing budget. This allows those skilled in the art to completely reproduce the construction and deployment process of the endogenous intelligent scheduling agent based on the above network structure, training method, and inference constraints.

[0049] Specifically, in step S5, based on the dynamic scheduling priority weight, the service payload is dynamically reshaped by skipping levels in the programmable push-in-first-out queue, and the remaining latency budget characteristic value is written back to the IPv6 hop-by-hop extension header. The updated latency budget outbound IPv6 packet is then sent through the physical port corresponding to the egress port identifier. It should be noted that, given that the intrinsic intelligent scheduling agent has generated a dynamic scheduling priority weight for the current packet reflecting its latency urgency and environmental congestion, but this weight remains a logical numerical state and has not yet been translated into actual physical queue ranking behavior, and the latency budget in the packet extension header has not been updated to the remaining value after deduction for this hop, direct sending would prevent downstream nodes from obtaining accurate budget status for subsequent scheduling decisions. Therefore, the technical solution of this application further reshapes the service payload by dynamically skipping levels in the programmable push-in-first-out queue based on the dynamic scheduling priority weight, writes back the remaining latency budget characteristic value to the IPv6 hop-by-hop extension header, and sends the updated latency budget outbound IPv6 packet through the physical port corresponding to the egress port identifier. Through the above processing, the intelligent reasoning results can be implemented into microsecond-level physical queuing reshaping actions. At the same time, it ensures that when a message leaves the current hop, the budget value carried in its extended header is the latest real remaining quota, so that the next hop white-box node can continue to perform the same perception and scheduling closed loop based on the updated budget value, realizing hop-by-hop deterministic bearing across the entire link.

[0050] Figure 6 This document describes a method for deterministic bearer communication in a substation IPv6 white-box network, based on an embodiment of this application. It involves dynamically reshaping the service payload within a programmable push-in-first-out queue, writing back the remaining delay budget characteristic value to the IPv6 hop-by-hop extension header, and sending an updated delay budget outbound IPv6 packet via the physical port corresponding to the outbound port identifier. Figure 6 As shown, step S5 includes: S51, based on the maximum capacity depth constant of the queue and the safety margin of the queue offset, calculating the absolute index position of the dynamic scheduling priority weight scalar, and reshaping the service payload by inserting it into the programmable push-in first-out queue according to the index to obtain the reshaped service payload; S52, through the hardware packet editing module, overwriting the hop-by-hop extension header type length value field of the remaining effective delay budget characteristic value, and performing binary concatenation assembly and verification with the reshaped service payload to generate an outbound IPv6 packet with an updated extension header; S53, based on the verified packet outbound port identifier driving the physical transceiver channel of the underlying network interface card, performing parallel-to-serial conversion and physical signal modulation ejection on the outbound IPv6 packet with the updated extension header.

[0051] In step S51, based on the maximum queue carrying depth constant and the queuing offset safety margin, the absolute index position of the dynamic scheduling priority weight scalar is calculated, and the service payload is reshaped by skipping levels in the programmable push-in-first-out queue according to this index to obtain the reshaped service payload. It should be noted that, given that the dynamic scheduling priority weight scalar is a continuous floating-point number between 0 and 1, and the physical storage structure of the programmable push-in-first-out queue uses discrete integer slots for indexing, it is necessary to map the continuous weight values ​​to absolute integer positions in the queue to drive the hardware linked list pointer to complete the actual physical queue insertion operation, allowing high-urgency GOOSE trip messages or SV sampled value messages to bypass low-priority best-effort traffic and obtain priority transmission opportunities. Based on this, the technical solution of this application further calculates the absolute index position of the dynamic scheduling priority weight scalar based on the maximum queue carrying depth constant and the queuing offset safety margin, and reshapes the service payload by skipping levels in the programmable push-in-first-out queue according to this index to obtain the reshaped service payload. Through the above processing, the reasoning results of the endogenous intelligent agent can be accurately converted into microsecond-level skip-queue actions in the physical queue, so that protection-type messages with tight latency can obtain priority outbound ranking matching their urgency during the queuing stage.

[0052] Figure 7 This document describes a flowchart illustrating a deterministic bearer communication method for a substation IPv6 white-box network, based on an embodiment of this application. The method involves calculating the absolute index position of a dynamic scheduling priority weight scalar based on the maximum bearer depth constant and queuing offset safety margin, and then reshaping the service load by inserting it into a programmable first-in-first-out queue according to this index to obtain the reshaped service load. Figure 7 As shown, step S51 includes: S511, locking the target message into the first-out queue based on the verified message egress port identifier, and performing bit-by-bit traversal and concatenation of the remaining delay budget carried in the hop-by-hop extension header of each existing message in the target message egress queue to obtain the remaining budget vector of the queued messages; S512, performing serialization calibration calculation on the subsequent bit delay caused by single message insertion based on the egress port line rate and message length to obtain the serialization delay of a single slot; S513, performing ideal scheduling on the dynamic scheduling priority weight scalar based on the maximum capacity depth constant of the queue and the queuing offset safety margin. Bit mapping is used to obtain the candidate queue depth index, and the remaining budget vector of the queued messages is searched in reverse from the tail to the head of the queue by single-slot serialization to delay the timeout. The minimum feasible lower bound that makes all subsequent stored messages not time out after deduction and postponement is obtained. The candidate queue depth index and the value of the minimum feasible lower bound are taken as the later value to generate the deadline safe feasible index; S514, based on the deadline safe feasible index, the hardware linked list pointer is manipulated to perform microsecond-level skip-level reordering of GOOSE / SV service payloads with deadline safe anchoring to generate the skip-level reshaped service payload.

[0053] In steps S511 and S512, the target is locked into the first-out queue based on the verified message exit port identifier. The remaining delay budget carried by each existing message in the first-out queue is traversed and concatenated bit by bit to obtain the remaining budget vector of the queued messages. Then, the subsequent bit delay caused by the insertion of a single message is serialized and calculated based on the exit port line rate and message length to obtain the serialized delay delay of a single slot. It should be noted that, given that the absolute index position calculation in the existing method is an isolated ranking logic, its insertion decision is completed independently based on the weight scalar of the current incoming message itself, without including the information on the coupling relationship between the remaining delay budget and the existing existing messages in the queue. When multiple high-weight messages compete for the front of the queue simultaneously under the concurrent flood of substation faults, each insertion will apply a cascading cumulative effect of a serialized delay to the squeezed existing messages, which may cause critical protection messages with more urgent remaining budgets to time out due to reverse squeezing, triggering a deadline reversal. Based on this, the technical solution of this application further locks the target message into the first-out queue based on the verified message exit port identifier. The remaining delay budget carried in the hop-by-hop extension header of each existing message in the first-out queue is then traversed and concatenated bit by bit to obtain the remaining budget vector of the queued messages. Subsequently, based on the exit port line rate and message length, the subsequent delay caused by a single message insertion is serialized and calculated to obtain the serialized delay delay per slot. Through the above processing, the original hidden deadline distribution of existing messages in the queue list is effectively modeled explicitly as a one-dimensional ordered vector that can be mathematically operated on, and the physical delay caused by a single insertion action to subsequent messages is quantified, providing a quantitative relational data foundation for subsequent judgments on whether insertion will cause existing messages to time out.

[0054] More specifically, in a concrete example of this application, after locking the target and pushing it into the first-out queue based on the verified packet egress port identifier on the hardware resource plane, all currently existing packets in the queue are traversed, and the remaining delay budget field carried in the IPv6 hop-by-hop extension header of each packet is read one by one. These packets are then sequentially concatenated according to their physical ranking from the head to the tail of the queue to construct a vector of remaining budget for the queued packets. The j-th component of this vector represents the remaining available delay allowance for the j-th ranked existing packet in the queue. Subsequently, based on the physical line rate of the egress port and the byte length of the current inbound packet, the forced delay time for each subsequent packet after inserting a single packet is calculated and denoted as the single-slot serialization delay. The calculation expression is as follows:

[0055] in, Delay for single-slot serialization represents the additional physical time that all subsequent existing packets in the queue are forced to wait after a packet is inserted into the queue. The length of the current inbound message in bytes. This is the physical line rate of the output port.

[0056] In the actual operation of substation bus differential protection, the two ends of the protection device need to complete the exchange of sampled values ​​and the calculation of comparison criteria within a very short time window. When a short-circuit fault occurs in the power system, a massive number of GOOSE trip messages and SV sampled value messages flood into the same output port of the white-box switch at the same time. If the cumulative delay experienced by a certain existing protection message exceeds the remaining delay budget carried in its hop-by-hop extension header, the time when the message arrives at the protection device at the other end will exceed the deterministic delay boundary, directly causing the protection signal to be lost or the criterion sampling window to be misaligned. By constructing the remaining budget vector of the queued message and calibrating the serialized delay delay of a single slot, the deadline margin of each existing message and the physical delay caused by a single queuing are transformed into numerical parameters that can be compared and verified one by one, thus making up for the blindness of the existing methods in terms of the coupling relationship of the deadline of existing messages from the information level.

[0057] In step S513, the dynamic scheduling priority weight scalar is ideally ranked and mapped based on the maximum capacity depth constant of the queue and the queuing offset safety margin to obtain the candidate queue depth index. Then, a reverse feasibility inversion search is performed on the remaining budget vector of the queued messages from the tail to the head using single-slot serialization delay. The minimum feasible lower bound is calculated to ensure that all subsequent existing messages do not time out after deducting the delay. The candidate queue depth index is then compared with this minimum feasible lower bound, and a deadline-safe feasible index is generated. It should be noted that since existing budget information alone cannot directly constrain queue-jumping behavior, the ideal ranking obtained from the original weight mapping needs to be aligned and collided with the deadline constraints of the existing messages to find a safe ranking that simultaneously satisfies both the scheduling aggression of AI inference and the safety of the existing message deadline. Otherwise, high-weight messages will still blindly occupy the front of the queue, causing cascading timeouts of subsequent existing messages. Based on this, the technical solution of this application further performs an ideal ranking mapping on the dynamic scheduling priority weight scalar based on the maximum capacity depth constant of the queue and the queuing offset safety margin to obtain the candidate queue depth index. Then, by using single-slot serialization to delay the latency, it performs a reverse feasibility inversion search from the tail to the head of the queue for the remaining budget vector of the queued messages, finding the minimum feasible lower bound that ensures all subsequent existing messages do not time out after deducting the delay. The candidate queue depth index is then compared with this minimum feasible lower bound, and the later value is used to generate the deadline-safe feasible index. Through the above processing, the isolated single-message ranking calculation is effectively upgraded to a dual-constraint queue insertion decision, respecting the priority judgment given by the intrinsic intelligent agent while strictly ensuring that no existing message in the queue times out due to the insertion of a new message, mathematically preventing deadline reversal.

[0058] More specifically, in a concrete example of this application, firstly, based on the dynamic scheduling priority weight scalar combined with the maximum capacity depth constant of the queue and the queuing offset safety margin, the candidate queue depth index is calculated according to the original linear mapping logic. This index represents the ideal insertion position expected by AI inference when the deadline constraint of existing messages is not considered. Then, a reverse feasibility inversion search is performed, traversing each component of the remaining budget vector of messages in the queue from the tail to the head. For each tentative insertion position, it is verified that after a single-slot serialization delay, the remaining budget of all existing messages following that position, minus the delay and the queuing offset safety margin, is still non-negative. The search process finds the minimum feasible position closest to the head of the queue that ensures all subsequent existing messages do not time out, and this is recorded as the lower bound of the constraint. Finally, the larger of the candidate queue depth index and the lower bound of the constraint, i.e., the later the physical ranking, is taken to generate the deadline safety feasible index, the calculation expression of which is:

[0059] in, The deadline-safe and feasible index represents the final valid ranking of the packet after double-constraint anchoring. This is the candidate queue depth index, which is the ideal ranking calculated from the original weight mapping logic. This is the remaining delay budget for the j-th stock packet in the queue message remaining budget vector. The delay for single-slot serialization represents the additional physical time that subsequent stored packets are forced to wait after a packet is inserted. This is a safety margin for queuing bias, used to prevent critical timeouts under boundary conditions.

[0060] When the deadline constraints of existing messages are more stringent than the ideal ranking in AI inference, the above formula shifts new messages to a safe position rather than forcibly preempting them, mathematically preventing deadline reversal. When the ideal ranking is already within the safe range, the formula degenerates into the original logic without sacrificing scheduling aggressiveness. Under the peak of concurrent protection messages in substations, even if multiple high-priority tripping messages compete for the front of the queue simultaneously, this inversion search mechanism ensures that each insertion will not cause any existing sampled value frames or existing tripping commands in the queue to be squeezed out of time, thus upgrading the local greedy scheduling of pushing messages into the first-out queue to a globally deterministic scheduling that takes into account the deadline protection of the entire queue.

[0061] In step S514, the hardware linked list pointer is manipulated based on the deadline-safe feasible index to perform a microsecond-level skip-queue reordering of the GOOSE / SV service payload with deadline-safe anchoring, generating the skip-reshaped service payload. It should be noted that since the deadline-safe feasible index obtained in the previous step remains at the logical level and has not yet been transformed into a real physical queuing action, and existing methods may cause cascading timeouts by directly performing skip-queueing based on ideal ranking, it is necessary to ultimately implement the secure ranking after deadline coupling verification into hardware linked list pointer operations to complete deterministic and secure physical reordering. Based on this, the technical solution of this application further manipulates the hardware linked list pointer based on the deadline-safe feasible index to perform a microsecond-level skip-queue reordering of the GOOSE / SV service payload with deadline-safe anchoring, generating the skip-reshaped service payload. Through the above processing, the insertion point is no longer an ideal bit that may cause cascading timeouts, but a safe bit after strict verification of the coupling relationship during the cutoff period. This ensures that the substation can guarantee low-latency preemption of high-priority tripping messages and strictly adhere to the deterministic boundaries of the entire network's existing messages in the scenario of concurrent faults and flood peaks.

[0062] More specifically, in a concrete example of this application, the port outbound queue manager directly manipulates the hardware linked list pointer based on the deadline-safe feasible index, locating the queue gap between the predecessor and successor nodes corresponding to that index in the programmable push-in-first-out (PIF) linked storage structure. Subsequently, the buffer descriptor corresponding to the GOOSE / SV service payload is inserted into this gap, the next pointer of the predecessor node is modified to point to the address of the newly inserted descriptor, and the next pointer of the new descriptor is set to point to the original successor node address, completing the deadline-safe microsecond-level stream-level reordering. The queue-ready payload is output as the reordered service payload to the head-of-queue preparation area for subsequent extension header write-back and eject transmission stages.

[0063] In substation differential protection scenarios, regardless of the number of concurrent high-priority packets flooding into the white-box switch at the moment of a fault, the protection signal frames and sampled value frames already in the queue will not miss their respective delivery deadlines due to preemption by new packets. By incorporating the coupling relationship between queued packet deadlines into the queue-jumping decision, the systemic risk of deadline reversal caused by the original isolated weighted positioning algorithm under concurrent surges is eliminated. The improved scheduling mechanism ensures that every queue-jumping operation pushed into the first-out queue undergoes deadline feasibility verification, ensuring that any existing packet, even after being postponed by a later position, still meets its remaining delay budget constraint. This theoretically reduces the deterministic delay violation probability of the port outgoing queue to zero, eliminating the risk of protection maloperation or refusal to operate due to deadline reversal at the scheduling layer. This achieves the technical objective of maintaining the aggressiveness of inherent intelligent dynamic scheduling while ensuring the determinism of the entire queue.

[0064] In step S52, the hardware packet editing module overwrites the remaining effective delay budget characteristic value with the hop-by-hop extension header type length value field, and performs binary concatenation assembly and checksum recalculation with the restructured service payload to generate an outbound IPv6 packet with an updated extension header. It should be noted that since the restructured service payload has completed physical queuing, but its corresponding IPv6 hop-by-hop extension header still carries the old, unupdated budget value, if it is directly outbound with this old value, the next-hop white-box switch will make scheduling decisions based on an artificially inflated budget, failing to accurately determine the true remaining urgency of the packet, leading to a break in the hop-by-hop deterministic bearer closed loop. Based on this, the technical solution of this application further uses the hardware packet editing module to overwrite the remaining effective delay budget characteristic value with the hop-by-hop extension header type length value field, and performs binary concatenation assembly and checksum recalculation with the restructured service payload to generate an outbound IPv6 packet with an updated extension header. Through the above processing, it is effectively ensured that when a message leaves the current hop, the budget value carried in its extension header is the latest real remaining amount after deducting the current hop's dwell time, so that downstream nodes can continue to perform sensing and scheduling based on this updated value.

[0065] More specifically, in a concrete example of this application, when the restructured service payload is pushed to the head of the programmable push-in-first-out queue and is about to be ejected from the station, the hardware packet editing engine is activated. First, the remaining valid delay budget characteristic value is read from the packet metadata register and converted into binary encoding according to network byte order. Then, the starting offset of the value field corresponding to the type length value of the delay budget in the IPv6 hop-by-hop options extension header is located, and the new binary encoding is directly written into this value field space by byte overwriting, replacing the original old budget value. After overwriting, the updated IPv6 basic header and hop-by-hop extension header are used as prefixes and concatenated with the restructured service payload in a continuous buffer to form a complete packet frame structure. Finally, the checksum field of the upper-layer transport protocol is recalculated based on the IPv6 pseudo-header, and the updated checksum value is written back to the corresponding position, thereby generating an outbound IPv6 packet with an updated extension header for subsequent physical port ejection.

[0066] In step S53, the underlying network interface card's physical transceiver channel is driven by the verified message egress port identifier to perform parallel-to-serial conversion and physical signal modulation ejection transmission on the outbound IPv6 message after the extension header is updated. It should be noted that since the outbound IPv6 message after the extension header is updated still resides in the internal buffer of the white-box switch as parallel data and has not yet been converted into a serial signal that can be transmitted over optical fiber or copper cable, the corresponding physical transceiver channel needs to be precisely selected based on the verified egress port identifier to complete the final signal conversion and transmission before the message can be delivered to the next-hop device within the substation. Based on this, the technical solution of this application further uses the verified message egress port identifier to drive the underlying network interface card's physical transceiver channel to perform parallel-to-serial conversion and physical signal modulation ejection transmission on the outbound IPv6 message after the extension header is updated. Through the above processing, the message, after intelligent scheduling and extension header update, is effectively converted into a physical layer signal with deterministic timing and sent into the fiber optic link within the substation, completing the entire deterministic bearer closed loop from inbound perception to outbound transmission for this hop node.

[0067] More specifically, in a concrete example of this application, the verified message egress port identifier is converted into the corresponding physical transceiver channel number and pin address on the network interface card through the hardware abstraction layer. Then, a transmit enable instruction is written to the transmit control register of that channel, triggering the MAC layer transmit state machine to start. The MAC layer transmit state machine reads the parallel data bytes of the outbound IPv6 packet after updating the extended header sequentially from the egress buffer, inserts a preamble and a start-of-frame delimiter at the beginning of the frame, and appends a frame check sequence to the end of the frame. After frame encapsulation, the physical encoding sublayer performs parallel-to-serial conversion on the parallel data bytes, converting each parallel byte into a serial bit stream according to the physical layer encoding rules. The serial bit stream is modulated by the physical medium-related sublayer, converted into an optical pulse signal of the corresponding wavelength in an optical port scenario, and ejected via the optical fiber interface corresponding to the physical transceiver channel to the communication optical cable within the substation, for transmission to the next-hop white-box switch.

[0068] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A deterministic bearer communication method for IPv6 white-box networks in substations, characterized in that, include: Step 1: Based on the delay tolerance constraints of substation control services, the end-to-end delay budget is encoded and embedded into the IPv6 hop-by-hop option extension header, and the substation source service packet payload is protocol encapsulated to generate IPv6 service packets carrying the delay budget. Step 2: Parse the IPv6 service packets carrying the latency budget and calculate the single-hop dwell time through the programmable data face of the white-box switch, extract the service payload and egress port identifier, and subtract the dynamic dwell time of the current hop from the latency budget in the hop-by-hop extension header to obtain the characteristic value of the remaining latency budget. Step 3: Based on the egress port identifier, perform micro-burst traffic status acquisition and structured tensor mapping on the queue of the target sending port to generate the micro-burst feature matrix of the egress queue. Step 4: Using a lightweight, intrinsically intelligent scheduling agent deployed on a white-box switch, multi-dimensional feature fusion and forward reasoning are performed on the remaining latency budget feature value and the micro-burst feature matrix of the egress queue to obtain the dynamic scheduling priority weight. Step 5: Based on the dynamic scheduling priority weight, the service payload is dynamically reshaped by skipping levels in the programmable push-in first-out queue, and the remaining delay budget feature value is written back to the IPv6 hop-by-hop extension header. The updated delay budget outbound IPv6 packet is sent through the physical port corresponding to the egress port identifier.

2. The deterministic bearer communication method for substation IPv6 white-box networks according to claim 1, characterized in that, The substation source-side service message payload includes the GOOSE message payload and the SV sampled value message payload.

3. The deterministic bearer communication method for substation IPv6 white-box networks according to claim 2, characterized in that, Step one includes: Step 1.1: Based on the protocol stack encapsulation overhead coefficient and the fixed equipment processing compensation amount, static overhead is deducted from the preset end-to-end latency scalar to obtain the service latency budget characteristic value. Step 1.2: Based on the IPv6 hop-by-hop option protocol specification, network byte order encoding is performed on the service delay budget characteristic value and it is written into a specific type length value field to generate a delay budget extension header structure; Step 1.3: Using protocol layer topology splicing rules, perform multi-layer encapsulation, assembly, verification, and recalculation of the destination IPv6 address, delay budget extension header structure, and substation source-end service packet payload to generate an IPv6 service packet carrying the delay budget.

4. The deterministic bearer communication method for substation IPv6 white-box networks according to claim 1, characterized in that, Step two includes: Step 2.1: The hardware clock synchronization unit performs inbound stamping at the moment the first bit of the message arrives, and performs programmable decapsulation and parsing of the IPv6 service message carrying the delay budget to extract the service payload, target IPv6 address, current hop delay budget and message inbound timestamp. Step 2.2: Perform hardware routing table lookup for the target IPv6 address to generate the egress port identifier; Step 2.3: Capture the message outbound timestamp through the outbound side hardware clock and combine it with the hardware processing compensation constant to dynamically deduct the dwell time from the current hop delay budget to obtain the characteristic value of the remaining delay budget.

5. The deterministic bearer communication method for substation IPv6 white-box networks according to claim 1, characterized in that, Step three includes: Step 3.1: Based on the exit port identifier, locate the target physical transmission port, and perform a status scan of the queue at a microsecond frequency to extract the absolute stacking depth index and the queuing rate increment parameter. Step 3.2: By mapping the row vector of the baseline state, perform multidimensional tensor mapping of congestion features on the two-dimensional column vector composed of the absolute stacking depth index of the queue and the queuing rate increment parameter to obtain the real-time micro-burst feature matrix of the exit queue. Step 3.3: Perform hardware readiness verification and re-marking on the egress port identifier to generate a verified message egress port identifier.

6. The deterministic bearer communication method for substation IPv6 white-box networks according to claim 1, characterized in that, Step four includes: Step 4.1: Based on the global delay lower limit threshold and the global delay upper limit threshold, normalize the delay dimension extrema of the remaining delay budget feature values ​​to obtain normalized delay budget feature values. Step 4.2: Perform multi-dimensional state fusion and splicing on the real-time micro-burst feature matrix of the exit queue and the normalized delay budget feature values ​​to obtain a comprehensive multi-dimensional state vector; Step 4.3: Based on the pre-trained model weight matrix and bias term constant vector, perform AI forward inference and weight generation on the comprehensive multidimensional state vector to obtain the dynamic scheduling priority weight scalar.

7. The deterministic bearer communication method for substation IPv6 white-box networks according to claim 1, characterized in that, Step five includes: Step 5.1: Based on the maximum capacity depth constant of the queue and the safety margin of the queue offset, calculate the absolute index position of the dynamic scheduling priority weight scalar, and reshape the service load by skipping the level in the programmable push-in first-out queue according to the index to obtain the service load after skipping the level. Step 5.2: Using the hardware packet editing module, the remaining effective delay budget characteristic value is overwritten by hop-by-hop extension header type length value field, and then binary concatenated with the service payload after the over-level reshaping is assembled, checked and recalculated to generate an outbound IPv6 packet with the updated extension header. Step 5.3: Based on the verified message egress port identifier, drive the underlying network interface card physical transceiver channel, and perform parallel-to-serial conversion and physical signal modulation on the outbound IPv6 message after updating the extended header and eject it.

8. The deterministic bearer communication method for substation IPv6 white-box networks according to claim 7, characterized in that, Step 5.1 includes: Based on the verified message exit port identifier, the target is locked into the first-out queue. The remaining delay budget carried by each existing message in the first-out queue is traversed and concatenated bit by bit to obtain the remaining budget vector of the queued messages. The serialization calibration calculation of the subsequent bit delay caused by single message insertion is performed based on the line rate of the export port and the message length to obtain the serialization delay time of a single slot. Based on the maximum capacity depth constant of the queue and the safety margin of the queue offset, the dynamic scheduling priority weight scalar is ideally ranked and mapped to obtain the candidate queue depth index. Then, by using the serialization delay of the single slot, the remaining budget vector of the queued messages is searched in reverse from the tail to the head of the queue to find the minimum feasible lower bound that all the remaining messages in the later slots do not time out after deducting the delay. The candidate queue depth index and the value of the minimum feasible lower bound are then compared to the later value to generate the deadline safe feasible index. Based on the deadline-safe and feasible index, the hardware linked list pointer is manipulated to perform microsecond-level skip-queue reordering of GOOSE / SV service payloads with deadline-safe anchoring, generating skip-level reshaped service payloads.

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