A multi-protocol compatible terminal diagnostic instrument intelligent detection system and method

Abstract

This invention relates to the field of distributed control system monitoring and testing technology, and discloses an intelligent detection system and method for a multi-protocol compatible terminal diagnostic instrument. The system includes: a status feature acquisition unit that captures interaction frames, generates a timestamp sequence by adding timestamps through an internal hardware timer, and extracts a protocol type identifier vector; a timing status arbitration unit that routes the data to a dedicated thread to calculate the time interval deviation, filling in a fixed value when the deviation exceeds a threshold to generate a timing correction deviation, and calculating feature parameters using a sliding filter window queue to output a signal; and a dynamic control unit that rewrites the internal register settings based on the signal to reconstruct the instruction outgoing time window. This invention eliminates the misalignment of the measurement and control benchmark caused by heterogeneous protocol stack switching, blocks data pool pollution caused by interference surges, and improves the timeliness of congestion state identification.

Description

Technical Field

[0001] This invention relates to an intelligent testing system and method for a multi-protocol compatible terminal diagnostic instrument, belonging to the field of distributed control system monitoring and testing technology. Background Technology

[0002] Ensuring the stability of data interaction for diagnostic instruments in complex environments is fundamental to maintaining test accuracy and continuity. The mainstream industry approach involves capturing the arrival time series of communication frames from external buses and establishing a fixed-period polling test monitoring architecture based on static clock triggering logic. While this method provides timing monitoring capabilities for single control buses, existing monitoring methods largely focus on localized improvements to the test equipment hardware, with less emphasis on optimizing software control methods. For example, Chinese invention patent application CN115000000A discloses a multi-protocol bus data monitoring system and method. This solution is suitable for scenarios with stable network traffic and no protocol switching. However, in complex scenarios involving transient alternating scheduling of multiple protocols, the lack of an in-situ isolation mechanism for chip-level internal reconfiguration overhead leads to nonlinear coupling between hardware switching delays and network communication delays in the time domain. This easily causes fundamental misalignment of the monitoring timing, resulting in test blind spots and data pool contamination under severe interference. Therefore, how to dynamically adjust the control flow injection phase to eliminate timing congestion while eliminating hardware reconfiguration delays has become a key technical bottleneck that needs to be addressed.

[0003] From the perspective of the physical mechanisms of chip reconfiguration and protocol stack scheduling, when a multi-protocol compatible terminal diagnostic instrument alternately calls different protocol stacks to establish a temporary diagnostic link, the internal controller's register configuration remapping, cache clearing, and state machine transitions will all generate specific internal processing delays. This delay, accompanied by chip resource allocation, exhibits nonlinear fluctuations and is a dynamic overhead generated within the system, rather than the inherent communication delay of the bus transmission link. As external traffic and protocol types increase, the external arbitration delay jitter caused by sudden bus loads and the processing delay generated by the diagnostic instrument switching protocol stacks will undergo temporal nonlinear transient coupling. Traditional systems treat the diagnostic instrument as an instantaneous switching node and rely solely on the bus frame arrival interval to establish a test benchmark. This mismatch between physical presupposition and actual boundaries makes it impossible for the monitoring device to separate the diagnostic instrument's own hardware-level internal reconfiguration overhead from pure bus physical faults under complex operating conditions. This leads to a fundamental misalignment of the monitoring timing benchmark, resulting in test blind spots and data pool contamination in the time series, and causing a deterioration in the fault identification rate.

[0004] Therefore, the technical problem to be solved by this invention is how to capture the protocol type identifier vector and eliminate hardware reconfiguration delay according to the protocol switching delay matrix, rewrite the timer comparison register to adjust the instruction outgoing time window on the basis of blocking the sliding filter window contaminated by sudden artifacts, and eliminate the timing blockage in the bus arbitration stage by dynamically adjusting the control flow injection phase. Summary of the Invention

[0005] To address the problems in the background art, the technical solution of the present invention is as follows: A multi-protocol compatible terminal diagnostic instrument intelligent detection system, the system comprising: The status feature acquisition unit is connected to the heterogeneous control network to capture interaction frames on the heterogeneous control network. It adds an absolute timestamp with a precision of 1μs to each interaction frame through an internal hardware timer to generate a timestamp sequence and transmits the extracted protocol type identifier vector of the current interaction frame. The timing state arbitration unit, consisting of a physical received timestamp sequence and a protocol type identifier vector, includes the following steps: Step S1: Distribute the timestamp sequence to the corresponding protocol measurement and control sub-thread according to the protocol type identifier vector; Step S2: Calculate the core time interval deviation in the protocol measurement and control sub-thread, and when the core time interval deviation exceeds the safety deviation threshold, forcibly rewrite the core time interval deviation of the current period to a fixed boundary padding value to generate the timing correction deviation. Step S3: Push the timing correction deviation into the sliding filter window buffer queue to calculate the mean characteristic parameter. When the mean characteristic parameter is less than the safety deviation threshold, output the timing blocking status signal. The dynamic control unit physically receives timing blocking status signals. Its control output interface is physically coupled to the multi-protocol compatible terminal diagnostic instrument. It is used to rewrite the setting value of the internal timer comparison register of the multi-protocol compatible terminal diagnostic instrument according to the timing blocking status signals to reconstruct the instruction outgoing time window.

[0006] Preferably, the dynamic control unit is equipped with a multi-level compensation state machine. The multi-level compensation state machine is used to accumulate the number of times the discrete triggering conditions are met consecutively by a discrete counting variable. When the core time interval deviation exceeds the safety deviation threshold, the instruction sending time window is reconstructed in stages according to the multi-level control boundary threshold. When the number of times the discrete triggering conditions are met consecutively exceeds the multi-level control boundary threshold, the sending request of the low-priority channel is suspended.

[0007] Preferably, in step S1, the timing state arbitration unit processes the timestamp sequence through the following subordinate features: Step S11, the timestamp sequence is distributed to different protocol measurement and control sub-threads according to the protocol type identifier vector, so that each protocol independently calculates its own core time interval deviation and maintains its own independent sliding filter window buffer queue; Step S12, when the discrete triggering conditions are met simultaneously in different protocol measurement and control sub-threads, the priority screening rule based on security weight is activated to hard truncate the sending requests of low-priority channels and widen the transient physical trigger time difference between heterogeneous protocols.

[0008] Preferably, in step S3, the timing state arbitration unit processes the data through the following subordinate features: Step S31, pushes the timing correction deviation into a sliding filter window buffer queue with a fixed integer length to complete the smoothing process; Step S32, sums up the timing correction deviations of each period retained in the sliding filter window buffer queue and divides them by the length of the sliding filter window buffer queue to calculate the mean feature parameter.

[0009] Preferably, the state feature acquisition unit includes a bus adapter chip and an internal hardware timer; the bus adapter chip connects to a heterogeneous control network to capture interaction frames; the internal hardware timer is used to add an absolute timestamp with a precision of 1μs to each interaction frame to generate a timestamp sequence.

[0010] Preferably, the dynamic control unit is used to directly rewrite the setting value of the internal timer comparison register of the multi-protocol compatible terminal diagnostic instrument according to the timing blocking status signal, so as to reconstruct the instruction outgoing time window.

[0011] Preferably, the counting clock accuracy of the internal hardware timer is 1μs; in step S3, the discrete triggering condition is that the mean characteristic parameter is less than the preset blocking time threshold.

[0012] Preferably, the dynamic control unit is also used to discretely count the number of continuous output timing blocking state signals, and suspend the transmission request of the low-priority channel when the number of continuous cycles exceeds a set safety cycle threshold.

[0013] Preferably, the status feature acquisition unit, the timing status arbitration unit, and the dynamic control unit are integrated inside the same microprocessor chip; the microprocessor chip is coupled to the internal bus of the multi-protocol compatible terminal diagnostic instrument through a bus adapter chip.

[0014] A method for intelligent testing of a multi-protocol compatible terminal diagnostic instrument, used to run an intelligent testing system for a multi-protocol compatible terminal diagnostic instrument, includes the following steps: Step S101: Capture interaction frames on the heterogeneous control network, add an absolute timestamp with a precision of 1μs to each interaction frame through an internal hardware timer to generate a timestamp sequence, and pass through the extracted protocol type identifier vector of the current interaction frame. Step S102: Distribute the timestamp sequence to the corresponding protocol measurement and control sub-thread according to the protocol type identifier vector; Step S103: Calculate the core time interval deviation in the protocol measurement and control sub-thread, and when the core time interval deviation exceeds the safety deviation threshold, force the core time interval deviation of the current period to be rewritten to a fixed boundary padding value to generate the timing correction deviation; push the timing correction deviation into the sliding filter window buffer queue to calculate the mean feature parameter, and output the timing blocking status signal when the mean feature parameter is less than the safety deviation threshold. Step S104: Rewrite the setting value of the internal timer comparison register of the multi-protocol compatible terminal diagnostic instrument according to the timing blocking status signal to reconstruct the instruction outgoing time window.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. In the intelligent detection of multi-protocol compatible terminal diagnostic instrument, the status feature acquisition unit extracts the protocol type identification vector simultaneously when collecting communication interaction data. The timing status arbitration unit retrieves the corresponding hardware reconstruction delay constant from the preset protocol switching delay matrix based on the vector, and actively deducts the delay caused by the reconfiguration of internal registers when calculating the frame interval. This isolates the alternating switching loss of the main control chip itself from the delay distortion caused by network burst traffic, eliminates the measurement and control benchmark misalignment problem induced by the alternating scheduling of mixed protocols, and ensures that subsequent control actions directly target external communication link topology anomalies, maintaining the benchmark continuity of the monitoring device and the accuracy of communication fault capture under high load measurement and control conditions.

[0016] 2. The timing distortion mutation elimination operator built into the timing state arbitration unit performs amplitude boundary verification on the calculated inter-frame time interval deviation. When encountering non-ideal physical packet loss or electromagnetic surge interference that causes external sampling data to exceed the preset boundary, the in-situ amplitude limiting correction is initiated through a single-cycle rejection mechanism. The abnormal deviation value of that cycle is forcibly filled into a fixed boundary value, suppressing the cumulative effect of sudden noise in the sliding filter window buffer queue, preventing the filter output from producing numerical smoothing lag, avoiding the test system from erroneously triggering safety protection polling due to transient distortion, and maintaining the benchmark stability of measurement and control judgment under harsh external electromagnetic interference conditions.

[0017] 3. The multi-level compensation state machine inside the dynamic control unit accumulates the number of consecutive triggers of blocking judgment by discrete counting variables. When the inter-frame time interval deviates from the normal range, it reconstructs the command outgoing time window in stages according to the preset multi-level control boundary threshold. By upgrading the single fixed delay adjustment to the graded gradient delay correction, when encountering continuous nonlinear load impact, it automatically suspends the control flow of non-critical communication protocols and tilts all system test bandwidth to the currently blocked channel, avoiding control state oscillation and adaptive logic deadlock caused by insufficient adjustment, and avoiding collision nodes of heterogeneous protocols in the bus arbitration stage, realizing closed-loop control of control flow adjustment under high load conditions. Attached Figure Description

[0018] Figure 1 This is the overall logic flowchart of the detection system of the present invention; Figure 2 This is a structural diagram of the multi-level compensation state machine of the present invention.

[0019] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0021] A multi-protocol compatible terminal diagnostic instrument intelligent testing system, the system includes: The status feature acquisition unit is connected to the heterogeneous control network to capture interaction frames on the heterogeneous control network. It adds an absolute timestamp with a precision of 1μs to each interaction frame through an internal hardware timer to generate a timestamp sequence and transmits the extracted protocol type identifier vector of the current interaction frame. The timing state arbitration unit, consisting of a physical received timestamp sequence and a protocol type identifier vector, includes the following steps: Step S1: Distribute the timestamp sequence to the corresponding protocol measurement and control sub-thread according to the protocol type identifier vector; Step S2: Calculate the core time interval deviation in the protocol measurement and control sub-thread, and when the core time interval deviation exceeds the safety deviation threshold, forcibly rewrite the core time interval deviation of the current period to a fixed boundary padding value to generate the timing correction deviation. Step S3: Push the timing correction deviation into the sliding filter window buffer queue to calculate the mean characteristic parameter. When the mean characteristic parameter is less than the safety deviation threshold, output the timing blocking status signal. The dynamic control unit physically receives timing blocking status signals. Its control output interface is physically coupled to the multi-protocol compatible terminal diagnostic instrument. It is used to rewrite the setting value of the internal timer comparison register of the multi-protocol compatible terminal diagnostic instrument according to the timing blocking status signals to reconstruct the instruction outgoing time window.

[0022] Preferably, the dynamic control unit is equipped with a multi-level compensation state machine. The multi-level compensation state machine is used to accumulate the number of times the discrete triggering conditions are met consecutively by a discrete counting variable. When the core time interval deviation exceeds the safety deviation threshold, the instruction sending time window is reconstructed in stages according to the multi-level control boundary threshold. When the number of times the discrete triggering conditions are met consecutively exceeds the multi-level control boundary threshold, the sending request of the low-priority channel is suspended.

[0023] Preferably, in step S1, the timing state arbitration unit processes the timestamp sequence through the following subordinate features: Step S11, the timestamp sequence is distributed to different protocol measurement and control sub-threads according to the protocol type identifier vector, so that each protocol independently calculates its own core time interval deviation and maintains its own independent sliding filter window buffer queue; Step S12, when the discrete triggering conditions are met simultaneously in different protocol measurement and control sub-threads, the priority screening rule based on security weight is activated to hard truncate the sending requests of low-priority channels and widen the transient physical trigger time difference between heterogeneous protocols.

[0024] Preferably, in step S3, the timing state arbitration unit processes the data through the following subordinate features: Step S31, pushes the timing correction deviation into a sliding filter window buffer queue with a fixed integer length to complete the smoothing process; Step S32, sums up the timing correction deviations of each period retained in the sliding filter window buffer queue and divides them by the length of the sliding filter window buffer queue to calculate the mean feature parameter.

[0025] Preferably, the state feature acquisition unit includes a bus adapter chip and an internal hardware timer; the bus adapter chip connects to a heterogeneous control network to capture interaction frames; the internal hardware timer is used to add an absolute timestamp with a precision of 1μs to each interaction frame to generate a timestamp sequence.

[0026] Preferably, the dynamic control unit is used to directly rewrite the setting value of the internal timer comparison register of the multi-protocol compatible terminal diagnostic instrument according to the timing blocking status signal, so as to reconstruct the instruction outgoing time window.

[0027] Preferably, the counting clock accuracy of the internal hardware timer is 1μs; in step S3, the discrete triggering condition is that the mean characteristic parameter is less than the preset blocking time threshold.

[0028] Preferably, the dynamic control unit is also used to discretely count the number of continuous output timing blocking state signals, and suspend the transmission request of the low-priority channel when the number of continuous cycles exceeds a set safety cycle threshold.

[0029] Preferably, the status feature acquisition unit, the timing status arbitration unit, and the dynamic control unit are integrated inside the same microprocessor chip; the microprocessor chip is coupled to the internal bus of the multi-protocol compatible terminal diagnostic instrument through a bus adapter chip.

[0030] A method for intelligent testing of a multi-protocol compatible terminal diagnostic instrument, used to run an intelligent testing system for a multi-protocol compatible terminal diagnostic instrument, includes the following steps: Step S101: Capture interaction frames on the heterogeneous control network, add an absolute timestamp with a precision of 1μs to each interaction frame through an internal hardware timer to generate a timestamp sequence, and pass through the extracted protocol type identifier vector of the current interaction frame. Step S102: Distribute the timestamp sequence to the corresponding protocol measurement and control sub-thread according to the protocol type identifier vector; Step S103: Calculate the core time interval deviation in the protocol measurement and control sub-thread, and when the core time interval deviation exceeds the safety deviation threshold, force the core time interval deviation of the current period to be rewritten to a fixed boundary padding value to generate the timing correction deviation; push the timing correction deviation into the sliding filter window buffer queue to calculate the mean feature parameter, and output the timing blocking status signal when the mean feature parameter is less than the safety deviation threshold. Step S104: Rewrite the setting value of the internal timer comparison register of the multi-protocol compatible terminal diagnostic instrument according to the timing blocking status signal to reconstruct the instruction outgoing time window.

[0031] Example 1: Currently, the distributed control bus monitors concurrent communication in heterogeneous control networks. When high-load burst traffic enters the multi-protocol compatible terminal diagnostic instrument, the diagnostic instrument alternately calls different physical layer and link layer protocol stacks to adapt to different controlled units. During the protocol stack switching process, the main control chip inside the diagnostic instrument undergoes register configuration remapping and cache clearing, resulting in microsecond-level hardware reconstruction delay. This delay fluctuates with changes in chip resource allocation and is superimposed on the arbitration delay caused by burst traffic from the external bus. If the monitoring device only collects the interval between interactive frames and establishes a static polling benchmark at a fixed period, it is difficult to distinguish between a true bus physical fault and the transient timing stretching caused by normal protocol switching. The test benchmark will shift on the time axis, thereby causing test blind spots and data pool contamination.

[0032] To eliminate the impact of hardware reconfiguration delay on timing characteristics, the status feature acquisition unit connects to the heterogeneous control network through a bus adapter chip, and captures the interaction frames between the multi-protocol compatible terminal diagnostic instrument and each controlled unit in real time. The internal hardware timer adds an absolute timestamp to each captured interaction frame to generate a timestamp sequence, where the counting clock precision of the internal hardware timer is 1μs. At the same time, the status feature acquisition unit transmits and extracts the inherent protocol type identifier vector in the current interaction frame, and sends the timestamp sequence and protocol type identifier vector as input to the timing status arbitration unit.

[0033] The timing state arbitration unit has a built-in protocol switching delay matrix. In the initial state, this matrix adopts a two-dimensional bidirectional associative array structure and is fixed in the static random access memory of the timing state arbitration unit. Its row index and column index uniquely map to different protocol type numbers. Before the system performs local online adaptive calibration, each grid node of the matrix pre-stores the static hardware reconstruction delay constant determined according to the general semiconductor manufacturing process manual. For example, the initial reference delay constant for switching from the first protocol to the second protocol is set to 12μs, and the initial reference delay constant for switching from the second protocol to the first protocol is set to 15μs, thereby providing a basic time domain alignment reference for cross-protocol scheduling.

[0034] Within each processing cycle, the timing state arbitration unit reads the protocol type identifier vector of the current interaction frame. Protocol type identifier vector of the previous interaction frame ,when When in a cross-protocol stack handover condition, the system determines that it is currently in a handover operation and retrieves the protocol handover delay offset that matches the current protocol handover pair from the protocol handover delay matrix. When calculating the frame interval, subtract the hardware reconstruction delay constant and calculate the core time interval deviation using the following formula: ,in, This represents the core time interval deviation for the current period. The absolute timestamp of the current interaction frame. The absolute timestamp of the previous interaction frame. For protocol switching delay offset, when When the current state is determined to be in a single protocol continuous communication mode, the timing state arbitration unit calculates the core time interval deviation using the following formula: Through the above processing, the internal processing delay caused by protocol stack switching is deducted from the interaction frame interval, and the core time interval deviation corresponds to the external link timing change after deducting the intrinsic switching delay.

[0035] After calculating the core time interval deviation, the timing state arbitration unit calls the timing distortion mutation elimination operator to perform timing distortion elimination on the current cycle. In this embodiment, a safety deviation threshold is used to perform amplitude boundary verification. Set to 50μs, and also serving as the blocking time threshold in the discrete triggering condition, as long as Exceeding the safety deviation threshold The timing state arbitration unit forcibly rewrites the core time interval deviation of the current cycle to a fixed boundary fill value. Generate timing correction deviation ;when At that time, the original value is retained as the timing correction deviation for that period, so as to Calculated, with a fixed boundary fill value of 75 μs, if Exceed If the cycle is too short, it is identified as an extreme mutation sampling point that exceeds the normal network jitter range. The corresponding physical situation is usually non-ideal physical packet loss or electromagnetic surge interference.

[0036] The timing state arbitration unit pushes the timing correction deviation into the length. Smoothing is performed in a sliding filter window buffer queue of 4, and the mean feature parameter is calculated as follows: ,in, The mean characteristic parameter, The length of the sliding filter window buffer queue. Circular indexing of historical samples; For the sliding filter window cache queue, the historical number The timing correction deviation per cycle and the length of the sliding filter window buffer queue are set to 4. This is to offset the 8.5% transient packet loss interference while controlling the data group delay caused by the sliding smoothing within 2 communication cycles. The safety deviation threshold is set to 50μs, which corresponds to the standard communication cycle of 30μs to 40μs in heterogeneous control networks. If the threshold is lower than 30μs, normal interaction is easily misjudged as blocking. If it is higher than 60μs, it is difficult to capture transient timing stretching faults in time.

[0037] In subsequent determinations, the time-series state arbitration unit periodically compares the mean characteristic parameter. Deviation from safety threshold ,when When the signal is received, it indicates that the effective idle transmission margin after deducting the intrinsic switching delay is lower than the safety boundary. The system determines that the multi-protocol compatible terminal diagnostic instrument is currently in a bus timing blocking state and outputs a timing blocking status signal. After the dynamic control unit physically receives this signal, it directly rewrites the setting value of the internal timer compare register of the multi-protocol compatible terminal diagnostic instrument through the control output interface, delaying the allowable external trigger clock of the next diagnostic instruction by 10μs, thereby reconstructing the instruction external transmission time window. Adjusting the injection phase of the bus control flow reduces repeated collisions during the bus arbitration phase.

[0038] To suppress control oscillations caused by continuous timing blockages, a multi-level compensation state machine is set up inside the dynamic control unit. This state machine uses discrete counting variables... Accumulate the number of times the discrete triggering condition is continuously satisfied: when hour, Add 1; when hour, In this embodiment, the first-level threshold is reset to zero. Set to 3, second-level threshold Set to 6, existing in the current cycle. When the amplitude deviates, the dynamic control unit adjusts accordingly. and , The comparison results show that the tiered reconstruction instruction is sent out during the window. achieve and less than When, maintain a fixed step time correction of 10μs; when achieve When the system is subjected to continuous load impact, the dynamic control unit triggers high-priority arbitration, suspends the transmission request of the low-priority channel, and adjusts the delay time step to 50μs, so that the high-priority diagnostic channel avoids the collision window of the low-priority protocol in the bus arbitration phase.

[0039] The priority selection rule based on safety weights is implemented by a protocol priority mapping table pre-configured in non-volatile memory. The mapping table sets protocol types related to vehicle power safety and real-time core diagnostics as high priority, and protocol types corresponding to regular vehicle information or entertainment interaction as low priority. When different protocol measurement and control sub-threads simultaneously meet discrete triggering conditions within the same physical time window, the timing state arbitration unit reads the protocol type identifier vector corresponding to each sub-thread, retrieves the corresponding safety weight value in the protocol priority mapping table, and selects the core diagnostic channel with the highest safety weight value as the admission channel. For channels with lower safety weight values, the timing state arbitration unit sends a hard truncation command to its protocol measurement and control sub-thread, suspending its transmission request, thereby widening the transient physical triggering time difference between heterogeneous protocols.

[0040] With the cooperation of the state feature acquisition unit, the timing state arbitration unit, and the dynamic control unit, when a heterogeneous control network experiences high-load heterogeneous protocol mixed concurrent impact, the timing state arbitration unit first uses the protocol switching delay matrix to deduct the hardware reconstruction delay, and then uses the timing distortion mutation elimination operator to limit abnormal sampling points to enter the sliding filter window buffer queue, so that the mean characteristic parameter changes with the congestion of the external communication link. The dynamic control unit rewrites the setting value of the internal timer comparison register according to the timing blockage status signal, and pushes the instruction outgoing time window to migrate according to the current bus state. Under the condition that the number of concurrent protocols is greater than or equal to 3, after adopting the system of this embodiment, the false alarm rate and false negative rate of communication faults are reduced from 5.2% before adopting this system to below 0.05%, and the average diagnostic response delay is shortened by more than 35%. This control method actively adjusts the time position of the control flow entering the bus arbitration stage by delaying the instruction outgoing trigger clock by 10μs or 50μs, making it easier for the reconstructed outgoing command to obtain the bus idle arbitration right and reducing the cascading blockage caused by repeated collision retransmission.

[0041] Example 2: The current distributed control bus multi-protocol measurement and control test platform injects pulse interference streams of preset density and protocol reconfiguration commands into a heterogeneous control network to form a monitoring field with high load, multiple protocols, and strong interference. The platform is equipped with a physical bus simulator with a clock resolution of 20ns, a hardware flow generator with an output frame rate of 50,000 frames / second, and a data storage and capture unit with a sampling rate of 100MHz. During the test, a random pulse voltage decay sequence with an amplitude of 1.5V is superimposed on the physical signal of the heterogeneous control network, and a discrete packet loss mode with a target frame loss rate of 8.5% is introduced into the transmission medium. This generates a timestamp sequence and a protocol type identifier vector, which serve as the raw input of the status feature acquisition unit.

[0042] Before the experiment, all key control parameters were fixed. The standard frame period of the heterogeneous control network was in the range of 30μs to 40μs, with a safe deviation from the threshold. Below 30μs, the system is prone to misinterpreting normal bus waveforms as blocking states; above 40μs, the risk of missing transient timing stretching faults increases. Combined with the amplitude limiting correction and sliding filtering in this embodiment, a safe deviation from the threshold is achieved. A value of 50 μs is used as the discrete baseline for state transition, and the length of the sliding filter window buffer queue is also taken. The smoothing depth affecting the timing correction deviation will be affected when both a discrete packet loss rate of 8.5% and a 1.5V transient voltage pulse interference are present. Setting it to 4 can smooth out numerical jumps caused by single-cycle packet loss and control the data group delay caused by sliding window updates within two communication cycles. This is the first-level threshold of the multi-level compensation state machine. Set it to 3, the second-level threshold. The value of 6 is used to distinguish between transient jitter and continuous blockage, and to form a hierarchical and sequential control path.

[0043] The experiment included four sample groups. The complete system sample group consisted of a state feature acquisition unit, a timing state arbitration unit, and a dynamic control unit, and enabled protocol switching delay matrix, amplitude limiting correction, sliding filter window buffer queue, and multi-level compensation state machine. The control group maintained the same hardware architecture, but disabled the delay deduction function of the protocol switching delay matrix, thus reducing the protocol switching delay offset. The value is always equal to 0. Control group 2 is used as the upper limit sample group for parameters, and the safe deviation from the threshold is maintained. Set it to 150μs, and adjust the length of the sliding filter window buffer queue. Set to 12, with control group 3 as the lower limit sample group for parameters, the safety deviation threshold is set. Set it to 10μs, and adjust the length of the sliding filter window buffer queue. Set to 1, the above sample group was operated under low load, medium load, high load and overload conditions respectively, and the false alarm rate, false alarm rate and average response delay were recorded.

[0044] In the complete system sample, the test load rate under low load conditions was 15%, the number of concurrent protocols was 1, the frame loss rate was 0, and the timestamp sequence input by the status feature acquisition unit did not contain cross-protocol concurrent impacts. After the timing state arbitration unit completed timing correction, the false alarm rate was 0.01%, the false alarm rate was 0.02%, and the average response delay was 12.3μs. When the load rate increased to 45%, the number of concurrent protocols increased to 2, the frame loss rate was 2.1%, and the system began to show cross-protocol switching and local packet loss superposition. The timing state arbitration unit split the timestamp sequence according to the protocol type identifier vector and smoothed the timing correction deviation after amplitude limiting by sliding window. The false alarm rate was 0.02%, the false alarm rate was 0.03%, and the average response delay was 18.6μs.

[0045] Under high load conditions, the test load rate of the complete system sample group was 85%, the number of concurrent protocols was 3, the frame loss rate was 8.5%, and the state feature acquisition unit extracted the protocol type identifier vector of the current interaction frame. The timing state arbitration unit synchronously reads the protocol type identifier vector of the previous interaction frame. ;when At that time, retrieve the corresponding protocol switching delay offset from the protocol switching delay matrix. , and according to Calculate the core time interval deviation; when At that time, according to The core time interval deviation is calculated, and then the timing state arbitration unit pushes the timing correction deviation into the length. A sliding filter window buffer queue of 4, and according to... After obtaining the mean characteristic parameters and processing as described above, the false alarm rate under this operating condition is 0.04%, the false alarm rate is 0.05%, and the average response delay is 28.4μs. When the load is increased to the overload condition, the test load rate is 95%, the number of concurrent protocols is 4, the frame loss rate is 12.3%, and the complete system sample still maintains the joint processing of cross-protocol switching and sudden packet loss. The false alarm rate is 0.08%, the false alarm rate is 0.11%, and the average response delay is 48.7μs.

[0046] In control group 1, under the same load gradient, the protocol switching delay offset is not deducted. The internal delays caused by main control chip register remapping and cache clearing are directly included in the frame interval calculation. Under low load conditions, the test load rate is 15%, the number of concurrent protocols is 1, the frame loss rate is 0, the false alarm rate is 1.15%, the false alarm rate is 0.85%, and the average response latency is 15.4μs. Under medium load conditions, the test load rate is 45%, the number of concurrent protocols is 2, the frame loss rate is 2.1%, the false alarm rate increases to 3.42%, the false alarm rate increases to 2.18%, and the average response latency increases to 34.2μs. Under high load conditions, the test load rate is 85%. With 3 concurrent protocols, the frame loss rate was 8.5%, the false alarm rate was 5.12%, the false alarm rate was 4.88%, and the average response latency was 62.5 μs. Under overload conditions, with a test load rate of 95% and 4 concurrent protocols, the frame loss rate was 12.3%, the false alarm rate reached 9.14%, the false alarm rate reached 8.65%, and the average response latency increased to 114.2 μs. The above data indicate that when the protocol switching delay offset is always equal to 0, the internal processing delay generated by cross-protocol stack switching is mistakenly incorporated into the external link congestion timing. The timing state arbitration unit has difficulty separating the hardware intrinsic delay from the delay distortion caused by network burst traffic.

[0047] Under the same input conditions of high load, three concurrent protocols, and an 8.5% frame loss rate, control group two used a 150μs safety deviation threshold and a sliding filter window buffer queue of length 12. Due to the excessively high threshold and long sliding window, the buffer queue's sensitivity to sudden timing distortions decreased, resulting in a false alarm rate of 0.12%, but a false alarm rate of 6.25%, and an average response delay of 78.3μs. Control group three, under the same input conditions, used a 10μs safety deviation threshold and a sliding filter window buffer of length 1. In the queue, the timing distortion and mutation elimination operator lacks sufficient multi-cycle smoothing support. High-frequency electromagnetic surges and non-ideal packet loss are more likely to directly affect the judgment results. The false alarm rate rises to 8.45%, the false alarm rate is 0.09%, and the average response delay is 41.6μs. Compared with the complete system sample group under the same high load conditions, the false alarm rate of 0.04%, the false alarm rate of 0.05%, and the average response delay of 28.4μs are mainly reflected in the increased false alarm rate and response delay of the control group 2, while the control group 3 is mainly reflected in the increased false alarm rate.

[0048] As the test load rate increased from 15% to 45%, 85%, and further to 95%, the average response delay of the complete system sample was 12.3μs, 18.6μs, 28.4μs, and 48.7μs, respectively. No exponential timing divergence caused by arbitration collisions of heterogeneous protocol buses was observed. During this process, the multi-level compensation state machine used discrete counting variables... Tracking mean characteristic parameter Below the safety deviation threshold The number of consecutive cycles; when continuous blocking reaches the corresponding threshold, the dynamic control unit rewrites the setting value of the internal timer comparison register of the multi-protocol compatible terminal diagnostic instrument and reconstructs the instruction outgoing time window. This delays the entry of the control flow into the bus arbitration phase, thereby reducing the waiting time caused by invalid collisions.

[0049] When creating a transient physical trigger time difference between heterogeneous protocols, the dynamic control unit sends a time-domain isolation pulse signal to the physical bus driver chip of the multi-protocol compatible terminal diagnostic instrument, forcibly locking the physical layer transceiver enable pin corresponding to the low-priority protocol, so that it is in a high blocking state for a 50μs safety isolation period. As a result, the level signal of the low-priority protocol is delayed in being injected into the bus, and the differential signal of the high-priority protocol obtains the access opportunity of the current bus physical medium during this period. In conjunction with the aforementioned comparison register setting value rewriting action, the timing continuity and measurement and control stability under high load boundary conditions are maintained.

[0050] Example 3: After a multi-protocol compatible terminal diagnostic instrument from different chip batches is connected to a heterogeneous control network, the main control chip is affected by manufacturing process disturbances, resulting in individual differences in the hardware reconfiguration delay during protocol stack switching. If the protocol switching delay matrix only uses the initial static parameters, the timing state arbitration unit will still leave a time-domain alignment residual after deducting the hardware reconfiguration delay. This residual, when superimposed with high-load burst traffic, will cause the distribution of the core time interval deviation to shift, thereby affecting the mean characteristic parameter and the safety deviation threshold. Discrete comparison between them.

[0051] To correct the aforementioned residuals, the state feature acquisition unit and the timing state arbitration unit are connected to the benchmark test calibration bench. First, they receive the calibration enable control command, and then retrieve the general calibration test benchmark environment with zero-load background flow. The main control chip sends alternating switching protocol stack commands through the bus adapter chip, and alternately schedules the first protocol and the second protocol within 1000 consecutive sampling cycles. The internal hardware timer captures the trigger edge control signal of each protocol stack switching action, as well as the start flag of the first interactive frame after the switch, thereby obtaining the discrete delay sample set.

[0052] After reading the discrete delay sample set, the timing state arbitration unit removes discrete anomalies that deviate from the sample mean by more than three times the variance, and calculates the arithmetic mean of the remaining valid delay samples. This arithmetic mean is used as the protocol handover delay offset for the specific protocol handover pair between the first protocol and the second protocol. The specific memory address is written to the internal non-volatile memory to update the protocol switching delay matrix. During subsequent operation, the timing status arbitration unit retrieves the corresponding protocol switching delay offset from the updated matrix based on the protocol type identifier vector. This offset is deducted when calculating the core time interval deviation to match the matrix parameters with the actual switching delay of the current chip.

[0053] When environmental electromagnetic noise changes, the timing state arbitration unit also adjusts the safety deviation threshold based on the rate of change of the time interval distribution of the previous 5 consecutive idle frames. When the global network monitoring indicator reports that the parasitic noise level of the current physical bus is higher than 0.5V and the average timing jitter rate is greater than 12%, external interference will widen the normal frame gap. At this time, the timing status arbitration unit will adjust the safety deviation threshold according to the upward trend of the timing jitter rate. The timing state is stepped up from the standard 50μs to 65μs to reduce the probability of interference noise triggering pseudo-timing blocking state signals. When the parasitic noise level fed back by the global network monitoring indicator drops below 0.2V, the timing state arbitration unit will safely deviate from the threshold. Restore to the initial setting of 50μs, so that the discrete triggering conditions are re-corresponding to the bus idle transmission margin under low noise conditions.

[0054] Protocol handover delay matrix initialization parameter update and security deviation threshold After dynamic adjustment and coordination, the intelligent detection system of the multi-protocol compatible terminal diagnostic instrument can adapt to the topology switching of heterogeneous control networks and the discreteness of individual hardware processes. When the system is running under concurrent high load test conditions, the average alignment residual is reduced to less than 1μs. In the continuous 72-hour boundary stress test, the false alarm rate and the false alarm rate are maintained within the bottom line of 0.05%. The threshold judgment of the timing state arbitration unit is consistent with the current physical bus state. The dynamic control unit rewrites the setting value of the internal timer comparison register of the multi-protocol compatible terminal diagnostic instrument accordingly to maintain the stability of the control state machine transition.

[0055] Example 4: This example combines Figures 1 to 2 This paper describes an intelligent testing system and method for a multi-protocol compatible terminal diagnostic instrument, such as... Figure 1 As shown, the heterogeneous control network accesses and acquires interaction frames to capture them. The captured interaction frames are input to an internal hardware timer to execute an additional 1μs precision absolute timestamp and pass through to extract the protocol type identifier vector. The resulting timestamp sequence and protocol type identifier vector are physically received and then enter step S1: measurement and control sub-thread splitting. The timestamp sequence is split to the corresponding sub-thread according to the protocol type identifier vector. Then, step S2: timing deviation is calculated to calculate the core time interval deviation. When the core time interval deviation exceeds the deviation threshold, it is forcibly rewritten to a fixed boundary padding value to generate a timing correction deviation. The timing correction deviation is then pushed into the sliding filter window in step S3: feature extraction and judgment to calculate the mean feature parameter. When the mean feature parameter is less than the threshold, a timing blocking status signal is output. This timing blocking status signal is input to the reconstruction instruction external transmission time window process to rewrite the setting value of the timer comparison register according to the timing blocking status signal. Finally, the setting value is rewritten through physical coupling control and applied to the multi-protocol compatible terminal diagnostic instrument.

[0056] like Figure 2As shown, the multi-level compensation state machine includes an initial counting state, a fixed-step time correction state, and a suspended low-priority channel state. In the initial counting state, the discrete counting variable is cleared to zero. The machine remains in the initial counting state as long as the mean characteristic parameter is less than the safety deviation threshold and the discrete counting variable has not reached the first-level threshold. When the mean characteristic parameter is less than the safety deviation threshold and the discrete counting variable reaches the first-level threshold, the machine transitions to the fixed-step time correction state to maintain the fixed-step time correction. In the fixed-step time correction state, if the mean characteristic parameter is greater than or equal to the safety deviation threshold, the count is cleared and the machine returns to the initial counting state. If the mean characteristic parameter is less than the safety deviation threshold and the discrete counting variable reaches the second-level threshold, the machine transitions to the suspended low-priority channel state to perform a step adjustment for the delayed sending request of the suspended low-priority channel. In the suspended low-priority channel state, when the mean characteristic parameter is greater than or equal to the safety deviation threshold, the machine also returns to the initial counting state.

[0057] Example 5: After the status feature acquisition unit is connected to the field node network branch topology, the internal hardware timer first completes the reference time axis alignment. The 32-bit counter register in this timer is driven by a passive crystal oscillator and increments from zero. The counter register touches... When the maximum count boundary is reached, a value flip will occur in the next counting cycle, causing a discontinuous jump in the timestamp sequence. To prevent this jump from entering subsequent timing calculations, when the timing state arbitration unit detects that the timestamp of the current captured interaction frame wraps around the previous interaction frame, it determines that the internal hardware timer's count register has overflowed and flipped, and calls the in-situ period compensation calculation method to accumulate the timestamp of the current cycle by a fixed period constant of 4294967296μs, and outputs a linearly spliced ​​continuous timestamp sequence. After this compensation, the overflow of the underlying count register will not change the sequential relationship of the interaction frames on the continuous time axis, and the subsequent core time interval deviation calculation can still be performed along the same time base.

[0058] When a master-slave routing node switch occurs during a diagnostic test of a branch network topology at a field node, the timing state arbitration unit synchronously refreshes the sliding filter window buffer queue. The dynamic control unit sends a single-cycle reset pulse signal to the configuration bus of the timing state arbitration unit to clear the length... The historical time-series correction bias is retained in the sliding filter window buffer queue with a value of 4, and the discrete count variable is also included. By setting it to zero, the historical time-series correction deviation formed under the previous topology no longer participates in the calculation of the mean characteristic parameter under the new topology, and the multi-level compensation state machine also restarts from the initial counting state to respond to the time-series changes of the current branch.

[0059] After completing the above clearing and zeroing, the status feature acquisition unit continues to capture the interaction frames in the new topology branch and adds an absolute timestamp by the internal hardware timer. The timing status arbitration unit recalculates the core time interval deviation and generates the timing correction deviation based on the new timestamp sequence and protocol type identifier vector, and pushes it into the refreshed sliding filter window buffer queue. The dynamic control unit adjusts the setting value of the internal timer comparison register of the multi-protocol compatible terminal diagnostic instrument accordingly, so that the instruction outgoing timing window is realigned with the control flow timing of the new topology branch, and avoids the residual data in the old topology from continuing to affect the current bus injection phase.

[0060] Example 6: When a heterogeneous control network operates for an extended period, the ambient temperature will experience a slow, rapid change. The passive crystal oscillator used by the internal hardware timer will be affected by thermal stress, causing its resonant frequency to drift with temperature. This results in a gradual accumulation of clock skew in the absolute timestamp sequence. After continuous operation exceeding 168 hours, this skew will alter the core time interval deviation. The distribution of the mean feature parameter after sliding filter makes the mean feature parameter... Deviation from the on-site physical timing; deviation from the safety threshold During the comparison, the system may produce a false judgment of blocking caused by non-fault factors.

[0061] To correct the thermal frequency drift of the passive crystal oscillator, the timing state arbitration unit uses the protocol type identifier vector. The reference link, indicating a continuous idle state, tracks long-period clock residuals. After the data storage and capture unit records 500 consecutive idle interaction frames that satisfy the same protocol identifier, the timing status arbitration unit reads the current [frame number]. absolute timestamp of a frame and history absolute timestamp of a frame And combined with the preset standard protocol communication cycle Calculate the frequency scaling correction factor : ,in, This is the frequency scaling correction factor. For the current number The absolute timestamp of the frame, For the first time in history The absolute timestamp of the frame, For the preset standard protocol communication cycle, the timing state arbitration unit first identifies the current protocol through the protocol type identifier vector extracted by the state feature acquisition unit, and then retrieves the standard communication cycle corresponding to the protocol in the idle and silent state from the protocol silence feature table. Only when the protocol type identifier vector remains constant and is in the idle and silent state for 500 consecutive sampling cycles is the standard communication cycle assigned to it. This ensures that the frequency scaling correction factor matches the physical timing of the current protocol.

[0062] Obtain the frequency scaling correction factor Subsequently, the timing status arbitration unit writes it to the local cache register and corrects the core time interval deviation within the subsequent data processing window. : ,in, This is the corrected core time interval. The core time interval deviation This is a frequency scaling correction factor. After this correction, the time-domain cumulative deviation caused by the variation in the passive crystal oscillator resonant frequency is no longer passed to the sliding filter window buffer queue, and the subsequently obtained mean characteristic parameters... It can continue to match the physical timing of the site and reduce bus congestion and misjudgment caused by clock source aging.

[0063] After receiving the timing congestion status signal after clock calibration, the dynamic control unit directly adjusts the setting value of the internal timer compare register of the multi-protocol compatible terminal diagnostic instrument, and reconstructs the instruction outgoing time window. The phase drift is limited to within 0.02μs error range as the core time interval is updated synchronously with the corrected value, enabling the intelligent detection system of the multi-protocol compatible terminal diagnostic instrument to maintain the stability of the control state machine transition under high load and variable temperature conditions.

[0064] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A multi-protocol compatible terminal diagnostic instrument intelligent detection system, characterized in that, The system includes: The status feature acquisition unit is connected to the heterogeneous control network to capture interaction frames on the heterogeneous control network. It adds an absolute timestamp with a precision of 1μs to each interaction frame through an internal hardware timer to generate a timestamp sequence and transmits the extracted protocol type identifier vector of the current interaction frame. The timing state arbitration unit, consisting of a physical received timestamp sequence and a protocol type identifier vector, includes the following steps: Step S1: Distribute the timestamp sequence to the corresponding protocol measurement and control sub-thread according to the protocol type identifier vector; Step S2: Calculate the core time interval deviation in the protocol measurement and control sub-thread, and when the core time interval deviation exceeds the safety deviation threshold, forcibly rewrite the core time interval deviation of the current period to a fixed boundary padding value to generate the timing correction deviation. Step S3: Push the timing correction deviation into the sliding filter window buffer queue to calculate the mean characteristic parameter. When the mean characteristic parameter is less than the safety deviation threshold, output the timing blocking status signal. The dynamic control unit physically receives timing blocking status signals. Its control output interface is physically coupled to the multi-protocol compatible terminal diagnostic instrument. It is used to rewrite the setting value of the internal timer comparison register of the multi-protocol compatible terminal diagnostic instrument according to the timing blocking status signals to reconstruct the instruction outgoing time window.

2. The intelligent detection system for a multi-protocol compatible terminal diagnostic instrument according to claim 1, characterized in that, The dynamic control unit has a multi-level compensation state machine. The multi-level compensation state machine is used to accumulate the number of times the discrete triggering conditions are met consecutively by a discrete counting variable. When the core time interval deviation exceeds the safety deviation threshold, the instruction sending time window is reconstructed in stages according to the multi-level control boundary threshold. When the number of times the discrete triggering conditions are met consecutively exceeds the multi-level control boundary threshold, the sending request of the low-priority channel is suspended.

3. The intelligent detection system for a multi-protocol compatible terminal diagnostic instrument according to claim 1, characterized in that, In step S1, the timing state arbitration unit processes the timestamp sequence through the following subordinate features: Step S11, the timestamp sequence is distributed to different protocol measurement and control sub-threads according to the protocol type identifier vector, so that each protocol independently calculates its own core time interval deviation and maintains its own independent sliding filter window buffer queue; Step S12, when the discrete triggering conditions are met simultaneously in different protocol measurement and control sub-threads, the priority screening rule based on security weight is activated to hard truncate the sending requests of low-priority channels and widen the transient physical trigger time difference between heterogeneous protocols.

4. The intelligent detection system for a multi-protocol compatible terminal diagnostic instrument according to claim 1, characterized in that, In step S3, the timing state arbitration unit processes the data through the following subordinate features: Step S31, pushes the timing correction deviation into a sliding filter window buffer queue with a fixed integer length to complete the smoothing process; Step S32, sums up the timing correction deviations of each period retained in the sliding filter window buffer queue and divides them by the length of the sliding filter window buffer queue to calculate the mean feature parameter.

5. The intelligent detection system for a multi-protocol compatible terminal diagnostic instrument according to claim 1, characterized in that, The status feature acquisition unit includes a bus adapter chip and an internal hardware timer; the bus adapter chip connects to a heterogeneous control network to capture interaction frames; the internal hardware timer is used to add an absolute timestamp with a precision of 1μs to each interaction frame to generate a timestamp sequence.

6. The intelligent detection system for a multi-protocol compatible terminal diagnostic instrument according to claim 1, characterized in that, The dynamic control unit is used to directly rewrite the setting value of the internal timer comparison register of the multi-protocol compatible terminal diagnostic instrument according to the timing blocking status signal, so as to reconstruct the instruction outgoing time window.

7. The intelligent detection system for a multi-protocol compatible terminal diagnostic instrument according to claim 1, characterized in that, The internal hardware timer has a counting clock accuracy of 1μs; in step S3, the discrete triggering condition is that the mean characteristic parameter is less than the preset blocking time threshold.

8. The intelligent detection system for a multi-protocol compatible terminal diagnostic instrument according to claim 1, characterized in that, The dynamic control unit is also used to discretely count the number of continuous output timing blocking state signals, and suspend the transmission request of low-priority channels when the number of continuous cycles exceeds the set safety cycle threshold.

9. The intelligent detection system for a multi-protocol compatible terminal diagnostic instrument according to claim 1, characterized in that, The status feature acquisition unit, timing status arbitration unit, and dynamic control unit are integrated into the same microprocessor chip; the microprocessor chip is coupled to the internal bus of the multi-protocol compatible terminal diagnostic instrument through a bus adapter chip.

10. A method for intelligent detection of a multi-protocol compatible terminal diagnostic instrument, used to run the intelligent detection system for a multi-protocol compatible terminal diagnostic instrument as described in claim 1, characterized in that, Includes the following steps: Step S101: Capture interaction frames on the heterogeneous control network, add an absolute timestamp with a precision of 1μs to each interaction frame through an internal hardware timer to generate a timestamp sequence, and pass through the extracted protocol type identifier vector of the current interaction frame. Step S102: Distribute the timestamp sequence to the corresponding protocol measurement and control sub-thread according to the protocol type identifier vector; Step S103: Calculate the core time interval deviation in the protocol measurement and control sub-thread, and when the core time interval deviation exceeds the safety deviation threshold, force the core time interval deviation of the current period to be rewritten to a fixed boundary padding value to generate the timing correction deviation; push the timing correction deviation into the sliding filter window buffer queue to calculate the mean feature parameter, and output the timing blocking status signal when the mean feature parameter is less than the safety deviation threshold. Step S104: Rewrite the setting value of the internal timer comparison register of the multi-protocol compatible terminal diagnostic instrument according to the timing blocking status signal to reconstruct the instruction outgoing time window.

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