Digital dummy block type data acquisition system and communication method based on double-line bus

Abstract

This invention discloses a segmented data acquisition system and communication method for a digital dummy based on a two-wire bus. The system includes a host computer, at least one partition master node, a group of slave nodes corresponding to the partition master nodes, and a two-wire bus connecting the partition master nodes and the slave node groups. The partition master node supplies power to the slave nodes via the two-wire bus and sends synchronization pulse signals on the two-wire bus using voltage modulation. The slave nodes use the synchronization pulse signals to trigger sensor sampling and upload sensor data on the two-wire bus using current modulation. The two-wire bus serves as a single physical transmission channel, simultaneously enabling power supply, synchronization signal transmission, and data feedback. This invention solves the technical problems of complex wiring, poor synchronization, weak anti-interference, and low reliability in traditional digital dummy data acquisition systems, achieving accurate, synchronous, and conflict-free data acquisition from multiple sensors in digital dummies under high-impact environments.

Description

Technical Field

[0001] This invention relates to the field of automotive crash testing technology, specifically to a digital dummy segmented data acquisition system and communication method based on a dual-wire bus. Background Technology

[0002] In high-impact testing scenarios such as car crash tests, it is necessary to simultaneously collect data from multiple locations on the dummy, including the head, chest, pelvis, and limbs, as well as acceleration, force, and displacement sensors. Because the collision process is extremely short and dynamically changes rapidly, multiple sensor nodes typically need to have microsecond-level synchronization accuracy to ensure that the data collected by each channel is consistent on the timeline.

[0003] Traditional crash test dummy data acquisition systems typically use multiple independent wiring harnesses to connect sensors and the data acquisition unit. As the number of sensors increases, the complexity of the wiring harnesses significantly increases, not only adding to the wiring difficulty of the crash test dummy and the weight of the acquisition system, but also making it more susceptible to electromagnetic interference. Under impact conditions, traditional voltage signal transmission methods are easily affected by noise coupling, leading to problems such as data errors, packet loss, or asynchronous acquisition.

[0004] On the other hand, while two-wire communication or integrated power supply and communication technologies exist in the industrial field—for example, simultaneously achieving power supply and data transmission via a two-wire bus, or superimposing communication signals on the power supply line using carrier modulation to reduce wiring—these technologies are primarily geared towards general industrial measurement or control scenarios. They typically emphasize data transmission and do not adequately consider the high-precision synchronous acquisition requirements of multiple nodes. They lack a unified synchronization triggering mechanism suitable for collision testing scenarios, making it difficult to meet the high-precision time synchronization requirements between multiple sensor nodes during collision testing. Under high-speed collision conditions, the sensor nodes inside a digital dummy may experience transient mechanical impacts of 50g to 200g or more, accompanied by strong vibrations and electromagnetic interference. This places high demands on the structural reliability, communication stability, real-time performance, and synchronization accuracy of the data acquisition system. Existing two-wire or carrier communication solutions are mostly designed based on stable operating conditions and are not optimized for high-impact environments such as collision tests. Under the combined effects of strong mechanical impact and electromagnetic interference, problems such as communication errors, latency jitter, and synchronization drift can easily occur.

[0005] Therefore, existing technologies lack a data acquisition system that can simultaneously simplify wiring harnesses, enhance anti-interference capabilities, and support high-precision synchronous acquisition of multiple sensors under high-impact environments. Summary of the Invention

[0006] The purpose of this invention is to provide a digital dummy block data acquisition system and communication method based on a two-wire bus, so as to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides the following technical solution: A digital dummy block data acquisition system based on a two-wire bus includes a host computer, at least one partition master node, a slave node group corresponding to the partition master node, and a two-wire bus connecting the partition master node and the slave node group, wherein the slave node group includes multiple slave nodes. The partition master node is used to supply power to the slave node through the two-wire bus and to send a synchronization pulse signal on the two-wire bus by voltage modulation. The slave node uses the synchronization pulse signal to trigger the sensor sampling action and uploads sensor data on the two-wire bus through current modulation. The dual-wire bus is a single physical transmission channel used to simultaneously realize power supply, synchronization signal transmission and data return; Furthermore, the partition master node includes a partition master node MCU, a voltage modulation module, and a current monitoring module; The voltage modulation module includes a voltage switching circuit and at least two linear regulators with different output voltage amplitudes. The voltage switching circuit is controlled by a first N-type MOSFET and a P-type MOSFET to control the voltage signal output on the two-wire bus and generate a synchronous voltage signal. The linear regulators are connected to the two-wire bus through isolation diodes. The voltage switching circuit is driven by the partition master node MCU to make the two-wire bus maintain a first voltage state during the asynchronous phase and switch to a second voltage state during the synchronous pulse, thereby forming the synchronous pulse signal. The current monitoring module sequentially includes a current detection unit, a signal amplification unit, and a first voltage comparator. The current detection unit is connected to the current fluctuation signal of the dual-wire bus acquisition circuit, and then the acquired raw signal is sent to the signal amplification unit to complete the amplitude amplification. The amplified signal is sent to the first voltage comparator to complete the level discrimination, thereby identifying the signal uploaded by the slave node through current modulation, and sending the identified signal to the partition master node MCU, ultimately realizing the decoding and extraction of the sensor signal.

[0008] Furthermore, the slave node includes a slave node MCU, a current modulation module, and a voltage monitoring module; The slave node MCU is used to control the current modulation module and read signals from the voltage monitoring module; The current modulation module is used to control the magnitude of the current flowing through the two-wire bus according to the digital signal, and to convert the digital signal into a current signal for uploading. The voltage monitoring module is used to monitor voltage changes on the two-wire bus and identify synchronization signals sent by the partition master node.

[0009] Furthermore, the voltage monitoring module includes a second voltage comparator, a voltage input unit, and a reference voltage module. The positive input terminal of the second voltage comparator is connected to the voltage input unit of the two-wire bus, and the negative input terminal is connected to the reference voltage module. It is used to output a trigger signal when a pulse occurs in the voltage of the two-wire bus, triggering the slave node to enter the data acquisition or data upload state and thus outputting the signal to the slave node MCU.

[0010] Furthermore, the current modulation module includes a second N-type MOSFET, an adjustable current virtual load, and an AD conversion module; The source of the second N-type MOSFET is connected to one end of the adjustable current virtual load, and the other end of the adjustable current virtual load is connected to the two-wire bus. The drain of the second N-type MOSFET is grounded, and the gate is connected to the digital signal output terminal of the slave node MCU. This is used to change the current of the two-wire bus by controlling the conduction state of the second N-type MOSFET, thereby converting the analog physical quantity signal of the sensor acquired by the AD conversion module into a digital signal and uploading it to the two-wire bus.

[0011] Furthermore, the slave node also includes a power management module; The power management module includes a high power supply rejection ratio linear regulator, which draws power from the two-wire bus and steps it down to provide stable power to the internal circuits of the slave node.

[0012] Furthermore, during the power-on configuration phase, the host computer uses SPI chip select to enable the partition master node to send configuration commands to the slave node, setting the sampling rate, sampling information, communication frequency, address information, and dedicated upload time slot information of the slave node.

[0013] The present invention also provides a communication method for the digital dummy data acquisition system described above, comprising the following steps: Configuration phase: The host computer sends configuration commands to the slave nodes through the partition master node to set the sampling rate, address information, and dedicated upload time slot sampling parameters of the slave nodes; Synchronization Phase: The partition master node sends synchronization pulses on the two-wire bus through the voltage modulation module to provide a unified acquisition timing reference for the slave nodes; Response phase: The slave node identifies the synchronization pulse through the voltage monitoring module and latches the current data on the rising edge of the synchronization pulse according to the preset dedicated time slot matched by its own address; Data upload phase: After the slave node detects the falling edge of the synchronization pulse, it starts timing and uploads the encoded sensor data through the current modulation module within the corresponding time slot according to its own matched dedicated upload time slot; Acquisition Phase: The partition master node detects the current change of the two-wire bus through the sampling resistor, distinguishes the corresponding slave node uploading according to the binding relationship between the time slot and the slave address, and decodes the current signal to obtain sensor data.

[0014] Compared with the prior art, the beneficial effects of the present invention are: 1) This invention solves the technical problems of complex wiring harnesses, poor synchronization, weak anti-interference and low reliability of traditional digital dummy data acquisition systems by using a modular architecture design, dual-wire bus power supply and communication integration, and dual-mode communication of voltage modulation synchronization and current modulation data. It achieves accurate, synchronous and conflict-free data acquisition of digital dummy multi-sensor under high-impact environments.

[0015] 2) This invention adopts a modular architecture design, dividing the sensors of different areas of the digital dummy into zones such as head, chest, abdomen, and limbs for management. Within each zone, the corresponding zone master node completes sensor access, data acquisition, synchronization control, and data aggregation. Compared to the traditional approach where each sensor requires a separate power supply line, communication line, and synchronization line, this invention significantly reduces the number of long-distance cross-regional wiring harnesses through zoned aggregation and dual-line bus connection, thereby reducing the wiring density within the digital dummy, minimizing the space occupied by wiring harnesses, and facilitating the internal structure layout and sensor expansion of the digital dummy.

[0016] 3) This invention transmits synchronization signals on a two-wire bus using voltage modulation. Each slave node can simultaneously identify the sampling trigger time based on the bus voltage amplitude or voltage change edge, thereby achieving synchronous sampling of multiple sensors within the same partition. Since the synchronization information is directly superimposed on the power supply bus for transmission, without relying on complex software polling or node-by-node instruction triggering, it can effectively reduce inter-node trigger delay and timing jitter, and improve the time consistency of high-speed dynamic signals in collision tests.

[0017] 4) During the configuration phase, this invention allows for flexible allocation of bus parameters and upload time slots based on the actual number of sensors, sensor addresses, sampling rate, and communication frequency. When the number of sensors needs to be increased, expansion can be achieved by adding slave nodes or adjusting time slot configurations, without requiring significant modifications to the main control hardware structure and system wiring harness. This approach improves system scalability and is suitable for data acquisition needs of different models of digital dummies and different crash test projects.

[0018] 5) This invention reduces the number of independent wiring harnesses between the sensors and the host computer or centralized data acquisition unit, thereby reducing cable length, the number of connectors, and the number of fixing structures, thus reducing the added weight inside the digital dummy. Reducing the number of wiring harnesses also lowers material costs, assembly costs, and subsequent maintenance costs, and reduces the impact of the wiring harnesses on the dummy's structural motion characteristics.

[0019] 6) This invention is particularly suitable for transient high-impact scenarios such as collision tests, impact tests, and drop tests. Its partitioned architecture can adapt to the characteristics of limited internal space, dispersed sensor distribution, multiple acquisition channels, and high synchronization requirements of digital dummies; the integrated dual-wire bus power supply and communication structure reduces weak points in mechanical connections; and the voltage modulation synchronization and current modulation data upload methods improve synchronization accuracy and communication stability under complex operating conditions. Therefore, this invention can improve the engineering applicability and long-term reliability of digital dummy data acquisition systems in actual collision tests. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the core module connection of a digital dummy block data acquisition system based on a dual-wire bus according to the present invention; Figure 2 This is a schematic diagram of the overall framework of a digital dummy block data acquisition system based on a dual-wire bus according to the present invention. Figure 3 This is a schematic diagram of the overall architecture deployment of a digital dummy block data acquisition system based on a dual-wire bus according to the present invention; Figure 4 This is a schematic diagram of the sampling timing of a digital dummy block data acquisition system based on a two-wire bus according to the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This embodiment provides a segmented data acquisition system for digital dummies based on a two-wire bus. This system is suitable for complex operating conditions such as automotive crash testing, which involve high impact, high transients, and strong electromagnetic interference. The system comprises a host computer, four partition master nodes, four sets of slave nodes corresponding one-to-one with the four partition master nodes, and four two-wire buses.

[0023] Among them, such as Figure 3As shown, the four partition master nodes are independently deployed, corresponding to the anatomical regions of the digital dummy, such as the head, torso, upper limbs, and lower limbs. Each partition master node is connected to its corresponding slave node group via an independent two-wire bus. Multiple slave nodes are connected to each two-wire bus, and each slave node is bound to a sensor at its corresponding location. The partitions are completely independent at the electrical level, with no direct connection between them. Logical data management relationships are established only during the host computer configuration phase. In actual operation, the partitions do not interfere with each other, thus achieving distributed data acquisition and regional isolation.

[0024] Compared to traditional centralized cabling solutions, this partitioned structure significantly reduces the number and length of cabling bundles. Furthermore, even if one area is damaged during a collision or impact, it will not affect the data acquisition capabilities of other areas, thereby greatly improving the robustness and reliability of the system.

[0025] like Figure 1 As shown, each partition master node includes a voltage modulation module, a current monitoring module, and a partition master node MCU. The partition master node MCU uses an STM32G4 series microcontroller, preferably a high-frequency model. The STM32G4 series microcontroller is based on the high-performance Arm Cortex-M4 core, features a floating-point unit, supports a clock frequency of up to 170MHz, and integrates abundant timer resources, a high-speed SPI interface, and a high-precision ADC interface, meeting the requirements of high-speed PWM generation, precise time-slot control, synchronous detection, and high-speed data processing in this system. Furthermore, this series of microcontrollers possesses high analog performance and digital processing capabilities, exhibiting significant advantages in mixed-signal processing, making it suitable for the complex control scenarios of voltage modulation and current detection in this system.

[0026] like Figure 2 As shown, the voltage modulation module is used to multiplex power supply and synchronization signals on a two-wire bus. This module employs a dual-LDO parallel power supply structure, comprising a first and a second voltage regulator unit. The first unit outputs 6.6V, and the second outputs 7V. Both voltage regulator units preferably use the TPS7A47 series low-noise, low-dropout linear regulator. The TPS7A47 series has an extremely high power supply rejection ratio, effectively suppressing input power fluctuations and exhibiting low output noise, providing excellent stability in high-precision analog systems. Furthermore, the outputs of the two voltage regulator units are connected in parallel to the two-wire bus via series isolation diodes. The preferred isolation diodes are SS14 Schottky diodes, which utilize their unidirectional conduction characteristics to achieve voltage isolation and interlocking control. This structure ensures that only one voltage source effectively powers the bus at any given time, avoiding mutual interference between the two power supplies and preventing current backflow.

[0027] A voltage switching circuit is incorporated into the 7V voltage path. This circuit comprises a complementary structure consisting of a first N-type MOSFET and a P-type MOSFET, controlled by a PWM signal output from an STM32G4 microcontroller. The voltage switching circuit uses a P-type MOSFET (model A03407A) and an N-type MOSFET (IRLML6344N), resulting in a switching structure with low on-resistance and high switching speed, enabling stable and reliable voltage modulation at high frequencies. In this embodiment, the current modulation frequency is set to 1MHz, and the voltage synchronization frequency is set to 20kHz. High-speed switching control of the 7V voltage generates a synchronization pulse signal superimposed on the two-wire bus. Since the synchronization signal shares the same transmission path as the supply voltage, no additional synchronization cable is required, further simplifying the system structure.

[0028] The slave node includes a slave node MCU, a current modulation module, a voltage monitoring module, and a power management module. The slave node MCU can also use an STM32G4 series microcontroller as the control core to realize data acquisition control, communication encoding, and time slot scheduling.

[0029] The power management module obtains a 6.6V to 7V voltage from the two-wire bus and converts it to the 5V supply voltage required by the system. This module includes a linear regulator, preferably a TPS7A47 series LDO, which has high PSRR characteristics and can effectively suppress high-frequency interference signals from the bus, ensuring the power supply stability of the subsequent analog acquisition module and thus improving the overall measurement accuracy.

[0030] The voltage monitoring module is used to detect synchronization pulse signals on the two-wire bus and includes a second voltage comparator, a voltage input unit, and a reference voltage module. The second voltage comparator uses a TLV3021 high-speed comparator. This comparator features fast response, low power consumption, and strong output drive capability, making it suitable for high-speed signal detection scenarios. Its positive input terminal is connected to the two-wire bus via the voltage input module, proportionally reducing the bus voltage. The negative input terminal is connected to a high-precision reference voltage provided by the reference voltage module. The reference voltage module uses a REF5040, a high-precision reference voltage source with extremely low temperature drift and high stability. Its output voltage is stable and reliable, serving as the comparator's reference. When the bus voltage jumps from 6.6V to 7V, the voltage after voltage division exceeds the reference voltage, causing the comparator output level to flip, thus recognizing the synchronization pulse.

[0031] The current modulation circuit is used to realize data communication from the slave device to the master device. It includes a second N-type MOSFET, an adjustable current virtual load, and an AD conversion module. The AD conversion module uses an AD7980 analog-to-digital converter. The AD7980 is a 16-bit high-precision successive approximation ADC with a maximum sampling rate of 1MSPS. It also features low power consumption and high linearity, meeting the dual requirements of high precision and high-speed sampling in this system. This device has a short conversion time and low sampling delay, which is beneficial for achieving synchronous acquisition of multiple channels. Controlled by an STM32G4 microcontroller, it enables high-precision digital processing of sensor signals. The gate of the second N-type MOSFET is controlled by the microcontroller output signal and enhanced by the gate driver. The source is connected in series with the adjustable current virtual load and then connected to a two-wire bus. The drain is grounded to form a loop. The adjustable current virtual load uses a 200Ω modulation resistor. When the second N-type MOSFET is turned on, current flows to ground through the modulation resistor, thereby increasing the bus current; when the second N-type MOSFET is turned off, the current path is broken, and the bus current decreases. By controlling the on and off states of the second N-type MOSFET, a small current disturbance signal in the range of 0mA to 30mA can be generated on the bus, thereby enabling data transmission.

[0032] On the master node side, a 1Ω precision sampling resistor is connected in series on the two-wire bus to convert the current signal into a voltage signal. The sampled voltage signal is then amplified by the INA299A1 current sense amplifier. This device has high bandwidth and high-precision differential detection capability, enabling it to accurately capture minute current changes. Subsequently, the amplified high-frequency signal is decoupled using a capacitor and sent to the next stage. This signal is further amplified by the TLV9061 operational amplifier, which has high bandwidth, low noise, and good stability. In this embodiment, a gain of 100x is set to ensure the signal amplitude is within a range suitable for subsequent digital processing. Finally, the master node decodes the signal and stores it in Flash memory, awaiting reconstructed data to be read by the host computer after the experiment.

[0033] Based on the above system architecture, the communication method in this embodiment includes the following steps: During phases t0 to t1, the system is in the initialization and configuration phase. The host computer establishes communication connections with each partition master node via the SPI interface, and sends system operating parameters, including sampling rate, communication frequency, number of nodes, address mapping relationship, and corresponding time slot allocation information. After receiving the configuration command, each partition master node further sends the parameters to its corresponding slave nodes. The slave nodes complete the initialization configuration and write their corresponding time slot number and delay parameters into local registers or non-volatile memory units. The delay parameters are used for distributed timing alignment after subsequent synchronization triggering. Their allocation method can be determined based on node address order, topology location, or preset strategy, thereby forming an ordered transmission sequence under multi-node conditions.

[0034] During this phase, the partition master node continuously provides a stable DC power supply voltage to the slave nodes via a two-wire bus, maintaining the bus in a first voltage state. This first voltage state ensures the stable operation of the internal power management module of the slave node and provides a reference voltage condition for subsequent synchronization and communication processes. While drawing power, the slave node receives a low-speed configuration signal from the master node through a voltage monitoring module, achieving multiplexing of the power supply path and the configuration communication path, thereby avoiding the introduction of additional communication links.

[0035] After the system completes the initial configuration, the host computer issues a test start command to trigger the sampling process, then exits bus control and enters a high-impedance state, no longer participating in the real-time communication and control process. The system control is completely taken over by the master nodes of each partition.

[0036] At time t1, each partition master node initiates a synchronization triggering process based on its internal timer or dedicated trigger circuit. The voltage modulation module controls the transition of the two-wire bus voltage, switching the bus from a first voltage state to a second voltage state, thereby generating a synchronization trigger pulse. The voltage transition amplitude is limited to a range that does not affect the power supply stability of the slave nodes, allowing the synchronization signal to be embedded in the power supply path for transmission without disrupting power supply continuity.

[0037] During the period from t1 to t2, such as Figure 4 As shown, the master node periodically modulates the bus voltage, switching between a second voltage state and a first voltage state to form a synchronization pulse sequence with a fixed frequency. This synchronization pulse sequence is used not only to establish the system's global time base but also as a start marker for the synchronization frame, used to unify the sampling trigger times of each slave node. To improve synchronization reliability, the synchronization pulse preferably has a distinct rising edge characteristic and carries frame start information through duty cycle or pulse interval encoding.

[0038] Each slave node monitors the voltage change signal on the two-wire bus in real time through a voltage monitoring module. When a voltage transition exceeds a preset threshold, an input capture interrupt is triggered, and a synchronization signal is determined to have arrived. Upon synchronization edge triggering, the slave immediately initiates its internal sampling control logic to sample the sensor output signal and drives the AD conversion module to complete the analog-to-digital conversion, latching the sampling result into a local register or buffer. Simultaneously, the slave calibrates its local clock based on this synchronization signal to align with the master node's time base, eliminating errors caused by clock drift between nodes.

[0039] At time t2, the master node's synchronization voltage switches from the second voltage state back to the first voltage state, ending the synchronization trigger phase. After completing synchronization sampling, the slave nodes enter the waiting-to-upload phase. Each slave calculates its own data transmission start time based on pre-configured delay parameters. These delay parameters are used to construct a distributed time slot scheduling mechanism, enabling each node to access the bus sequentially under a unified synchronization benchmark. By staggering transmission times, conflicts caused by multiple nodes simultaneously driving the bus are avoided.

[0040] During the period from t2 to t3, the slave node continuously counts the time difference between the synchronization trigger moment and the current moment, and compares it with the delay parameters stored in the configuration phase. When the time matching condition is met, the slave node initiates the data transmission process in its corresponding time slot, encodes the previously latched sampled data according to a predetermined encoding rule, and loads it onto the two-wire bus through the current modulation module. The current modulation module controls the switching devices to turn on and off, causing a detectable change in the current flowing through the bus, thereby realizing the transmission of data on the power supply path.

[0041] Meanwhile, the master node detects current changes in real time through sampling resistors on the bus side. These changes are then processed by a pre-amplifier circuit and a post-shaping circuit to convert the current signal into a recognizable voltage signal. Subsequently, the partitioned master node MCU analyzes this signal and, combined with time slot allocation information and address mapping, distinguishes and receives data from different slave nodes without conflict.

[0042] During the period from t3 to t4, the master node sequentially receives and decodes data from all slave nodes, and performs integrity verification and caching on the received data. Preferably, a verification field can be introduced into the data frame to improve data reliability.

[0043] At time t4, the master node completes the reception and parsing of all slave data, and reconstructs and stores the data according to the time sequence and node number.

[0044] After the test, the host computer regains control of the system, reads data from each partition master node and integrates it to form a complete data acquisition result.

[0045] Overall, the system constructs a data acquisition mechanism that deeply couples power supply and communication by coordinating power supply, voltage synchronization triggering, and current modulation communication on the same two-wire bus. This enables both synchronization and communication signals to be transmitted based on the power supply path, thus ensuring the stability of power supply and the reliability of communication even under high-impact and strong electromagnetic interference environments, and achieving high-precision synchronous acquisition and stable data transmission from multiple nodes.

[0046] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A segmented data acquisition system for a digital dummy based on a dual-wire bus, characterized in that, It includes a host computer, at least one partition master node, a slave node group corresponding to the partition master node, and a two-wire bus connecting the partition master node and the slave node group, wherein the slave node group includes multiple slave nodes; The partition master node is used to supply power to the slave node through the two-wire bus and to send a synchronization pulse signal on the two-wire bus by voltage modulation. The slave node uses the synchronization pulse signal to trigger the sensor sampling action and uploads sensor data on the two-wire bus through current modulation. The two-wire bus is a single physical transmission channel used to simultaneously achieve power supply, synchronization signal transmission, and data return.

2. The digital dummy segmented data acquisition system based on a dual-wire bus according to claim 1, characterized in that, The partition master node includes a partition master node MCU, a voltage modulation module, and a current monitoring module; The voltage modulation module includes a voltage switching circuit and at least two linear regulators with different output voltage amplitudes. The voltage switching circuit is controlled by a first N-type MOSFET and a P-type MOSFET to control the voltage signal output on the two-wire bus and generate a synchronous voltage signal. The linear regulators are connected to the two-wire bus through isolation diodes. The voltage switching circuit is driven by the partition master node MCU to make the two-wire bus maintain a first voltage state during the asynchronous phase and switch to a second voltage state during the synchronous pulse, thereby forming the synchronous pulse signal. The current monitoring module sequentially includes a current detection unit, a signal amplification unit, and a first voltage comparator. The current detection unit is connected to the current fluctuation signal of the dual-wire bus acquisition circuit, and then the acquired raw signal is sent to the signal amplification unit to complete the amplitude amplification. The amplified signal is sent to the first voltage comparator to complete the level discrimination, thereby identifying the signal uploaded by the slave node through current modulation, and sending the identified signal to the partition master node MCU, ultimately realizing the decoding and extraction of the sensor signal.

3. The digital dummy segmented data acquisition system based on a dual-wire bus according to claim 1, characterized in that, The slave node includes a slave node MCU, a current modulation module, and a voltage monitoring module; The slave node MCU is used to control the current modulation module and read signals from the voltage monitoring module; The current modulation module is used to control the magnitude of the current flowing through the two-wire bus according to the digital signal, and to convert the digital signal into a current signal for uploading. The voltage monitoring module is used to monitor voltage changes on the two-wire bus and identify synchronization signals sent by the partition master node.

4. The digital dummy segmented data acquisition system based on a dual-wire bus according to claim 3, characterized in that, The voltage monitoring module includes a second voltage comparator, a voltage input unit, and a reference voltage module. The positive input terminal of the second voltage comparator is connected to the voltage input unit of the two-wire bus, and the negative input terminal is connected to the reference voltage module. It is used to output a trigger signal when a pulse occurs in the voltage of the two-wire bus, triggering the slave node to enter the data acquisition or data upload state and thus outputting the signal to the slave node MCU.

5. A segmented data acquisition system for a digital dummy based on a dual-wire bus according to claim 3, characterized in that, The current modulation module includes a second N-type MOSFET, an adjustable current virtual load, and an AD conversion module. The source of the second N-type MOSFET is connected to one end of the adjustable current virtual load, and the other end of the adjustable current virtual load is connected to the two-wire bus. The drain of the second N-type MOSFET is grounded, and the gate is connected to the digital signal output terminal of the slave node MCU. This is used to change the current of the two-wire bus by controlling the conduction state of the second N-type MOSFET, thereby converting the analog physical quantity signal of the sensor acquired by the AD conversion module into a digital signal and uploading it to the two-wire bus.

6. The digital dummy segmented data acquisition system based on a dual-wire bus according to claim 3, characterized in that, The slave node also includes a power management module; The power management module includes a high power supply rejection ratio linear regulator, which draws power from the two-wire bus and steps it down to provide stable power to the internal circuits of the slave node.

7. The digital dummy segmented data acquisition system based on a dual-wire bus according to claim 1, characterized in that, During the power-on configuration phase, the host computer uses SPI chip select to enable the partition master node to send configuration commands to the slave node, setting the sampling rate, sampling information, communication frequency, address information, and dedicated upload time slot information of the slave node.

8. A communication method for a digital dummy segmented data acquisition system as described in any one of claims 1-7, characterized in that, Includes the following steps: Configuration phase: The host computer sends configuration commands to the slave nodes through the partition master node to set the sampling rate, address information, and dedicated upload time slot sampling parameters of the slave nodes; Synchronization Phase: The partition master node sends synchronization pulses on the two-wire bus through the voltage modulation module to provide a unified acquisition timing reference for the slave nodes; Response phase: The slave node identifies the synchronization pulse through the voltage monitoring module and latches the current data on the rising edge of the synchronization pulse according to the preset dedicated time slot matched by its own address; Data upload phase: After the slave node detects the falling edge of the synchronization pulse, it starts timing and uploads the encoded sensor data through the current modulation module within the corresponding time slot according to its own matched dedicated upload time slot; Acquisition Phase: The partition master node detects the current change of the two-wire bus through the sampling resistor, distinguishes the corresponding slave node uploading according to the binding relationship between the time slot and the slave address, and decodes the current signal to obtain sensor data.

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