Planar optical switching network based on multi-mask splicing, optical switching chip and system

Abstract

This invention provides a planar optical switching network, optical switching chip, and system based on multi-mask splicing. The planar optical switching network includes multiple mask-level optical switching units; these units are disposed on the same substrate, the same wafer region, or the same optical switching package; each unit occupies an area within the exposure size range of one mask; different units are optically connected via cross-mask optical interconnect channels and cross-mask optical splicing interfaces, collectively forming a complete large-scale planar optical switching network. Using this invention, an ultra-large-scale optical switching network spanning multiple photomasks can be realized, saving mask resources and optimizing cost and process.

Description

Technical Field

[0001] This invention relates to the fields of optical communication and silicon photonics integration technology, and in particular to a planar optical switching network, optical switching chip and system based on multi-mask splicing. Background Technology

[0002] With the increasing demands for bandwidth, energy efficiency, and scalability from data centers, artificial intelligence computing clusters, high-performance computing, and optical communication systems, large-port-count optical switches have attracted widespread attention. Silicon photonics platforms, capable of achieving high density, low cost, and large-scale integration using CMOS-like processes, have thus become a crucial technological approach for building large-scale optical switching networks.

[0003] Existing optical switching networks often employ cross-bar (vertical and horizontal) matrices, Bene... (Bene) Network, Spanke-Bene Spunk-Benise networks, PILOSS (Path-Independent Insertion-Loss) networks, Banyan networks, dilated networks, or other multi-level planar topologies are all suitable for optical switching. Cross-bar matrix structures are particularly advantageous due to their simplicity, regular layout, high repeatability, and symmetry, making them ideal for integration with MEMS (Micro-Electromechanical System) optical switching units to construct high-port-count, low-loss, and low-crosstalk optical switching networks. Existing wafer-level silicon photonics MEMS optical switches utilize multiple mask-level switch blocks (independent optical switch array units that can be fabricated within a standard reticle size range) spliced ​​together to achieve large-scale optical switches exceeding the size limitations of a single mask. Related work has shown that introducing widened or tapered waveguides at the mask boundaries can significantly reduce splicing losses.

[0004] However, the cross-bar matrix structure requires N×N switch units, and the number of units increases quadratically with the number of ports. For scenarios requiring reduced switch unit numbers, improved routing regularity, reduced local crossovers, and adaptation to planar cabling, Spanke-Bene... PILOSS, Bene -like, Banyan-like, dilated, and other topologies and their variations are attractive. These planar arrangement topologies are often used to implement permutation switching, rearrangeable non-blocking, or strictly non-blocking routing.

[0005] However, most existing planar optical switching topologies are designed for a single chip region or a single mask area. Their layout, port arrangement, routing resources, and control strategies typically assume that all input and output connections are completed within a single mask size. When the number of ports, area, or routing complexity of a planar optical switching network exceeds the limitations of a single mask size, there is still a lack of effective systematic design for how to combine multiple mask-level planar optical switching units into a larger-scale optical switching network, or how to break down a complete large-scale switching matrix that originally needed to be implemented beyond the scope of a single mask into multiple mask-level sub-regions and restore its overall switching function through cross-region routing. Summary of the Invention

[0006] This invention provides a planar optical switching network, optical switching chip, and system based on multi-mask splicing, to realize an ultra-large-scale optical switching network spanning multiple photomasks, saving mask resources and optimizing cost and process.

[0007] On one hand, embodiments of the present invention provide a planar optical switching network based on multi-mask splicing, comprising: multiple mask-level optical switching units; the multiple optical switching units are disposed in the same substrate, or the same wafer region, or the same optical switching package; each optical switching unit occupies an area within the exposure size range of a mask and includes internal routing resources and at least one peripheral routing resource; Different optical switching units are optically connected through cross-mask optical interconnect channels and cross-mask optical splicing interfaces, forming a complete large-scale planar optical switching network.

[0008] Optionally, the optical switching unit has full local planar optical switching capability and can operate as an independent optical switching unit.

[0009] Optionally, at least one peripheral routing channel, boundary row, boundary column, reserved row, reserved column, redundant row, or redundant column in the optical switching unit is configured as the cross-mask optical interconnect channel, so that the multiple optical switching units are combined into the complete large-scale planar optical switching network through cross-regional routing.

[0010] Optionally, the optical switching unit is a partition in the complete large-scale planar optical switching network, and the partition includes any one or more of the following: sub-networks or sub-arrays divided according to topology, partial switching levels, partial routing areas, or specific port groups divided according to functional levels.

[0011] Optionally, the optical switching unit includes some switching nodes, some routing paths, some switching stages, some port groups, or some control areas; any one of the optical switching units leads some ports or connection nodes of internal routing resources to external routing resources, and then connects with other optical switching units through the cross-mask optical interconnect channel and the cross-mask optical splicing interface to form the complete large-scale planar optical switching network.

[0012] Optionally, the peripheral routing resources are located in the edge region, boundary region, reserved region, or redundant routing region of the optical switching unit; The peripheral routing resources include one or more waveguide channels, routing rows, routing columns, boundary waveguides, spare waveguides, redundant waveguides, optical switch nodes, couplers, cross-connect structures, or mode conversion structures; The peripheral routing resources are optically connected to the internal routing resources through boundary optical switches, 2×2 optical switches, configurable couplers, fixed couplers, waveguide branches, beam combiners, or routing nodes, enabling optical signals to switch between the internal planar optical switching network and the cross-unit optical interconnect channel.

[0013] Optionally, the waveguide channel in the peripheral routing resource simultaneously undertakes the functions of cross-mask interconnection, testing, monitoring, calibration, backup path, or fault bypass; the waveguide channel is connected to an optical power monitor, test port, calibration loop, backup optical path, or path verification circuit.

[0014] Optionally, the 2×2 optical switch is located in the internal routing resources, at the connection node between the internal routing resources and the external routing resources, or in the external routing resources.

[0015] Optionally, the 2×2 optical switch includes any one or more of the following: Mach-Zehnder interferometer optical switch, directional coupler optical switch, microring resonator optical switch, thermo-optical switch, electro-optical switch, and phase change material optical switch.

[0016] Optionally, the plurality of optical switching units are arranged in an M×K array, where M and K are positive integers.

[0017] Optionally, the internal planar optical switching network, peripheral routing resources, input / output port groups, and cross-mask optical interconnect channels of the optical switching unit all have any one or more of the following characteristics: central symmetry, rotational symmetry, mirror symmetry, and translational periodicity. The multiple optical switching units arranged in the M×K array are formed by repeatedly exposing the same mask through one or more operations such as translation, mirroring, and rotation.

[0018] Optionally, the cross-mask optical splicing interface is located between adjacent photolithography exposure areas, adjacent optical exchange units, adjacent photonic chips, or adjacent optical exchange chips.

[0019] Optionally, the cross-mask optical splicing interface includes at least one of the following structures: direct waveguide splicing structure, widened waveguide, tapered waveguide, adiabatic mode extender, multimode waveguide, multimode interference waveguide, shallowly etched wide ridge waveguide, subwavelength grating mode converter, effective refractive index gradient structure, multilayer waveguide transition structure, directional coupler, adiabatic coupler, vertical coupler, spot size converter, grating-assisted coupler, polymer optical bridge, silicon nitride optical bridge, tilted waveguide interface, and redundant parallel splicing interface.

[0020] Optionally, the cross-mask optical splicing interface includes a splicing structure formed by a combination of tapered waveguides and multimode waveguides.

[0021] Optionally, the cross-mask optical splicing interface includes a shallowly etched wide ridge waveguide; the deeply etched high-constraint waveguide in the cross-mask optical interconnect channel transitions into the shallowly etched wide ridge waveguide near the boundary; the shallowly etched wide ridge waveguide is disposed across the mask boundary, or disposed on both sides of the boundary and directly spliced ​​at the boundary.

[0022] Optionally, the cross-mask optical splicing interface includes a multi-layer waveguide transition structure; Optical signals are coupled from a first waveguide layer to a second waveguide layer, which is a silicon nitride waveguide layer, a polymer waveguide layer, or a low refractive index difference waveguide layer, and has an optical mode size larger than that of the first waveguide layer; the second waveguide layer carries cross-mask optical interconnects at the mask boundary, and then couples the optical signals back to the first waveguide layer.

[0023] On the other hand, embodiments of the present invention also provide an optical switching chip, including the aforementioned planar optical switching network based on multi-mask splicing.

[0024] On the other hand, embodiments of the present invention also provide an optical switching system, including the aforementioned planar optical switching network based on multi-mask splicing and a controller; The controller is used to configure the routing status.

[0025] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: The planar optical switching network and optical switching chip based on multi-mask splicing provided in this invention introduce cross-mask interconnect channels and cross-mask optical splicing interfaces into the planar optical switching network architecture, enabling multiple mask-level optical switching units to be spliced ​​within the same substrate or package to form a complete large-scale planar optical switching network. Thus, the planar optical switching network, originally limited by the exposure size of a single mask, can be expanded by splicing multiple local complete optical switching units, or it can be implemented as a single complete switching matrix split into multiple mask exposure size regions and then combined, thereby breaking through the physical size bottleneck of photolithography equipment and realizing the manufacturability of ultra-large-scale optical switching networks.

[0026] Furthermore, the existing or reserved peripheral routing channels, boundary rows, boundary columns, reserved rows, reserved columns, redundant rows, or redundant columns of the optical switching unit itself can be configured as cross-mask optical interconnect channels. By reusing these channel resources originally used for local routing or redundancy backup for cross-unit interconnection, the introduction of additional cross-mask wiring, additional waveguide cross-connect structures, external fiber optic patch cords, or additional intermediate interconnect structures can be reduced. This not only saves chip area and reduces layout complexity but also reduces insertion loss and crosstalk introduced by additional wiring and cross-connect structures, while simultaneously reducing control complexity.

[0027] Furthermore, the internal network, peripheral routing resources, port groups, and cross-mask interconnection channels of the optical switching unit are designed with symmetrical structures exhibiting central symmetry, rotational symmetry, mirror symmetry, translational periodicity, or combinations thereof. Thus, the same mask pattern can be reused in different exposure areas through translation, rotation, mirroring, or combinations thereof, forming an M×K multi-mask optical switching network. In other words, multiple optical switching units arranged in an M×K array can be formed by repeatedly exposing the same mask through one or more operations such as translation, mirroring, and rotation. This approach reduces the need for additional mask fabrication, lowers manufacturing costs, and shortens the layout development cycle. Furthermore, since all optical switching units are replicated using the same master mask, the critical dimensions between different optical switching units are highly consistent, effectively reducing mode mismatch at the splicing interface and improving the optical performance and process consistency after splicing multiple optical switching units.

[0028] Furthermore, while retaining the local planar optical switching capabilities of each optical switching unit (as an independent and complete unit), the coordinated configuration of horizontal and / or vertical peripheral routing resources, cross-mask interconnect channels, and cross-mask splicing interfaces enables multiple optical switching units to collaboratively form an optical switching network with a larger number of ports through hierarchical routing strategies. This allows for simultaneous support of optical path expansion across submodules, cross-masks, cross-chips, and even wafer-level applications, providing a flexible multi-level interconnect architecture for various application scenarios such as data center optical interconnects and AI computing clusters.

[0029] Furthermore, by setting cross-mask optical splicing interfaces in the boundary connection areas of cross-mask optical interconnect channels, additional insertion loss, reflection, and crosstalk caused by mask splicing errors, chip boundary alignment errors, interlayer alignment errors, or packaging assembly errors can be reduced.

[0030] Furthermore, by employing widened waveguides, tapered waveguides, multimode waveguides, multimode interference waveguides, shallowly etched wide-ridge waveguides, multilayer waveguide transition structures, subwavelength grating mode converters, polymer optical bridges, silicon nitride optical bridges, or other mode extension / mode matching structures, the tolerance of cross-mask optical interconnect channels to lateral offset, longitudinal offset, and angular deviation can be improved, thereby enhancing the manufacturability and yield of multi-mask spliced ​​optical switching networks.

[0031] Furthermore, by introducing optical power monitors, splitters, test ports, calibration loops, backup paths, or redundant parallel splicing interfaces near peripheral channels or cross-mask optical splicing interfaces, path verification, link loss calibration, crosstalk monitoring, fault detection, and backup path selection can be achieved, thereby improving the testability, maintainability, and reliability of large-scale optical switching networks. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a planar optical switching network based on multi-mask splicing provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a single optical switching unit in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of two optical switching units spliced ​​together to form a 1×2 array in an embodiment of the present invention; Figure 4 Based on the large-scale Bene constituting optical switching units in the embodiments of the present invention A schematic diagram of a network topology; Figure 5 This is a schematic diagram illustrating the process of forming a 1×2 multi-mask optical switching network in a switch-and-select architecture network using the same mask in an embodiment of the present invention; Figure 6 This is a schematic diagram illustrating the process of forming a 2×2 multi-mask optical switching network using the same mask in an embodiment of the present invention; Figure 7 It is formed by repeatedly exposing the same mask on different exposure areas of the wafer. Figure 6 A flowchart of the cross-mask optical switching network structure is shown. Figure 8 These are several schematic diagrams of cross-mask optical splicing interfaces in embodiments of the present invention; Figure 9 This is a schematic diagram of the monitoring, calibration, and backup path of the peripheral interconnection channel in an embodiment of the present invention. Detailed Implementation

[0033] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] The design challenges of cross-mask planar optical switching networks lie not only in the physical splicing loss at the physical boundaries of the effective circuit patterns on the photomask between adjacent waveguides, but also in how to define cross-mask routing resources at the network architecture level, how to avoid additional cross-mask wiring and additional waveguide crossings (i.e., on a silicon photonic chip, two optical waveguides physically cross each other without direct connection, allowing optical signals to continue transmitting in their original directions), how to maintain local planar switching capability, how to perform path selection among multiple optical switching units, and how to reduce mask costs and layout complexity caused by multiple mask exposures. Simply adding external interconnect waveguides, fiber optic patch cords, additional couplers, or intermediate interconnect structures between multiple planar optical switching units often introduces additional insertion loss, crosstalk, area overhead, control complexity, and packaging complexity.

[0035] To this end, embodiments of the present invention provide a planar optical switching network and an optical switching chip based on multi-mask splicing, so as to realize an ultra-large-scale optical switching network spanning multiple photolithographic masks, saving mask resources, and is especially suitable for planar optical switching networks that require a large number of ports (such as 64×64, 128×128, 256×256 and above). By splitting a single large-size switching network into multiple mask-sized optical switching units and splicing them at the wafer level, the low cost and manufacturability of the ultra-large-scale optical switching network are achieved.

[0036] Furthermore, in multi-mask lithography, the use of different mask patterns for different regions significantly increases mask fabrication costs, layout verification costs, and process development complexity. For large-scale planar optical switching networks, if the port orientation, boundary channels, and interfaces across switch array submodules of each switch array submodule need to be designed separately, it is detrimental to low-cost manufacturing and large-scale replication. Therefore, in some embodiments of this application, the concept of mask reuse can be introduced during the planar optical switching network design stage, enabling the mask pattern of the same optical switching unit to be reused through translation, rotation, mirroring, etc., reducing mask fabrication costs, shortening the layout development cycle, and improving process consistency between different optical switching units. Moreover, aligned cross-mask interconnect channels and cross-mask optical splicing interfaces can be naturally formed between different exposure areas, allowing optical signals to cross mask boundaries with low loss, ensuring the overall performance of the spliced ​​network.

[0037] like Figure 1 The diagram shown is a schematic representation of a planar optical switching network based on multi-mask splicing provided in an embodiment of the present invention.

[0038] The planar optical switching network 100 of this embodiment includes: a plurality of mask-level optical switching units 10; the plurality of optical switching units 10 are disposed in the same substrate, or the same wafer region, or the same optical switching package; each optical switching unit 10 occupies an area within a mask exposure size (reticle-scale).

[0039] Different optical switching units 10 are interconnected via cross-mask optical interconnect channels (including...) Figure 1 The horizontal cross-reticle channel and the vertical cross-reticle channel) and the cross-mask optical splicing interface (including Figure 1 The internal splicing interfaces in the network are used for optical connection to form a complete large-scale planar optical switching network.

[0040] like Figure 1 As shown, the optical switching area within the exposure size range of each mask can include local input ports, local output ports, and local switching paths; it can also include a portion of internal routing resources, a portion of peripheral routing resources, a portion of switching stages, or a portion of switching matrices in a large-scale planar optical switching network.

[0041] Depending on different design requirements, each optical switching unit 10 can adopt one of the following two modes: (1) Independent Switching Unit Mode: In this mode, each optical switching unit 10 has complete local planar optical switching capabilities and can operate as an independent optical switching unit. The optical switching unit 10 includes complete local input ports, local output ports, and local switching paths, and can function as an independent local optical switching unit to complete local optical path switching within its corresponding area. At least one peripheral routing channel, boundary row, boundary column, reserved row, reserved column, redundant row, or redundant column in the optical switching unit 10 is configured as a cross-mask optical interconnect channel for interconnection with other units. Multiple locally complete optical switching units 10 can be combined into a larger-scale optical switching network through cross-mask interconnection.

[0042] The advantages of this model are: each unit can operate independently, giving the planar optical switching network 100 modular characteristics; multiplexing boundary / reserved channels into cross-unit interconnection channels allows for interconnection between units without increasing the floor plan area, improving resource utilization. Furthermore, interconnection between different optical switching units is easily expandable, offering excellent flexibility. Multiple locally complete switching units can be interconnected to form a larger-scale network while retaining the flexibility of each unit operating independently, facilitating hierarchical routing and fault isolation.

[0043] (2) Network Partitioning Mode: In this mode, the optical switching unit 10 serves as a partition within a complete large-scale planar optical switching network and does not necessarily constitute a complete optical switch itself. For example, an optical switching unit may contain only a portion of switching nodes, a portion of routing paths, a portion of switching stages, a portion of port groups, or a portion of control areas. Any optical switching unit can connect to other optical switching units by leading out some ports or connection nodes of its internal routing resources to horizontal and / or vertical peripheral routing resources, and then connecting them via cross-mask optical interconnect channels and cross-mask optical splicing interfaces to form a large-scale planar optical switching network with complete switching capabilities.

[0044] It should be noted that the partition may include any one or more of the following: sub-networks or sub-arrays divided according to topology, partial switching levels, partial routing areas, or specific port groups divided according to functional levels. This embodiment of the invention does not limit the specific partitions.

[0045] The advantage of this mode is that it can accurately reproduce arbitrary topological structures (such as Bene). The topology is divided into partitions (such as PILOSS, etc.), so that the topology size is not limited by the mask size, and each partition can be optimized individually according to functional requirements.

[0046] The two modes mentioned above are not mutually exclusive. In different areas of the same network, some units can adopt mode (1) and some units can adopt mode (2) to adapt to the traffic characteristics and functional requirements of different areas.

[0047] like Figure 2 The diagram shown is a structural schematic of a single optical switching unit in an embodiment of the present invention.

[0048] Each optical switching unit 10 includes internal routing resources and at least one peripheral routing resource. The internal routing resources are primarily located within the internal switching area of ​​the optical switching unit 10 and are used to perform local optical path switching within the corresponding optical switching unit 10, i.e., connecting local input ports to local output ports. The peripheral routing resources are located on one or more sides of the internal switching area, such as the upper boundary area, lower boundary area, left boundary area, right boundary area, layout edge area, reserved area, or redundant routing area of ​​the optical switching unit, and are configured as cross-mask optical interconnect channels for optically connecting one optical switching unit to an adjacent or non-adjacent optical switching unit.

[0049] It should be noted that, Figure 2The diagram only provides a simplified illustration of peripheral routing resources, where several horizontally or vertically extending straight waveguides represent peripheral routing resources or cross-mask optical interconnect channels. This does not imply that peripheral routing resources are limited to the quantity or form shown in the diagram. In actual implementation, the number of peripheral routing resources can be flexibly designed based on the number of ports in the optical switching unit, array size, target bandwidth, cross-unit connection requirements, redundancy requirements, monitoring requirements, and layout cabling constraints. For example, one, two, four, eight, or more peripheral interconnect channels can be set up in one or more boundary areas of the optical switching unit 10. Multiple sets of parallel channels, hierarchical channels, spare channels, or channels with non-uniform spacing can also be set up. The number of peripheral channels on different boundaries can be the same or different. The layout form of peripheral routing resources is not limited to straight waveguides; it can include curved waveguides, zigzag routes, multi-level routes, configurable switch paths, couplers, waveguide crossovers, mode conversion structures, or combinations thereof, and can be adaptively arranged according to port locations, splicing boundaries, and internal switching topology.

[0050] The peripheral routing resources may include upper boundary routing rows, lower boundary routing rows, left boundary routing columns, right boundary routing columns, boundary waveguides, reserved waveguides, spare waveguides, redundant waveguides, optical switch nodes, couplers, cross-connect structures, mode conversion structures, or combinations thereof. The peripheral routing resources can be optically connected to the internal routing resources via boundary optical switches, 2×2 optical switches, configurable couplers, fixed couplers, waveguide branches, combiners, or routing nodes, enabling optical signals to switch between the internal planar optical switching network and the cross-mask optical interconnect channel.

[0051] Among them, the waveguide channel in the peripheral routing resources simultaneously undertakes the functions of cross-mask interconnection, testing, monitoring, calibration, backup path, or fault bypass; the waveguide channel is connected to the optical power monitor, test port, calibration loop, backup optical path, or path verification circuit.

[0052] The 2×2 optical switch can be located in internal routing resources, at the connection node between internal and external routing resources, or in external routing resources. The 2×2 optical switch can be, for example, any one or more of the following: Mach-Zehnder interferometer optical switch, directional coupler optical switch, microring resonator optical switch, thermo-optical optical switch, electro-optical optical switch, phase change material optical switch, etc.

[0053] In some embodiments, at least a portion of the peripheral routing resources are permanently excluded from the local optical path switching function and used only as cross-mask optical interconnect channels.

[0054] In some embodiments, at least a portion of the peripheral routing resources can switch between local routing and cross-mask interconnect functions based on the control state. For example, when there are many local connection requests, some peripheral routing resources can be used as local routing resources; when there are many cross-unit connection requests, channel congestion, abnormal loss, or fault detour requirements, some peripheral routing resources can be reconfigured as cross-mask optical interconnect channels.

[0055] Each optical switching unit 10 may include a first port group, a second port group, and a cross-unit interconnection port group. The first port group can serve as a local input port group, the second port group can serve as a local output port group, and the cross-unit interconnection port group is connected to peripheral routing resources for connecting to cross-mask optical interconnection channels of adjacent or non-adjacent optical switching units.

[0056] In some embodiments, the cross-unit interconnection port group may be located at the upper boundary, lower boundary, left boundary, right boundary, or a combination thereof of the optical switching unit, and connected to the corresponding cross-unit interconnection port group in the adjacent optical switching unit through the cross-mask optical splicing interface.

[0057] In some embodiments, the first port group and the second port group may further include external I / O interfaces for realizing input-output coupling between the optical switching unit and external optical fibers, external photonic chips, photonic interposers, packaging substrates or system-level optical interconnect structures.

[0058] The external I / O interface may include an edge coupler, a grating coupler, a spot-size converter, a fiber array coupling interface, or a combination thereof. The external I / O interface is typically located on the outer boundary of the multi-mask array and is used for optical signal input or output facing the outside of the optical switching network. The external I / O interface primarily faces the outer boundary of the entire multi-mask optical switching network and is used to receive or output system-level optical signals.

[0059] In contrast to the external I / O interfaces, the cross-unit interconnect port group may include internal splicing interfaces. These internal splicing interfaces primarily face the internal boundaries between adjacent optical switching units and are used to connect cross-mask optical interconnect channels.

[0060] In some embodiments, multiple optical switching units 10 can be arranged in an M×K array configuration, where M and K are positive integers. For example, they can be arranged in 1×2, 2×1, 2×2, and other array configurations. Moreover, by reconfiguring routing resources near the cut boundary in the original topology as cross-mask interconnect channels, no additional dedicated interconnect waveguides are required, saving chip area and reducing design complexity. One-dimensional and two-dimensional array arrangements provide flexible scalability, allowing the selection of an appropriate splicing dimension based on the target network size. One-dimensional splicing is suitable for scenarios with smaller scaling requirements (such as doubling the number of ports), while two-dimensional splicing (M×K) can achieve significant scaling (such as increasing the number of ports by M×K times).

[0061] For example Figure 3 The diagram shown is a schematic diagram of the structure of two optical switching units spliced ​​into a 1×2 array in an embodiment of the present invention.

[0062] In this example, two optical switching units 10-1 and 10-2 are spliced ​​along the D1 direction (east-west direction) to form a 1×2 array. Each optical switching unit constitutes a complete network. The upper boundary routing line 31 and lower boundary routing line 32 of each optical switching unit are configured as cross-mask interconnect channels. The upper boundary routing line 31 and lower boundary routing line 32 extend along the D1 direction and can serve as inter-module optical interconnect channels in the D1 direction, providing lateral cross-mask optical interconnect paths between adjacent optical switching units. These boundary routing lines can be located in the upper or lower boundary region of the optical switching unit and interface with the corresponding boundary channels of adjacent optical switching units through splicing interfaces located at the mask boundary 30.

[0063] In this embodiment, the remaining routing resources within the optical switching unit can perform local permutation switching, that is, mapping local input ports to local output ports according to the required permutation. The upper boundary routing line 31 and lower boundary routing line 32 do not participate in or only partially participate in local permutation switching, but are primarily used for cross-mask interconnection. In one implementation, the upper boundary routing line 31 and lower boundary routing line 32 can be permanently used as cross-mask interconnection channels. In another implementation, the upper boundary routing line 31 and lower boundary routing line 32 can be connected to the internal switching network via optical switch nodes, configurable couplers, or routing nodes, thereby switching between local routing functions and cross-mask interconnection functions according to the control state.

[0064] The planar optical switching network based on multi-mask splicing provided in this invention divides a large-scale optical switching network into multiple sub-units limited by mask size, allowing each sub-unit to be manufactured using the same mask pattern through repeated exposure. This enables the construction of a large-scale optical switching network that far exceeds the area limitation of a single mask within the capabilities of existing photolithography equipment, while reducing mask manufacturing costs and improving manufacturing yield.

[0065] Reference Figure 4 , Figure 4 This illustrates a large-scale Bene system based on optical switching units in embodiments of the present invention. A schematic diagram of a network topology.

[0066] In this structure, a large-scale planar optical switching network is divided into two mask-level regions, 41 and 42, along the D1 direction by the mask boundary, forming a 1×2 multi-mask splicing structure. The two mask-level regions are connected through internal splicing interfaces and cross-mask optical interconnect channels, together constituting a complete large-scale optical network.

[0067] and Figure 3 The difference between the embodiments shown is that, Figure 4 In the embodiment shown, the networks of mask-level regions 41 and 42 do not have complete optical switching functions on their own. When the two are spliced ​​together, they form a large-scale planar optical switching network, which can be used as a large optical switch.

[0068] In this embodiment, the remaining routing resources not configured for cross-mask interconnection continue to function as an internal routing matrix within the unified large-scale optical switching network. Some boundary paths, reserved paths, redundant paths, or connection nodes derived from the internal routing network can permanently perform cross-mask interconnection functions, or they can switch between local routing functions and cross-mask interconnection functions through optical switch nodes, configurable couplers, or routing nodes.

[0069] It should be noted that, although Figure 3 and Figure 4 An example of a 1×2 array spliced ​​along the D1 direction is shown. Those skilled in the art will understand that... Figure 2 The optical switching unit 10 shown may also include peripheral routing resources located at the upper and lower boundaries, thereby supporting cross-mask optical interconnects along the D2 direction (north-south direction). Therefore, multiple optical switching units can also be arranged in other array configurations, and larger-scale multi-mask optical switching networks can be realized by utilizing the peripheral interconnect resources at the corresponding boundaries. This embodiment of the invention does not limit the scope of the invention.

[0070] When multiple optical masks are stitched together, the boundary interconnect channels of adjacent optical switching units are optically connected at the mask boundaries via cross-mask optical splicing interfaces. This allows optical signals to be coupled from the internal routing network of one optical switching unit to its boundary interconnect channel, and then via this boundary interconnect channel into adjacent, intermediate, or target optical switching units. In this way, the present invention can achieve cross-submodule, cross-mask, cross-chip, or wafer-level optical path extension while retaining local planar arrangement switching capabilities.

[0071] Unlike traditional planar optical switching networks designed for a single mask area, this invention introduces cross-mask interconnect design during the optical switching network architecture design phase. By configuring peripheral rows, peripheral columns, boundary channels, reserved channels, or redundant channels in the planar switching topology as cross-mask optical interconnect channels, or by routing some internal routing nodes of a large-scale switching matrix to these channels, multiple planar optical switching units that were originally limited to the size of a single mask can be spliced ​​together to form a larger-scale multi-mask optical switching network.

[0072] To further reduce the cost of mask manufacturing and improve the process consistency between different optical switching units, symmetrical designs can be adopted in some embodiments. For example, the internal planar optical switching network, peripheral routing resources, input / output port groups, and cross-mask optical interconnect channels of the optical switching unit 10 may have any one or more of the following characteristics: central symmetry, rotational symmetry, mirror symmetry, and translational periodicity.

[0073] The aforementioned symmetrical design allows the same photomask pattern to be reused in different exposure areas through rotation, mirroring, and other operations. Multiple optical switching units can be formed through translation, mirroring, rotation, or combinations thereof, eliminating the need to fabricate a separate photomask for each area. The peripheral interconnect channels and splicing interfaces between adjacent optical switching units are aligned at the photomask boundaries, achieving cross-photomask optical interconnection. This structural design significantly reduces photomask manufacturing costs and shortens the layout development cycle. Furthermore, because it uses the same master copy, the process consistency between different units is extremely high, which is beneficial for optical path alignment and performance uniformity after splicing.

[0074] For example, to form a 1×2 or 2×1 multi-mask topology, a large-scale planar optical switching topology can be first divided into two mask regions along a mask boundary, and then each region can be mapped to its corresponding layout region. The basic mask pattern can satisfy mirror symmetry, rotation multiplexing, or boundary interface matching relationships in the splicing direction, enabling the two regions to form a continuous optical path connection at their internal boundaries through cross-mask channels. It should be noted that this implementation does not preclude each region from having a local switching path simultaneously.

[0075] Figure 5 This diagram illustrates the process of forming a 1×2 multi-mask optical switching network in a switch-and-select architecture network using the same mask.

[0076] Reference Figure 5When forming a 1×2 multi-mask optical switching network, a first optical switching unit 101 can be formed by first exposure using a mask pattern, and then a second optical switching unit 102 can be formed by translating, mirroring, or rotating the same mask pattern 180°. Since the first optical switching unit 101 and the second optical switching unit 102 have complementary boundary channels and aligned cross-mask optical splicing interfaces in the splicing direction, a continuous optical interconnection path can be formed at the mask boundary 30 between them. For example, the right boundary channel of the first optical switching unit 101 can be aligned with the left boundary channel of the second optical switching unit 102 to form a horizontal splicing structure; or the lower boundary channel of the first optical switching unit 101 can be aligned with the upper boundary channel of the second optical switching unit 102 to form a vertical splicing structure.

[0077] Planar optical switching topologies suitable for the aforementioned 1×2 or 2×1 mask multiplexing designs can include optical switching networks with uniaxial mirror symmetry, boundary periodicity, or boundary matching that can be achieved through port rearrangement. Examples include switch-and-select networks, N-planar networks, double-layer optical switching networks, and dilated bezels. Network, PILOSS-like network, Bene -like networks or other multi-level planar optical switching networks can meet the port alignment and boundary interconnection requirements between adjacent mask exposure areas through port rearrangement, boundary channel reservation, redundant row / column settings, or internal routing-level symmetry design.

[0078] For example, to form a 2×2 multi-mask implementation, a two-dimensional planar optical switching topology, such as a PILOSS or PILOSS-like network, can be divided into four mask regions along the horizontal and vertical mask boundaries. These four mask regions can respectively carry some of the switching nodes, some routing channels, some port groups, and some peripheral routing resources from the original topology, and are connected across mask optical interconnect channels in the east-west and north-south directions via internal splicing interfaces.

[0079] In some embodiments, the basic reticle pattern suitable for a 2×2 array can be designed to have central symmetry, 90° rotational symmetry, 180° rotational symmetry, quadruple rotational multiplexing, or a combination thereof. With this design, the same mask pattern can be repeatedly exposed in different exposure areas at different orientations such as 0°, 90°, 180°, and 270°, thereby forming four optical switching units in the 2×2 array. Since the basic mask pattern has corresponding peripheral interconnect channels and splicing interfaces in all four boundary directions, after each optical switching unit is rotated 90°, 180°, or 270°, its east-west and north-south channels can still be aligned at adjacent mask boundaries.

[0080] In a 2×2 array, the first, second, third, and fourth mask regions can be formed from the same mask pattern in ways such as 0°, 90°, 180°, 270°, mirroring, or translation. Regions with different orientations have aligned peripheral interconnect channels and cross-mask optical splicing interfaces at adjacent internal boundaries, thus forming a two-dimensional multi-mask switching matrix.

[0081] like Figure 6 The diagram shown is a schematic representation of the process of forming a 2×2 multi-mask optical switching network using the same mask in an embodiment of the present invention.

[0082] First, in the first mask region, an optical switching unit 1 is formed using a mask pattern with a 0° orientation. Then, in the second mask region, an optical switching unit 2 is formed by mirroring the mask in the first mask region vertically. Next, in the third mask region, an optical switching unit 3 is formed by mirroring the mask in the first mask region horizontally. Finally, in the fourth mask region, an optical switching unit 4 is formed by mirroring the mask in the third mask region vertically.

[0083] Compared to 1×2 or 2×1 topology implementations, 2×2 topology implementations not only require alignment of boundary interfaces in a single direction, but also require that cross-mask channels in both horizontal and vertical directions be connected to the corresponding internal splicing interfaces of adjacent regions. For example... Figure 6 As shown, at the first splicing boundary 301, the boundary interfaces of optical switching unit 1 and optical switching unit 3, and optical switching unit 2 and optical switching unit 4 are aligned; at the second splicing boundary 302, the boundary interfaces of optical switching unit 1 and optical switching unit 2, and optical switching unit 3 and optical switching unit 4 are aligned.

[0084] Furthermore, when forming an N×M multi-mask array, the aforementioned 1×2, 2×1, or 2×2 mask multiplexing units can be used as basic splicing units. Exposure can be repeated in multiple exposure areas through translation, mirroring, 90° rotation, 180° rotation, 270° rotation, or combinations thereof. For a one-dimensional array extending only in one direction, uniaxial mirror symmetry and unidirectional peripheral interconnect channels can be primarily relied upon. For a two-dimensional array extending in two directions, a basic mask pattern with both east-west and north-south peripheral interconnect resources, satisfying central or rotational symmetry, is preferred. In this way, the same mask can be reused in different array locations, forming a larger-scale N×M multi-mask optical switching network.

[0085] To further explain in detail the process of forming the cross-mask optical switching network structure Figure 7 This demonstrates the formation of wafers by repeatedly exposing different exposure areas using the same mask. Figure 6 The flowchart of the cross-mask optical switching network structure shown includes the following steps:

[0086] Step 1: Expose the upper left region R1 of the wafer or substrate using a mask pattern; Step 2: Mirror the mask in the upper left area vertically and then translate it to the upper right area R2, then expose the upper right area R2. Step 3: Mirror the mask in the upper left area horizontally and then move it to the lower left area R3, then expose the lower left area R3. Step 4: Mirror the mask in the lower left area vertically and then move it to the lower right area R4, then expose the lower right area R4.

[0087] The final result is a 2×2 array consisting of 4 optical switching units, with the external I / O interface located at the outer edge and the internal splicing interface located between adjacent optical switching units.

[0088] In this embodiment of the invention, the cross-mask optical splicing interface can be located between adjacent photolithography exposure areas, adjacent optical switching units, adjacent photonic chips, or adjacent optical switching chips. It is used to reduce insertion loss, reflection, and crosstalk caused by mask splicing errors, lateral offsets, longitudinal offsets, angular deviations, interlayer alignment errors, or packaging assembly errors, and to achieve low-loss optical connections between cross-unit optical interconnect channels. Specifically, the cross-mask optical splicing interface can be located at the end of the cross-mask optical interconnect channel, at the splicing boundary of adjacent optical switching units, at the boundary coupling region of peripheral routing resources, or in the transition region between the internal splicing interface and the cross-mask optical interconnect channel. The cross-mask optical splicing interface can be designed as an optical connection structure with higher tolerance to lateral offsets, longitudinal offsets, angular deviations, etching linewidth deviations, exposure splicing deviations, interlayer overlay errors, or wafer-level assembly errors.

[0089] The cross-mask optical splicing interface can be implemented in various ways at the physical level, such as including at least one of the following structures: direct waveguide splicing structure, widened waveguide, tapered waveguide, adiabatic mode extender, multimode waveguide, multimode interference waveguide, self-imaging waveguide segment, shallowly etched wide ridge waveguide, subwavelength grating mode converter, effective refractive index gradient structure, multilayer waveguide transition structure, directional coupler, adiabatic coupler, vertical coupler, spot-size converter, grating-assisted coupler, polymer optical bridge, silicon nitride optical bridge, tilted waveguide interface, bent low-reflection interface, redundant parallel splicing interface, or a combination thereof.

[0090] Because photolithographic splicing may introduce alignment errors (lateral offset, longitudinal offset, angular deviation, etc.), directly splicing waveguides will result in significant insertion loss and reflection. By enlarging the optical mode size or using a gradient transition through the above structure, the sensitivity of the optical field to boundary offsets can be reduced, greatly reducing the insertion loss of the optical interconnect channel across the mask.

[0091] Reference Figure 8 , Figure 8 Several schematic diagrams of cross-mask optical splicing interfaces are shown in embodiments of the present invention. Among them: Figure 8 (a) is a schematic diagram of a cross-mask optical splicing interface formed by a tapered waveguide and a multimode waveguide region. This structure is used to expand the optical mode size near the mask boundary and improve the tolerance of lateral splicing errors.

[0092] In this example, the cross-mask optical splicing interface includes a multimode splicing structure formed by a tapered gradient waveguide and a multimode region. The ordinary single-mode waveguide in the cross-mask optical interconnect channel gradually widens near the mask boundary via a first tapered gradient segment, gradually expanding the originally strongly constrained single-mode optical field into a larger optical mode. Following the first tapered gradient segment, a multimode waveguide region, a multimode interference waveguide region, a self-imaging waveguide segment, or other wide waveguide mode extension regions can be connected. The multimode region can be configured to span the mask boundary, or it can be separately located on both sides of the mask boundary and joined at the boundary.

[0093] exist Figure 8 In the structure shown in (a), the optical signal enters the first tapered transition section from the ordinary single-mode waveguide of the first optical switching unit, and then enters the wide waveguide or multimode waveguide region via this tapered transition section. Because the wide waveguide region has a larger effective mode area, the sensitivity of the optical field to lateral offset, boundary splicing errors, and lithographic splicing alignment deviations is reduced. After the optical signal crosses the mask boundary, it can gradually narrow through the second tapered transition section and return to the ordinary single-mode waveguide mode in the second optical switching unit. The first and second tapered transition sections can be linear tapered transition structures, exponential tapered transition structures, spline curve tapered transition structures, multi-level tapered transition structures, segmented adiabatic tapered transition structures, subwavelength-assisted tapered transition structures, or other adiabatic mode extension structures. The multimode region can utilize multimode propagation, self-imaging effects, mode extension effects, or mode averaging effects to improve the manufacturing tolerance and alignment tolerance of the cross-mask optical interconnect channel. This type of structure, which combines a tapered gradient structure with a multimode region, can serve as an embodiment of an optical splicing interface across mask plates, but the present invention is not limited to this structure.

[0094] Figure 8 (b) is a schematic diagram of a shallow-etched wide-ridge waveguide cross-mask optical splicing interface. This structure reduces mode mismatch and scattering loss by lowering the transverse and vertical optical field constraints of the waveguide near the mask boundary.

[0095] In this example, the cross-mask optical splicing interface includes a shallowly etched wide-ridge waveguide. The deeply etched, highly constrained waveguide in the cross-mask optical interconnect channel gradually or segmentally transitions into a shallowly etched wide-ridge waveguide near the mask boundary. The shallowly etched wide-ridge waveguide may include a wide-ridge region, a shallowly etched slab region, a ridged waveguide transition section, and a mode conversion section connecting to a conventional single-mode waveguide. By reducing the refractive index constraint in the lateral and vertical directions of the waveguide, the shallowly etched wide-ridge waveguide can increase the optical mode size and reduce mode mismatch at the mask boundary caused by linewidth deviation, etching depth deviation, or splicing offset.

[0096] exist Figure 8In the structure shown in (b), the deeply etched single-mode waveguide in the first optical switching unit transitions to a shallowly etched wide-ridge waveguide near the splicing boundary. This shallowly etched wide-ridge waveguide spans the mask boundary or is positioned on either side of the boundary and directly spliced ​​at the boundary. The optical signal exhibits a large lateral optical field distribution and low boundary scattering sensitivity within the shallowly etched wide-ridge waveguide region, thus reducing insertion loss caused by boundary roughness, etching deviation, exposure splicing deviation, and lateral offset. After crossing the mask boundary, the shallowly etched wide-ridge waveguide can transition back to the deeply etched single-mode waveguide in the second optical switching unit via a reverse mode conversion section. This structure is particularly suitable for boundary mode extension from deeply etched strip waveguides to shallowly etched wide-ridge waveguides in silicon photonics platforms, and can also be applied to low-constraint boundary splicing structures in silicon nitride, lithium niobate, polymer, or other integrated photonic material platforms.

[0097] Figure 8 (c) is a schematic diagram of a multi-layer waveguide transition type cross-mask optical splicing interface. This structure achieves optical bridge-type cross-mask interconnection at the mask boundary by transitioning the optical signal from the first waveguide layer to the second waveguide layer with a larger mode size or higher alignment tolerance.

[0098] In this example, the cross-mask optical splicing interface includes a multi-layer waveguide transition structure. The optical signal can first be coupled from a first waveguide in a first waveguide layer to a second waveguide in a second waveguide layer. Subsequently, the second waveguide layer carries the cross-mask optical interconnect at mask boundaries, core boundaries, or unit boundaries. Finally, the optical signal is coupled from the second waveguide layer back to the target waveguide in the first waveguide layer. The first waveguide layer can be a silicon waveguide layer, a silicon nitride waveguide layer, a lithium niobate waveguide layer, a III-V waveguide layer, or other high refractive index difference waveguide layers. The second waveguide layer can be a silicon nitride waveguide layer, a polymer waveguide layer, a silicon oxide waveguide layer, a low refractive index difference waveguide layer, a wide-mode-field waveguide layer, or other optical bridging layers with a large optical mode size.

[0099] exist Figure 8In the structure shown in (c), the optical signal in the first optical switching unit is first coupled from the first waveguide layer to the second waveguide layer via a vertical adiabatic coupler, a directional coupler, an interlayer gradient coupler, a spot size converter, or a grating-assisted coupler. The optical bridge waveguide in the second waveguide layer has a large mode size and high alignment tolerance, and crosses or connects to adjacent optical switching units at the mask boundary. Subsequently, the optical signal is coupled back from the second waveguide layer to the first waveguide layer in the adjacent optical switching unit via another interlayer coupling structure. In this way, the larger mode size of the second waveguide layer can be used to reduce the losses caused by boundary alignment errors, interlayer overlay errors, chip assembly errors, and mask splicing errors. This structure can also be used for cross-unit interconnection between different material platforms, such as silicon waveguide to silicon nitride optical bridge, silicon waveguide to polymer optical bridge, silicon waveguide to low refractive index difference optical bridge, or heterogeneous integrated optical bridge between different photonic chips.

[0100] It should be noted that the above three cross-mask optical splicing interfaces can be used individually or in combination. For example, Figure 8 The tapered waveguide and multimode region shown in (a) can be compared with... Figure 8 The shallow-etched wide-ridge waveguide combination shown in (b) can simultaneously improve the lateral offset tolerance and etching error tolerance; Figure 8 The multilayer waveguide transition structure shown in (c) can be used with Figure 8 The combination of mode extension structures shown in (a) can realize a cross-mask optical bridge with a larger mode size.

[0101] Furthermore, any of the above structures can be combined with monitoring ports, splitters, calibration ports, redundant parallel splicing interfaces, spare waveguides, or fault bypass paths to improve the testability, calibrability, and fault tolerance of multi-mask optical switching networks.

[0102] like Figure 9 The diagram shown is a schematic representation of the monitoring, calibration, and backup path of the peripheral interconnection channel in an embodiment of the present invention.

[0103] This example illustrates a cross-mask optical interconnect channel (including a lateral optical interconnect channel 91 and a longitudinal optical interconnect channel 92), an optical power monitor 901, a beam splitter 902, a test / calibration port 903, an optional calibration loop 93, a spare cross-mask channel 94, and a selection channel for the primary channel. Figure 9 The lateral optical interconnect channel 91 or the spare channel (in the middle) Figure 9 The backup cross-mask channel 94 includes a first optical switch node 904-1 and a second optical switch node 904-2. The test / calibration port 903 may include independent test and calibration ports, or a port that combines test and calibration functions.

[0104] In some embodiments, some peripheral interconnect channels may be further connected to the optical power monitor 901, the beam splitter 902, the test port, the calibration port, or the calibration loop. The peripheral interconnect channels may be cross-mask optical interconnect channels located in the boundary region, peripheral row, peripheral column, reserved channel, or redundant channel of the optical switching unit. By setting up monitoring and calibration structures near such channels, online detection, path verification, link loss calibration, crosstalk monitoring, fault detection, or automatic calibration of the cross-mask optical connection status between adjacent optical switching units can be performed.

[0105] In some embodiments, a beam splitter or beam splitter coupler can be disposed on the cross-mask optical interconnect channel. The beam splitter couples a small portion of the optical power from the main optical path and directs this portion of the optical signal to an optical power monitor. The optical power monitor can be an on-chip photodetector, a germanium photodetector, a III-V photodetector, a thermophotodetector, an external detection port, or a combination thereof. By detecting this split optical power, the transmission power, insertion loss variation, connection status, and long-term drift information of the cross-mask optical interconnect channel can be obtained.

[0106] In some embodiments, the cross-mask optical interconnect channel can be connected to a test port or a calibration port. The test port can be used to inject test optical signals during chip testing, wafer-level testing, post-packaging testing, or system operation. The calibration port can be used to import calibration optical signals of known power, known wavelength, or known modulation format, and to calibrate the loss, channel equalization parameters, switching status, and splicing interface quality of the cross-mask optical interconnect channel by monitoring output power, crosstalk power, or reflected power.

[0107] In some embodiments, a portion of the peripheral interconnect channels can form a calibration loop. The calibration loop may include cross-mask optical interconnect channels, return channels, splitters, optical power monitors, and one or more configurable optical switch nodes. By propagating a test optical signal along the calibration loop and returning it to the monitoring port, the controller can obtain the round-trip loss, channel consistency, connection correctness, and relative loss differences between different paths. This calibration result can be further used to correct routing tables, update path selection weights, adjust optical switch states, compensate for inter-channel loss differences, or identify abnormal splicing interfaces.

[0108] In some embodiments, some peripheral interconnect channels can serve as backup channels or fault bypass paths. A primary cross-mask optical interconnect channel and at least one backup cross-mask optical interconnect channel can be configured between two adjacent optical switching units. The primary and backup channels can be connected to internal routing resources via 2×2 optical switches, M×N optical switches, configurable couplers, selectors, MEMS optical switches, thermo-optic switches, electro-optic switches, or phase-change material optical switches, respectively. When the loss of the primary cross-mask channel is too high, the splicing interface is abnormal, the optical power is below a preset threshold, the crosstalk is above a preset threshold, the switching unit fails, or the channel is occupied by other connection requests, the controller can select a backup cross-mask channel as an alternative path.

[0109] In some embodiments, the controller can automatically determine the status of cross-mask optical interconnect channels based on feedback signals from the optical power monitor. If the insertion loss of a channel exceeds a preset threshold, or its output power is lower than a preset threshold, the controller can mark the channel as an abnormal channel and reduce its priority in subsequent routing or remove it from the set of available paths. If the monitoring results of the backup channel meet preset conditions, the controller can switch the input optical signal from the original primary channel to the backup channel, thereby achieving fault bypass or dynamic rerouting.

[0110] In some embodiments, the controller can simultaneously consider parameters such as path length, insertion loss, channel occupancy status, monitoring power, crosstalk level, temperature drift, historical fault records, and service priority to select cross-mask optical interconnect paths. In this way, peripheral interconnect channels can be used not only for optical connections between adjacent optical switching units, but also for monitoring, testing, calibration, backup path switching, and fault recovery, thereby improving the testability, maintainability, yield, and system reliability of multi-mask optical switching networks.

[0111] In some embodiments, the monitoring port, test port, and backup channel can be used in combination with the aforementioned cross-mask optical splicing interface. For example, placing a beam splitter and optical power monitor near the splicing interface composed of a tapered waveguide and a multimode region allows for real-time monitoring of the transmission loss of the splicing interface; placing a redundant parallel splicing interface near the shallowly etched wide-ridge waveguide splicing structure allows for switching to another wide-ridge splicing path when one wide-ridge splicing path is abnormal; placing a test port and return loop in the multilayer waveguide optical bridge structure allows for calibration of interlayer coupling efficiency, optical bridge loss, and mask boundary connection quality.

[0112] Through the above structure, the present invention enables online monitoring, automatic calibration, and fault bypass of cross-cell interconnect channels in large-scale multi-mask optical switching networks. Compared to structures that only provide fixed cross-mask channels, it can further improve the stability and availability of multi-mask optical switching networks under conditions of manufacturing errors, packaging errors, temperature drift, device aging, and local channel failures.

[0113] The planar optical switching network and optical switching chip based on multi-mask splicing provided in this invention introduce cross-mask interconnect channels and cross-mask optical splicing interfaces into the planar optical switching network architecture, enabling multiple mask-level optical switching units to be spliced ​​within the same substrate or package to form a complete large-scale planar optical switching network. Thus, the planar optical switching network, originally limited by the exposure size of a single mask, can be expanded by splicing multiple local complete optical switching units, or it can be implemented as a single complete switching matrix by being split into multiple mask exposure size regions and then combined.

[0114] The planar optical switching network based on multi-mask splicing provided in this invention can also be used to form optical switching packages, optical switching modules, or optical switching systems. The optical switching system may include the aforementioned planar optical switching network based on multi-mask splicing and a controller. The controller is used to configure routing states and can also control the switching of mask-level optical switching units in the planar optical switching network between different operating states or different optical path switching states. The controller can be any electronic, electrical, or computing device capable of generating, regulating, transmitting, and / or managing control signals. For example, the controller may include an MCU (Microcontroller Unit), an FPGA (Field-Programmable Gate Array), a DSP (Digital Signal Processor), a DAQ (Data Acquisition Card), a computer control system, or any combination thereof.

[0115] The optical switching system can be used for data center optical path switching, artificial intelligence computing cluster interconnection, optical computing interconnection, chip-to-chip optical interconnection, on-chip optical switching, wafer-level optical switching, large-port-count optical switching nodes, or combinations thereof.

[0116] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0117] In this application's embodiments, "multiple" refers to two or more. The descriptions of "first," "second," etc., appearing in this application's embodiments are merely illustrative and for distinguishing the described objects; they have no order and do not indicate a specific limitation on the number of devices in this application's embodiments, nor do they constitute any limitation on the embodiments of this application.

[0118] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A planar optical switching network based on multi-mask splicing, characterized in that, include: Multiple mask-level optical switching units; The plurality of optical switching units are disposed in the same substrate, or the same wafer region, or the same optical switching package; Each of the optical switching units occupies an area within a mask exposure size range and includes internal routing resources and at least one peripheral routing resource; Different optical switching units are optically connected through cross-mask optical interconnect channels and cross-mask optical splicing interfaces, forming a complete large-scale planar optical switching network.

2. The planar optical switching network based on multi-mask splicing according to claim 1, characterized in that, The optical switching unit has complete local planar optical switching capabilities and can operate as an independent optical switching unit.

3. The planar optical switching network based on multi-mask splicing according to claim 2, characterized in that, At least one peripheral routing channel, boundary row, boundary column, reserved row, reserved column, redundant row, or redundant column in the optical switching unit is configured as the cross-mask optical interconnect channel, so that the multiple optical switching units are combined into the complete large-scale planar optical switching network through cross-regional routing.

4. The planar optical switching network based on multi-mask splicing according to claim 1, characterized in that, The optical switching unit is a partition in the complete large-scale planar optical switching network. The partition includes any one or more of the following: sub-networks or sub-arrays divided according to topology, partial switching levels, partial routing areas, or specific port groups divided according to functional levels.

5. The planar optical switching network based on multi-mask splicing according to claim 4, characterized in that, The optical switching unit includes some switching nodes, some routing paths, some switching stages, some port groups, or some control areas; any one of the optical switching units leads some ports or connection nodes of internal routing resources to external routing resources, and then connects with other optical switching units through the cross-mask optical interconnect channel and the cross-mask optical splicing interface to form the complete large-scale planar optical switching network.

6. The planar optical switching network based on multi-mask splicing according to claim 1, characterized in that, The peripheral routing resources are located in the edge region, boundary region, reserved region, or redundant routing region of the optical switching unit; The peripheral routing resources include one or more waveguide channels, routing rows, routing columns, boundary waveguides, spare waveguides, redundant waveguides, optical switch nodes, couplers, cross-connect structures, or mode conversion structures; The peripheral routing resources are optically connected to the internal routing resources through boundary optical switches, 2×2 optical switches, configurable couplers, fixed couplers, waveguide branches, beam combiners, or routing nodes, enabling optical signals to switch between the internal planar optical switching network and the cross-unit optical interconnect channel.

7. The planar optical switching network based on multi-mask splicing according to claim 6, characterized in that, The waveguide channels in the peripheral routing resources simultaneously serve as cross-mask interconnects, testing, monitoring, calibration, backup paths, or fault bypass functions; the waveguide channels are connected to optical power monitors, test ports, calibration loops, backup optical paths, or path verification circuits.

8. The planar optical switching network based on multi-mask splicing according to claim 6, characterized in that, The 2×2 optical switch is located in the internal routing resources, at the connection node between the internal routing resources and the external routing resources, or in the external routing resources.

9. The planar optical switching network based on multi-mask splicing according to claim 6, characterized in that, The 2×2 optical switch includes any one or more of the following: Mach-Zehnder interferometer optical switch, directional coupler optical switch, microring resonator optical switch, thermo-optical optical switch, electro-optical optical switch, and phase change material optical switch.

10. The planar optical switching network based on multi-mask splicing according to claim 1, characterized in that, The plurality of optical switching units are arranged in an M×K array, where M and K are positive integers.

11. The planar optical switching network based on multi-mask splicing according to claim 10, characterized in that, The internal planar optical switching network, peripheral routing resources, input / output port groups, and cross-mask optical interconnect channels of the optical switching unit all have any one or more of the following characteristics: central symmetry, rotational symmetry, mirror symmetry, and translational periodicity. The multiple optical switching units arranged in the M×K array are formed by repeatedly exposing the same mask through one or more operations such as translation, mirroring, and rotation.

12. The planar optical switching network based on multi-mask splicing according to claim 1, characterized in that, The cross-mask optical splicing interface is located between adjacent photolithography exposure areas, adjacent optical exchange units, adjacent photonic cores, or adjacent optical exchange chips.

13. The planar optical switching network based on multi-mask splicing according to claim 1, characterized in that, The cross-mask optical splicing interface includes at least one of the following structures: direct waveguide splicing structure, widened waveguide, tapered waveguide, adiabatic mode extender, multimode waveguide, multimode interference waveguide, shallowly etched wide ridge waveguide, subwavelength grating mode converter, effective refractive index gradient structure, multilayer waveguide transition structure, directional coupler, adiabatic coupler, vertical coupler, spot size converter, grating-assisted coupler, polymer optical bridge, silicon nitride optical bridge, tilted waveguide interface, and redundant parallel splicing interface.

14. The planar optical switching network based on multi-mask splicing according to claim 13, characterized in that, The cross-mask optical splicing interface includes a splicing structure formed by a combination of tapered gradient waveguides and multimode waveguides.

15. The planar optical switching network based on multi-mask splicing according to claim 13, characterized in that, The cross-mask optical splicing interface includes a shallowly etched wide ridge waveguide; the deeply etched high-constraint waveguide in the cross-mask optical interconnect channel transitions into the shallowly etched wide ridge waveguide near the boundary; the shallowly etched wide ridge waveguide is arranged across the mask boundary, or is arranged on both sides of the boundary and directly spliced ​​at the boundary.

16. The planar optical switching network based on multi-mask splicing according to claim 13, characterized in that, The cross-mask optical splicing interface includes a multi-layer waveguide transition structure; Optical signals are coupled from a first waveguide layer to a second waveguide layer, which is a silicon nitride waveguide layer, a polymer waveguide layer, or a low refractive index difference waveguide layer, and has an optical mode size larger than that of the first waveguide layer; the second waveguide layer carries cross-mask optical interconnects at the mask boundary, and then couples the optical signals back to the first waveguide layer.

17. An optical switching chip, characterized in that, Includes a planar optical switching network based on multi-mask splicing as described in any one of claims 1-16.

18. An optical switching system, characterized in that, Includes a planar optical switching network based on multi-mask splicing as described in any one of claims 1-16 and a controller; The controller is used to configure the routing status.

Images