Multi-mode fusion-based micro communication card structure design method

Abstract

This invention relates to the field of communication technology, and more particularly to a design method for a micro communication card structure based on multi-standard integration. The method includes: constructing control logic; substrate wiring design; device layout modeling; firmware logic configuration; and constructing a packaging structure model. This invention integrates chip selection control logic, circuit layout, and packaging structure model into a unified structure, creating quantifiable constraints between structural, electrical, and control parameters. Furthermore, it utilizes a virtual simulation environment to verify the firmware configuration. Simultaneously, by constructing a three-dimensional model of the packaging structure, it ensures coordination between chip density, packaging thickness, and structural support areas, thereby reducing localized heat accumulation and structural stress concentration. This effectively solves the problems of poor communication timing consistency and decreased signal integrity caused by differences in signal propagation paths and enhanced electrical coupling during the integration of multiple communication units.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a design method for a micro communication card structure based on multi-standard fusion. Background Technology

[0002] With the rapid development of IoT terminals, miniaturized smart devices, and embedded communication modules, the requirements for communication access capabilities of terminal devices are gradually evolving from single network access to multi-network compatibility and dynamic access. Achieving multi-network identity recognition within a limited structural space has become an important development trend for micro communication modules. However, under the condition of strictly limited card size, the integration of multiple communication units can easily lead to increased differences in signal paths, enhanced electrical coupling, and limited structural layout, making it difficult to guarantee communication timing consistency. At the same time, frequent changes in different network states can easily affect the stability of communication links, resulting in decreased communication reliability and difficulty in maintaining network access continuity. This poses a challenge to achieving stable communication access capabilities for micro communication modules under high-density integration conditions.

[0003] Existing micro communication cards are typically based on a single communication unit structure or integrate multiple communication units through simple parallel connection. In the structural design process, the focus is mainly on achieving electrical conduction, while lacking systematic constraints on the consistency of signal propagation paths, electrical interference coupling relationships, and communication control coordination relationships. This results in differences in signal propagation delays between different communication units, causing inconsistent response times of control commands among the communication units. This can easily lead to data transmission interruptions or identification anomalies during communication switching. At the same time, under the condition of limited structural space, the dense layout of components enhances the parasitic capacitance and parasitic inductance effects, further affecting signal integrity and communication stability. This makes it difficult for the communication unit selection process to achieve a stable response according to changes in communication status, thereby reducing the overall communication reliability and network access stability of the micro communication card. Summary of the Invention

[0004] To address this, the present invention provides a micro communication card structure design method based on multi-standard fusion. This method overcomes the problems of poor communication timing consistency and reduced signal integrity caused by differences in signal propagation paths and enhanced electrical coupling during the integration of multiple communication units in the prior art by constructing a collaborative constraint design mechanism among structural parameters, electrical connection relationships, and communication control relationships.

[0005] To achieve the above objectives, this invention provides a method for designing a micro communication card structure based on multi-standard fusion, comprising: Based on the functional requirements of the multi-standard integrated micro communication card, an MCU is used as the core control unit to connect several surface-mount SIM chips and matching components. A virtual file system interface is added between the MCU and the main control chip of the terminal device to obtain the circuit schematic and the chip selection control logic built based on the circuit schematic. Based on the circuit schematic, and combined with the physical dimensions and contact positions of a standard SIM card, the signal lines connecting the MCU to each chip are made of equal length and isolated during the substrate wiring process to obtain the printed circuit board design. Based on the printed circuit board design drawing, the MCU, the surface mount SIM chip, and the matching components are arranged at designated positions on the board to obtain a semi-finished component layout model of the micro communication card. Firmware is built based on the chip selection control logic and the semi-finished component layout model, and the firmware is configured in the virtual simulation environment of the MCU to obtain firmware logic configuration results. Based on the printed circuit board, the chip selection control logic, and the firmware logic configuration results, a three-dimensional model of the multi-standard integrated packaging structure is constructed to obtain the packaging structure design results.

[0006] Furthermore, the process of constructing chip selection control logic based on the circuit schematic includes: Based on the connection topology between the MCU and each of the patch SIM chips in the circuit schematic, a multi-channel priority decision framework is established, an initial priority weight is preset for the operator network corresponding to each patch SIM chip, and a dynamic priority mapping table based on service type is established. Based on the virtual file system interface defined in the circuit schematic, an instruction set for transmitting real-time network quality parameters of each of the patch SIM chips is defined therein; Based on the signal connection relationship between the MCU and each of the patch SIM chips in the circuit schematic, a periodic polling mechanism is constructed to collect network quality data of each of the patch SIM chips through the virtual file system interface, and then perform filtering and normalization processing. Configure a fuzzy comprehensive evaluation algorithm to calculate the access suitability score of each of the patch SIM chips based on the network quality data, service type priority, and initial priority weight; Based on the access suitability score, combined with the preset handover threshold and hysteresis comparison mechanism, the optimal network access decision is generated and mapped to the corresponding patch SIM chip selection instruction. A buffering and retransmission mechanism designed to keep the data link uninterrupted during handover; The chip selection control logic is constructed by integrating the multi-channel priority decision framework, the instruction set, the periodic polling mechanism, the fuzzy comprehensive evaluation algorithm, the patch SIM chip selection instruction, and the caching and retransmission mechanism.

[0007] Furthermore, the process of obtaining the printed circuit board design drawing based on the circuit schematic includes: Based on the length, width, and thickness constraints of a standard SIM card, the external boundary dimensions of the printed circuit board are determined to obtain a board external constraint model. According to the standard SIM card contact position specification, the communication contact area and contact lead-out path are defined on the substrate shape constraint model to obtain the contact layout model. Based on the connection relationship between the MCU and each of the surface mount SIM chips in the circuit schematic, the clock signal lines, reset signal lines and data signal lines from the MCU to each surface mount SIM chip are designed to be of equal length, so that the length deviation of each corresponding signal line is within a preset error range, so as to obtain an equal length signal wiring model. Based on the equal-length signal wiring model, electrical isolation spacing or grounding isolation structure is set between adjacent signal lines to obtain the printed circuit board design.

[0008] Furthermore, the construction process of the semi-finished component layout model includes: Based on the printed circuit board design drawing, determine the location of the central control area of ​​the MCU on the printed circuit board; Based on the chip selection control logic, the functional connection priority of each of the patch SIM chips relative to the MCU is determined, and the positions of each patch SIM chip are arranged according to the functional connection priority. Based on the principles of minimizing the signal path length between each surface-mount SIM chip and the MCU, and minimizing electromagnetic interference, the spatial distribution of each surface-mount SIM chip is optimized. Based on the electrical connection relationship between the matching element and the corresponding patch SIM chip, the matching element is placed in the vicinity of the corresponding patch SIM chip to obtain the layout model of the semi-finished component.

[0009] Furthermore, the firmware construction process includes: Based on the chip selection control logic, a network quality parameter acquisition module is constructed for collecting communication status parameters of each of the patch SIM chips; a chip selection decision module is constructed for generating corresponding patch SIM chip selection instructions based on the access suitability score; a chip communication control module is constructed for generating MCU control pin output signals based on the patch SIM chip selection instructions; and a virtual file system interface management module is constructed for realizing data interaction control between the terminal device main control chip and the MCU. The firmware program is constructed by integrating the network quality parameter acquisition module, the chip selection decision module, the chip communication control module, and the virtual file system interface management module.

[0010] Furthermore, the process of obtaining the firmware logic configuration result includes: Load the firmware program in the virtual simulation environment of the MCU; Construct a virtual patch SIM chip model to simulate the communication status of each patch SIM chip; The data access process of the terminal device's main control chip is simulated based on the virtual file system interface. Verify the correctness of the firmware program's selection control logic for the patch SIM chip to obtain the firmware logic configuration result.

[0011] Furthermore, the process of constructing a three-dimensional model of a multi-standard integrated packaging structure includes: A three-dimensional structural model of the substrate is constructed based on the printed circuit board design drawing; Based on the semi-finished component layout model, construct a three-dimensional solid model of the MCU, each surface mount SIM chip and matching components; A three-dimensional model of communication contacts was constructed based on the standard SIM card contact specifications. The three-dimensional structural model of the substrate, the three-dimensional solid models of each real-time chip, and the three-dimensional model of the communication contact are spatially assembled to obtain the three-dimensional model of the multi-standard fusion packaging structure.

[0012] Furthermore, the process of obtaining the packaging structure design results includes: The external structure of the package is constructed based on the aforementioned three-dimensional model; Based on the standard SIM card thickness limit, the height of each component inside the package is constrained and adjusted. Construct a model of the encapsulation material filling region; The outer shape of the package is integrated with the model of the package material filling area to obtain the package structure design result.

[0013] Furthermore, the construction process of the fuzzy comprehensive evaluation algorithm includes: Establish membership functions for network quality parameters; Construct a business type priority membership function; Construct a fuzzy evaluation matrix based on the membership function; The comprehensive evaluation result of each patch SIM chip is calculated based on the fuzzy evaluation matrix to obtain the access suitability score.

[0014] Furthermore, the packaging structure design results include: structural definition data of the printed circuit board, structural definition data of the MCU, structural definition data of the surface mount SIM chip, structural definition data of the matching components, structural definition data of the communication contacts, and structural definition data of the package body. The structural definition data is used to guide the physical manufacturing process of the multi-standard converged micro communication card.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: by integrating and constructing the chip selection control logic, circuit structure layout, and packaging structure model, a quantifiable constraint relationship is formed between various structural parameters, electrical parameters, and control parameters. During the substrate routing stage, the signal lines between the MCU and each surface-mount SIM chip are treated with equal length and isolation, ensuring that the propagation delay difference between communication channels is controlled within a preset delay tolerance range. This reduces clock skew and data sampling errors caused by path length differences, ensuring the timing consistency of chip selection instructions across multiple channels. Furthermore, the spatial positions of the MCU, surface-mount SIM chips, and matching components are constrained through the semi-finished component layout model, ensuring that the high-frequency signal path length, power supply loop area, and coupling distance are controlled. Within a controllable range, the impact of parasitic capacitance and inductance on signal integrity is reduced, and electrical stability during multi-mode signal switching is improved. Furthermore, by combining a virtual simulation environment to verify the firmware program's logic configuration, a matching relationship is established between the chip's selection control logic's task scheduling cycle and the MCU's instruction execution cycle, thus avoiding data link interruptions caused by control response lag or conflicts. Simultaneously, by constructing a three-dimensional model of the packaging structure, a coordinated relationship is established between chip layout density, packaging thickness, and structural support areas, thereby reducing local heat accumulation and structural stress concentration. This effectively solves the problems of poor communication timing consistency and decreased signal integrity caused by differences in signal propagation paths and enhanced electrical coupling during the integration of multiple communication units. Attached Figure Description

[0016] Figure 1 This is a flowchart of the micro communication card structure design method based on multi-standard fusion in this embodiment; Figure 2 A flowchart for constructing the chip selection control logic in this embodiment; Figure 3 This is a flowchart illustrating the construction process of the semi-finished component layout model in this embodiment; Figure 4 This is a flowchart illustrating the firmware logic configuration result obtained in this embodiment. Detailed Implementation

[0017] To make the objectives and advantages of the present invention clearer, the present invention will be further described below with reference to embodiments; it should be understood that the specific embodiments described herein are merely for explaining the present invention and are not intended to limit the present invention.

[0018] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0019] Please see Figure 1 The diagram shows a flowchart of a micro communication card structure design method based on multi-standard fusion in this embodiment. This embodiment provides a micro communication card structure design method based on multi-standard fusion, including: Based on the functional requirements of the multi-standard integrated micro communication card, an MCU is used as the core control unit to connect several surface-mount SIM chips and matching components. A virtual file system interface is added between the MCU and the main control chip of the terminal device to obtain the circuit schematic and the chip selection control logic built based on the circuit schematic. Based on the circuit schematic, and combined with the physical dimensions and contact positions of a standard SIM card, the signal lines connecting the MCU to each chip are made of equal length and isolated during the substrate wiring process to obtain the printed circuit board design. Based on the printed circuit board design drawing, the MCU, the surface mount SIM chip, and the matching components are arranged at designated positions on the board to obtain a semi-finished component layout model of the micro communication card. Firmware is built based on the chip selection control logic and the semi-finished component layout model, and the firmware is configured in the virtual simulation environment of the MCU to obtain firmware logic configuration results. Based on the printed circuit board, the chip selection control logic, and the firmware logic configuration results, a three-dimensional model of the multi-standard integrated packaging structure is constructed to obtain the packaging structure design results.

[0020] In this embodiment, the multi-standard fusion-based micro communication card structure design method is applied to communication terminal scenarios that require integrating multiple operator network access capabilities within a single card size. The external dimensions of the micro communication card are consistent with those of a standard SIM card, preferably 15.0mm in length, 12.0mm in width, and 0.76mm in thickness. The MCU is a microcontroller unit with multi-channel SIM interface control capabilities, used to execute chip selection control logic and output chip selection control signals. The patch SIM chips are user identification chips corresponding to different operator networks, each with independent power supply pins, clock pins, reset pins, and data communication pins. Matching components include pull-up resistors, decoupling capacitors, and impedance matching resistors for stabilizing signal transmission. The decoupling capacitors reduce power supply ripple amplitude, and the impedance matching resistors reduce signal reflection. The virtual file system interface is integrated into the MCU. The internal logic communication interface of the MCU is used to receive network quality detection commands sent by the main control chip of the terminal device and to feed back the communication status of the currently selected surface mount SIM chip to the main control chip of the terminal device. The printed circuit board is an insulating substrate used to carry the MCU, surface mount SIM chip and matching components, and conductive lines for connecting each device are formed inside. The semi-finished component layout model is a spatial layout model of each device built on the printed circuit board design drawing, used to define the relative positional relationship and signal path length between the MCU and each surface mount SIM chip. The firmware program is a control program used to control the MCU to execute surface mount SIM chip selection commands and manage communication status. The package structure 3D model is an overall package space model built on the printed circuit board and device layout, used to define the package boundary and structural thickness, so that the correspondence between each structural component, electrical connection relationship and control logic is clear and complete.

[0021] This invention improves the overall system design consistency and controllability by integrating chip selection control logic, circuit layout, and packaging structure modeling to achieve coordinated constraints and overall optimization among parameters. First, by controlling the length and isolation of signal paths, the difference in multi-channel propagation delay is reduced, thereby improving the timing consistency of chip selection instructions. Second, by optimizing the spatial layout of key components and high-frequency circuit parameters, the impact of parasitic effects is reduced, thereby improving signal integrity and electrical stability. Third, simulation matching verification between the control logic and the MCU execution cycle reduces control response lag and conflict risks. Furthermore, through three-dimensional optimization design of the packaging structure, local heat accumulation and structural stress concentration are reduced, thereby improving overall packaging reliability and long-term operational stability.

[0022] Please see Figure 2 As shown, this is a flowchart of the chip selection control logic construction in this embodiment. In this embodiment, the process of constructing the chip selection control logic based on the circuit schematic includes: Based on the connection topology between the MCU and each of the patch SIM chips in the circuit schematic, a multi-channel priority decision framework is established, an initial priority weight is preset for the operator network corresponding to each patch SIM chip, and a dynamic priority mapping table based on service type is established. Based on the virtual file system interface defined in the circuit schematic, an instruction set for transmitting real-time network quality parameters of each of the patch SIM chips is defined therein; Based on the signal connection relationship between the MCU and each of the patch SIM chips in the circuit schematic, a periodic polling mechanism is constructed to collect network quality data of each of the patch SIM chips through the virtual file system interface, and then perform filtering and normalization processing. Configure a fuzzy comprehensive evaluation algorithm to calculate the access suitability score of each of the patch SIM chips based on the network quality data, service type priority, and initial priority weight; Based on the access suitability score, combined with the preset handover threshold and hysteresis comparison mechanism, the optimal network access decision is generated and mapped to the corresponding patch SIM chip selection instruction. A buffering and retransmission mechanism designed to keep the data link uninterrupted during handover; The chip selection control logic is constructed by integrating the multi-channel priority decision framework, the instruction set, the periodic polling mechanism, the fuzzy comprehensive evaluation algorithm, the patch SIM chip selection instruction, and the caching and retransmission mechanism.

[0023] In this embodiment, a multi-channel priority decision framework is used to establish a quantifiable priority evaluation basis for the operator networks corresponding to each patch SIM chip. Specifically, a unique chip identifier IDi is assigned to each patch SIM chip, and an initial priority benchmark value is set for the operator network corresponding to each chip identifier IDi. This benchmark value is used to characterize the access priority of each operator network in the default state. At the same time, a service type set T={T1, T2, ..., Tn} is constructed according to the service types supported by the terminal device, where the service types include data transmission services, voice services, and low-power standby services. Further, a priority adjustment relationship is established between each service type and the chip identifier IDi, so that the priority benchmark value corresponding to each patch SIM chip under different service types is differentially adjusted, thereby forming a dynamic priority mapping relationship. This mapping relationship is used to output the basic priority evaluation results of each patch SIM chip under different service states for subsequent access suitability calculation.

[0024] In this embodiment, the virtual file system interface is a logical register mapping structure built inside the MCU, which includes an instruction input register area and a data output register area. The instruction input register area defines network quality acquisition instructions, chip status query instructions, and chip selection control instructions. The network quality acquisition instructions trigger the MCU to send a status read command to a specified surface-mount SIM chip. The data output register area defines a network quality parameter storage unit to store network quality data returned by each surface-mount SIM chip. The network quality data includes Received Signal Strength Indicator (RSSIi), Bit Error Rate (BERi), ​​and Response Time Delay (RTTi). RSSIi reflects wireless signal strength, BERi reflects communication reliability, and RTTi reflects communication response delay. Through the virtual file system interface, a data interaction channel is established between the MCU and the terminal device's main control chip to obtain standardized network quality data output results.

[0025] In this embodiment, a periodic polling mechanism is used to achieve real-time updates of the network quality status of each patch SIM chip. Specifically, a polling period τ is set within the MCU and adaptively selected within a preset selectable time scale range based on system processing capacity, communication load, and real-time requirements to determine the current polling period. Within each polling period, the MCU sends network quality acquisition commands to each patch SIM chip sequentially according to a preset chip identifier order and receives the corresponding network quality data RSSIi, BERi, and RTTi. To reduce the impact of instantaneous fluctuations on the evaluation results, a moving average filter is applied to M consecutive sampled data, where M is adaptively selected based on the degree of network fluctuation and sampling stability requirements, thereby obtaining the filtered network quality parameters RSSI'i, BER'i, and RTT'i. Subsequently, the filtered network quality parameters are normalized to convert each parameter into standardized parameters Qrssii, Qberi, and Qrtti with unified dimensions, to obtain a unified set of network quality evaluation parameters for subsequent suitability calculations.

[0026] In this embodiment, the fuzzy comprehensive evaluation algorithm is used to quantitatively evaluate the comprehensive communication performance of each patch SIM chip. Specifically, it constructs a network quality evaluation vector Qi={Qrssii, Qberi, Qrtti} based on normalized network quality parameters, and establishes the relative contribution relationship between parameters according to the differences in the impact of each evaluation parameter on communication stability and latency sensitivity. On this basis, signal strength, bit error rate, and latency characteristics are mapped to basic quality evaluation components, and a basic quality score Si is generated through nonlinear fusion. The strength of different evaluation components is dynamically adjusted by the system operating status and service requirements. Subsequently, the basic quality score Si is comprehensively corrected by combining the initial priority benchmark and service type-related adjustment relationship corresponding to each patch SIM chip to obtain the access suitability score Fi of each patch SIM chip. The access suitability score Fi is used to characterize the comprehensive access matching degree of each patch SIM chip in the current communication environment. The larger the value, the better the access suitability of the corresponding patch SIM chip in the current service scenario, thereby obtaining the access suitability evaluation result of each patch SIM chip.

[0027] In this embodiment, the optimal network access decision is achieved by comparing the access suitability scores Fi of each patch SIM chip. Specifically, based on the suitability difference between the target patch SIM chip and the currently accessing patch SIM chip, a handover judgment condition is constructed. When the access suitability score of the target patch SIM chip is consistently better than that of the currently accessing patch SIM chip within a duration window, the target patch SIM chip is determined to meet the handover condition. Here, a state-maintaining mechanism is introduced to suppress instantaneous fluctuations, and the handover decision is triggered only when the suitability advantage relationship remains consistent within a continuous observation period. Subsequently, the MCU generates the corresponding patch SIM chip selection instruction CMDsel, and controls the output state of the corresponding power pin, clock pin, and reset pin to put the target patch SIM chip into the communication conduction state, thereby achieving a stable network access handover decision.

[0028] In this embodiment, the caching and retransmission mechanism is implemented by setting up a data buffer area inside the MCU. The data buffer area is used to temporarily store the data sent or received by the main control chip of the terminal device during chip switching. After generating the chip SIM chip selection instruction CMDsel, the MCU first writes the current communication data into the data buffer area and records the current data transmission sequence number. After the target chip SIM chip establishes a communication connection, the MCU retransmits the data in the buffer area according to the data transmission sequence number, thereby restoring the communication data stream. Through the caching and retransmission mechanism, the amount of data loss during the chip SIM chip switching process is reduced to a preset allowable range, preferably with a data loss rate of less than 0.1%, thereby obtaining a continuous and stable data communication state.

[0029] This invention constructs a multi-channel priority decision framework and introduces an initial priority parameter and service requirement-related correction mechanism. This transforms the network access selection method for each SIM chip from a fixed selection method to a dynamic quantitative selection method based on service requirements and network capabilities, thereby improving the adaptability and rationality of network access decisions. By periodically collecting received signal strength, bit error rate, and communication delay, and combining filtering and normalization processing, the network quality evaluation results can effectively suppress the impact of instantaneous fluctuations, thus stably reflecting the channel state change trend and improving the reliability of the evaluation. By introducing a handover threshold and state persistence determination mechanism, access handover is triggered only when the suitability difference meets the amplitude and persistence conditions, thereby reducing the problem of frequent handover caused by short-term signal fluctuations and ensuring the stability of the communication link. In addition, by setting a data caching mechanism that matches the handover process, data during communication path handover can be continuously buffered and smoothly connected, thereby reducing the risk of data loss during handover. Therefore, this invention can achieve stable, continuous, and adaptive multi-SIM chip access control under the joint constraints of network quality changes and service requirement changes, thereby improving overall communication reliability and network access stability.

[0030] Specifically, the construction process of the fuzzy comprehensive evaluation algorithm includes: Establish membership functions for network quality parameters; Construct a business type priority membership function; Construct a fuzzy evaluation matrix based on the membership function; The comprehensive evaluation result of each patch SIM chip is calculated based on the fuzzy evaluation matrix to obtain the access suitability score.

[0031] In this embodiment, the network quality parameter membership function is used to convert the normalized network quality parameters into corresponding fuzzy evaluation levels, thereby establishing a mapping relationship between network quality parameters and communication performance evaluation. Specifically, for the normalized received signal strength parameter Qrssii, a monotonically increasing membership function μr(Qrssii) is constructed, such that the larger the received signal strength parameter, the closer its corresponding membership value is to the evaluation set belonging to "high-quality communication state"; for the normalized bit error rate parameter Qberi, a monotonically decreasing membership function μb(Qberi) is constructed, such that the smaller the bit error rate parameter, the closer its corresponding membership value is to the evaluation set belonging to "high-reliability communication state"; for the normalized response delay parameter Qrtt... i. Construct a monotonically decreasing membership function μt(Qrtti) such that the smaller the response delay, the closer its corresponding membership value is to the evaluation set belonging to the "low-latency communication state"; further, map each network quality parameter to a pre-defined set of multiple fuzzy evaluation levels V={V1, V2, ..., Vm}, where the fuzzy evaluation level set includes excellent, good, medium and poor levels, so that each network quality parameter can be represented in the form of a membership vector, thereby obtaining the network quality membership representation result corresponding to each patch SIM chip.

[0032] In this embodiment, the service type priority membership function is used to characterize the differences in sensitivity of different service types to network quality parameters. Specifically, firstly, a corresponding membership mapping relationship is established based on the communication characteristics of each service in the service type set, so that services sensitive to latency exhibit higher membership in the low latency evaluation level, services sensitive to bit error rate exhibit higher membership in the low bit error rate evaluation level, and services sensitive to coverage capability exhibit higher membership in the high signal strength evaluation level. Furthermore, the importance of each network quality dimension is dynamically adjusted through the service type priority correction coefficient, and the original correction coefficient is mapped to a fuzzy weight vector, thereby adaptively changing the contribution of each network quality parameter under different service scenarios. Therefore, compared with the fixed weight evaluation method, this method can dynamically reconstruct the evaluation structure according to the differences in service types, thereby improving the matching accuracy between access suitability assessment and actual communication needs.

[0033] In this embodiment, the fuzzy evaluation matrix is ​​used to integrate the calculation results of the network quality parameter membership function and the service type priority membership function. Specifically, for each patch SIM chip, a corresponding network quality membership matrix Ri is constructed based on its network quality parameter membership vector, where each row of Ri corresponds to a network quality parameter and each column corresponds to a fuzzy evaluation level. Simultaneously, the network quality membership matrix Ri is weighted according to the fuzzy weight vector Wj corresponding to the current service type, thereby obtaining a weighted fuzzy evaluation matrix Bi, which reflects the comprehensive evaluation results of each network quality parameter under the current service type conditions.

[0034] In this embodiment, the comprehensive evaluation result is obtained by performing fuzzy synthesis operation on the weighted fuzzy evaluation matrix Bi. Specifically, by performing weighted summation on the weighted fuzzy evaluation matrix Bi column by column, a comprehensive membership vector Ci = {ci1, ci2, ..., cim} is obtained, where the comprehensive membership vector Ci represents the degree of comprehensiveness of the corresponding patch SIM chip belonging to each fuzzy evaluation level. Then, according to the numerical mapping relationship corresponding to the preset fuzzy evaluation level, the comprehensive membership vector Ci is converted into the corresponding basic quality score Si, so that the basic quality score Si can represent the comprehensive communication performance of the corresponding patch SIM chip in a continuous numerical form. Furthermore, combined with the initial priority weight Wi, the basic quality score Si is weighted to obtain the access suitability score Fi of the corresponding patch SIM chip, so that the access suitability score Fi simultaneously reflects the real-time communication quality of the network and the basic priority characteristics of the operator's network.

[0035] In this embodiment, through the above-mentioned network quality parameter membership function construction, service type priority membership function construction, fuzzy evaluation matrix construction, and comprehensive evaluation result calculation process, the original network quality parameters are transformed from discrete measurement values ​​into continuous fuzzy evaluation results. Furthermore, the network state characteristics and service demand characteristics are uniformly quantified and represented through weight fusion, enabling the communication capabilities of each patch SIM chip to be compared using a unified evaluation scale. This yields an access suitability score that can be directly used for chip selection control logic calls.

[0036] By constructing a membership function for network quality parameters, communication link status indicators such as received signal strength, bit error rate, and response delay are transformed from discrete measurement expressions into continuously changing membership expressions. This allows communication quality changes to be described gradually and avoids the instability caused by abrupt evaluations. Furthermore, by introducing a service type priority membership function, the different requirements of various services for link stability, latency, and coverage can be flexibly integrated into the evaluation process, enabling the evaluation results to adaptively adjust to changes in service scenarios and improve scenario adaptability. Simultaneously, a fuzzy comprehensive evaluation mechanism is used to uniformly fuse multi-dimensional communication parameters, allowing various heterogeneous communication indicators to participate in the comprehensive judgment in a continuous contribution form under the same evaluation framework, thereby reducing the interference of single indicator fluctuations on the overall evaluation results. Furthermore, by using the comprehensive evaluation results to characterize access suitability and forming a collaborative reference with historical network stability factors, network selection not only reflects the current instantaneous communication status but also takes into account long-term operational reliability. This provides stable support for network access decisions in multi-mode communication environments and improves the selection consistency and communication reliability of patch SIM chips in complex communication scenarios.

[0037] Specifically, the process of obtaining the printed circuit board design drawing based on the circuit schematic includes: Based on the length, width, and thickness constraints of a standard SIM card, the external boundary dimensions of the printed circuit board are determined to obtain a board external constraint model. According to the standard SIM card contact position specification, the communication contact area and contact lead-out path are defined on the substrate shape constraint model to obtain the contact layout model. Based on the connection relationship between the MCU and each of the surface mount SIM chips in the circuit schematic, the clock signal lines, reset signal lines and data signal lines from the MCU to each surface mount SIM chip are designed to be of equal length, so that the length deviation of each corresponding signal line is within a preset error range, so as to obtain an equal length signal wiring model. Based on the equal-length signal wiring model, electrical isolation spacing or grounding isolation structure is set between adjacent signal lines to obtain the printed circuit board design.

[0038] In this embodiment, the substrate shape constraint model is used to define the spatial boundary range of the printed circuit board, enabling it to achieve mechanical matching and electrical contact with the standard SIM card socket. Specifically, the length of the standard SIM card is preferably 14.8mm to 15.0mm, the width is preferably 11.8mm to 12.0mm, and the thickness is preferably 0.70mm to 0.76mm. When determining the shape of the printed circuit board, the length of the substrate is preferably 0.05mm to 0.20mm smaller than the length of the standard SIM card, and the width of the substrate is preferably 0.05mm to 0.20mm smaller than the width of the standard SIM card to reserve space for the encapsulation adhesive layer. The thickness of the substrate is preferably 0.10mm to 0.25mm, so that the overall thickness meets the thickness requirements of the standard SIM card after device mounting and encapsulation. Through the above dimensional constraints, the printed circuit board can form a stable contact relationship with the standard SIM card socket after encapsulation, thereby obtaining a substrate shape constraint model whose structural dimensions meet the assembly requirements.

[0039] In this embodiment, the contact layout model is used to establish the electrical connection path between the printed circuit board and the terminal device card slot. Specifically, the standard SIM card preferably has 6 or 8 contacts, the spacing between the centers of each contact is preferably 0.80mm to 1.20mm, and the effective contact area of ​​each contact is preferably 0.60mm × 0.60mm to 1.00mm × 1.00mm. Conductive contact areas are set at corresponding positions on the substrate surface, and each contact area is connected to the corresponding power pin, ground pin, clock pin, reset pin, and data communication pin of the MCU through conductive traces. The contact areas preferably adopt a gold-plated conductive layer structure, and the gold plating layer thickness is preferably 0.03μm to 0.10μm to reduce contact resistance and improve oxidation resistance. Through the above methods, a stable conductive path is formed between the contact areas and the terminal device card slot spring pins, thereby obtaining a contact layout model that meets the electrical connection requirements.

[0040] In this embodiment, the equal-length signal routing model is used to ensure the consistency of communication timing between the MCU and each surface-mount SIM chip. Specifically, the connection paths of the clock signal line, reset signal line, and data signal line from the MCU to each surface-mount SIM chip are determined according to the circuit schematic. The longest signal path length is used as the reference path length. By adjusting the routing paths of other signal lines, the length deviation of each corresponding type of signal line is preferably controlled within the range of 0.05mm to 0.50mm. During the routing process, a serpentine compensation routing structure is preferably used to compensate for the length of shorter signal paths. At the same time, the signal line width is preferably 0.05mm to 0.15mm to ensure a balance between conductivity and routing space. Through the above equal-length routing design, the clock signal and control signal received by each surface-mount SIM chip are kept synchronized, thereby obtaining an equal-length signal routing model that meets the requirements of communication timing consistency.

[0041] In this embodiment, the electrical isolation spacing or grounding isolation structure is used to reduce electromagnetic coupling interference between adjacent signal lines. Specifically, the spacing between adjacent signal lines is preferably 0.05mm to 0.20mm; for high-frequency clock signal lines, a grounding isolation conductor or grounding copper foil area is preferably provided in the adjacent area to form a shielding path between the signal line and the grounding structure; the grounding isolation structure is connected to the substrate ground layer through vias to form a low-impedance grounding loop; at the same time, decoupling capacitors are preferably placed near the power pins of the MCU and surface-mount SIM chip, with a capacitance preferably of 0.01μF to 0.10μF and a placement distance preferably less than 1.0mm, to reduce the interference of power supply noise on the signal lines; through the above electrical isolation design, the crosstalk amplitude during signal transmission is reduced to a preset range, thereby obtaining a printed circuit board design that meets the communication requirements for signal integrity.

[0042] In this embodiment, after completing the above-mentioned substrate shape constraint model, contact layout model, equal-length signal wiring model, and electrical isolation structure design, the various structural models are integrated by printed circuit design software, and a printed circuit board design drawing file containing a substrate outline layer, contact conductive layer, signal wiring layer, and ground layer is output. The printed circuit board design drawing file is preferably a standard circuit board manufacturing format file for subsequent processing and manufacturing of the printed circuit board.

[0043] By establishing a substrate shape constraint model, the length, width, and thickness dimensions of the printed circuit board are matched with the structural dimensions of a standard SIM card. This ensures that the overall dimensions of the packaged substrate can form a stable mechanical contact with the terminal device's card slot and maintain constant contact pressure, keeping the contact resistance within a stable range. By constructing a contact layout model, a correspondence is established between the contact center spacing, contact area, and conductive layer thickness, thus balancing the contact area and contact current density, reducing the current load per unit area and minimizing contact interface resistance fluctuations, enabling stable transmission of power and data signals. By constructing an equal-length signal routing model, the length deviation of the corresponding signal lines of each surface-mount SIM chip is controlled within a preset range, ensuring consistency between the signal propagation path length and signal propagation time, thereby ensuring stable transmission of power and data signals for each surface-mount SIM chip. The clock and control signals received by the IM chip are synchronized in time to avoid data sampling offsets or communication errors caused by propagation delay differences. Simultaneously, by setting signal line spacing and grounding isolation structures, a constraint relationship is established between the spatial spacing between signal lines and the electromagnetic field coupling strength, reducing parasitic capacitance and inductance between adjacent signal lines, thereby reducing crosstalk amplitude and improving signal edge stability. Furthermore, by placing decoupling capacitors near the power supply pins, a filtering relationship is established between the decoupling capacitor capacitance and the power supply voltage fluctuation frequency, thereby absorbing instantaneous current fluctuations and reducing the impact of power supply noise on signal transmission. Therefore, through the coordinated constraints between substrate size parameters, contact structure parameters, signal path length parameters, and electrical isolation parameters, the printed circuit board achieves stable and reliable signal transmission while meeting structural assembly requirements.

[0044] Please see Figure 3 The diagram shows a flowchart of the construction process of the semi-finished component layout model in this embodiment. In this embodiment, the construction process of the semi-finished component layout model includes: Based on the printed circuit board design drawing, determine the location of the central control area of ​​the MCU on the printed circuit board; Based on the chip selection control logic, the functional connection priority of each of the patch SIM chips relative to the MCU is determined, and the positions of each patch SIM chip are arranged according to the functional connection priority. Based on the principles of minimizing the signal path length between each surface-mount SIM chip and the MCU, and minimizing electromagnetic interference, the spatial distribution of each surface-mount SIM chip is optimized. Based on the electrical connection relationship between the matching element and the corresponding patch SIM chip, the matching element is placed in the vicinity of the corresponding patch SIM chip to obtain the layout model of the semi-finished component.

[0045] In this embodiment, the central control area serves as the reference area for MCU deployment, enabling the MCU to form balanced signal connection paths with each surface-mount SIM chip and communication contact. Specifically, based on the printed circuit board design, a two-dimensional coordinate system of the printed circuit board is established, with the geometric center of the board as the reference origin. The MCU is preferably deployed in an area within 0.00mm to 1.50mm from the geometric center of the board, minimizing the average signal path length from the MCU to each surface-mount SIM chip and communication contact. Simultaneously, the pin orientation of the MCU is preferably towards the communication contact area, allowing the MCU's power pins, clock pins, and data signal pins to connect to their corresponding conductive traces via the shortest path, thereby reducing signal path length and minimizing the influence of parasitic parameters to achieve the desired MCU central control area deployment result.

[0046] In this embodiment, the functional connection priority is used to reflect the access frequency and communication importance of each surface-mount SIM chip in the chip selection control logic. Specifically, the call frequency or priority weight is calculated based on the access suitability of each surface-mount SIM chip in the chip selection control logic. Surface-mount SIM chips with higher priority weights are placed closer to the MCU, with a preferred signal path length to the MCU of 1.00mm to 5.00mm; surface-mount SIM chips with lower priority weights are placed relatively farther from the MCU, with a preferred signal path length to the MCU of 3.00mm to 10.00mm. Through this method, surface-mount SIM chips with higher communication call frequencies have shorter signal propagation paths, thereby reducing signal propagation delay and improving communication response speed, thus obtaining a surface-mount SIM chip layout result optimized based on functional connection priority.

[0047] In this embodiment, the optimized spatial distribution is used to reduce electromagnetic interference and signal crosstalk during signal transmission. Specifically, the center-to-center spacing between each surface-mount SIM chip is preferably 1.50mm to 6.00mm to reduce the electromagnetic coupling strength between adjacent chips. Simultaneously, the signal pins of each surface-mount SIM chip are preferably oriented towards the MCU to avoid signal traces crossing or looping, thereby reducing parasitic inductance and capacitance. For high-frequency signal path areas, it is preferable to avoid multiple surface-mount SIM chips forming a closed-loop layout to prevent the formation of electromagnetic coupling loops. Further preferably, the surface-mount SIM chips are radially or linearly distributed along the circumference of the MCU, resulting in a divergent connection structure for the signal paths, thus achieving a spatial distribution layout with minimal signal interference.

[0048] In this embodiment, the matching element is used to stabilize the power signal, clock signal, and data signal of the corresponding surface-mount SIM chip. Specifically, the matching element includes a decoupling capacitor, a resistor, or a filter capacitor; the decoupling capacitor is preferably placed between the power pin and the ground pin of the corresponding surface-mount SIM chip, and the placement distance is preferably 0.20mm to 1.00mm, to reduce the power path impedance and improve power stability; the matching resistor is preferably placed in series on the clock signal path or data signal path to reduce signal reflection; the filter capacitor is preferably placed between the power path and ground to reduce high-frequency noise components; by placing the matching element close to the corresponding surface-mount SIM chip, the connection path length between the matching element and the surface-mount SIM chip is minimized, thereby improving the signal regulation effect of the matching element, thus obtaining the matching element placement result.

[0049] In this embodiment, after determining the MCU placement location, optimizing the spatial distribution of the surface mount SIM chip, and arranging the matching components nearby, a component layout structure model is established using printed circuit design software. This model includes the MCU 3D package outline model, the surface mount SIM chip package outline model, and the matching component package outline model. Simultaneously, collision detection is performed on the spacing between components to ensure that the minimum spacing between components is preferably greater than 0.10mm, meeting the requirements of manufacturing and packaging processes. Furthermore, a semi-finished component layout model file containing the spatial coordinates, package dimensions, and pin connection relationships of each component is output. Based on this semi-finished component layout model, the component placement and assembly of the micro communication card can be directly completed.

[0050] By placing the MCU in the central control area of ​​the printed circuit board, a relatively balanced signal transmission path is formed between the MCU and each surface-mount SIM chip and communication contact, thereby reducing the propagation time difference between different signal paths and avoiding communication timing offset problems caused by path imbalance. Simultaneously, according to the chip selection control logic, surface-mount SIM chips with higher communication call frequencies are preferentially placed closer to the MCU, shortening the corresponding signal path length. This reduces the distributed resistance and inductance of the conductive path, minimizing energy loss during signal propagation and improving signal edge stability. Surface-mount SIM chips with lower communication call frequencies are placed in relatively outer areas, maintaining an orderly overall layout and avoiding localized issues. The excessive concentration of components leads to enhanced electromagnetic coupling. Further optimization of the spatial spacing and signal pin orientation between the surface-mount SIM chips disperses the signal paths and avoids crossings, reducing the signal loop area and thus lowering electromagnetic coupling strength and signal crosstalk. Furthermore, by placing matching elements adjacent to the corresponding surface-mount SIM chips, the matching elements can regulate power and signals with shorter connection paths, thereby improving power response speed and suppressing high-frequency noise propagation. Based on the coordinated optimization of the spatial relationships and signal path structures of the above components, a harmonious overall structure is formed, integrating signal propagation paths, power stability, and electromagnetic interference suppression capabilities, thereby improving the communication stability and operational reliability of the micro-communication card.

[0051] Specifically, the firmware construction process includes: Based on the chip selection control logic, a network quality parameter acquisition module is constructed for collecting communication status parameters of each of the patch SIM chips; a chip selection decision module is constructed for generating corresponding patch SIM chip selection instructions based on the access suitability score; a chip communication control module is constructed for generating MCU control pin output signals based on the patch SIM chip selection instructions; and a virtual file system interface management module is constructed for realizing data interaction control between the terminal device main control chip and the MCU. The firmware program is constructed by integrating the network quality parameter acquisition module, the chip selection decision module, the chip communication control module, and the virtual file system interface management module.

[0052] In this embodiment, the firmware is deployed in the program storage unit inside the MCU to realize the functions of status acquisition, selection decision, and communication control of each surface-mount SIM chip. Specifically, firstly, the overall functional architecture of the firmware is established based on the chip selection control logic, and corresponding functional module storage areas are divided in the program storage area of ​​the MCU. At the same time, a running data cache area is established in the data storage area of ​​the MCU to store the communication status parameters of each surface-mount SIM chip, so that the firmware can independently store and call the communication status parameters of each surface-mount SIM chip during operation. Among them, the communication status parameters include signal strength parameters, communication delay parameters, error rate parameters, registration status parameters, and network type identifier parameters, forming a data foundation that can be called by the chip selection decision module.

[0053] In this embodiment, the network quality parameter acquisition module is used to periodically acquire the communication status parameters of each surface-mount SIM chip. Specifically, a timed scheduling mechanism based on the system clock is established within the MCU, and when the timed scheduling mechanism is triggered, the communication control interface function is called, causing the MCU to send a status query command to each surface-mount SIM chip through the corresponding communication control pin. Subsequently, the response data returned by each surface-mount SIM chip is received, and the response data is parsed into the corresponding communication status parameters. The acquired communication status parameters are further processed by data format conversion and cache storage to obtain a structured network quality parameter data table. The network quality parameter data table is used to record the unique OIN identifier information and corresponding communication status parameters of each surface-mount SIM chip, so that the communication status of each surface-mount SIM chip can be tracked in real time.

[0054] In this embodiment, the chip selection decision module generates corresponding patch SIM chip selection instructions based on the network quality parameter data table. Specifically, it first reads the communication status parameters of each patch SIM chip in the network quality parameter data table and calculates the access suitability score corresponding to each patch SIM chip according to the preset access suitability calculation rules. Then, it sorts the access suitability scores to determine the target patch SIM chip with the highest access suitability score. Furthermore, it converts the chip identification information corresponding to the target patch SIM chip into the corresponding chip selection control code to obtain the chip selection instruction data structure. The chip selection instruction data structure includes a target chip number field, a control pin status field, and an instruction validity identifier field, enabling the chip selection instruction to be directly parsed and executed by the chip communication control module.

[0055] In this embodiment, the chip communication control module generates corresponding MCU control pin output signals according to the chip selection instruction. Specifically, the chip communication control module calls the MCU's general-purpose input / output control register interface to map the control pin status field in the chip selection instruction to the corresponding control pin's level state, enabling the enable pin of the corresponding surface-mount SIM chip to be in an active state, while simultaneously disabling the enable pins of other surface-mount SIM chips, thereby achieving the selection control of the target surface-mount SIM chip. Simultaneously, the chip communication control module establishes a chip switching state flag variable to record the number of the surface-mount SIM chip currently in the selected state, enabling the firmware program to avoid repeated switching operations and maintain stable communication during execution.

[0056] In this embodiment, the virtual file system interface management module is used to realize data interaction between the terminal device's main control chip and the MCU. Specifically, a virtual file mapping table is established in the MCU's data storage area, and corresponding virtual file nodes are allocated to each surface-mount SIM chip. This allows the terminal device's main control chip to read the communication status information of the corresponding surface-mount SIM chip or send chip control request commands by accessing the virtual file nodes. At the same time, the virtual file system interface management module parses the access commands sent by the terminal device's main control chip and converts them into corresponding internal control operations of the MCU, thereby enabling the terminal device's main control chip to monitor and manage the selection process of the surface-mount SIM chip.

[0057] In this embodiment, after constructing the network quality parameter acquisition module, chip selection decision module, chip communication control module, and virtual file system interface management module, the functional modules are integrated using a firmware integration tool, and a unified main control program entry function is established. The main control program entry function is used to sequentially initialize the system clock, input / output control interface, data storage area, and each functional module during MCU power-on initialization, enabling each module to enter a runnable state. Subsequently, the network quality parameter acquisition module and chip selection decision module are periodically called through a loop scheduling mechanism, and the chip communication control module is called to perform chip switching operations when the chip selection state changes. Simultaneously, the virtual file system interface management module maintains data interaction with the terminal device's main control chip, thus forming a complete and executable firmware program structure. Finally, the firmware program is compiled to generate the corresponding executable program file and written into the MCU program storage unit, enabling the MCU to automatically select and control communication between multiple surface-mount SIM chips based on the firmware program.

[0058] Through firmware development, the network quality parameter acquisition module continuously acquires status parameters reflecting the communication stability and link reliability of each patch SIM chip. These status parameters are then processed by the chip selection decision module to generate an access suitability score, quantifying communication link quality changes and converting them into comparable control criteria. Since communication status parameters directly reflect wireless link propagation loss, signal integrity, and data transmission success probability, changes in the access suitability score synchronously characterize the effective transmission capability of communication links corresponding to different patch SIM chips. This allows the chip communication control module to adjust the MCU control pin output state based on the access suitability score, ensuring that the communication link always establishes a connection through the patch SIM chip with higher transmission capability and stronger communication stability. Simultaneously, a virtual file system interface... The management module enables a continuous data transmission and control closed loop in the communication status parameter acquisition process, chip selection decision process, and control pin output process. This allows changes in the communication link status to be quickly transmitted to the control execution layer and generate corresponding pin control responses, thereby reducing the impact of link quality degradation on data transmission continuity. Furthermore, through the coordinated action of data caching, status judgment, and control execution among various functional modules, the communication status perception, decision-making, and execution processes are seamlessly connected in time and form a stable control path in structure. This ensures that the communication link selection result can be stably mapped to the MCU control pin output status, thereby improving the communication stability, link switching accuracy, and overall operational reliability of the micro communication card in multi-standard network environments. This enables intelligent selection control of multi-surface SIM chips based on adaptive adjustment of communication status.

[0059] Please see Figure 4 As shown, this is a flowchart of obtaining the firmware logic configuration result in this embodiment. In this embodiment, the process of obtaining the firmware logic configuration result includes: Load the firmware program in the virtual simulation environment of the MCU; Construct a virtual patch SIM chip model to simulate the communication status of each patch SIM chip; The data access process of the terminal device's main control chip is simulated based on the virtual file system interface. Verify the correctness of the firmware program's selection control logic for the patch SIM chip to obtain the firmware logic configuration result.

[0060] In this embodiment, the virtual simulation environment of the MCU is used to verify the running logic and control behavior of the firmware program without the need for actual hardware. Specifically, a corresponding virtual processor kernel model is established based on the instruction set architecture of the MCU, and a program storage area, a data storage area, and an input / output control register mapping area are configured in the virtual processor kernel model. Subsequently, the executable program file generated by compiling the firmware program is loaded into the program storage area, and the executable program file is executed through the virtual processor kernel model, so that the firmware program runs in the virtual environment according to a preset control flow. At the same time, a running status monitoring unit is established in the data storage area to record the chip selection instructions, control pin states, and data access records during the firmware program's operation, thereby obtaining the virtual loading and running results of the firmware program.

[0061] In this embodiment, the virtual patch SIM chip model is used to simulate the communication status and response behavior of an actual patch SIM chip under different network environments. Specifically, a unique chip identifier is assigned to each virtual patch SIM chip model, and a corresponding network quality parameter generation unit is established to generate corresponding received signal strength parameters, bit error rate parameters, response delay parameters, and network registration status parameters. Simultaneously, a communication command response unit is established in the virtual patch SIM chip model, enabling it to output corresponding network quality parameter data when it receives a status query command sent by the MCU through the virtual input / output control register. Furthermore, by pre-setting different network status change sequences, the network quality parameters of each virtual patch SIM chip model change over time, thereby obtaining virtual communication status data results that can be used to verify the chip selection control logic.

[0062] In this embodiment, the virtual file system interface simulation process is used to verify the data interaction logic between the terminal device's main control chip and the MCU. Specifically, a virtual main control chip access model is established in the virtual simulation environment, and chip status query request instructions and chip selection control request instructions are sent to the MCU through the virtual file system interface; simultaneously, network quality parameter data and chip selection status data returned by the MCU are read to form a complete data access interaction process; further, by recording the virtual file node access path and access results, the data mapping relationship and data access logic of the virtual file system interface are verified, thereby obtaining the virtual file system interface access verification result.

[0063] In this embodiment, the selection control logic correctness verification process is used to confirm that the firmware program can correctly generate patch SIM chip selection instructions based on changes in network quality parameters. Specifically, by controlling the changes in network quality parameters of each virtual patch SIM chip model, the access suitability score of at least one virtual patch SIM chip model is made higher than the access suitability score corresponding to the currently selected chip; then, it is detected whether the firmware program generates the corresponding chip selection instruction, and whether the state of the corresponding control pin in the MCU virtual input / output control register changes accordingly; at the same time, it is verified that the firmware program maintains the current chip selection state unchanged when the change in access suitability score does not meet the switching conditions; through the above method, the selection decision logic and control execution logic of the firmware program are completely verified, thereby obtaining the chip selection control logic verification result.

[0064] In this embodiment, after completing the firmware loading, virtual patch SIM chip model construction, virtual file system interface access simulation, and selection control logic verification, the chip selection instruction generation record, control pin state change record, and data interaction record during the firmware operation are integrated, and a firmware logic configuration result file containing the chip selection control mapping relationship, control pin configuration status, and data interaction verification results is output. This enables the firmware logic configuration result to be directly used for the actual hardware deployment and configuration of the MCU, thereby making the control logic of the multi-standard fusion micro communication card verifiable and deployable.

[0065] By loading firmware into a virtual simulation environment and constructing a virtual patch SIM chip model, an observable dynamic response relationship is established between communication status parameters, chip selection instructions, and MCU control pin states. Changes in communication status parameters directly cause changes in access suitability scores, which in turn drive corresponding adjustments in chip selection instructions and control pin output states, thus forming a complete closed-loop response link from network quality input, logic decision processing to hardware control output. Simultaneously, by simulating the data access process of the terminal device's main control chip through a virtual file system interface, a consistent data mapping relationship is established between data access requests, firmware logic processing results, and control execution states, thereby verifying the synchronization and consistency between the data interaction process and the control execution process. Furthermore, by recording the generation time of chip selection instructions, the process of control pin state changes, and the process of communication status parameter changes, a corresponding matching relationship is established between the communication state change rate, logic decision response rate, and control execution response rate, thereby verifying that the firmware can output correct and stable control results under different communication state conditions. Therefore, the correctness of the firmware logic configuration can be accurately verified before actual deployment, and the control reliability of the multi-standard fusion-based micro communication card can be improved.

[0066] Specifically, the process of constructing a 3D model of a multi-standard integrated packaging structure includes: A three-dimensional structural model of the substrate is constructed based on the printed circuit board design drawing; Based on the semi-finished component layout model, construct a three-dimensional solid model of the MCU, each surface mount SIM chip and matching components; A three-dimensional model of communication contacts was constructed based on the standard SIM card contact specifications. The three-dimensional structural model of the substrate, the three-dimensional solid models of each real-time chip, and the three-dimensional model of the communication contact are spatially assembled to obtain the three-dimensional model of the multi-standard fusion packaging structure.

[0067] In this embodiment, the process of constructing a three-dimensional structural model of the substrate based on the printed circuit board design drawing includes: firstly, reading the substrate outline data, layer thickness parameters, and conductive layer distribution information from the printed circuit board design drawing, and generating a two-dimensional boundary outline of the substrate based on the outline data; then, stretching and modeling the two-dimensional boundary outline along the vertical direction according to the layer thickness parameters to form a substrate solid structure with actual thickness; further, constructing corresponding conductive layer regions and interlayer conductive structures in the substrate solid structure according to the conductive trace areas and via positions in the printed circuit board design drawing, thereby obtaining a three-dimensional structural model of the substrate consistent with the actual printed circuit board, so that the three-dimensional structural model of the substrate can reflect the spatial structural characteristics and interlayer connection relationships of the actual substrate.

[0068] In this embodiment, the process of constructing a three-dimensional solid model of the MCU, each surface-mount SIM chip, and matching components based on the semi-finished component layout model includes: firstly, reading the spatial coordinate position, package size parameters, and pin distribution information of each component in the semi-finished component layout model; then, constructing a corresponding three-dimensional solid contour model according to the package size parameters of each component, and constructing a pin structure model consistent with the actual package pins at the bottom of the solid contour model; further, based on the spatial coordinate position recorded in the semi-finished component layout model, positioning the three-dimensional solid model of each component to the corresponding layout area of ​​the substrate three-dimensional structure model, so that the pin position of each component corresponds to the conductive trace position of the substrate, thereby obtaining a component three-dimensional solid assembly model consistent with the actual component layout state.

[0069] In this embodiment, the process of constructing a three-dimensional model of communication contacts based on the standard SIM card contact specifications includes: constructing corresponding contact entity structure models according to the number of contacts, contact arrangement order, and contact size parameters of the standard SIM card contact area; simultaneously, according to the contact layout area defined in the printed circuit board design drawing, placing each contact entity structure model in a designated location area of ​​the substrate three-dimensional structure model; furthermore, constructing a conductive connection structure between each contact entity structure model and the substrate conductive layer, so that the three-dimensional model of communication contacts can reflect the actual electrical connection path relationship between the terminal device main control chip and the MCU, thereby obtaining the three-dimensional structure model of communication contacts.

[0070] In this embodiment, the process of spatially assembling the substrate 3D structural model, the 3D solid models of each chip, and the 3D model of the communication contact includes: establishing a unified 3D spatial coordinate system and using the substrate 3D structural model as the assembly reference model; then, based on the spatial coordinate parameters recorded in the semi-finished component layout model, assembling the 3D solid models of each chip and the 3D solid models of matching components to the corresponding positions of the substrate 3D structural model; simultaneously assembling the communication contact 3D model to the corresponding contact area of ​​the substrate; further verifying the spatial position of each component 3D solid model after assembly to confirm that there is no spatial interference between the components and to ensure that the pins of each component and the corresponding conductive traces form a correct spatial correspondence; finally, outputting a complete 3D assembly model file containing the substrate structure, component structure, and communication contact structure.

[0071] This invention unifies and coordinates the spatial assembly of the substrate's three-dimensional structural model, the three-dimensional solid models of each chip, and the three-dimensional model of the communication contacts. This ensures that all components form a consistent spatial representation relationship within the same three-dimensional coordinate system, allowing the relative positional relationship between chip pins and communication contacts to directly reflect the continuity of the actual electrical connection path, thereby reducing the risk of contact discontinuity caused by spatial offset. Furthermore, by spatially mapping the structural support state through the correspondence between the substrate thickness distribution and the chip solid volume, the load transfer path tends to be uniformly distributed, thus avoiding structural instability caused by localized stress concentration. Simultaneously, by indirectly characterizing the heat diffusion channel through the adaptation relationship between the chip outline and the substrate envelope space, heat can be continuously diffused along areas with better thermal conductivity, thereby reducing the impact of localized heat accumulation on device stability. In addition, by spatially matching the communication contact structure and the chip connection area, the contact interface maintains a stable fit, thereby improving interface consistency and connection reliability during electrical signal transmission.

[0072] Specifically, the process of obtaining the packaging structure design results includes: The external structure of the package is constructed based on the aforementioned three-dimensional model; Based on the standard SIM card thickness limit, the height of each component inside the package is constrained and adjusted. Construct a model of the encapsulation material filling region; The outer shape of the package is integrated with the model of the package material filling area to obtain the package structure design result.

[0073] Specifically, the packaging structure design results include: structural definition data of the printed circuit board, structural definition data of the MCU, structural definition data of the surface mount SIM chip, structural definition data of the matching components, structural definition data of the communication contacts, and structural definition data of the package body. The structural definition data is used to guide the physical manufacturing process of the multi-standard converged micro communication card.

[0074] In this embodiment, the process of constructing the package shape structure based on the three-dimensional model includes: using the three-dimensional structure model of the printed circuit board as the reference support, extracting the outermost contour boundary of the three-dimensional solid model of each chip, the three-dimensional solid model of the matching component, and the three-dimensional model of the communication contact in a unified spatial coordinate system, and generating an overall envelope surface based on the outermost contour boundary, and then performing continuity correction and boundary closure processing on the envelope surface to form a complete package shape structure model. The envelope surface and the outer contour of the printed circuit board maintain a preset structural gap relationship to provide continuous space for filling the package material.

[0075] In this embodiment, the process of constraining and adjusting the height of each component inside the package according to the thickness limit of the standard SIM card includes: establishing a height reference axis perpendicular to the plane of the printed circuit board, and obtaining the maximum projected height of the three-dimensional solid model of each component in the direction of the height reference axis; comparing the maximum projected height with the allowable height range of the package's external structure; when the projected height of any component is close to or exceeds the allowable height range, adjusting the embedding depth, mounting base position, or local structural embedding relationship of the corresponding component on the printed circuit board, so that the overall distribution of each component in the height direction remains within the allowable envelope of the package's external structure, while keeping the spatial connection relationship and electrical connection correspondence between each component unchanged.

[0076] In this embodiment, the process of constructing the packaging material filling region model includes: generating an internal solid space of the package based on the package's external structural model, and subtracting the solid volume occupied by the three-dimensional structural model of the printed circuit board, the three-dimensional solid models of each chip, the three-dimensional solid models of the matching components, and the three-dimensional model of the communication contacts from the solid space using Boolean operations to obtain the remaining enclosed space region; defining the remaining enclosed space region as the packaging material filling region model, wherein the packaging material filling region model forms a continuous bonding interface with the outer surface of each component to ensure that the packaging material can form a complete structural support during the physical realization process.

[0077] In this embodiment, the process of integrating the outer shape of the package with the model of the package material filling area includes: under a unified three-dimensional coordinate system, the outer shape of the package is used as the outer boundary constraint body, and the model of the package material filling area is used as the inner filling definition body for structural association, and a topological correspondence between the outer boundary of the package and the inner filling area is established to form a package structure design result with complete structural boundary definition and inner filling definition, so that the outer shape of the package and the inner filling structure maintain a consistent correspondence.

[0078] In this embodiment, the process of generating the structural definition data includes: extracting structural features from the three-dimensional structural models corresponding to the printed circuit board, MCU, surface mount SIM chip, matching components, communication contacts, and package, generating structural description information including spatial position parameters, structural contour parameters, relative assembly relationship parameters, and interface contact relationship parameters, and storing it in a unified data format so that each structural definition data can be directly used to guide the positioning and installation of corresponding components, the control of the filling range of packaging materials, and the overall package forming process.

[0079] By extracting the spatial contour boundaries of each component based on a 3D model and constructing the package's external shape structure, a direct correspondence is established between the package's external envelope and the spatial distribution of internal components, ensuring that the package size effectively constrains the internal structure. Furthermore, by adjusting the projection distribution of each component in the height direction, the component height superposition relationship is kept consistent with the package's allowable height range, preventing local structures from exceeding the package boundary and causing structural interference or stress concentration. Simultaneously, by constructing a package material filling region model, a continuous bonding interface is formed between the package material filling space and the outer surfaces of each component, enabling the package material to provide uniform support and achieve continuous stress transmission path distribution, further ensuring the overall stability of the package structure. Finally, by integrating the package's external shape structure and the package material filling region model and generating structural definition data, a clear spatial correspondence and assembly constraint relationship is established between the structural parameters, ensuring coordination and unity among the package's external dimensions, internal component spatial layout, and package material filling range.

[0080] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for designing a micro communication card structure based on multi-standard fusion, characterized in that, include: Based on the functional requirements of the multi-standard integrated micro communication card, an MCU is used as the core control unit to connect several surface-mount SIM chips and matching components. A virtual file system interface is added between the MCU and the main control chip of the terminal device to obtain the circuit schematic and the chip selection control logic built based on the circuit schematic. Based on the circuit schematic, and combined with the physical dimensions and contact positions of a standard SIM card, the signal lines connecting the MCU to each chip are made of equal length and isolated during the substrate wiring process to obtain the printed circuit board design. Based on the printed circuit board design drawing, the MCU, the surface mount SIM chip, and the matching components are arranged at designated positions on the board to obtain a semi-finished component layout model of the micro communication card. Firmware is built based on the chip selection control logic and the semi-finished component layout model, and the firmware is configured in the virtual simulation environment of the MCU to obtain firmware logic configuration results. Based on the printed circuit board, the chip selection control logic, and the firmware logic configuration results, a three-dimensional model of the multi-standard integrated packaging structure is constructed to obtain the packaging structure design results.

2. The micro communication card structure design method based on multi-standard fusion according to claim 1, characterized in that, The process of constructing chip selection control logic based on circuit schematics includes: Based on the connection topology between the MCU and each of the patch SIM chips in the circuit schematic, a multi-channel priority decision framework is established, an initial priority weight is preset for the operator network corresponding to each patch SIM chip, and a dynamic priority mapping table based on service type is established. Based on the virtual file system interface defined in the circuit schematic, an instruction set for transmitting real-time network quality parameters of each of the patch SIM chips is defined therein; Based on the signal connection relationship between the MCU and each of the patch SIM chips in the circuit schematic, a periodic polling mechanism is constructed to collect network quality data of each of the patch SIM chips through the virtual file system interface, and then perform filtering and normalization processing. Configure a fuzzy comprehensive evaluation algorithm to calculate the access suitability score of each of the patch SIM chips based on the network quality data, service type priority, and initial priority weight; Based on the access suitability score, combined with the preset handover threshold and hysteresis comparison mechanism, the optimal network access decision is generated and mapped to the corresponding patch SIM chip selection instruction. A buffering and retransmission mechanism designed to keep the data link uninterrupted during handover; The chip selection control logic is constructed by integrating the multi-channel priority decision framework, the instruction set, the periodic polling mechanism, the fuzzy comprehensive evaluation algorithm, the patch SIM chip selection instruction, and the caching and retransmission mechanism.

3. The micro communication card structure design method based on multi-standard fusion according to claim 1, characterized in that, The process of obtaining a printed circuit board design based on the circuit schematic includes: Based on the length, width, and thickness constraints of a standard SIM card, the external boundary dimensions of the printed circuit board are determined to obtain a board external constraint model. According to the standard SIM card contact position specification, the communication contact area and contact lead-out path are defined on the substrate shape constraint model to obtain the contact layout model. Based on the connection relationship between the MCU and each of the surface mount SIM chips in the circuit schematic, the clock signal lines, reset signal lines and data signal lines from the MCU to each surface mount SIM chip are designed to be of equal length, so that the length deviation of each corresponding signal line is within a preset error range, so as to obtain an equal length signal wiring model. Based on the equal-length signal wiring model, electrical isolation spacing or grounding isolation structure is set between adjacent signal lines to obtain the printed circuit board design.

4. The micro communication card structure design method based on multi-standard fusion according to claim 1, characterized in that, The construction process of the semi-finished component layout model includes: Based on the printed circuit board design drawing, determine the location of the central control area of ​​the MCU on the printed circuit board; Based on the chip selection control logic, the functional connection priority of each of the patch SIM chips relative to the MCU is determined, and the positions of each patch SIM chip are arranged according to the functional connection priority. Based on the principles of minimizing the signal path length between each surface-mount SIM chip and the MCU, and minimizing electromagnetic interference, the spatial distribution of each surface-mount SIM chip is optimized. Based on the electrical connection relationship between the matching element and the corresponding patch SIM chip, the matching element is placed in the vicinity of the corresponding patch SIM chip to obtain the layout model of the semi-finished component.

5. The micro communication card structure design method based on multi-standard fusion according to claim 1, characterized in that, The firmware construction process includes: Based on the chip selection control logic, a network quality parameter acquisition module is constructed for collecting communication status parameters of each of the patch SIM chips; a chip selection decision module is constructed for generating corresponding patch SIM chip selection instructions based on the access suitability score; a chip communication control module is constructed for generating MCU control pin output signals based on the patch SIM chip selection instructions; and a virtual file system interface management module is constructed for realizing data interaction control between the terminal device main control chip and the MCU. The firmware program is constructed by integrating the network quality parameter acquisition module, the chip selection decision module, the chip communication control module, and the virtual file system interface management module.

6. The micro communication card structure design method based on multi-standard fusion according to claim 1, characterized in that, The process of obtaining the firmware logical configuration result includes: Load the firmware program in the virtual simulation environment of the MCU; Construct a virtual patch SIM chip model to simulate the communication status of each patch SIM chip; The data access process of the terminal device's main control chip is simulated based on the virtual file system interface. Verify the correctness of the firmware program's selection control logic for the patch SIM chip to obtain the firmware logic configuration result.

7. The micro communication card structure design method based on multi-standard fusion according to claim 1, characterized in that, The process of constructing a 3D model of a multi-standard integrated packaging structure includes: A three-dimensional structural model of the substrate is constructed based on the printed circuit board design drawing; Based on the semi-finished component layout model, construct a three-dimensional solid model of the MCU, each surface mount SIM chip and matching components; A three-dimensional model of communication contacts was constructed based on the standard SIM card contact specifications. The three-dimensional structural model of the substrate, the three-dimensional solid models of each real-time chip, and the three-dimensional model of the communication contact are spatially assembled to obtain the three-dimensional model of the multi-standard fusion packaging structure.

8. The micro communication card structure design method based on multi-standard fusion according to claim 7, characterized in that, The process of obtaining the packaging structure design results includes: The external structure of the package is constructed based on the aforementioned three-dimensional model; Based on the standard SIM card thickness limit, the height of each component inside the package is constrained and adjusted. Construct a model of the encapsulation material filling region; The outer shape of the package is integrated with the model of the package material filling area to obtain the package structure design result.

9. The micro communication card structure design method based on multi-standard fusion according to claim 2, characterized in that, The construction process of the fuzzy comprehensive evaluation algorithm includes: Establish membership functions for network quality parameters; Construct a business type priority membership function; Construct a fuzzy evaluation matrix based on the membership function; The comprehensive evaluation result of each patch SIM chip is calculated based on the fuzzy evaluation matrix to obtain the access suitability score.

10. The micro communication card structure design method based on multi-standard fusion according to claim 1, characterized in that, The packaging structure design results include: structural definition data of printed circuit board, structural definition data of MCU, structural definition data of surface mount SIM chip, structural definition data of matching components, structural definition data of communication contacts, and structural definition data of package body. Among them, the structural definition data is used to guide the physical manufacturing process of multi-standard converged micro communication card.

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