Digital dimming control device and lighting device

Abstract

This disclosure relates to a digital dimming control device and a lighting device, belonging to the field of lighting control technology; dimming control is achieved by directly adjusting the current output to the load through a digital dimming circuit; the digital dimming control device includes a main power supply circuit, a first conversion circuit, a main control circuit, and a digital dimming circuit; the main power supply circuit is used to convert AC power to DC power, the input terminal of the first conversion circuit is electrically connected to the output terminal of the main power supply circuit, and is used to convert the supply voltage into a first voltage and / or a second voltage; the power supply terminal of the main control circuit is electrically connected to the first output terminal of the first conversion circuit, and is used to generate a digital signal; the power supply terminal of the digital dimming circuit is connected to the second output terminal of the first conversion circuit, the signal input terminal of the digital dimming circuit is connected to the signal output terminal of the main control circuit, and the current output terminal of the digital dimming circuit is used to be electrically connected to the load; the digital dimming circuit is used to receive and decode the digital signal, and adjust the current output to the load.

Description

Technical Field

[0001] This disclosure relates to the field of lighting control technology, and in particular to a digital dimming control device and a lighting device. Background Technology

[0002] With the rapid development of the smart home industry, smart home lighting systems have gradually become a standard feature in modern homes. Users' demands for lighting quality are no longer limited to simple on / off control, but are evolving towards intelligent and personalized features such as dimming and color temperature adjustment, scene linkage, and human-centered lighting. To meet these needs, lighting control systems typically require dimming drive circuits to achieve precise control over the brightness and color temperature of LED lights.

[0003] Currently, in the field of smart home lighting, the mainstream dimming control solutions mainly include two methods. The first is pulse width modulation (PWM) dimming, which works by controlling the periodic on and off of the dimming chip, using the duty cycle to adjust the output power and the brightness of the LED. The second is PWM-to-analog dimming, which converts the pulse width modulation signal into an analog level, and then uses this analog level to control the output current.

[0004] However, for pulse width modulation (PWM) dimming, high-frequency noise is easily generated when the operating frequency is set too low; while increasing the frequency will lead to a decrease in the dimming gray level and a worse dimming effect, and the flicker effect of this method is obvious. Although the PWM-to-analog dimming method has a relatively high operating frequency and the noise problem is improved, the output current is prone to jitter under low brightness dimming conditions, resulting in unstable dimming in the low brightness range. Summary of the Invention

[0005] In order to solve the above-mentioned technical problems, or at least partially solve the above-mentioned technical problems, this disclosure provides a digital dimming control device and a lighting device.

[0006] In a first aspect, this disclosure provides a digital dimming control device. The digital dimming control device includes a main power supply circuit, a first conversion circuit, a main control circuit, and a digital dimming circuit. The main power supply circuit converts alternating current (AC) to direct current (DC) to provide a power supply voltage to the load. The input terminal of the first conversion circuit is electrically connected to the output terminal of the main power supply circuit, and is used to convert the power supply voltage into a first voltage and / or a second voltage. The power supply terminal of the main control circuit is electrically connected to the first output terminal of the first conversion circuit, and is used to generate a digital signal. The power supply terminal of the digital dimming circuit is connected to the second output terminal of the first conversion circuit, the signal input terminal of the digital dimming circuit is connected to the signal output terminal of the main control circuit, and the current output terminal of the digital dimming circuit is electrically connected to the load. The digital dimming circuit receives and decodes the digital signal, and adjusts the current output to the load.

[0007] Compared with the prior art, the technical solution provided in this disclosure has the following beneficial technical effects: The main control circuit generates digital signals and transmits them to the digital dimming circuit. The digital dimming circuit directly receives and decodes these digital signals to adjust the current output to the load. This replaces the indirect adjustment mode of controlling the switching transistor to turn on and off through the duty cycle in the traditional PWM dimming method. As a result, the adjustment process of the output current no longer depends on periodic switching action, avoiding flickering and high-frequency noise caused by the resonance between the PWM switching frequency and the load. This further improves the visual and auditory comfort during the dimming process.

[0008] Meanwhile, since the dimming control is driven directly by digital signals throughout the process, there is no need to convert digital signals to analog signals for transition. This eliminates the current jitter problem in the low brightness range caused by the limited conversion accuracy in the PWM to analog scheme, and achieves stable output across the entire dimming range. Furthermore, the digital dimming circuit directly regulates the current, eliminating the need for external components such as power inductors in the switching power supply. This simplifies the circuit structure, reduces the risk of electromagnetic interference, and improves the overall reliability and applicability of the system.

[0009] In some embodiments, a second conversion circuit is further included; the input terminal of the second conversion circuit is electrically connected to the signal output terminal of the main control circuit, the output terminal of the second conversion circuit is electrically connected to the signal input terminal of the digital dimming circuit, and the power supply terminal of the second conversion circuit is electrically connected to the first output terminal of the first conversion circuit; the second conversion circuit is configured to perform level adaptation on the signal output by the main control circuit, so that the signal level received by the signal input terminal of the digital dimming circuit matches the operating voltage of the digital dimming circuit.

[0010] In some embodiments, the second conversion circuit includes: a plurality of first switching transistors; the control terminal of each first switching transistor is the power supply terminal of the second conversion circuit, the first terminal of each first switching transistor is electrically connected to a signal output terminal of the main control circuit, and the second terminal of each first switching transistor is electrically connected to a signal input terminal of the digital dimming circuit.

[0011] In some embodiments, the second conversion circuit includes: a plurality of first resistors and a plurality of second resistors; a first end of the first resistor is the power supply terminal of the second conversion circuit, and a second end of one of the first resistors is electrically connected to the control terminal of one of the first switching transistors; a first end of the second resistor is the power supply terminal of the second conversion circuit, and a second end of one of the second resistors is electrically connected to the first end of one of the first switching transistors.

[0012] In some embodiments, the digital dimming circuit includes: a digital dimming chip; the digital dimming chip includes: a clock signal input terminal, an enable signal input terminal, and a data signal input terminal; the clock signal input terminal, enable signal input terminal, and data signal input terminal of the digital dimming chip are all signal input terminals of the digital dimming circuit; the power supply terminal of the digital dimming chip is the power supply terminal of the digital dimming circuit; the output terminal of the digital dimming chip is the output terminal of the digital dimming circuit.

[0013] In some embodiments, the digital dimming control device includes a plurality of digital dimming circuits; the signal output terminal of the main control circuit includes a clock signal output terminal, an enable signal output terminal, and a data signal output terminal; the clock signal input terminals of all the digital dimming circuits are connected to the clock signal output terminal of the main control circuit, the enable signal input terminals of all the digital dimming circuits are connected to the enable signal output terminal of the main control circuit, and the data signal input terminal of each digital dimming circuit is independently connected to one data signal output terminal of the main control circuit.

[0014] In some embodiments, the plurality of digital dimming circuits include: a first digital dimming circuit and a second digital dimming circuit; the data signal output terminal of the main control circuit includes a first data signal output terminal and a second data signal output terminal; The power supply terminal of the first digital dimming circuit is electrically connected to the power supply terminal of the second digital dimming circuit. The clock signal input terminal of the first digital dimming circuit is electrically connected to the clock signal input terminal of the second digital dimming circuit. The enable signal input terminal of the first digital dimming circuit is electrically connected to the enable signal input terminal of the second digital dimming circuit. The data signal input terminal of the first digital dimming circuit is connected to the first data signal output terminal of the main control circuit through the first switching transistor. The data signal input terminal of the second digital dimming circuit is connected to the second data signal output terminal of the main control circuit.

[0015] In some embodiments, the first digital dimming circuit further includes: a plurality of third resistors; the first end of the third resistor is the power supply terminal of the first digital dimming circuit, and the second end of one of the third resistors is electrically connected to the second end of one of the first switching transistors.

[0016] In some embodiments, the second digital dimming circuit includes a second switching transistor; the second conversion circuit further includes a plurality of fourth resistors and a plurality of fifth resistors; the control terminal of the second switching transistor is electrically connected to the second terminal of one of the fourth resistors, the first terminal of the second switching transistor is the data signal input terminal of the second digital dimming circuit, and the second terminal of the second switching transistor is electrically connected to the data signal input terminal of the digital dimming chip; the first terminal of the fourth resistor is the power supply terminal of the second conversion circuit, the first terminal of the fifth resistor is the power supply terminal of the second conversion circuit, and the second terminal of the fifth resistor is electrically connected to the first terminal of the second switching transistor.

[0017] Secondly, this disclosure also provides a lighting device, which includes: a luminaire and a digital dimming control device as provided in some of the above embodiments, wherein the digital dimming control device is electrically connected to the luminaire.

[0018] The lighting device described above has the same structure and beneficial technical effects as the digital dimming control device provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0020] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A structural block diagram of a digital dimming control device provided in an embodiment of this disclosure; Figure 2 A schematic diagram of a main power supply circuit provided in an embodiment of this disclosure; Figure 3 A circuit diagram of a digital dimming control device provided in an embodiment of this disclosure; Figure 4 A circuit diagram of another digital dimming control device provided in an embodiment of this disclosure; Figure 5This is a structural block diagram of a lighting device provided in an embodiment of the present disclosure.

[0022] Among them, 1 is the main power supply circuit; 11 is the first switch sub-circuit; 12 is the second switch sub-circuit; 2 is the first conversion circuit; 3 is the main control circuit; 4 is the digital dimming circuit; 40 is the digital dimming chip; 41 is the first digital dimming circuit; 42 is the second digital dimming circuit; 5 is the second conversion circuit; 100 is the digital dimming control device; 110 is the lamp; 200 is the lighting device; R1 is the first resistor; R2 is the second resistor; R3 is the third resistor; R4 is the fourth resistor; R5 is the fifth resistor; Q1 is the first switching transistor; Q2 is the second switching transistor. Detailed Implementation

[0023] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0024] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0025] With the rapid development of the smart home industry, smart home lighting systems have gradually become a standard feature in modern homes. Users' demands for lighting quality are no longer limited to simple on / off control, but are evolving towards intelligent and personalized features such as dimming and color temperature adjustment, scene linkage, and human-centered lighting. To meet these needs, lighting control systems typically require dimming drive circuits to achieve precise control over the brightness and color temperature of LED lights.

[0026] Currently, in the field of smart home lighting, the mainstream dimming control solutions mainly include two methods. The first is pulse width modulation (PWM) dimming, which works by controlling the periodic on and off of the dimming chip, using the duty cycle to adjust the output power and the brightness of the LED. The second is PWM-to-analog dimming, which converts the PWM signal into an analog level, and then uses this analog level to control the output current.

[0027] However, for pulse width modulation (PWM) dimming, high-frequency noise is easily generated when the operating frequency is set too low; while increasing the frequency will lead to a decrease in the dimming gray level and a worse dimming effect, and the flicker effect of this method is obvious. Although the PWM-to-analog dimming method has a relatively high operating frequency and the noise problem is improved, the output current is prone to jitter under low brightness dimming conditions, resulting in unstable dimming in the low brightness range.

[0028] Furthermore, in terms of color temperature adjustment, existing technologies mainly employ either Cool White / Warm White (CW) or Correlated Color Temperature (CCT) methods. CW adjusts color temperature by separately controlling the duty cycles of the yellow and white light power supplies, while CCT uses one dimming power supply to control brightness and another color temperature chip to control color temperature, achieving a mixed-light effect. Regarding color temperature adjustment, CW suffers from discontinuous color temperature changes during switching, often exhibiting a problem of turning off before brightening, especially noticeable at low brightness levels. CCT, in mixed-light conditions, is prone to high-frequency howling and flickering. Moreover, these existing dimming solutions typically require switching power supply topologies such as buck or boost circuits to achieve power conversion. These circuits inevitably include power inductors and control chips, increasing the complexity of the external circuitry and potentially causing electromagnetic interference.

[0029] To address the above problems, this disclosure provides a digital dimming control device. Figure 1 This is a structural block diagram of a digital dimming control device according to an embodiment of the present disclosure; the digital dimming control device 100 includes: a main power supply circuit 1, a first conversion circuit 2, a main control circuit 3, and a digital dimming circuit 4.

[0030] The main power supply circuit 1 is used to convert AC power into DC power to provide power supply voltage for the load; the input terminal of the first conversion circuit 2 is electrically connected to the output terminal of the main power supply circuit 1, and is used to convert the power supply voltage into a first voltage and / or a second voltage.

[0031] The power supply terminal of the main control circuit 3 is electrically connected to the first output terminal of the first conversion circuit 2 to generate digital signals.

[0032] The power supply terminal of the digital dimming circuit 4 is connected to the second output terminal of the first conversion circuit 2, the signal input terminal of the digital dimming circuit 4 is connected to the signal output terminal of the main control circuit 3, and the current output terminal of the digital dimming circuit 4 is used to connect to the load. The digital dimming circuit 4 is used to receive and decode digital signals and adjust the current output to the load.

[0033] The first conversion circuit 2 is used to convert the power supply voltage output by the main power supply circuit 1 into a first voltage and / or a second voltage. This means that the first conversion circuit 2 can output one or two low-voltage logic voltages according to actual needs, wherein the first voltage is used to power the main control circuit 3 and the second voltage is used to power the digital dimming circuit 4.

[0034] It should be noted that when the main control circuit 3 and the digital dimming circuit 4 have the same operating voltage, the first conversion circuit 2 can output only one voltage to power both of them. In this case, the voltage is used as both the first voltage and the second voltage. When the operating voltages of the two circuits are different, for example, the main control circuit 3 is 3.3V and the digital dimming circuit 4 is 5V, the first conversion circuit 2 will output two different voltages respectively.

[0035] The signal input terminal of the digital dimming circuit 4 is connected to the signal output terminal of the main control circuit 3, and the current output terminal of the digital dimming circuit 4 is used to connect to the load. The digital dimming circuit 4 is used to receive and decode the digital signal, and adjust the current output to the load. Here, decoding refers to the digital dimming circuit 4 parsing the received digital signal into a corresponding current setpoint. It can be understood that each digital code value sent by the main control circuit 3 corresponds to a specific current value, and the digital dimming circuit 4 internally converts this code value into a corresponding analog current output through digital control logic. This decoding process does not involve the generation of PWM signals or duty cycle conversion; instead, it directly maps the digital code value to a current value.

[0036] Directly adjusting the output current to the load means that the digital dimming circuit 4 outputs a stable DC current based on the decoded current setting value. Once set, this current remains unchanged and there is no periodic switching. This is fundamentally different from the principle of generating average current through high-speed switching in the traditional PWM dimming method. The latter actually outputs a high-frequency pulse current, and the brightness of the LED depends on the average value of the pulse, rather than a constant DC value.

[0037] The main control circuit 3 encodes the dimming and color adjustment instructions required by the user into digital signals and sends them to the signal input terminal of the digital dimming circuit 4 through its signal output terminal. After receiving the digital signal, the digital dimming circuit 4 decodes it to obtain the target current value, and then directly adjusts the current output to the LED load based on the target current value.

[0038] The current output terminal of the digital dimming circuit 4 is connected to the negative terminal of the load, and the positive terminal of the load is connected to the power supply voltage output by the main power supply circuit 1. Therefore, the current path of the load is as follows: the current flows from the output terminal of the main power supply circuit 1 through the positive terminal of the load, the negative terminal of the load, the current output terminal of the digital dimming circuit 4, the inside of the digital dimming circuit 4, and finally to ground, forming a complete current loop. The digital dimming circuit 4 controls the conduction degree of its internal current regulator to limit the current flowing through the loop to the target current value, thereby determining the luminous brightness of the LED load.

[0039] Since the main control circuit 3 and the digital dimming circuit 4 directly transmit digital signals, and the digital dimming circuit 4 directly adjusts the output current according to the decoded digital signal, there is no PWM signal generation link in the entire dimming control link, and there is no need to change the output power by adjusting the duty cycle; therefore, the current output terminal of the digital dimming circuit 4 outputs a stable DC current, and there is no periodic switching action between on and off.

[0040] Meanwhile, the digital dimming circuit 4 directly sets the output current value based on the digital code value. The magnitude of the output current is uniquely determined by the digital code value, and there is no accuracy loss or noise interference in the analog signal transmission process. In this embodiment, the digital dimming circuit 4 directly maps the digital code value to the current setting value. The entire mapping relationship is guaranteed by digital control logic, which has good repeatability and consistency. Even in the low brightness range, it can stably output the set current and avoid the problem of low brightness jitter.

[0041] The digital dimming circuit 4 directly regulates the current, which is essentially a linear regulation method. There is no need to set up power inductors, high-frequency switching transistors and other switching power supply components in the power path. In this way, not only is the material cost and circuit board area reduced, but the high-frequency vibration and howling of the magnetic core caused by the power inductor is also eliminated. At the same time, the electromagnetic interference caused by high-frequency switching action in the switching power supply circuit is reduced.

[0042] In one alternative implementation, the load is an LED lamp.

[0043] Reference Figure 2 In one optional embodiment, the main power supply circuit 1 includes: a fuse F1, an inductor L1, a capacitor CX1, a varistor VR1, and an AC / DC unit.

[0044] The first input terminal of the main power supply circuit 1 is connected to the neutral line N, and the second input terminal of the main power supply circuit 1 is connected to the live line L.

[0045] The first input terminal of inductor L1 is electrically connected to the neutral wire N, and the second input terminal of inductor L1 is electrically connected to the second terminal of fuse F1. The first terminal of fuse F1 is electrically connected to the live wire L. The first output terminal of inductor L1 is electrically connected to the first terminal of capacitor, and also to the first terminal of varistor VR1 and the first input terminal of AC / DC unit. The second output terminal of inductor L1 is electrically connected to the second terminal of capacitor CX1, and also to the first terminal of varistor VR1 and the second input terminal of AC / DC unit.

[0046] The fuse provides overcurrent and short-circuit protection. When a large current is generated in the circuit, the fuse blows, cutting off the AC power and preventing fire and damage to components. The inductor is a common-mode inductor, which suppresses common-mode interference on the mains line, prevents the power supply's own switching noise from flowing back into the grid, and meets electromagnetic compatibility requirements. The capacitor is connected between the live and neutral wires to filter out differential-mode high-frequency interference, absorb ripple spikes in the AC input, and smooth the input waveform. The varistor is connected in parallel at the AC input terminal to protect against lightning strikes and grid surges. When a momentary high voltage occurs in the grid (lightning strike, closing surge), the resistance of VR1 decreases sharply, dissipating high-voltage energy and protecting the downstream AC / DC unit from breakdown. The AC / DC unit receives the filtered AC power and integrates a rectifier bridge, switching transformer, PWM control circuit, and feedback voltage regulation circuit to output a stable DC voltage, i.e., the supply voltage, and to provide input power to the subsequent first conversion circuit 2.

[0047] In one alternative implementation, the main power supply circuit 1 may adopt a flyback switching power supply topology, or a buck or boost switching power supply topology.

[0048] In one alternative implementation, the first conversion circuit 2 can be implemented using a low-dropout linear regulator (LDO). When the voltage difference between the supply voltage output by the main power supply circuit 1 and the required first voltage or second voltage is small, the LDO has advantages such as simple circuit, small output ripple, and good EMC characteristics. When the voltage difference is large, the first conversion circuit 2 can also be implemented using a DC-DC buck converter to achieve higher conversion efficiency.

[0049] In one alternative implementation, the main control circuit 3 can be a microcontroller (MCU), a microprocessor (MPU), or an application-specific integrated circuit (ASIC). The main control circuit 3 can have a built-in wireless communication module, such as Bluetooth, Wi-Fi, Zigbee, or a 2.4G proprietary protocol, so that it also has wireless receiving capabilities and can receive control commands from external control terminals, such as mobile phone apps, remote controls, and smart speakers, and generate corresponding digital signals.

[0050] In one optional implementation, the digital dimming circuit 4 can be an integrated circuit chip that integrates digital communication protocol parsing and current drive control. Internally, it may include a digital control core and a digital-to-analog converter module. The digital control core receives and decodes the digital signals sent by the main control circuit 3, and transmits the decoded digital quantity to the digital-to-analog converter module. The digital-to-analog converter module converts the digital quantity into an analog reference voltage or reference current, which is then output by the internal current regulator to determine the corresponding current value.

[0051] In an alternative implementation, when the load requires high power, multiple parallel digital dimming circuits 4 can be configured in the device to expand the output power.

[0052] In one optional implementation, the digital dimming circuit 4 may also integrate a current sampling feedback loop to sample the current value output to the load in real time and compare it with the target value. Based on the comparison result, the output current is dynamically adjusted to eliminate deviations caused by factors such as temperature changes and power supply voltage fluctuations, thereby improving dimming accuracy and stability.

[0053] In summary, this application generates a digital signal through the main control circuit 3 and transmits it to the digital dimming circuit 4. The digital dimming circuit 4 directly receives and decodes this digital signal to adjust the current output to the load. This replaces the indirect adjustment mode of controlling the switching transistor's on and off through the duty cycle in the traditional PWM dimming method. This eliminates the dependence of the output current adjustment process on periodic switching actions, avoiding flickering and high-frequency noise caused by the resonance between the PWM switching frequency and the load, further improving visual and auditory comfort during dimming. Simultaneously, since the dimming control is driven directly by digital signals throughout, there is no need to convert the digital signal to an analog signal for transition. This eliminates the current jitter problem in the low-brightness range caused by limited conversion accuracy in PWM-to-analog schemes, achieving stable output across the entire dimming range. Furthermore, the digital dimming circuit 4 directly adjusts the current, eliminating the need for external components such as power inductors in the switching power supply. This simplifies the circuit structure, reduces the risk of electromagnetic interference, and improves the overall reliability and applicability of the system.

[0054] like Figure 3 As shown, in some embodiments, the digital dimming control device 100 further includes a second conversion circuit 5.

[0055] The input terminal of the second conversion circuit 5 is electrically connected to the signal output terminal of the main control circuit 3, the output terminal of the second conversion circuit 5 is electrically connected to the signal input terminal of the digital dimming circuit 4, and the power supply terminal of the second conversion circuit 5 is electrically connected to the first output terminal of the first conversion circuit 2.

[0056] The second conversion circuit 5 is configured to perform level adaptation on the signal output by the main control circuit 3, so that the signal level received at the signal input terminal of the digital dimming circuit 4 matches the operating voltage of the digital dimming circuit 4.

[0057] Level adaptation refers to adjusting the signal level output by the main control circuit 3 to a level range that the digital dimming circuit 4 can correctly recognize when the high-level voltage value output by the signal output terminal of the main control circuit 3 is inconsistent with the high-level voltage value expected to be received by the digital dimming circuit 4.

[0058] For example, the operating voltage of the main control circuit 3, i.e., the first voltage, is 3.3V, and the high level output by the signal output terminal is 3.3V; while the operating voltage of the digital dimming circuit 4, i.e., the second voltage, is 5V, and the signal input terminal requires the received high level to be close to 5V in order for the internal logic to correctly recognize it as a high level. In this case, if the 3.3V signal output from the main control circuit 3 is directly connected to the 5V signal input terminal of the digital dimming circuit 4, the internal logic of the digital dimming circuit 4 may not reliably recognize the 3.3V level as a high level, thus leading to communication errors or malfunctions.

[0059] The function of the second conversion circuit 5 is to solve the above-mentioned level mismatch problem, so that the main control circuit 3 and the digital dimming circuit 4 can communicate reliably. When the operating voltage of the main control circuit 3 and the operating voltage of the digital dimming circuit 4 are the same, for example, both are 3.3V, the second conversion circuit 5 is not necessary. At this time, the signal output terminal of the main control circuit 3 can be directly connected to the signal input terminal of the digital dimming circuit 4.

[0060] The power supply terminal of the second conversion circuit 5 is connected to the first output terminal of the first conversion circuit 2. This means that the pull-up resistor or other power-required components in the second conversion circuit 5 obtain the required reference voltage or power supply voltage from the first conversion circuit 2 to ensure that the high level of the output terminal can reach the voltage value expected by the digital dimming circuit 4.

[0061] In this embodiment, the main control circuit 3 generates a digital signal containing dimming and color adjustment instructions and sends it to the second conversion circuit 5 through its signal output terminal. The second conversion circuit 5 performs level adaptation on the received digital signal and sends the adapted signal to the signal input terminal of the digital dimming circuit 4 through its output terminal. The digital dimming circuit 4 receives the level-adapted signal and decodes it, and directly adjusts the current output to the load according to the decoding result.

[0062] Because of the second conversion circuit 5, the main control circuit 3 and the digital dimming circuit 4 can operate independently at their respective preferred operating voltages, without having to select devices with specific voltage specifications to accommodate the other's level requirements.

[0063] For example, the main control circuit 3 can be a low-power microcontroller powered by 3.3V to reduce power consumption; the digital dimming circuit 4 can be a driver chip powered by 5V to obtain a wider driving voltage range and better current driving capability.

[0064] The second conversion circuit 5 completes the level matching between the two, enabling circuit modules in different voltage domains to work together reliably. In this embodiment, the second conversion circuit 5 achieves flexible matching between different voltage domains without sacrificing the low power consumption advantage of the main control circuit 3 or the driving capability advantage of the digital dimming circuit 4 for the sake of level compatibility. This expands the range of optional components and reduces the system design cost.

[0065] Simultaneously, the power supply terminal of the second conversion circuit 5 is connected to the first output terminal of the first conversion circuit 2, meaning that the reference voltage during the level adaptation process originates from the first voltage output by the first conversion circuit 2. Since the first conversion circuit 2 provides power to the main control circuit 3 while also providing a reference voltage to the second conversion circuit 5, the high-level voltage output by the main control circuit 3 and the reference voltage of the second conversion circuit 5 share the same source, for example, both being 3.3V. This allows the second conversion circuit 5 to accurately use the output level of the main control circuit 3 as the judgment benchmark, avoiding level determination offsets caused by different reference voltage sources, and ensuring the accuracy and consistency of level adaptation.

[0066] Reference Figure 3 In some embodiments, the second conversion circuit 5 includes a plurality of first switching transistors Q1.

[0067] The control terminal of each first switch Q1 is the power supply terminal of the second conversion circuit 5. The first terminal of each first switch Q1 is electrically connected to a signal output terminal of the main control circuit 3, and the second terminal of each first switch Q1 is electrically connected to a signal input terminal of the digital dimming circuit 4.

[0068] The control terminal is the power supply terminal of the second conversion circuit 5, which means that the control terminal of each first switching transistor Q1 is electrically connected to the power supply terminal of the second conversion circuit 5, that is, the control terminal receives the first voltage output from the first conversion circuit 2.

[0069] Since the first voltage is also used to power the main control circuit 3, the voltage value of the main control circuit 3 when it outputs a high level is equal to the voltage value of the control terminal, for example, both are 3.3V.

[0070] The first terminal of each first switch Q1 is electrically connected to a signal output terminal of the main control circuit 3, meaning that each signal output terminal of the main control circuit 3 is connected to the first terminal of a corresponding first switch Q1. For example, when there is multiple signal transmission between the main control circuit 3 and the digital dimming circuit 4, such as clock signals, enable signals, and data signals, each signal output terminal of the main control circuit 3 is connected to the first terminal of a corresponding first switch Q1; it can be understood that the number of first switches Q1 is the same as the number of signals output by the main control circuit 3 to the digital dimming circuit 4.

[0071] The second terminal of each first switching transistor Q1 is electrically connected to a signal input terminal of the digital dimming circuit 4. This means that the second terminal of each first switching transistor Q1 is connected to a corresponding signal input terminal of the digital dimming circuit 4, and the voltage at the second terminal is the voltage actually received by the signal input terminal of the digital dimming circuit 4.

[0072] For example, the high-level voltage output by the main control circuit 3 is 3.3V, and the digital dimming circuit 4 needs to receive a 5V high-level signal to work; the first switching transistor Q1 is an NMOS transistor, and the control terminal (gate) is connected to a fixed voltage of 3.3V.

[0073] When the main control circuit 3 outputs a high level of 3.3V at the signal output terminal, the first terminal (source) potential of the first switching transistor Q1 is 3.3V, and the control terminal (gate) potential is 3.3V. The two voltages are equal, that is, Vgs=Vg-Vs=3.3V-3.3V=0, and the first switching transistor Q1 is in the off state.

[0074] Since the first switching transistor Q1 is turned off, the potential of the second terminal, i.e. the drain, of the first switching transistor Q1 is determined by other components on the side of the digital dimming circuit 4. A pull-up resistor can be provided on the side of the digital dimming circuit 4. This pull-up resistor pulls the signal input terminal high to the operating voltage 5V of the digital dimming circuit 4. Therefore, the potential of the second terminal is pulled high to 5V, and the signal input terminal of the digital dimming circuit 4 receives a 5V high level.

[0075] When the main control circuit 3 outputs a low level of 0V, the potential of the first terminal of the first switching transistor Q1, i.e., the source, is 0V, and the potential of the control terminal of the first switching transistor Q1, i.e., the gate, is 3.3V. Vgs = Vg - Vs = 3.3V - 0V = 3.3V, so the first switching transistor Q1 is turned on. The second terminal of the first switching transistor Q1, i.e., the drain, is connected to the first terminal (source) through the turned-on first switching transistor Q1, and the potential is pulled down to close to 0V. The signal input terminal of the digital dimming circuit 4 receives a low level.

[0076] In this embodiment, the digital signal generated by the main control circuit 3 is transmitted to the first terminal of the first switching transistor Q1 via the signal output terminal. The control terminal of the first switching transistor Q1 is connected to a fixed first voltage, i.e., the power supply terminal of the second conversion circuit 5. When the signal output terminal of the main control circuit 3 outputs a high level, since the high-level voltage is equal to the control terminal voltage, the first switching transistor Q1 is turned off, and the signal input terminal of the digital dimming circuit 4 is pulled up to its own operating voltage, i.e., the second voltage, through the pull-up element, thus being identified as a high level. When the signal output terminal of the main control circuit 3 outputs a low level, the first switching transistor Q1 is turned on, and its second terminal is pulled down to a low level, which is then identified as a low level by the digital dimming circuit 4.

[0077] Since the control terminal of each first switch Q1 is connected to the same fixed voltage, namely the power supply terminal of the second conversion circuit 5, the main control circuit 3 does not need to provide additional control signals. Therefore, the main control circuit 3 only needs to send data according to the normal digital signal output logic, and the first switch Q1 automatically completes the level adaptation. In this embodiment, the first switch Q1 automatically switches its on or off state based entirely on the voltage difference between the output level of the main control circuit 3 and the fixed voltage of the control terminal. The main control circuit 3 does not need to participate in the level adaptation process, which further saves the control resources of the main control circuit 3.

[0078] Meanwhile, since the control terminals of multiple first switching transistors Q1 are connected to the power supply terminal of the second conversion circuit 5, the level adaptation reference of all first switching transistors Q1 is unified, the level conversion direction of multiple signals is consistent, and the delay characteristics are consistent, ensuring that the timing relationship between multiple signals does not shift during the level adaptation process, and ensuring that the communication timing between the main control circuit 3 and the digital dimming circuit 4 is correct.

[0079] In some embodiments, the second conversion circuit 5 includes a plurality of first resistors R1 and a plurality of second resistors R2.

[0080] The first end of the first resistor R1 is the power supply terminal of the second conversion circuit 5, and the second end of the first resistor R1 is electrically connected to the control terminal of the first switch Q1; the first end of the second resistor R2 is the power supply terminal of the second conversion circuit 5, and the second end of the second resistor R2 is electrically connected to the first end of the first switch Q1.

[0081] The first end of the first resistor R1 is the power supply terminal of the second conversion circuit 5, meaning that one end of each first resistor R1 is connected to the power supply terminal of the second conversion circuit 5, that is, connected to the first voltage output by the first conversion circuit 2, so that the other end of the first resistor R1 is pulled up to the first voltage; the second end of the first resistor R1 is connected to the control terminal of the first switching transistor Q1. Therefore, the function of the first resistor R1 is to pull up the control terminal of the first switching transistor Q1 to the first voltage, providing a certain DC bias voltage for the control terminal.

[0082] The first end of the second resistor R2 is the power supply terminal of the second conversion circuit 5, meaning that one end of each second resistor R2 is connected to the power supply terminal of the second conversion circuit 5, which is also connected to the first voltage output by the first conversion circuit 2. The second end of the second resistor R2 is connected to the first end of the first switch Q1, and the first end of the first switch Q1 is also connected to the signal output terminal of the main control circuit 3. Therefore, the second resistor R2 is connected between the power supply terminal and the signal output terminal of the main control circuit 3. The function of the second resistor R2 is to pull the potential of the signal output terminal to the same potential as the power supply terminal, i.e., the first voltage, when the signal output terminal of the main control circuit 3 outputs a high level, so that the voltage of the first end of the first switch Q1 is consistent with the voltage of the control terminal, thereby ensuring that the first switch Q1 is turned off.

[0083] The electrical connection between the second end of a first resistor R1 and the control terminal of a first switch Q1, and the electrical connection between the second end of a second resistor R2 and the first terminal of a first switch Q1, refers to the correspondence between the first resistor R1, the second resistor R2, and the first switch Q1. For each signal, a first resistor R1 and a second resistor R2 are provided. The first resistor R1 is connected to the power supply terminal and the control terminal of the corresponding switch, and the second resistor R2 is connected to the power supply terminal and the first terminal of the corresponding switch. When there are multiple signals, each signal corresponds to a set of first resistor R1, second resistor R2, and first switch Q1, and the signals from different signals are independent of each other.

[0084] For example, the power supply voltage of the second conversion circuit 5 is 3.3V, and the first switching transistor Q1 is an NMOS transistor. The first resistor R1 pulls up the gate of the NMOS transistor to 3.3V, fixing the gate potential at 3.3V. The second resistor R2 is connected between the 3.3V power supply terminal and the source of the NMOS transistor, while the source of the NMOS transistor is simultaneously connected to the signal output terminal of the main control circuit 3. When the main control circuit 3 outputs a high level of 3.3V, the source is also at 3.3V through the internal pull-up or drive of the main control circuit 3. At this time, the gate voltage and the source voltage are equal, the gate-source voltage Vgs = 0V, and the NMOS transistor is turned off. When the main control circuit 3 outputs a low level of 0V, the source is pulled down to 0V by the main control circuit 3, while the gate is maintained at 3.3V through the first resistor R1. At this time, the gate-source voltage Vgs = 3.3V, which is greater than the threshold voltage of the NMOS transistor, and the NMOS transistor is turned on.

[0085] In this embodiment, the first resistor R1 pulls up the control terminal of the first switch Q1 to the power supply voltage of the second conversion circuit 5, so that the control terminal obtains a certain fixed potential, avoiding the uncertain level state that may occur due to the control terminal being floating, and ensuring that the first switch Q1 can reliably switch between the on and off states according to the change of its first terminal voltage; the second resistor R2 is connected between the power supply terminal of the second conversion circuit 5 and the first terminal of the first switch Q1. When the signal output terminal of the main control circuit 3 outputs a high level, the second resistor R2 pulls up the potential of the signal output terminal to the same potential as the power supply terminal, so that the potential of the first terminal of the first switch Q1 is consistent with the potential of the control terminal, ensuring that the first switch Q1 is in the off state; when the signal output terminal of the main control circuit 3 outputs a low level, since the signal output terminal of the main control circuit 3 has sufficient pull-down drive capability, the presence of the second resistor R2 will not affect the node being pulled down to a low level state. At this time, there is a voltage difference between the control terminal and the first terminal of the first switch Q1, and the first switch Q1 is turned on.

[0086] One end of the first resistor R1 and the second resistor R2 are both connected to the same power supply terminal of the second conversion circuit 5. This power supply terminal is from the same source as the power supply voltage of the main control circuit 3. Therefore, the voltage reference on the first resistor R1 and the second resistor R2 is from the same source as the high-level voltage output by the main control circuit 3. This embodiment ensures through the same source design that under any operating condition, when the main control circuit 3 outputs a high level, the voltage at the first terminal of the first switch Q1 is the same as the voltage at the control terminal, so that the first switch Q1 is turned on only when the main control circuit 3 outputs a low level and turned off when it outputs a high level.

[0087] Meanwhile, the first resistor R1 and the second resistor R2 work together. The first resistor R1 is used to ensure the voltage stability of the control terminal, and the second resistor R2 is used to ensure that the first terminal can reach the same voltage as the control terminal when the main control circuit 3 outputs a high level. This makes the conduction and turn-off state of the first switch Q1 determined only by the output level of the main control circuit 3, and will not be affected by factors such as the control terminal or the first terminal being floating, leakage current, or noise interference, further improving the circuit's working stability and anti-interference capability.

[0088] In one optional implementation, the resistance value of the first resistor R1 can be selected between 10kΩ and 100kΩ, so that the control terminal obtains sufficient pull-up strength while avoiding excessive static power consumption.

[0089] In one optional implementation, the resistance value of the second resistor R2 can be selected between 1kΩ and 10kΩ, so that when the main control circuit 3 outputs a high level, it can quickly pull up the first terminal to the same potential as the control terminal.

[0090] In one optional implementation, the second conversion circuit 5 may include the same number of first switching transistors Q1 as the number of signal paths output by the main control circuit 3, and a corresponding number of first resistors R1 and second resistors R2. For example, there may be three signal transmissions between the main control circuit 3 and the digital dimming circuit 4: a clock signal, an enable signal, and a data signal; the second conversion circuit 5 includes three sets of first switching transistors Q1 and corresponding first resistors R1 and second resistors R2, respectively, to perform level adaptation for these three signals. The level adaptation principle for each signal is the same as described for a single signal above.

[0091] In some embodiments, the digital dimming circuit 4 includes a digital dimming chip 40; the digital dimming chip 40 includes a clock signal input terminal CLK4, an enable signal input terminal EN4, and a data signal input terminal DATA4.

[0092] The clock signal input terminal CLK4, enable signal input terminal EN4, and data signal input terminal DATA4 of the digital dimming chip 40 are all signal input terminals of the digital dimming circuit 4; the power supply terminal of the digital dimming chip 40 is the power supply terminal of the digital dimming circuit 4; and the output terminal of the digital dimming chip 40 is the output terminal of the digital dimming circuit 4.

[0093] The clock signal input terminal CLK4 refers to the pin of the digital dimming chip 40 used to receive the clock signal issued by the main control circuit 3. This clock signal is a periodic square wave signal used to provide a synchronous beat for data transmission.

[0094] The enable signal input terminal EN4 refers to the pin of the digital dimming chip 40 used to receive the enable signal issued by the main control circuit 3. This enable signal is used to control the working state of the digital dimming chip 40. When the enable signal is active, such as active high, the digital dimming chip 40 is activated and enters the normal working state, and can respond to clock signals and data signals. When the enable signal is inactive, the digital dimming chip 40 enters the sleep, standby or reset state.

[0095] The data signal input terminal DATA4 refers to the pin of the digital dimming chip 40 used to receive the data signal sent by the main control circuit 3. This data signal carries the digital code value containing dimming and color adjustment instructions.

[0096] The clock signal input terminal CLK4, the enable signal input terminal EN4, and the data signal input terminal DATA4 are all signal input terminals of the digital dimming circuit 4. This means that the digital dimming circuit 4, as a functional module, has an external signal interaction interface composed of the above three input pins of the digital dimming chip 40. The main control circuit 3 communicates with the digital dimming chip 40 through these three pins. The enable signal is used to control the activation state of the chip, the clock signal is used to synchronize data transmission, and the data signal is used to carry specific dimming and color adjustment instructions.

[0097] In an optional implementation, the digital dimming chip 40 may further include a first current output pin and a second current output pin, which are respectively used to connect to the negative terminals of the first LED load and the second LED load. The two output channels can be controlled independently, that is, the main control circuit 3 can set the output current of the first current output pin and the second current output pin respectively by sending different digital code values, thereby realizing independent dimming or color mixing of the two LED loads.

[0098] In this embodiment, the main control circuit 3 is connected to the clock signal input terminal, enable signal input terminal, and data signal input terminal of the digital dimming chip 40 through its signal output terminal. The main control circuit 3 first sets the enable signal to an active level, and the digital dimming chip 40 enters normal operation in response to the active level. Then, the main control circuit 3 generates a periodic square wave signal at the clock signal output terminal and synchronously sends out a data bit at the data signal output terminal at each edge of the square wave signal. The digital dimming chip 40 latches the level value at the data signal input terminal at the edge of the clock signal. After several clock cycles, the digital dimming chip 40 receives a complete data code value. After the data code value is decoded internally by the digital dimming chip 40, it is converted into the corresponding current setting value and outputs the corresponding current to the LED load through its current output terminal.

[0099] The digital dimming chip 40 is equipped with an independent enable signal input terminal. The main control circuit 3 can set the enable signal to an invalid level when dimming output is not needed, so that the digital dimming chip 40 enters a sleep or standby state, thereby reducing the power consumption of the entire device during standby. This ensures the timeliness of dimming response and effectively reduces standby power consumption, making it particularly suitable for intelligent lighting scenarios that require long standby or intermittent operation.

[0100] Because independent clock and data input terminals are provided, the timing of data transmission is clearly defined by the clock signal. Each bit of data sent by the main control circuit 3 is synchronized with the edge of the clock signal, and the digital dimming chip 40 latches the data at the clock edge, thereby avoiding data misalignment or bit errors caused by mismatched data transmission rates or timing deviations. Compared to schemes that do not have independent clock signals and rely on asynchronous data transmission, this embodiment achieves synchronous serial communication between the main control circuit 3 and the digital dimming chip 40 by introducing a clock signal, significantly improving the reliability and accuracy of data transmission.

[0101] like Figure 4 As shown, in some embodiments, the digital dimming control device 100 includes a plurality of digital dimming circuits 4; the signal output terminals of the main control circuit 3 include a clock signal output terminal CLK, an enable signal output terminal EN, and a data signal output terminal DATA.

[0102] The clock signal input terminal CLK4 of all digital dimming circuits 4 is connected to the clock signal output terminal CLK of the main control circuit 3. The enable signal input terminal EN4 of all digital dimming circuits 4 is connected to the enable signal output terminal EN of the main control circuit 3. The data signal input terminal DATA4 of each digital dimming circuit 4 is independently connected to one data signal output terminal DATA of the main control circuit 3.

[0103] The clock signal input terminal CLK4 of all digital dimming circuits 4 is connected to the clock signal output terminal CLK of the main control circuit 3. This means that the clock signal output terminal CLK of the main control circuit 3 is simultaneously connected to the clock signal input terminal CLK4 of each digital dimming circuit 4 via a signal line, i.e., multiple digital dimming circuits 4 share the same clock signal. In this connection method, the clock signal issued by the main control circuit 3 arrives at all digital dimming circuits 4 simultaneously, and all digital dimming circuits 4 synchronously sample data under the control of this clock signal.

[0104] The connection between the enable signal input terminal EN4 of all digital dimming circuits 4 and the enable signal output terminal EN of the main control circuit 3 means that the enable signal output terminal EN of the main control circuit 3 is simultaneously connected to the enable signal input terminal EN4 of each digital dimming circuit 4 via a signal line. In other words, multiple digital dimming circuits 4 share the same enable signal. Under this connection method, the enable signal issued by the main control circuit 3 simultaneously acts on all digital dimming circuits 4, and all digital dimming circuits 4 are simultaneously activated or simultaneously deactivated. This can be understood as the enable signal also being a broadcast signal; the main control circuit 3 uses a single enable signal to uniformly control the operating state of all digital dimming circuits 4.

[0105] Each digital dimming circuit 4's data signal input terminal DATA4 is independently connected to a data signal output terminal DATA of the main control circuit 3. This means the main control circuit 3 has multiple data signal output terminals DATA, each connected to a corresponding digital dimming circuit 4's data signal input terminal DATA4. Different digital dimming circuits 4 have their own independent signal transmission paths with the main control circuit 3. Unlike the broadcast connection of clock and enable signals, the data signals use a point-to-point independent connection, allowing the main control circuit 3 to send different data content to each digital dimming circuit 4. The number of data signal input terminals is the same as the number of digital dimming circuits 4. For example, when the digital dimming control device 100 includes n digital dimming circuits 4, the main control circuit 3 has correspondingly n data signal output terminals DATA, each connected to a digital dimming circuit 4's data signal input terminal DATA4.

[0106] In one optional embodiment, when the digital dimming control device 100 includes a plurality of digital dimming circuits 4, the output terminal of each digital dimming circuit 4 can be connected to a plurality of LED loads one by one; for example, the output terminal of the first digital dimming circuit 41 is connected to the first LED load, the output terminal of the second digital dimming circuit 42 is connected to the second LED load, and so on.

[0107] Meanwhile, the main control circuit 3 can send different digital code values ​​to each digital dimming circuit 4 to make each LED load present different brightness or color temperature, thereby realizing multi-channel independent dimming or multi-zone lighting control.

[0108] In one alternative implementation, multiple digital dimming circuits 4 can be packaged into a multi-channel structure within the same chip, meaning that a single digital dimming chip 40 integrates multiple current output channels, each with independent data receiving logic and a current regulator. This implementation is equivalent to integrating multiple digital dimming circuits 4 into a single package, but the channels still share a clock and enable, and have independent data inputs; its operating principle is the same as in this embodiment.

[0109] In this embodiment, the clock signal output from the clock signal output terminal of the main control circuit 3 is simultaneously received by all digital dimming circuits 4, and the enable signal output from the enable signal output terminal acts simultaneously on all digital dimming circuits 4. The data signal is sent from each data output terminal of the main control circuit 3 to the corresponding digital dimming circuit 4. During operation, the main control circuit 3 first sets the enable signal to an active level, and all digital dimming circuits 4 are simultaneously activated and enter the working state. Then, the main control circuit 3 generates a periodic square wave signal at the clock signal output terminal, and all digital dimming circuits 4 synchronously prepare to receive data under the control of the clock signal. The main control circuit 3 sends digital signals containing dimming and color adjustment instructions to the corresponding digital dimming circuits 4 through each data output terminal. Each digital dimming circuit 4 receives and decodes the digital signal from its own data input terminal, and adjusts the current output to the load according to the decoding result.

[0110] The clock signal and enable signal adopt a shared connection method, and the clock signal and enable signal received by all digital dimming circuits 4 are completely synchronized. There is no timing deviation caused by signal path differences, which ensures that multiple digital dimming circuits 4 work together under a unified timing reference.

[0111] Because the data signals are connected independently, each digital dimming circuit 4 can receive independent dimming and color temperature commands from the main control circuit 3. The main control circuit 3 can send different brightness codes or color temperature commands to different digital dimming circuits 4, so that each digital dimming circuit 4 can independently control the current of the LED load connected to it. Multiple digital dimming circuits 4 share the same clock and the same enable, and due to the independence of the data signals, each digital dimming circuit 4 can output a different current value than other circuits.

[0112] Meanwhile, when the maximum output power of a single digital dimming circuit 4 is insufficient to meet the load requirements, the total power can be shared by increasing the number of digital dimming circuits 4. Each digital dimming circuit 4 is responsible for driving a portion of the LED load, and the total output power is the sum of the output power of each digital dimming circuit 4, thereby meeting the needs of high-power lighting scenarios without the need to redesign the main control circuit 3, reducing the difficulty and cost of power expansion.

[0113] Reference Figure 4 In some embodiments, the multiple digital dimming circuits 4 include: a first digital dimming circuit 41 and a second digital dimming circuit 42; the data signal output terminal of the main control circuit 3 includes a first data signal output terminal and a second data signal output terminal.

[0114] The power supply terminal of the first digital dimming circuit 41 is electrically connected to the power supply terminal of the second digital dimming circuit 42. The clock signal input terminal of the first digital dimming circuit 41 is electrically connected to the clock signal input terminal of the second digital dimming circuit 42. The enable signal input terminal of the first digital dimming circuit 41 is electrically connected to the enable signal input terminal of the second digital dimming circuit 42. The data signal input terminal of the first digital dimming circuit 41 is connected to the first data signal output terminal of the main control circuit 3 through the first switching transistor Q1. The data signal input terminal of the second digital dimming circuit 42 is connected to the second data signal output terminal of the main control circuit 3.

[0115] The power supply terminal of the first digital dimming circuit 41 is electrically connected to the power supply terminal of the second digital dimming circuit 42. This means that the power supply pins of the two digital dimming circuits 4 are connected together by wires and are connected to the second output terminal of the first conversion circuit 2. In this connection method, the two digital dimming circuits 4 are powered by the same power supply and their respective power supply voltages are exactly the same. There is no need to set up a separate power supply branch for each digital dimming circuit 4, which simplifies the layout of the power supply line.

[0116] The clock signal input terminal of the first digital dimming circuit 41 is electrically connected to the clock signal input terminal of the second digital dimming circuit 42. This means that the clock signal input pins of the two digital dimming circuits 4 are connected together and are connected to the clock signal output terminal of the main control circuit 3. One clock signal issued by the main control circuit 3 arrives at the clock signal input terminals of the two digital dimming circuits 4 at the same time, and the two digital dimming circuits 4 work synchronously under the same clock beat.

[0117] The enable signal input terminal of the first digital dimming circuit 41 is electrically connected to the enable signal input terminal of the second digital dimming circuit 42, which means that the enable signal input pins of the two digital dimming circuits 4 are connected together and are connected to the enable signal output terminal of the main control circuit 3. One enable signal issued by the main control circuit 3 acts on the two digital dimming circuits 4 at the same time, and the two digital dimming circuits 4 are activated or turned off at the same time.

[0118] The data signal input terminal of the first digital dimming circuit 41 is connected to the first data signal output terminal of the main control circuit 3 via the first switch Q1. This means that the data signal input terminal of the first digital dimming circuit 41 is not directly connected to the first data signal output terminal of the main control circuit 3, but rather connected via the first switch Q1. The first end of the first switch Q1 is connected to the first data signal output terminal of the main control circuit 3, and the second end of the first switch Q1 is connected to the data signal input terminal of the first digital dimming circuit 41. The control terminal is connected to the power supply terminal of the second conversion circuit 5, i.e., the first voltage, for example, 3.3V. The first switch Q1 performs level adaptation on the signal output from the first data signal output terminal of the main control circuit 3, ensuring that the signal level received by the data signal input terminal of the first digital dimming circuit 41 matches the operating voltage of the first digital dimming circuit 41.

[0119] The connection between the data signal input terminal of the second digital dimming circuit 42 and the second data signal output terminal of the main control circuit 3 means that the data signal input terminal of the second digital dimming circuit 42 is directly connected to the second data signal output terminal of the main control circuit 3. In other words, the data signal transmission path of the second digital dimming circuit 42 is a direct connection, and the signal output from the second data signal output terminal of the main control circuit 3 directly enters the data signal input terminal of the second digital dimming circuit 42.

[0120] In this embodiment, the power supply terminals of the first digital dimming circuit 41 and the second digital dimming circuit 42 are interconnected, both receiving the second voltage from the first conversion circuit 2; their clock signal input terminals are interconnected, both receiving the same clock signal from the clock signal output terminal of the main control circuit 3; their enable signal input terminals are interconnected, both receiving the same enable signal from the enable signal output terminal of the main control circuit 3. The data signal input terminal of the first digital dimming circuit 41 is connected to the first data signal output terminal of the main control circuit 3 through the first switch Q1, and the first data signal is input to the first digital dimming circuit 41 after level adaptation by the first switch Q1; the data signal input terminal of the second digital dimming circuit 42 is directly connected to the second data signal output terminal of the main control circuit 3, and the second data signal of the main control circuit 3 is directly input to the second digital dimming circuit 42.

[0121] Since the power supply terminals of the two digital dimming circuits 4 are interconnected, their operating voltages are identical, eliminating the need for separate power supplies with different voltage specifications and simplifying the power distribution network. Because the clock signal input terminals of the two digital dimming circuits 4 are interconnected, they sample data synchronously under the control of the same clock signal. This eliminates data transmission timing differences caused by frequency deviations or phase asynchronies in their respective clock signals, ensuring that the two digital dimming circuits 4 operate collaboratively under a unified timing reference. Furthermore, because the enable signal input terminals of the two digital dimming circuits 4 are interconnected, they are simultaneously activated or deactivated under the control of the same enable signal. The main control circuit 3 can control the operating state of both digital dimming circuits 4 uniformly through a single enable signal, avoiding the need to allocate separate enable control pins for each digital dimming circuit 4.

[0122] Meanwhile, since the data signal input terminal of the first digital dimming circuit 41 is connected to the first data signal output terminal of the main control circuit 3 through the first switch Q1, while the data signal input terminal of the second digital dimming circuit 42 is directly connected to the second data signal output terminal of the main control circuit 3, there is a difference in the data signal transmission path between the two. For the first digital dimming circuit 41, which requires level adaptation through the first switch Q1, the first switch Q1 ensures that the signal level received at its data signal input terminal matches its own operating voltage, enabling the first digital dimming circuit 41 to correctly identify the data sent by the main control circuit 3. For the second digital dimming circuit 42, which does not require level adaptation, its data signal input terminal is directly connected to the data output terminal of the main control circuit 3, which can eliminate one switch and related resistor, saving circuit board area and material costs. This embodiment adapts to the different input signal level requirements of different digital dimming circuits 4 by simultaneously including a data channel with level adaptation through a switch and a directly connected data channel in the same device, without having to unify all data channels to the same connection method, making the design more flexible.

[0123] Since the power supply, clock signal input, and enable signal input terminals of the two digital dimming circuits 4 are all connected in parallel, sharing the same power line, clock signal line, and enable signal line, but their data signal input terminals are independent, the main control circuit 3 can send different digital code values ​​to the two digital dimming circuits 4 through the first and second data signal output terminals, causing the two digital dimming circuits 4 to output different current values, thereby achieving independent control of the two LED loads. For example, the first digital dimming circuit 41 can drive one white LED load, and the second digital dimming circuit 42 can drive one yellow LED load. By sending different digital code values ​​to the two digital dimming circuits 4 respectively, the main control circuit 3 independently controls the current of the two LED loads, achieving continuous adjustment of color temperature.

[0124] In one alternative implementation, the data signal input terminal of the second digital dimming circuit 42 is directly connected to the second data signal output terminal of the main control circuit 3. The operating voltage of the second digital dimming circuit 42 can be matched with the output level of the main control circuit 3 (for example, both are 3.3V), so it can be directly connected without level adaptation.

[0125] In one optional implementation, the outputs of the first digital dimming circuit 41 and the second digital dimming circuit 42 can be connected one-to-one with the two LED loads respectively. In this case, the two LED loads are driven independently by the two digital dimming circuits 4, and the main control circuit 3 controls the different brightness of the two LEDs by sending different digital code values ​​to the two digital dimming circuits 4 respectively. In another implementation, the outputs of the first digital dimming circuit 41 and the second digital dimming circuit 42 can also be connected in parallel to jointly drive the same LED load. In this case, the main control circuit 3 sends the same digital code value to the two digital dimming circuits 4, and the output currents of the two digital dimming circuits 4 are superimposed and supplied to the LED load. The total driving current is the sum of the two, thereby realizing the expansion of the single-channel power.

[0126] Reference Figure 4 In some embodiments, the first digital dimming circuit 41 further includes a plurality of third resistors R3.

[0127] The first end of the third resistor R3 is the power supply terminal of the first digital dimming circuit 41, and the second end of the third resistor R3 is electrically connected to the second end of the first switching transistor Q1.

[0128] The first end of the third resistor R3 is the power supply terminal of the first digital dimming circuit 41. This means that one end of each third resistor R3 is connected to the power supply terminal of the first digital dimming circuit 41, i.e., connected to the second voltage (e.g., 5V) output by the first conversion circuit 2, so that the other end (i.e., the second end) of the third resistor R3 is pulled high to this second voltage. The power supply terminal of the first digital dimming circuit 41 is the power supply pin of the digital dimming chip 40, and the voltage of this pin is the operating voltage of the digital dimming circuit 4, for example, 5V. It can be understood that one end of the third resistor R3 is connected to the VDD pin of the digital dimming chip 40 or a node at the same potential as the VDD pin. In the embodiment where the power supply terminals of the first digital dimming circuit 41 and the second digital dimming circuit 42 are interconnected, one end of the third resistor R3 can also be understood as a common node, which is connected to the power supply terminal of the first digital dimming circuit 41, i.e., connected to the positive terminal of the power supply.

[0129] The second end of a third resistor R3 is electrically connected to the second end of a first switching transistor Q1, meaning that the other end of each third resistor R3 is connected to the second end of a corresponding first switching transistor Q1. Since the second end of the first switching transistor Q1 is at the same node as the data signal input terminal of the digital dimming circuit 4, the third resistor R3 is actually connected between the power supply terminal and the data signal input terminal of the digital dimming circuit 4. When the first switching transistor Q1 is turned off, the third resistor R3 pulls the potential of the data signal input terminal high to the power supply voltage (i.e., the second voltage, for example, 5V) of the digital dimming circuit 4, thereby enabling the data signal input terminal of the digital dimming circuit 4 to receive a high-level signal consistent with its own operating voltage. It can be understood that the third resistor R3 is an implementation of the pull-up resistor in the aforementioned second conversion circuit 5, which works in conjunction with the first switching transistor Q1 to complete the level adaptation function.

[0130] For example, the first switching transistor Q1 is an NMOS transistor. Its control terminal (gate) is connected to the first voltage (e.g., 3.3V) output by the first conversion circuit 2, its first terminal (source) is connected to the data signal output terminal of the main control circuit 3, and its second terminal (drain) is connected to the data signal input terminal of the first digital dimming circuit 41. A third resistor R3 is connected between the power supply terminal (e.g., 5V) of the first digital dimming circuit 41 and the second terminal of the first switching transistor Q1. When the main control circuit 3 outputs a high level (3.3V), the NMOS transistor is turned off, and its second terminal is pulled high to 5V through the third resistor R3, so the data signal input terminal of the first digital dimming circuit 41 receives a 5V high level. When the main control circuit 3 outputs a low level (0V), the NMOS transistor is turned on, and its second terminal is pulled low to 0V, so the data signal input terminal of the first digital dimming circuit 41 receives a low level. Thus, the third resistor R3, in conjunction with the first switching transistor Q1, converts the 3.3V logic signal output by the main control circuit 3 into a 5V logic signal that the first digital dimming circuit 41 can recognize. The "multiple third resistors R3" mentioned here refer to the practice of assigning a corresponding third resistor R3 to each signal when multiple signals exist (e.g., multiple data signals corresponding to multiple digital dimming circuits 4). For example, if the data signal input terminal of the first digital dimming circuit 41 is connected to one data output terminal of the main control circuit 3 via the first switching transistor Q1, then a corresponding third resistor R3 is set between the power supply terminal of the first digital dimming circuit 41 and the second terminal of the first switching transistor Q1. If the data signal input terminal of the second digital dimming circuit 42 is directly connected to another data output terminal of the main control circuit 3, then no corresponding third resistor R3 is needed. Similarly, each data channel that undergoes level adaptation via a switching transistor is assigned a corresponding third resistor R3.

[0131] In this embodiment, the third resistor R3 is connected between the power supply terminal of the first digital dimming circuit 41 and the second terminal of the first switching transistor Q1. The second terminal of the first switching transistor Q1 is also connected to the data signal input terminal of the first digital dimming circuit 41. When the data signal output terminal of the main control circuit 3 outputs a high level, the first switching transistor Q1 is turned off, and the third resistor R3 pulls the second terminal of the first switching transistor Q1 (i.e., the data signal input terminal of the first digital dimming circuit 41) high to the power supply voltage of the first digital dimming circuit 41, so that the data signal input terminal of the first digital dimming circuit 41 receives a high-level signal consistent with its own operating voltage. When the data signal output terminal of the main control circuit 3 outputs a low level, the first switching transistor Q1 is turned on, and the data signal input terminal of the first digital dimming circuit 41 is pulled low to a low-level state, receiving a low-level signal.

[0132] Since the first end of the third resistor R3 is connected to the power supply terminal of the first digital dimming circuit 41, and the voltage of this power supply terminal is the operating voltage of the digital dimming circuit 41 itself (e.g., 5V), when the first switch Q1 is turned off, the potential of the data signal input terminal is pulled up to this operating voltage, which perfectly meets the high-level amplitude requirement of the first digital dimming circuit 41, without relying on other power supplies to provide a high-level reference. Unlike the situation where the high-level amplitude is insufficient due to connecting the pull-up resistor to other power domains (e.g., 3.3V), in this embodiment, the reference voltage of the third resistor R3 is the power supply voltage of the digital dimming circuit 4 itself, ensuring that the high-level amplitude is completely consistent with the operating voltage of the digital dimming circuit 4, avoiding the problem of unreliable logic recognition of the digital dimming circuit 4 due to insufficient high-level amplitude.

[0133] Since the third resistor R3 is located on the side of the first digital dimming circuit 41 and is connected to the second terminal of the first switching transistor Q1, and the second terminal of the first switching transistor Q1 is the signal output terminal after level adaptation, it does not generate additional load on the signal output terminal of the main control circuit 3. Unlike the scheme of setting the pull-up resistor on the side of the main control circuit 3 (in which case the pull-up resistor may increase the load on the signal output terminal of the main control circuit 3 and affect its driving capability), this embodiment sets the third resistor R3 on the side of the first digital dimming circuit 41, so that the signal output terminal of the main control circuit 3 only needs to drive the first terminal of the first switching transistor Q1, without driving the additional pull-up resistor, reducing the load on the signal output terminal of the main control circuit 3 and ensuring the driving margin and signal integrity of the signal output of the main control circuit 3.

[0134] Meanwhile, the third resistor R3 is connected to the second terminal of the first switching transistor Q1, which is also the data signal input terminal of the first digital dimming circuit 41. Therefore, the addition of the third resistor R3 will not affect the conduction state of the first switching transistor Q1. When the first switching transistor Q1 is turned on, its second terminal is connected to the first terminal through the conducting channel, and the data signal input terminal of the first digital dimming circuit 41 is pulled low. At this time, there is a voltage difference across the third resistor R3 (one end is the power supply voltage of the digital dimming circuit 4, and the other end is a low level close to 0V), which will generate a certain static current. However, since the resistance value of the third resistor R3 is appropriately selected (e.g., 10kΩ), this static current is very small and its impact on system power consumption can be ignored.

[0135] In one optional implementation, the resistance value of the third resistor R3 can be selected between 1kΩ and 100kΩ, preferably 10kΩ. Within this resistance range, the third resistor R3 can ensure that the signal input terminal is quickly pulled up to the power supply voltage when the switching transistor is turned off, and can limit the quiescent current to an acceptable range when the switching transistor is turned on.

[0136] In one optional implementation, when there are multiple data signals requiring level adaptation, the number of third resistors R3 is the same as the number of first switching transistors Q1, with each third resistor R3 corresponding to one first switching transistor Q1. For example, when level adaptation of data signals is required for multiple digital dimming circuits 4, a corresponding number of third resistors R3 can be set inside or outside each digital dimming circuit 4. Each third resistor R3 is connected between the power supply terminal of the corresponding digital dimming circuit 4 and the second terminal of the corresponding first switching transistor Q1. The setting method of each third resistor R3 is consistent with that described in this embodiment and will not be repeated here.

[0137] In some embodiments, the second digital dimming circuit 42 includes a second switching transistor Q2; the second conversion circuit 5 further includes a plurality of fourth resistors R4 and a plurality of fifth resistors R5.

[0138] The control terminal of the second switch Q2 is electrically connected to the second terminal of a fourth resistor R4. The first terminal of the second switch Q2 is the data signal input terminal of the second digital dimming circuit 42, and the second terminal of the second switch Q2 is electrically connected to the data signal input terminal of the digital dimming chip 40. The first terminal of the fourth resistor R4 is the power supply terminal of the second conversion circuit 5, the first terminal of the fifth resistor R5 is the power supply terminal of the second conversion circuit 5, and the second terminal of the fifth resistor R5 is electrically connected to the first terminal of the second switch Q2.

[0139] The second digital dimming circuit 42 includes a second switch Q2, meaning that a second switch Q2 is disposed inside the second digital dimming circuit 42 or on its signal transmission path. This second switch Q2 is used to perform level adaptation on the data signal entering the second digital dimming circuit 42. The structure of the second switch Q2 is similar to that of the first switch Q1; both are controlled switching devices, such as NMOS transistors or NPN transistors. The control terminal of the second switch Q2 is used to receive control signals. Its first terminal is connected to the data signal input terminal of the second digital dimming circuit 42 (i.e., the node connected to the second data signal output terminal of the main control circuit 3), and its second terminal is connected to the data signal input terminal of the digital dimming chip 40. In other words, the signal output from the second data signal output terminal of the main control circuit 3 first enters the first terminal of the second switch Q2, and after adaptation by the second switch Q2, is output from its second terminal to the data signal input terminal of the digital dimming chip 40.

[0140] The control terminal of the second switch Q2 is electrically connected to the second terminal of a fourth resistor R4. This means that the first terminal of the fourth resistor R4 is connected to the power supply terminal of the second conversion circuit 5, i.e., the first voltage output by the first conversion circuit 2, for example, 3.3V, and the second terminal is connected to the control terminal of the second switch Q2. The function of the fourth resistor R4 is to pull up the control terminal of the second switch Q2 to the power supply voltage of the second conversion circuit 5, providing a fixed DC bias voltage to the control terminal and preventing the control terminal from being in an uncertain level state due to floating. It can be understood that the fourth resistor R4 has the same function as the aforementioned first resistor R1, both used to provide a pull-up voltage to the control terminal of the switch.

[0141] The first end of the fourth resistor R4 is the power supply terminal of the second conversion circuit 5. This means that one end of the fourth resistor R4 is connected to the power supply terminal of the second conversion circuit 5. The voltage of this power supply terminal is the first voltage output by the first conversion circuit 2, for example, 3.3V. This voltage also provides the working power to the main control circuit 3 and serves as the reference voltage for the control terminal of the second switching transistor Q2.

[0142] The first end of the fifth resistor R5 is the power supply terminal of the second conversion circuit 5, meaning that one end of the fifth resistor R5 is also connected to the same power supply terminal of the second conversion circuit 5. The second end of the fifth resistor R5 is electrically connected to the first end of the second switch Q2, and the first end of the second switch Q2 is also the data signal input terminal of the second digital dimming circuit 42 (i.e., the node connected to the second data signal output terminal of the main control circuit 3). The fifth resistor R5 is connected between the power supply terminal and the first end of the second switch Q2. Its function is to pull up the potential of this node to the power supply terminal voltage, i.e., the first voltage, such as 3.3V, when the second data signal output terminal of the main control circuit 3 outputs a high level, so that the voltage of the first end of the second switch Q2 is consistent with the control terminal voltage, ensuring that the second switch Q2 is reliably turned off.

[0143] There are multiple fourth resistors R4 and fifth resistors R5, meaning that the second conversion circuit 5 can include multiple sets of fourth resistors R4 and fifth resistors R5, each corresponding to multiple second switching transistors Q2. Each set of fourth resistors R4 and fifth resistors R5 is used for level adaptation of one signal.

[0144] In this embodiment, the second switch Q2 is positioned on the data signal transmission path of the second digital dimming circuit 42. Its control terminal is pulled up to the power supply voltage of the second conversion circuit 5 through the fourth resistor R4, so that its control terminal obtains a fixed DC potential. The fifth resistor R5 is connected between the power supply terminal of the second conversion circuit 5 and the first terminal of the second switch Q2, wherein the first terminal of the second switch Q2 is also the data signal input terminal of the second digital dimming circuit 42, that is, the node connected to the second data signal output terminal of the main control circuit 3.

[0145] When the second data signal output terminal of the main control circuit 3 outputs a high level (the voltage value of this high level is the same as the power supply voltage of the second conversion circuit 5, for example, 3.3V), the voltage of the first terminal of the second switching transistor Q2 is 3.3V, and its control terminal is also maintained at 3.3V through the fourth resistor R4. Since the two voltages are equal, the second switching transistor Q2 is turned off. At this time, the second terminal of the second switching transistor Q2 is pulled high to the operating voltage (for example, 5V) of the digital dimming circuit 4 through the third resistor R3 (as described in the previous embodiment, connected between the power supply terminal and the signal input terminal of the digital dimming chip 40), and the data signal input terminal of the digital dimming chip 40 receives a 5V high level.

[0146] When the second data signal output terminal of the main control circuit 3 outputs a low level (e.g., 0V), the voltage of the first terminal of the second switch Q2 is 0V, and its control terminal is maintained at 3.3V through the fourth resistor R4. There is a voltage difference between the two, the second switch Q2 is turned on, and the second terminal of the second switch Q2 is pulled low to a low level. The data signal input terminal of the digital dimming chip 40 receives a low level.

[0147] Since the control terminal of the second switch Q2 is pulled up to the power supply terminal of the second conversion circuit 5 through the fourth resistor R4, and this power supply terminal is from the same source as the high-level voltage output by the main control circuit 3 (both are the first voltage output by the first conversion circuit 2, for example, 3.3V), when the main control circuit 3 outputs a high level, the voltage at the first terminal of the second switch Q2 is always consistent with the voltage at the control terminal, ensuring that the second switch Q2 is reliably turned off. Unlike designs where the control terminal voltage reference and the power supply voltage of the main control circuit 3 are from different sources (which could lead to misjudgment of the switch's conduction state due to voltage reference differences), this embodiment ensures reliable level adaptation through a design that uses the same source.

[0148] Since the fifth resistor R5 is connected between the power supply terminal of the second conversion circuit 5 and the first terminal of the second switching transistor Q2, when the second data signal output terminal of the main control circuit 3 outputs a high level, the fifth resistor R5 helps to pull the potential of this node up to the power supply voltage, so that the potential of the first terminal of the second switching transistor Q2 can quickly follow the potential change of the control terminal, ensuring that the two voltages are equal, thereby making the second switching transistor Q2 reliably off when the input is high. At the same time, when the main control circuit 3 outputs a low level, since the signal output terminal of the main control circuit 3 has sufficient pull-down drive capability, the presence of the fifth resistor R5 will not affect the node being pulled low to the low level state.

[0149] Simultaneously, the fourth resistor R4 and the fifth resistor R5 work together. The fourth resistor R4 ensures the voltage stability at the control terminal of the second switch Q2, while the fifth resistor R5 ensures that when the main control circuit 3 outputs a high level, the first terminal of the second switch Q2 reaches the same potential as the control terminal. Together, they ensure that the on / off state of the second switch Q2 is determined solely by the output level of the main control circuit 3, and is not affected by factors such as floating, leakage current, or noise interference at the control terminal or the first terminal. This improves the operational stability and anti-interference capability of the level matching circuit.

[0150] In one optional implementation, the value of the fourth resistor R4 can be selected between 10kΩ and 100kΩ to ensure sufficient pull-up strength at the control terminal while avoiding excessive static power consumption. The value of the fifth resistor R5 can be selected between 1kΩ and 10kΩ to ensure that when the main control circuit 3 outputs a high level, the first terminal can be quickly pulled up to the same potential as the control terminal, while preventing difficulty in pulling down the output due to insufficient pull-up resistance when the main control circuit 3 outputs a low level.

[0151] In one alternative implementation, when there are multiple data signals that require level adaptation, the number of the fourth resistor R4, the fifth resistor R5, and the second switch Q2 are the same and correspond one-to-one.

[0152] For example, when level adaptation is required for multiple data signal channels, each channel is equipped with a second switch Q2, a fourth resistor R4, and a fifth resistor R5. The connection method between the channels is consistent with that described in this embodiment, and they work independently without affecting each other.

[0153] For example, the first switching transistor Q1 and the second switching transistor Q2 can be switching devices such as transistors or relays; transistors include, but are not limited to, bipolar junction transistors (BJTs, commonly known as triodes), field effect transistors (FETs), or insulated gate bipolar transistors (IGBTs).

[0154] Among them, field-effect transistors include junction field-effect transistors (JFETs) and metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0155] The specific types of the first switch Q1 and the second switch Q2 can be selected according to actual needs, as long as they meet the requirements. This disclosure does not limit them.

[0156] Some embodiments of this disclosure also provide a lighting device, such as... Figure 5 As shown, the lighting device 200 includes a digital dimming control device 100 and a luminaire 110, with the luminaire 110 electrically connected to the digital dimming control device 100.

[0157] For example, the luminaire may include at least one semiconductor lighting device, such as an LED (Light Emitting Diode) lamp.

[0158] Lighting devices refer to a general term for products that integrate digital dimming control devices 100 with lamps, such as smart lamps, dimmable LED lamps, and smart lighting equipment.

[0159] The lighting device includes both a digital dimming control device 100 for dimming and color adjustment control and a lamp for emitting light. The lighting device is a combination of the digital dimming control device 100 and the lamp, wherein the digital dimming control device 100 is responsible for control and the lamp is responsible for performing the light emission function.

[0160] The electrical connection between the lamp 110 and the digital dimming control device 100 specifically includes: the positive input terminal of the lamp is connected to the power supply voltage output by the main power supply circuit 1 in the digital dimming control device 100, such as 48V, and the negative output terminal of the lamp is connected to the current output terminal of the digital dimming circuit 4 in the digital dimming control device 100.

[0161] The digital dimming control device 100 is connected in series between the main power supply circuit 1 and the digital dimming circuit 4 to the lamp. The DC current output by the main power supply circuit 1 flows into the digital dimming circuit 4 through the lamp, and then the magnitude of the current is adjusted by the digital dimming circuit 4.

[0162] In this embodiment, the lighting device 200 includes a digital dimming control device 100 and a lamp 110, which is electrically connected to the digital dimming control device 100. The digital dimming control device 100 provides a driving current to the lamp 110 and controls the magnitude of the current. The lamp 110 emits light under the action of the current flowing through its internal LED beads. The main power supply circuit 1 of the digital dimming control device 100 converts AC mains power into DC power supply voltage, which is applied to the positive terminal of the lamp. The main control circuit 3 of the digital dimming control device 100 generates a digital signal containing dimming and color adjustment instructions. The digital dimming circuit 4 of the digital dimming control device 100 receives and decodes the digital signal, and directly adjusts the magnitude of the current flowing through the lamp according to the decoding result. The luminous brightness of the lamp corresponds to the magnitude of the current flowing through its internal LED beads; the larger the current, the brighter the lamp, and the smaller the current, the dimmer the lamp.

[0163] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0164] The term "electrical connection" as used in this article includes both physical and non-physical connections. For example, an electrical connection between A and B can refer to an indirect connection through electromagnetic induction, capacitive coupling, or other similar methods. Alternatively, an electrical connection between A and B can also be a direct conductive path formed through contact between metal wires, cables, connectors, or interface terminals. Furthermore, an electrical connection between A and B can be a direct connection between A and B, or a connection between A and B through other structural elements.

[0165] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A digital dimming control device, characterized in that, include: The main power supply circuit is used to convert AC power into DC power to provide power supply voltage to the load. A first conversion circuit, wherein the input terminal of the first conversion circuit is electrically connected to the output terminal of the main power supply circuit, is used to convert the power supply voltage into a first voltage and / or a second voltage; The main control circuit is electrically connected to the first output terminal of the first conversion circuit and is used to generate digital signals. A digital dimming circuit, wherein the power supply terminal of the digital dimming circuit is connected to the second output terminal of the first conversion circuit, the signal input terminal of the digital dimming circuit is connected to the signal output terminal of the main control circuit, and the current output terminal of the digital dimming circuit is used to be electrically connected to the load. The digital dimming circuit is used to receive and decode the digital signal and adjust the current output to the load.

2. The digital dimming control device according to claim 1, characterized in that, It also includes a second conversion circuit; The input terminal of the second conversion circuit is electrically connected to the signal output terminal of the main control circuit, the output terminal of the second conversion circuit is electrically connected to the signal input terminal of the digital dimming circuit, and the power supply terminal of the second conversion circuit is electrically connected to the first output terminal of the first conversion circuit. The second conversion circuit is configured to perform level adaptation on the signal output by the main control circuit, so that the signal level received at the signal input terminal of the digital dimming circuit matches the operating voltage of the digital dimming circuit.

3. The digital dimming control device according to claim 2, characterized in that, The second conversion circuit includes: a plurality of first switching transistors; The control terminal of each first switch is the power supply terminal of the second conversion circuit, the first terminal of each first switch is electrically connected to a signal output terminal of the main control circuit, and the second terminal of each first switch is electrically connected to a signal input terminal of the digital dimming circuit.

4. The digital dimming control device according to claim 3, characterized in that, The second conversion circuit includes: a plurality of first resistors and a plurality of second resistors; The first end of the first resistor is the power supply terminal of the second conversion circuit, and the second end of the first resistor is electrically connected to the control terminal of the first switching transistor. The first end of the second resistor is the power supply terminal of the second conversion circuit, and the second end of the second resistor is electrically connected to the first end of the first switching transistor.

5. The digital dimming control device according to claim 3, characterized in that, The digital dimming circuit includes a digital dimming chip; the digital dimming chip includes a clock signal input terminal, an enable signal input terminal, and a data signal input terminal. The clock signal input terminal, enable signal input terminal, and data signal input terminal of the digital dimming chip are all signal input terminals of the digital dimming circuit; The power supply terminal of the digital dimming chip is the power supply terminal of the digital dimming circuit. The output terminal of the digital dimming chip is the output terminal of the digital dimming circuit.

6. The digital dimming control device according to claim 5, characterized in that, The digital dimming control device includes multiple digital dimming circuits; the signal output terminals of the main control circuit include a clock signal output terminal, an enable signal output terminal, and a data signal output terminal. The clock signal input terminals of all the digital dimming circuits are connected to the clock signal output terminal of the main control circuit, the enable signal input terminals of all the digital dimming circuits are connected to the enable signal output terminal of the main control circuit, and the data signal input terminal of each digital dimming circuit is independently connected to one data signal output terminal of the main control circuit.

7. The digital dimming control device according to claim 6, characterized in that, The plurality of digital dimming circuits include: a first digital dimming circuit and a second digital dimming circuit; the data signal output terminal of the main control circuit includes a first data signal output terminal and a second data signal output terminal; The power supply terminal of the first digital dimming circuit is electrically connected to the power supply terminal of the second digital dimming circuit, the clock signal input terminal of the first digital dimming circuit is electrically connected to the clock signal input terminal of the second digital dimming circuit, and the enable signal input terminal of the first digital dimming circuit is electrically connected to the enable signal input terminal of the second digital dimming circuit. The data signal input terminal of the first digital dimming circuit is connected to the first data signal output terminal of the main control circuit through the first switching transistor; The data signal input terminal of the second digital dimming circuit is connected to the second data signal output terminal of the main control circuit.

8. The digital dimming control device according to claim 7, characterized in that, The first digital dimming circuit also includes: a plurality of third resistors; The first end of the third resistor is the power supply terminal of the first digital dimming circuit, and the second end of the third resistor is electrically connected to the second end of the first switching transistor.

9. The digital dimming control device according to claim 7, characterized in that, The second digital dimming circuit includes: a second switching transistor; the second conversion circuit further includes: a plurality of fourth resistors and a plurality of fifth resistors; The control terminal of the second switch is electrically connected to the second terminal of the fourth resistor. The first terminal of the second switch is the data signal input terminal of the second digital dimming circuit. The second terminal of the second switch is electrically connected to the data signal input terminal of the digital dimming chip. The first end of the fourth resistor is the power supply terminal of the second conversion circuit, the first end of the fifth resistor is the power supply terminal of the second conversion circuit, and the second end of the fifth resistor is electrically connected to the first end of the second switching transistor.

10. A lighting device, characterized in that, include: The digital dimming control device as described in any one of claims 1-9; The luminaire is electrically connected to the digital dimming control device.

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