Multilayer low dielectric loss impedance flexible circuit board and manufacturing method

Abstract

This invention discloses a multilayer low-displacement flexible printed circuit board and its fabrication method, relating to the field of flexible printed circuit board technology. The flexible circuit board includes a bending region, a non-bending region, and at least one high-speed signal unit. The high-speed signal unit includes a differential signal line layer, a reference ground layer, and a low-displacement modified polymer dielectric layer located between the two. The low-displacement modified polymer dielectric layer includes a main low-displacement layer and an interface anchoring sublayer near the copper foil side. The main low-displacement layer is formed by curing a fluorinated aryl ether imide prepolymer, polyaryl ether resin, and thermally crosslinked monomer. The interface anchoring sublayer contains anchoring functional groups capable of interfacial interaction with the copper foil surface. This invention is beneficial for improving the interfacial bonding stability of low-profile copper foil and enhancing the impedance continuity and process stability of the bending region of the multilayer flexible circuit board.

Description

Technical Field

[0001] This invention relates to the field of flexible printed circuit board technology, specifically to a multilayer low dielectric loss flexible circuit board and its manufacturing method. Background Technology

[0002] Flexible printed circuit boards (FPCBs) are characterized by their thinness, bendability, and three-dimensional wiring capabilities, and are commonly used for high-speed connections, display connections, camera module connections, and wearable device connections within electronic devices. As signal rates increase, factors such as dielectric loss, copper foil surface condition, ground plane structure, variations in dielectric thickness after lamination, and changes in circuit pattern dimensions within multilayer FPCBs can all affect impedance continuity and transmission stability during high-speed differential signal transmission.

[0003] Chinese patent application CN110366330A discloses a method for laminating high-frequency FRCCs with high-frequency PI-type or LCP-type double-sided boards to form three- to six-layer FPCs, wherein the FRCC includes a copper foil layer and an ultra-low dielectric adhesive layer. This method offers insights into low-dielectric adhesive layers, low-profile copper foil, and high-frequency multilayer flexible circuit board structures. However, it primarily focuses on the combined lamination of high-frequency FRCCs with high-frequency double-sided boards, without providing specific designs for interface anchoring between the low-dissipation polymer dielectric layer and the low-profile copper foil, gradient changes in the reference ground aperture ratio in the bending region, and local impedance compensation based on lamination variations and bending radii.

[0004] The invention patent with authorization announcement number CN113133185B discloses a method of creating windows in the adhesive film within the bending area of ​​a multilayer flexible circuit board, and correspondingly placing grounding wires above the bottom layer signal lines to improve the high-frequency signal transmission during bending. This solution offers insights into structural adjustments in bending areas, but it primarily improves the transmission state through adhesive film windows and local grounding wire arrangements. It does not specifically address the gradient grid structure where the reference ground aperture decreases from the bending center to the non-bending area, nor the synergistic relationship between this gradient grid structure and the differential signal line width and spacing compensation sections.

[0005] The invention patent with publication number CN110944452A discloses a method for pre-stretching the inner layer circuit film and cover film in the warp and weft directions according to the materials, compensating for the impedance modules and impedance lines within the unit, and requiring separate impedance value calculations for flexible circuit board materials, cover films, or solder resist inks from different manufacturers due to differences in DK values. This solution is enlightening for impedance control of conventional flexible circuit boards, but its compensation logic mainly revolves around the film, cover film, copper thickness, and DK differences. For cases where the thickness change of low dielectric loss modified polymer film during lamination and curing, warp and weft dimension changes, copper foil surface treatment parameters, and bending zone design radius all affect the differential impedance, there is still a need for further refinement and coupling compensation.

[0006] Therefore, it is necessary to provide a new multilayer low dielectric impedance flexible circuit board and its fabrication method to form a more reasonable matching relationship between the low dielectric layer, the low profile copper foil interface bonding, the bending area reference ground structure and differential impedance compensation. Summary of the Invention

[0007] The purpose of this invention is to provide a multilayer low dielectric loss flexible circuit board and its manufacturing method, which improves the interfacial bonding stability between the low dielectric loss polymer dielectric layer and the low profile copper foil, and reduces the impact of changes in the reference ground structure in the bending area, changes in the thickness of the laminated dielectric, and changes in the pattern size of the signal line on the continuity of differential impedance.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] The present invention provides a multilayer low dielectric loss flexible circuit board, including a bending region, a non-bending region and at least one high-speed signal unit. The high-speed signal unit includes a differential signal line layer, at least one reference ground layer and a low dielectric loss modified polymer dielectric layer located between the differential signal line layer and the reference ground layer.

[0010] The differential signal line layer includes a pair of first signal lines and second signal lines, and the first signal lines, the second signal lines and the reference ground layer constitute a differential impedance transmission channel;

[0011] The low dielectric loss modified polymer dielectric layer includes a main low dielectric loss layer and an interface anchoring sublayer disposed on the side of the main low dielectric loss layer near the copper foil.

[0012] The main low dielectric loss layer is a continuous phase formed by curing fluorinated aryl ether imide prepolymer, polyaryl ether resin and thermally crosslinked monomer;

[0013] The interface anchoring sublayer contains at least one anchoring functional group selected from phosphate ester group, benzotriazole group, imidazole group, catechol group and trialkoxysilyl group;

[0014] The reference grounding layer within the bending region is a grid reference ground, and the opening ratio of the grid reference ground decreases from the bending center region to the non-bending region.

[0015] The first and second signal lines within the bending zone have at least one of a line width compensation segment and a line spacing compensation segment relative to the non-bending zone.

[0016] Furthermore, the high-speed signal unit is a stripline structure or a microstrip line structure;

[0017] When the high-speed signal unit is a stripline structure, the reference ground layer is respectively provided on both sides of the differential signal line layer;

[0018] When the high-speed signal unit is a microstrip line structure, a reference ground layer is provided on one side of the differential signal line layer, and a cover film or shielding film is provided on the other side.

[0019] Furthermore, the interface anchoring sublayer is disposed between the main low-displacement layer and the differential signal line layer, between the main low-displacement layer and the reference ground layer, or simultaneously disposed between the main low-displacement layer and the differential signal line layer and between the main low-displacement layer and the reference ground layer;

[0020] The thickness of the main low dielectric loss layer is 5μm~45μm, and the thickness of the interface anchoring sublayer is 0.1μm~3μm;

[0021] Based on the total amount of solid components in the interface anchoring sublayer, the raw materials of the interface anchoring sublayer include 50 to 95 parts by weight of low polarity film-forming resin, 0.5 to 10 parts by weight of anchoring functional group compound, 0.1 to 8 parts by weight of crosslinking aid, and 0 to 5 parts by weight of coupling agent.

[0022] Furthermore, based on the total amount of solid components in the main low-dielectric-loss layer, the raw materials of the main low-dielectric-loss layer include:

[0023] 40 to 80 parts by weight of fluorinated aryl ether imide prepolymer;

[0024] 5 to 35 parts by weight of polyarylether resin;

[0025] 3 to 20 parts by weight of thermally crosslinked monomer;

[0026] Low dielectric loss inorganic packing: 0-10 parts by weight;

[0027] Additives: 0.1 to 3 parts by weight.

[0028] Furthermore, the fluorinated aryl ether imide prepolymer is obtained by reacting a fluorinated aromatic diamine with an aromatic dianhydride;

[0029] The polyarylene ether resin is selected from at least one of polyphenylene ether, allyl-terminated polyphenylene ether, vinyl-terminated polyphenylene ether, maleimide-terminated polyphenylene ether, polyarylene ether ketone and polyarylene ether sulfone.

[0030] The thermal crosslinking monomer is selected from at least one of benzocyclobutene resin, aromatic monomers containing benzocyclobutene group, bismaleimide, norbornene imide and norbornene anhydride modified monomer;

[0031] The low dielectric loss inorganic filler is selected from at least one of fluorinated hollow silica, fluorinated porous silica, cage-type silsesquioxane, fluorinated boron nitride, and surface-silanized silica.

[0032] Furthermore, the bending area includes a bending center area and transition areas located on both sides of the bending center area;

[0033] The grid reference ground opening ratio in the bending center area is 40%~80%, the grid reference ground opening ratio in the transition area is 20%~60%, and the reference ground layer in the non-bending area is a continuous copper surface or a grid copper surface with an opening ratio of no more than 30%.

[0034] The line width compensation segment varies with the signal line width of the non-bending area by 2μm to 20μm, and the line spacing compensation segment varies with the signal line spacing of the non-bending area by 2μm to 20μm. The line width compensation segment and the line spacing compensation segment are connected to the signal line of the non-bending area through a gradual transition segment.

[0035] This invention also provides a method for manufacturing the above-mentioned multilayer low dielectric loss flexible circuit board, comprising the following steps:

[0036] S1. Mix the fluorinated aryl ether imide prepolymer, polyaryl ether resin, thermal crosslinking monomer, optional low dielectric loss inorganic filler, additives and organic solvent to obtain the main layer adhesive solution.

[0037] S2. Mix a low-polarity film-forming resin, an anchoring functional group compound, a crosslinking aid, an optional coupling agent, and an organic solvent to obtain an interface layer adhesive, wherein the anchoring functional group compound contains at least one anchoring functional group selected from phosphate ester group, benzotriazole group, imidazolium group, catechol group, and trialkoxysilyl group.

[0038] S3. Coat the interface layer adhesive on a low-profile copper foil or release carrier, pre-bake and then coat the main layer adhesive, and dry to obtain a B-order low-dielectric-loss modified polymer film including an interface anchoring sublayer and a main low-dielectric-loss layer.

[0039] S4. Obtain the lamination thickness variation value and warp and weft dimension variation value of the B-order low dielectric loss modified polymer film, and obtain the copper foil thickness, copper foil surface treatment parameters and bending zone design radius.

[0040] S5. Based on the target impedance design value, the laminate thickness variation value, the longitudinal and latitudinal dimension variation value, the copper foil thickness, the copper foil surface treatment parameters, and the bending zone design radius, generate the differential signal line width compensation value, the line spacing compensation value, and the reference ground layer grid opening compensation value; including: establishing a two-dimensional or three-dimensional electromagnetic field model containing the differential signal line width W, line spacing S, dielectric laminate thickness H, dielectric Dk, copper foil thickness T, copper foil roughness correction factor KRz, and reference ground opening ratio G; with the target differential impedance of 100Ω as a constraint, adjust W and S in 1μm steps, and adjust G in 1% steps until the simulated differential impedance deviates from the target value by ≤3Ω; then create an on-board impedance test coupon, and make feedback corrections to W, S, and G for the next batch based on the TDR test results;

[0041] S6. Fabricate a differential signal line layer and a reference ground layer according to the compensated line pattern, and stack and press the B-order low dielectric loss modified polymer film, the differential signal line layer and the reference ground layer together to obtain a multilayer circuit board.

[0042] S7. Drilling, metallizing, covering film lamination, shaping, and impedance testing of the multilayer circuit board are performed on the multilayer circuit board to obtain a multilayer low dielectric loss flexible circuit board.

[0043] 8. A method for manufacturing a multilayer low dielectric loss flexible circuit board according to claim 7, characterized in that, in step S1, the fluorinated aryl ether imide prepolymer is first dissolved in an organic solvent, then polyaryl ether resin is added and stirred, followed by the addition of thermal crosslinking monomer, optional low dielectric loss inorganic filler and additives, and after dispersion, the mixture is filtered and degassed to obtain the main layer adhesive solution.

[0044] In step S2, the low-polarity film-forming resin is first dissolved in an organic solvent, then an anchoring functional group compound and a crosslinking aid are added, and finally an optional coupling agent is added. After stirring, the mixture is filtered to obtain the interface layer adhesive.

[0045] The organic solvent is selected from at least one of N,N-dimethylacetamide, N-methylpyrrolidone, dimethylformamide, cyclohexanone, propylene glycol methyl ether acetate, toluene, and xylene.

[0046] Furthermore, in step S3, the wet film thickness of the interface layer adhesive is 0.5μm~10μm, the pre-baking temperature is 70℃~130℃, and the pre-baking time is 1min~15min;

[0047] The wet film thickness of the main layer adhesive is 10μm to 120μm. Drying is carried out by a stepped heating method, with a drying temperature of 80℃ to 170℃ and a drying time of 5min to 60min.

[0048] Furthermore, prior to step S3, the low-profile copper foil undergoes a surface post-treatment, which includes at least one of plasma treatment, ultraviolet ozone treatment, micro-etching treatment, benzotriazole treatment, and silane coupling treatment.

[0049] In step S6, the lamination and pressing are performed using either rapid pressing or pressure transmission; when using rapid pressing, the pressing temperature is 150℃ to 210℃, and the pressure is 50 kgf / cm². 2 ~150kgf / cm 2 The pressing time is 60s~600s; when using pressure transmission, the pressing temperature is 150℃~190℃, and the pressure is 10kgf / cm. 2 ~80kgf / cm 2 The pressing time is 30 min to 240 min;

[0050] After pressing, a post-curing treatment is performed at a temperature of 180℃~260℃ for a time of 20min~120min.

[0051] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0052] 1. The present invention adopts a layered dielectric structure of a main low dielectric loss layer and an interface anchoring sublayer. The main low dielectric loss layer undertakes the functions of low polarity, low dielectric loss and lamination size stability, while the interface anchoring sublayer undertakes the function of copper foil interface bonding. This layered design avoids uniformly introducing a large number of polar anchoring groups into the entire dielectric layer, which is beneficial to improve the interface bonding stability of low profile copper foil while maintaining high frequency transmission performance.

[0053] 2. The main low dielectric loss layer of the present invention is formed by curing fluorinated aryl ether imide prepolymer, polyaryl ether resin and thermal crosslinking monomer. The fluorinated aryl ether imide structure and polyaryl ether structure are beneficial to reducing the polarity of the dielectric, and the thermal crosslinking monomer is beneficial to forming a stable network after pressing and post-curing. This material combination is beneficial to reducing the excessive flow and subsequent dimensional drift of the B-stage film during the pressing process, thereby reducing the influence of dielectric thickness changes and warp and weft dimension changes on the impedance channel.

[0054] 3. In this invention, the reference grounding layer in the bending area is set as a grid reference ground with an aperture ratio that decreases from the bending center area to the non-bending area. The higher grid aperture ratio in the bending center area can reduce local bending rigidity and copper foil stress concentration, and the decreasing aperture ratio in the transition area can reduce impedance discontinuity caused by abrupt changes in the reference ground structure. When this structure is combined with the linewidth compensation section or the line spacing compensation section, it is beneficial to balance bending reliability and differential impedance continuity.

[0055] 4. The manufacturing method of the present invention incorporates the lamination thickness variation, warp and weft dimension variation, copper foil thickness, copper foil surface treatment parameters, and bending zone design radius of the B-order low dielectric loss modified polymer film into the circuit compensation logic. Compared with conventional compensation methods that rely solely on the dielectric constant of the material or the copper thickness, the present invention can better match the actual process variations of the low dielectric loss modified polymer film and the bending zone structure, which is beneficial to improving impedance consistency and batch production stability. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a schematic diagram of the overall structure of a multilayer low dielectric loss flexible circuit board according to one embodiment of the present invention.

[0058] Figure 2 This is a cross-sectional structural diagram of a high-speed signal unit according to one embodiment of the present invention.

[0059] Figure 3 This is a schematic diagram of the layered structure of a low dielectric loss modified polymer dielectric layer in one embodiment of the present invention.

[0060] Figure 4 This is a schematic diagram of the planar structure of the bending area, transition area and non-bending area in one embodiment of the present invention.

[0061] Figure 5 This is a flowchart illustrating a manufacturing method in one embodiment of the present invention.

[0062] Explanation of reference numerals in the attached diagram: 100, Multilayer low dielectric loss flexible circuit board; 10, Bending area; 11, Bending center area; 12, Transition area; 20, Non-bending area; 30, High-speed signal unit; 31, Differential signal line layer; 311, First signal line; 312, Second signal line; 313, Line width compensation section; 314, Line spacing compensation section; 315, Gradient transition section; 32, Reference ground layer; 321, Grid reference ground; 33, Low dielectric loss modified polymer dielectric layer; 331, Main low dielectric loss layer; 332, Interface anchoring sublayer; 34, Cover film; 35, Shielding film; 36, Metallized via. Detailed Implementation

[0063] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0064] See Figure 1 As shown, the multilayer low dielectric loss flexible circuit board 100 includes a bending region 10, non-bending regions 20 located on both sides of the bending region 10, and high-speed signal units 30 disposed throughout the bending region 10 and non-bending regions 20. The high-speed signal units 30 continuously traverse the bending region 10, enabling high-speed differential signals to maintain a continuous transmission path even when the flexible circuit board is bent. The non-bending regions 20 are used to house connection terminals, pads, or device connection areas, while the bending region 10 is used to accommodate the spatial bending requirements in the overall assembly. By coordinating the high-speed signal units 30 with the bending region 10, this invention not only improves impedance performance in a straight state but also ensures signal stability in a bent state.

[0065] See Figure 2 As shown, the high-speed signal unit 30 includes a differential signal line layer 31, a reference ground layer 32, and a low dielectric loss modified polymer dielectric layer 33 located between the differential signal line layer 31 and the reference ground layer 32 in the thickness direction. The differential signal line layer 31 includes a first signal line 311 and a second signal line 312, which together with the adjacent reference ground layer 32 form a differential impedance transmission channel. Figure 2 Taking a stripline structure with reference ground layers 32 on both sides of the differential signal line layer 31 as an example, this structure helps to ensure that the electromagnetic field is mainly distributed within the low dielectric loss modified polymer dielectric layer 33, and that the reference ground layer 32 provides a stable return path, thereby reducing the impact of external structural disturbances on the differential impedance. In other embodiments, the high-speed signal unit 30 can also be a microstrip line structure with a reference ground layer 32 on one side.

[0066] Furthermore, the cover film 34 covers the outer side of the circuit board to provide insulation and bending protection. The shielding film 35 can be disposed outside the cover film 34 or at an adjacent outer layer position to reduce the impact of external electromagnetic interference on the high-speed signal unit 30. The through-conducting structure shown in the figure can serve as a metallized via 36 to realize electrical connection or grounding connection between different conductive layers. Through the interlayer cooperation of the differential signal line layer 31, the reference ground layer 32, the low dielectric loss modified polymer dielectric layer 33, the cover film 34, and the shielding film 35, the present invention can form a relatively stable high-speed signal transmission environment within the limited thickness of the multilayer flexible circuit board.

[0067] See Figure 3As shown, the low dielectric loss modified polymer dielectric layer 33 includes a main low dielectric loss layer 331 and an interface anchoring sublayer 332 disposed on the main low dielectric loss layer 331 near the copper foil side. The main low dielectric loss layer 331 mainly undertakes the functions of low dielectric constant, low dielectric loss and laminate size stability, while the interface anchoring sublayer 332 mainly undertakes the function of interface enhancement for bonding with the copper foil surface. Figure 3 Taking the example of setting interface anchoring sublayers 332 on both sides of the main low dielectric loss layer 331, in practical applications, interface anchoring sublayers 332 can also be set on one or both sides of the main low dielectric loss layer 331 according to the contact position of the copper foil.

[0068] The purpose of this layered dielectric structure is to concentrate the anchoring functional groups in the interface region near the copper foil, rather than dispersing them uniformly throughout the entire dielectric layer. Thus, the interface anchoring sublayer 332 can improve the interfacial bonding stability with the low-profile copper foil through anchoring functional groups such as phosphate ester groups, benzotriazole groups, imidazole groups, catechol groups, or trialkoxysilane groups. Simultaneously, the main low-loss layer 331 maintains its low-polarity continuous phase, formed by curing fluorinated aryl ether imide prepolymer, polyaryl ether resin, and thermally crosslinked monomers, which helps maintain low dielectric loss. This design avoids relying solely on copper foil roughening to improve bonding strength, thereby balancing low-loss transport and interface reliability.

[0069] See Figure 4 As shown, the bending region 10 includes a bending center region 11 and transition regions 12 located on both sides of the bending center region 11. The non-bending region 20 is located outside the bending region 10. The reference ground layer 32 is formed as a grid reference ground 321 within the bending region 10, and the aperture ratio of the grid reference ground 321 decreases from the bending center region 11 to the non-bending region 20. The bending center region 11 adopts a higher aperture ratio, which is beneficial to reduce the rigidity of the copper layer and the concentration of bending stress; the transition region 12 adopts an intermediate aperture ratio, which is beneficial to the gradual transition of mechanical rigidity and electromagnetic reference environment; the non-bending region 20 can adopt a continuous copper surface or a low aperture ratio grid copper surface to provide a more stable reference ground. Different grid shapes in the figure are used to represent differences in aperture ratio, and the shape of the grid unit is not limited to square, triangular, honeycomb, or combinations thereof.

[0070] At the same time, such as Figure 4As shown, the first signal line 311 and the second signal line 312 are provided with a line width compensation section 313, a line spacing compensation section 314, and a gradual transition section 315 within the bending region 10. Since changes in the aperture ratio of the grid reference ground 321 cause changes in the local equivalent dielectric environment and return path, while providing only the grid reference ground 321 can improve bending reliability, it may cause impedance discontinuities between the bending region 10 and the non-bending region 20. This invention corrects the local impedance of the differential signal lines through the line width compensation section 313 and the line spacing compensation section 314, and reduces geometric abrupt changes in the line through the gradual transition section 315, thereby achieving a synergistic effect between improved bending reliability and improved differential impedance continuity.

[0071] See Figure 5 As shown, the manufacturing method of this invention includes S1 preparing the main layer adhesive, S2 preparing the interface layer adhesive, S3 preparing a B-order low dielectric loss modified polymer film, S4 obtaining lamination changes and design parameters, S5 generating impedance compensation values, S6 fabricating circuitry and laminating the composite, and S7 subsequent processing and impedance testing. This process integrates material preparation, interface construction, lamination change measurement, circuit compensation design, and finished product impedance verification into the same process logic, avoiding impedance design based solely on empirical linewidth or a single dielectric constant.

[0072] Specifically, S1 and S2 form the adhesives required for the main low-dissipation layer 331 and the interface anchoring sublayer 332, respectively, so that the low-dissipation function and the interface anchoring function are designed separately at the material stage; S3 forms a pressable B-order low-dissipation modified polymer film; S4 obtains the actual process parameters affecting impedance, such as the change in lamination thickness, the change in warp and weft dimensions, the copper foil thickness, the copper foil surface treatment parameters, and the design radius of the bending area; S5 generates the linewidth compensation value, the line spacing compensation value, and the grid opening compensation value of the reference ground layer based on these parameters; S6 converts the compensation results into the actual circuit and the stacked structure; S7 confirms the design results through subsequent processing and on-board impedance testing.

[0073] In this invention, the fluorinated aryl ether imide prepolymer is obtained by reacting a fluorinated aromatic diamine with an aromatic dianhydride. In the following examples, the fluorinated aryl ether imide prepolymer A is a soluble fluorinated aryl ether imide prepolymer obtained by reacting 2,2'-bis(trifluoromethyl)-4,4'-diaminobiphenyl, 4,4'-oxobis(phthalic anhydride), and 4,4'-(hexafluoroisopropylidene)diphthalic anhydride in N-methylpyrrolidone and then thermally imidizing it; in the prepolymer A, 2,2'-bis(trifluoromethyl)-4,4'-diaminobiphenyl is used as the fluorinated aromatic diamine, and 4,4'-oxobis(phthalic anhydride) and 4,4'-(hexafluoroisopropylidene)diphthalic anhydride are used as aromatic dianhydrides. Fluorinated aryl ether imide prepolymer B is a soluble fluorinated aryl ether imide prepolymer obtained by reacting 2,2-bis[4-(4-aminophenoxy)phenyl]hexafluoropropane, 4,4'-biphenyltetracarboxylic dianhydride and 4,4'-oxobisphthalic anhydride in N,N-dimethylacetamide and then thermally imidizing it.

[0074] In the following examples, the polyaryl ether resin is a vinyl-terminated polyphenylene ether resin, an allyl-terminated polyphenylene ether resin, or a maleimide-terminated polyphenylene ether resin. The thermal crosslinking monomer is 1,3-bis(2-benzocyclobutenyl)tetramethyldisiloxane, 4,4'-bismaleimide diphenylmethane, or a combination of both. The low dielectric loss inorganic filler is hollow silica surface-treated with tridecafluorooctyltriethoxysilane, cage-type silsesquioxane, or a combination of both. The low polarity film-forming resin is a vinyl-terminated polyphenylene ether resin or a fluorinated polyimide resin. The anchoring functional group compound is one or more of 2-methacryloyloxyethyl phosphate, 1H-benzotriazole, 1-vinylimidazolium, N-methacryloyldopamine, or 3-methacryloyloxypropyltrimethoxysilane. The crosslinking aid is one or a combination of triallyl isocyanurate and dicumyl peroxide. The additives are one or more of the following: polyether-modified polydimethylsiloxane leveling agent, hindered phenolic antioxidant 1010, and polycarboxylate dispersant.

[0075] The following examples and comparative examples all use a four-layer flexible printed circuit board (FPCB) prototype as the evaluation object. The prototype's stack-up structure is as follows: L1 reference ground layer, low-dispersion modified polymer dielectric layer, L2 differential signal line layer, low-dispersion modified polymer dielectric layer, L3 reference ground layer, cover film, and L4 auxiliary ground or shielding layer. The low-profile copper foil thickness is 12 μm, the copper foil surface roughness Rz is controlled between 0.35 μm and 0.55 μm, the target differential impedance is 100 Ω, the effective test length of the differential line is 100 mm, and the bending zone design radius is R = 1.5 mm. The bending zone includes the bending center area and the transition areas located on both sides of the bending center area.

[0076] Example 1:

[0077] The method for fabricating a multilayer low dielectric loss flexible circuit board according to this embodiment includes the following steps:

[0078] First, 60 parts by weight of fluorinated aryl ether imide prepolymer A were added to a mixed solvent of N-methylpyrrolidone and cyclohexanone in a mass ratio of 7:3, and stirred at 30°C until a homogeneous solution was formed. Then, 20 parts by weight of vinyl-terminated polyphenylene ether resin were added, and stirring was continued until dissolved or uniformly dispersed. Subsequently, 10 parts by weight of 1,3-bis(2-benzocyclobutenyl)tetramethyldisiloxane, 3 parts by weight of hollow silica surface-treated with tridecafluorooctyltriethoxysilane, 0.4 parts by weight of polycarboxylate dispersant, 0.3 parts by weight of polyether-modified polydimethylsiloxane leveling agent, and 0.3 parts by weight of hindered phenolic antioxidant 1010 were added. After dispersion using a high-speed dispersion method, the mixture was filtered through a 5μm filter and degassed under vacuum to obtain the main layer adhesive solution. The solid content of the main layer adhesive solution was controlled at 25%.

[0079] Separately, 85 parts by weight of vinyl-terminated polyphenylene ether resin were added to a mixed solvent of propylene glycol methyl ether acetate and toluene in a mass ratio of 6:4 and stirred to dissolve. Then, 3 parts by weight of 2-methacryloyloxyethyl phosphate, 2 parts by weight of triallyl isocyanurate and 1 part by weight of dicumyl peroxide were added, and the mixture was stirred and filtered to obtain the interface layer solution. The solid content of the interface layer solution was controlled at 12%.

[0080] A 12 μm thick low-profile copper foil was plasma-treated for 60 s. An interface layer adhesive was then coated onto the treated copper foil surface with a wet film thickness of 3 μm, and pre-baked at 100 °C for 5 min. Subsequently, a host layer adhesive was coated with a wet film thickness of 50 μm, and the film was sequentially dried at 90 °C, 130 °C, and 160 °C for 10 min at each temperature range to obtain a B-order low-dissipation modified polymer film comprising a 0.8 μm interface anchoring sublayer and an 18 μm host low-dissipation layer.

[0081] Laminated test pieces were prepared using B-order low-dielectric-loss modified polymer films from the same batch. The changes in lamination thickness and warp and weft dimensions were measured. Combined with copper foil thickness, copper foil surface roughness, plasma treatment time, and the design radius of the bending zone, a circuit pattern compensation file was generated. In Example 1, the grid reference ground aperture ratio in the bending center area was set to 60%, the grid reference ground aperture ratio in the transition area was set to 40%, and the reference ground layer aperture ratio in the non-bending area was set to 15%. Line width compensation sections and line spacing compensation sections were set for the first and second signal lines in the bending area. The line width compensation was +8μm, and the line spacing compensation was +6μm. The compensation sections were connected to the signal lines in the non-bending area via a gradual transition section.

[0082] According to the compensated circuit pattern, the L2 differential signal circuit layer was fabricated through dry film bonding, exposure, development, and etching, and the L1 and L3 reference ground layers were also fabricated. The B-order low-displacement modified polymer film, L1 reference ground layer, L2 differential signal circuit layer, and L3 reference ground layer were aligned and stacked according to the design, using a fast pressing method at a temperature of 180℃, a pressure of 100 kgf / cm², and a pressing time of 180 s. After pressing, it was cured at 230℃ for 60 min in a nitrogen atmosphere. Subsequently, drilling, hole metallization, cover film lamination, shaping, and on-board impedance testing were performed to obtain the multilayer low-displacement flexible circuit board of Example 1.

[0083] Example 2:

[0084] The method for fabricating a multilayer low dielectric loss flexible circuit board according to this embodiment includes the following steps:

[0085] First, 58 parts by weight of fluorinated aryl ether imide prepolymer A were added to a mixed solvent of N-methylpyrrolidone and cyclohexanone in a mass ratio of 7:3 and stirred at 30°C to dissolve. Then, 20 parts by weight of allyl-terminated polyphenylene ether resin were added and stirred until homogeneous. Subsequently, 7 parts by weight of 1,3-bis(2-benzocyclobutenyl)tetramethyldisiloxane, 3 parts by weight of 4,4'-bismaleimide diphenylmethane, 3 parts by weight of hollow silica surface-treated with tridecafluorooctyltriethoxysilane, 0.4 parts by weight of polycarboxylate dispersant, 0.3 parts by weight of polyether-modified polydimethylsiloxane leveling agent, and 0.3 parts by weight of hindered phenolic antioxidant 1010 were added. After dispersion, filtration, and vacuum degassing, the main layer adhesive was obtained, and the solid content of the main layer adhesive was controlled at 25%.

[0086] Separately, 84 parts by weight of vinyl-terminated polyphenylene ether resin were added to a mixed solvent of propylene glycol methyl ether acetate and toluene in a mass ratio of 6:4 and stirred to dissolve. Then, 2 parts by weight of 2-methacryloyloxyethyl phosphate, 1.5 parts by weight of 1H-benzotriazole, 2.5 parts by weight of triallyl isocyanurate, 1 part by weight of dicumyl peroxide and 1 part by weight of 3-methacryloyloxypropyltrimethoxysilane were added, stirred and filtered to obtain the interface layer solution. The solid content of the interface layer solution was controlled at 12%.

[0087] A low-profile copper foil was plasma-treated for 60 seconds, and an interface layer adhesive was applied to its surface. After pre-baking at 100°C for 5 minutes, a main layer adhesive was applied. A first interface anchoring sublayer and a main low-dissipation layer were formed using a stepped drying process at 90°C, 130°C, and 160°C. An interface layer adhesive was then applied to the other side of the main low-dissipation layer and dried to form a double-sided interface anchoring structure. The resulting B-order low-dissipation modified polymer film had a target thickness of 0.8 μm for the interface anchoring sublayer on each side and a target thickness of 18 μm for the main low-dissipation layer.

[0088] Example 2 obtained the lamination thickness variation, warp and weft dimension variation, copper foil thickness, copper foil surface roughness, plasma treatment time, and bending zone design radius of the B-order low dielectric loss modified polymer film, and generated a compensation file accordingly. The grid reference ground aperture ratio in the bending center area was 60%, the grid reference ground aperture ratio in the transition area was 40%, and the reference ground layer aperture ratio in the non-bending area was 15%; the linewidth compensation was +8μm, and the line spacing compensation was +6μm. Subsequently, differential signal line layers and reference ground layers were fabricated according to the compensated circuit pattern, and alignment, fast pressing at 180℃, post-curing at 230℃, drilling, hole metallization, cover film lamination, shape processing, and on-board impedance testing were performed to obtain the multilayer low dielectric loss flexible circuit board of Example 2.

[0089] Example 3:

[0090] The method for fabricating a multilayer low dielectric loss flexible circuit board according to this embodiment includes the following steps:

[0091] In preparation, 40 parts by weight of fluorinated aryl ether imide prepolymer A were added to N-methylpyrrolidone and stirred to dissolve. Then, 5 parts by weight of vinyl-terminated polyphenylene ether resin were added and stirred evenly. Subsequently, 3 parts by weight of 1,3-bis(2-benzocyclobutenyl)tetramethyldisiloxane and 0.1 parts by weight of polyether-modified polydimethylsiloxane leveling agent were added. No low-dissipation inorganic filler was added. After filtration and degassing, the main layer adhesive was obtained. The solid content of the main layer adhesive was controlled at 22%.

[0092] Separately, 95 parts by weight of vinyl-terminated polyphenylene ether resin were added to propylene glycol methyl ether acetate and stirred to dissolve. Then, 0.5 parts by weight of 2-methacryloyloxyethyl phosphate and 0.1 parts by weight of triallyl isocyanurate were added. After stirring and filtering, the interface layer solution was obtained. The solid content of the interface layer solution was controlled to be 8%.

[0093] An interface layer adhesive was coated on the surface of a low-profile copper foil that had been plasma-treated for 60 s, with a wet film thickness controlled at 0.5 μm, and pre-baked at 90 °C for 3 min. Subsequently, a main layer adhesive was coated, with a wet film thickness controlled at 10 μm, and dried sequentially at 80 °C, 120 °C, and 150 °C to obtain a B-order low-dissipation modified polymer film comprising a 0.1 μm interface anchoring sublayer and a 5 μm main low-dissipation layer.

[0094] In Example 3, after obtaining the lamination thickness variation, warp and weft dimension variation, copper foil thickness, copper foil surface roughness, plasma treatment time, and bending zone design radius of the same batch of adhesive films, a circuit compensation file was generated. The grid reference ground aperture ratio in the bending center area was 40%, the grid reference ground aperture ratio in the transition area was 20%, and the non-bending area used a grid copper surface with an aperture ratio of no more than 30%; the line width compensation and line spacing compensation were both 2μm. Subsequently, differential signal line layers and reference ground layers were fabricated according to the compensated circuit pattern, and the lamination, post-curing, drilling, hole metallization, cover film lamination, shape processing, and on-board impedance testing were completed to obtain the multilayer low dielectric loss flexible circuit board of Example 3.

[0095] Example 4:

[0096] The method for fabricating a multilayer low dielectric loss flexible circuit board according to this embodiment includes the following steps:

[0097] In preparation, 80 parts by weight of fluorinated aryl ether imide prepolymer B were added to a mixed solvent of N,N-dimethylacetamide and cyclohexanone in a mass ratio of 7:3 and stirred to dissolve. Then, 35 parts by weight of maleimide-terminated polyphenylene ether resin were added and stirred evenly. Subsequently, 10 parts by weight of 1,3-bis(2-benzocyclobutenyl)tetramethyldisiloxane, 10 parts by weight of 4,4'-bismaleimide diphenylmethane, 7 parts by weight of hollow silica surface-treated with tridecafluorooctyltriethoxysilane, 3 parts by weight of cage-type silsesquioxane, 1 part by weight of polycarboxylate dispersant, 1 part by weight of polyether-modified polydimethylsiloxane leveling agent, and 1 part by weight of hindered phenolic antioxidant 1010 were added. High-speed dispersion and filtration degassing were performed to obtain the main layer adhesive solution, and the solid content of the main layer adhesive solution was controlled at 28%.

[0098] Separately, 50 parts by weight of fluorinated polyimide resin were added to a mixed solvent of propylene glycol methyl ether acetate and toluene in a mass ratio of 5:5 and stirred to dissolve. Then, 5 parts by weight of 2-methacryloyloxyethyl phosphate, 2 parts by weight of 1-vinylimidazole, 3 parts by weight of N-methacryloyldopamine, 5 parts by weight of triallyl isocyanurate, 3 parts by weight of dicumyl peroxide and 5 parts by weight of 3-methacryloyloxypropyltrimethoxysilane were added, stirred and filtered to obtain the interface layer solution. The solid content of the interface layer solution was controlled to be 15%.

[0099] An interface layer adhesive was coated on a low-profile copper foil surface treated with plasma for 60 s and 3-methacryloyloxypropyltrimethoxysilane, with a wet film thickness controlled at 10 μm, and pre-baked at 130 °C for 10 min. Subsequently, a host layer adhesive was coated, with a wet film thickness controlled at 120 μm, and then dried in steps at 100 °C, 140 °C and 170 °C to obtain a B-order low-dissipation modified polymer film comprising a 3 μm interface anchoring sublayer and a 45 μm host low-dissipation layer.

[0100] In Example 4, after obtaining the lamination thickness variation, warp and weft dimension variation, copper foil thickness, copper foil surface roughness, surface treatment parameters, and bending zone design radius of the same batch of adhesive films, a circuit compensation file was generated. The grid reference ground aperture ratio in the bending center area was 80%, the grid reference ground aperture ratio in the transition area was 60%, and the reference ground layer in the non-bending area was a continuous copper surface or a grid copper surface with an aperture ratio of no more than 30%; the line width compensation and line spacing compensation were both 20μm. Subsequently, differential signal line layers and reference ground layers were fabricated according to the compensated circuit pattern, and lamination, post-curing, drilling, hole metallization, cover film lamination, shape processing, and on-board impedance testing were completed to obtain the multilayer low dielectric loss flexible circuit board of Example 4.

[0101] Example 5:

[0102] Example 5 uses the same specific raw materials as Example 1, namely 60 parts by weight of fluorinated aryl ether imide prepolymer A, 20 parts by weight of vinyl-terminated polyphenylene ether resin, 10 parts by weight of 1,3-bis(2-benzocyclobutenyl)tetramethyldisiloxane, 3 parts by weight of hollow silica surface-treated with tridecafluorooctyltriethoxysilane, and 1 part by weight of additives to prepare the main layer adhesive; and 85 parts by weight of vinyl-terminated polyphenylene ether resin, 3 parts by weight of 2-methacryloyloxyethyl phosphate, 2 parts by weight of triallyl isocyanurate, and 1 part by weight of dicumyl peroxide to prepare the interface layer adhesive.

[0103] Example 5 employs the same low-profile copper foil surface treatment, interface anchoring sublayer coating, main low-dissipation layer coating, stepped drying, lamination, post-curing, drilling, hole metallization, cover film lamination, and shape processing conditions as Example 1. Unlike Example 1, before formally fabricating the circuit pattern, Example 5 uses three sets of small-size laminated test pieces of the same batch of B-order low-dissipation modified polymer film to measure the lamination thickness variation and warp and weft dimension variation; simultaneously, the copper foil thickness, copper foil Rz, plasma treatment time, and bending zone design radius are recorded. These measured values ​​are then input into an impedance compensation calculation file to generate differential signal line width compensation values, line spacing compensation values, and reference ground layer grid opening compensation values. In Example 5, the grid reference ground opening ratio in the bending center area is adjusted to 62%, the grid reference ground opening ratio in the transition area is adjusted to 41%, and the reference ground layer opening ratio in the non-bending area is 15%; the line width compensation is adjusted to +9μm, and the line spacing compensation is adjusted to +7μm. After the fabrication is completed, Example 5 corrects the circuit pattern compensation file for the next batch based on the impedance test results, and obtains the multilayer low dielectric loss flexible circuit board of Example 5.

[0104] Comparative Example 1:

[0105] The main layer adhesive was prepared using the same fluorinated aryl ether imide prepolymer A, vinyl-terminated polyphenylene ether resin, 1,3-bis(2-benzocyclobutenyl)tetramethyldisiloxane, hollow silica surface-treated with tridecafluorooctyltriethoxysilane, and additives as in Example 1. The same bending zone grid reference ground, linewidth compensation section, line spacing compensation section, laminated structure, pressing conditions, and post-curing conditions as in Example 1 were used. The difference was that no interface layer adhesive was applied in Comparative Example 1, i.e., no interface anchoring sublayer was formed, allowing the main low dielectric loss layer to be directly pressed onto the low profile copper foil.

[0106] Comparative Example 2:

[0107] The same base layer adhesive, bending zone grid reference ground, line width compensation section, line spacing compensation section, laminated structure, pressing conditions, and post-curing conditions as in Example 1 were used, and an interface sublayer was set. The difference is that the interface sublayer of Comparative Example 2 is composed of 88 parts by weight of vinyl-terminated polyphenylene ether resin, 2 parts by weight of triallyl isocyanurate, and 1 part by weight of dicumyl peroxide, without the addition of compounds containing anchoring functional groups such as 2-methacryloyloxyethyl phosphate, 1H-benzotriazole, 1-vinylimidazole, N-methacryloyldopamine, or 3-methacryloyloxypropyltrimethoxysilane.

[0108] Comparative Example 3:

[0109] The same interface anchoring sublayer, bending zone grid reference ground, line width compensation section, line spacing compensation section, laminated structure, pressing conditions, and post-curing conditions as in Example 1 were used. The difference was that the main layer adhesive of Comparative Example 3 did not contain thermally crosslinking monomers such as 1,3-bis(2-benzocyclobutenyl)tetramethyldisiloxane, 4,4'-bismaleimide diphenylmethane, norbornene imide, or norbornene anhydride modified monomers. The main layer adhesive was prepared only from 60 parts by weight of fluorinated aryl ether imide prepolymer A, 20 parts by weight of vinyl-terminated polyphenylene ether resin, 3 parts by weight of hollow silica surface-treated with tridecafluorooctyltriethoxysilane, and 1 part by weight of additives.

[0110] Comparative Example 4:

[0111] The same low dielectric loss layer, interface anchoring sublayer, linewidth compensation section, line spacing compensation section, stacked structure, pressing conditions and post-curing conditions as in Example 1 are used; the difference is that the reference ground layer in the bending area of ​​Comparative Example 4 is changed to a continuous copper surface, and no grid reference ground with an opening ratio decreasing from the bending center area to the non-bending area is set.

[0112] Comparative Example 5:

[0113] The same low dielectric loss layer, interface anchoring sublayer, bend zone grid reference ground, laminated structure, pressing conditions and post-curing conditions as in Example 1 are used; the difference is that the first and second signal lines in the bend zone of Comparative Example 5 do not have line width compensation segments and line spacing compensation segments, and the differential signal lines in the bend zone use the same line width and line spacing as in the non-bend zone.

[0114] Comparative Example 6:

[0115] The same low dielectric loss layer, bending zone grid reference ground, line width compensation section, line spacing compensation section, laminated structure, pressing conditions and post-curing conditions as in Example 1 were used; the difference was that the amount of 2-methacryloyloxyethyl phosphate in the interface layer adhesive was reduced to 0.1 parts by weight, the wet film thickness of the interface layer adhesive was reduced to 0.2 μm, and the thickness of the interface anchoring sublayer after drying was 0.05 μm.

[0116] Comparative Example 7:

[0117] The same interface anchoring sublayer, laminated structure, pressing conditions, and post-curing conditions as in Example 1 were used; the difference was that the amount of 1,3-bis(2-benzocyclobutenyl)tetramethyldisiloxane in the main layer adhesive of Comparative Example 7 was reduced to 1 part by weight, the grid reference ground opening ratio in the bending center area was reduced to 20%, the line width compensation was +1 μm, and the line spacing compensation was 0 μm.

[0118] Comparative Example 8:

[0119] The same low dielectric loss layer, bending zone grid reference ground, line width compensation section, line spacing compensation section, laminated structure, pressing conditions and post-curing conditions as in Example 1 were used; the difference was that the amount of 2-methacryloyloxyethyl phosphate in the interface layer adhesive of Comparative Example 8 was increased to 15 parts by weight, the wet film thickness of the interface layer adhesive was increased to 15 μm, and the thickness of the interface anchoring sublayer after drying was 5 μm.

[0120] Test example:

[0121] Dielectric performance testing was used to evaluate the impact of the low-dissipation substrate layer and the interface anchoring sublayer on the performance of the high-frequency transmission medium. The test was conducted according to IPC-TM-650 2.5.5.15, using the split-pillar dielectric resonator method, with a test frequency of 10 GHz. Before the test, the material test pieces were placed in an environment of 23±2℃ and 50±5%RH for 24 hours. Five material test pieces were taken from each group, and the arithmetic mean values ​​of Dk and Df are recorded in the table.

[0122] Peel strength testing was used to evaluate the influence of interfacial anchoring sublayers and anchoring functional groups on the interfacial bonding stability of low-profile copper foil. The test was conducted according to IPC-TM-650 2.4.9E, using the flexible dielectric material peel strength test method, with a peel angle of 90° and a tensile speed of 50 mm / min. Five peel samples were taken from each group, and the peel force of the stable peel section was recorded and converted into peel strength per unit width. The arithmetic mean value is recorded in the table.

[0123] The lamination dimensional change test is used to evaluate the necessity of obtaining compensation parameters in the thermal crosslinking structure and fabrication method of the low dielectric loss layer. The test is conducted under the following feasible conditions: Before lamination of the B-order low dielectric loss modified polymer film, thickness measurement points and warp and weft optical reference marks are set on each sample; after lamination and post-curing treatment according to the corresponding embodiment or comparative example, the thickness and reference mark distance are remeasured at the same points; the lamination thickness change rate is calculated as the percentage of the thickness difference before and after lamination to the thickness before lamination, and the warp and weft dimensional change rate is calculated as the percentage of the difference of the reference mark distance before and after lamination to the distance before lamination; 5 samples are taken for each group, and the arithmetic mean value is recorded in the table.

[0124] Impedance testing is used to evaluate the effectiveness of differential impedance transmission channels, bend width compensation sections, line spacing compensation sections, and coupling compensation methods. The test is conducted according to IPC-TM-650 2.5.5.7, using the TDR method, with 100Ω as the target differential impedance, and the maximum deviation of the effective transmission section relative to the target impedance is taken. Five circuit boards are taken in each group, and three differential lines are tested on each circuit board. The arithmetic mean of the maximum deviation is recorded in the table.

[0125] Insertion loss testing is used to evaluate the combined effects of low dielectric loss materials, interface layer thickness, and bending region structure on high-frequency transmission loss. The test employs a vector network analyzer, with a frequency range of 10MHz to 20GHz, and uses TRL calibration. The absolute value of the Sdd21 insertion loss at 10GHz is taken from a 100mm differential line. Five circuit boards are used in each group, and the arithmetic mean value is recorded in the table.

[0126] The damp heat retention test was used to evaluate the effects of interfacial anchored sublayers, thermal cross-linked structures, and excessive anchored functional groups on environmental stability. The damp heat treatment was carried out according to the constant damp heat test in GB / T 2423.3-2016, with conditions set at 85℃, 85%RH, and 168h. After damp heat treatment, the peel strength and TDR impedance were retested. The table records the arithmetic mean of the peel strength and the maximum impedance deviation after damp heat treatment.

[0127] Dynamic bending test is used to evaluate the influence of the grid reference ground and line width / spacing compensation section in the bending area on the impedance stability after bending; the test conditions are set as bending radius R=1.5mm, 180° reciprocating bend, frequency 1Hz, 10000 cycles; 10 circuit boards are taken in each group, and the TDR impedance is re-measured and the appearance is observed after bending. The appearance observation items include whitening, copper surface cracks, interface delamination and cover film blistering.

[0128] The specific test results are shown in the following two tables:

[0129] project Dk Df Initial peel strength (N / mm) Peel strength after wet heat (N / mm) Lamination thickness change rate % meridional dimensional change rate % Dimensional change rate in the weft direction % Example 1 2.62 0.0034 0.82 0.70 5.8 0.18 0.22 Example 2 2.60 0.0031 0.93 0.85 4.6 0.14 0.17 Example 3 2.66 0.0046 0.63 0.47 10.2 0.42 0.49 Example 4 2.78 0.0051 0.86 0.71 3.9 0.11 0.15 Example 5 2.63 0.0034 0.83 0.72 5.7 0.17 0.21 Comparative Example 1 2.61 0.0033 0.44 0.26 5.9 0.18 0.23 Comparative Example 2 2.62 0.0035 0.54 0.35 5.8 0.19 0.22 Comparative Example 3 2.67 0.0044 0.74 0.53 11.8 0.51 0.58 Comparative Example 4 2.62 0.0034 0.81 0.69 5.8 0.18 0.22 Comparative Example 5 2.62 0.0034 0.82 0.70 5.8 0.18 0.22 Comparative Example 6 2.61 0.0034 0.50 0.31 5.9 0.18 0.23 Comparative Example 7 2.66 0.0047 0.71 0.50 12.5 0.57 0.64 Comparative Example 8 2.88 0.0065 0.96 0.75 5.5 0.20 0.2

[0130] project Initial maximum impedance deviation Ω Maximum impedance deviation Ω after 10,000 bends Maximum impedance deviation Ω after damp heat Sdd21 insertion loss absolute value dB / 100mm Dynamic bending passage situation Appearance description after bending Example 1 3.1 3.6 4.0 0.72 Passed on 9 / 10 One piece has slight indentations on the edge, with no obvious layering. Example 2 2.6 2.9 3.2 0.68 Passed on 10 / 10 No obvious whitening, cracks or delamination were observed. Example 3 4.7 5.2 6.1 0.92 Passed on 8 / 10 Slight whitening in the two bending areas Example 4 4.1 4.9 5.5 0.98 Passed on 8 / 10 One piece has a localized edge that is curled up. Example 5 2.2 2.7 3.1 0.71 Passed on 9 / 10 One piece has slight indentations on the edge, with no obvious layering. Comparative Example 1 3.3 4.8 7.2 0.73 Passed on 7 / 10 The two interfaces are slightly layered. Comparative Example 2 3.5 4.6 6.5 0.76 Passed on 8 / 10 1 piece of edge layering Comparative Example 3 4.6 6.8 8.1 0.90 Passed on 6 / 10 3 folded areas are white or warped Comparative Example 4 2.9 7.4 5.0 0.70 Passed 5 / 10 Three copper surfaces have microcracks, and two have whitened surfaces. Comparative Example 5 6.3 6.9 7.1 0.76 Passed on 8 / 10 The appearance is generally normal, but there are obvious local mutations in the TDR. Comparative Example 6 3.5 5.1 7.5 0.74 Passed on 7 / 10 2-layer interface Comparative Example 7 7.5 8.8 9.2 1.02 Passed 5 / 10 4 pieces are white or partially curled Comparative Example 8 4.3 5.7 7.8 1.18 Passed on 7 / 10 Two bent areas hardened and whitened

[0131] Analysis of experimental results:

[0132] As shown in Tables 1 and 2, in Example 1, Dk is 2.62, Df is 0.0034, the initial peel strength is 0.82 N / mm, the peel strength after damp heat is 0.70 N / mm, the lamination thickness change rate is 5.8%, the initial maximum impedance deviation is 3.1 Ω, and the maximum impedance deviation after 10,000 bends is 3.6 Ω. These data demonstrate that when using a complete combination of a low-dielectric-loss crosslinked substrate, an interface anchoring sublayer, a gradient grid reference ground, and linewidth / spacing compensation sections, the circuit board can achieve a relatively balanced result in terms of dielectric performance, interface bonding, lamination dimensional stability, impedance continuity, and bending reliability.

[0133] Example 2 employs a double-sided interface anchoring sublayer, using a composite anchoring system of 2-methacryloyloxyethyl phosphate and 1H-benzotriazole, and a composite crosslinking system of 1,3-bis(2-benzocyclobutenyl)tetramethyldisiloxane and 4,4'-bismaleimide diphenylmethane. Compared to Example 1, the initial peel strength of Example 2 increased from 0.82 N / mm to 0.93 N / mm, the peel strength after damp heat increased from 0.70 N / mm to 0.85 N / mm, Df decreased from 0.0034 to 0.0031, and the maximum impedance deviation after 10,000 bends decreased from 3.6 Ω to 2.9 Ω. This trend indicates that double-sided interface anchoring is beneficial for improving the interfacial bonding consistency of the double-sided copper foil, the composite crosslinking system is beneficial for further stabilizing the dielectric layer, and no significant high-frequency loss degradation was caused.

[0134] In Example 3, the thickness of the interface anchoring sublayer, the amount of anchoring functional group compound, the amount of thermally crosslinked monomer, the thickness of the main layer, and the linewidth / spacing compensation are all at a low level. The initial peel strength of Example 3 is 0.63 N / mm, the peel strength after wet heat is 0.47 N / mm, the lamination thickness change rate is 10.2%, and the initial maximum impedance deviation is 4.7 Ω. Its performance is weaker than that of Examples 1 and 2, but the initial peel strength is still higher than that of Comparative Example 1 (0.44 N / mm) and Comparative Example 6 (0.50 N / mm), indicating that the low-end range is still feasible, but not the preferred process window.

[0135] In Example 4, the thickness of the interface anchoring sublayer, the amount of anchoring functional group compound, the amount of thermally crosslinked monomer, the amount of low-dissipation inorganic filler, and the compensation amount were all at relatively high levels. The initial peel strength of Example 4 was 0.86 N / mm, the peel strength after wet heat was 0.71 N / mm, and the lamination thickness change rate was 3.9%, indicating that a higher degree of crosslinking helps control the change in lamination dimensions. However, the Df of Example 4 was 0.0051, and the absolute value of Sdd21 insertion loss was 0.98 dB / 100 mm, which was higher than that of Examples 1 and 2. Moreover, after dynamic bending, a local edge warping occurred in one piece. This trend indicates that although it is feasible in the high-end range, excessively high filler content, crosslinking density, or interface layer thickness may lead to poor high-frequency loss and flexibility.

[0136] Example 5 uses essentially the same material system as Example 1, but adds a compensation step involving variations in lamination thickness, warp and weft dimensions, copper foil surface treatment parameters, and the design radius of the bending zone. Example 5 has a Dk of 2.63, a Df of 0.0034, and an initial peel strength of 0.83 N / mm, which is essentially equivalent to Example 1. However, the initial maximum impedance deviation in Example 5 decreases from 3.1 Ω in Example 1 to 2.2 Ω, the maximum impedance deviation after 10,000 bends decreases from 3.6 Ω to 2.7 Ω, and the maximum impedance deviation after damp heat decreases from 4.0 Ω to 3.1 Ω. These results illustrate that the improvement in Example 5 mainly comes from the coupling compensation method, rather than changes in the dielectric properties of the material itself.

[0137] In Comparative Example 1, after removing the interface anchoring sublayer, Dk was 2.61 and Df was 0.0033, similar to Example 1. However, the initial peel strength decreased from 0.82 N / mm in Example 1 to 0.44 N / mm, and the peel strength after damp heat decreased from 0.70 N / mm to 0.26 N / mm, with slight delamination occurring at two interfaces. These results indicate that the interface anchoring sublayer primarily contributes to the interfacial bonding stability between the low-profile copper foil and the low-dissipation polymer dielectric layer, rather than simply altering the dielectric parameters of the host dielectric.

[0138] Comparative Example 2, which uses a standard interface sublayer but lacks specific anchoring functional groups, exhibits an initial peel strength of 0.54 N / mm and a peel strength after damp heat of 0.35 N / mm, both lower than that of Example 1. This result demonstrates that the interface layer itself is insufficient to achieve good interfacial bonding; anchoring functional groups such as phosphate ester groups, benzotriazole groups, imidazole groups, catechol groups, or trialkoxysilane groups substantially contribute to the stability of the copper foil interface.

[0139] In Comparative Example 3, after removing the thermally crosslinked monomer, the laminate thickness change rate increased from 5.8% in Example 1 to 11.8%, the warp dimension change rate increased from 0.18% to 0.51%, the weft dimension change rate increased from 0.22% to 0.58%, and the maximum impedance deviation after hygrothermal treatment increased to 8.1Ω. These results indicate that the thermally crosslinked structure in the low-dissipation matrix layer helps reduce dimensional drift after pressing and post-curing, and indirectly improves impedance stability.

[0140] Comparative Example 4 replaced the reference ground layer in the bending region with a continuous copper surface. Its initial maximum impedance deviation was 2.9Ω, slightly lower than the 3.1Ω of Example 1, indicating that the continuous copper surface can provide a more stable reference ground in its initial flat state. However, after 10,000 bends, the maximum impedance deviation in Comparative Example 4 increased to 7.4Ω, with only 5 / 10 of the dynamic bends passing, and microcracks and whitening appeared on the copper surface. This result demonstrates that the gradient grid reference ground of this invention mainly contributes to the release of bending stress and the stability of impedance after bending, rather than simply pursuing the initial impedance value.

[0141] Comparative Example 5 retains the gradient grid reference ground but removes the linewidth compensation section and the line spacing compensation section. Its initial maximum impedance deviation is 6.3Ω, which is significantly higher than 3.1Ω in Example 1, and the local abrupt change in TDR is obvious. This result shows that although the gradient grid reference ground is beneficial to bending reliability, the change in the reference ground aperture ratio will change the local electromagnetic environment. Therefore, it is necessary to improve impedance continuity through linewidth compensation sections or line spacing compensation sections in the bending area.

[0142] Comparative Example 6, by reducing the thickness of the interfacial anchoring sublayer to 0.05 μm and the amount of anchoring functional group compound to 0.1 parts by weight, showed an initial peel strength of 0.50 N / mm, a peel strength after damp heat of 0.31 N / mm, and a maximum impedance deviation of 7.5 Ω after damp heat. These results indicate that when the interfacial anchoring sublayer is too thin or the amount of anchoring functional group compound is too small, the interfacial coverage and anchoring effect are insufficient, making it difficult to adequately improve the interfacial stability of low-profile copper foil.

[0143] In Comparative Example 7, after reducing the thermal crosslinking monomer, the mesh opening ratio in the bending center region, and the linewidth / spacing compensation to lower levels, the laminate thickness change rate increased to 12.5%, the initial maximum impedance deviation increased to 7.5Ω, and the maximum impedance deviation increased to 8.8Ω after 10,000 bends, with a dynamic bend pass rate of 5 / 10. These results indicate that the thermal crosslinking structure, the mesh opening ratio in the bending center region, and the compensation segment all contribute to dimensional stability, stress release, and impedance continuity; excessively low values ​​of any of these three factors significantly reduce the overall performance.

[0144] Comparative Example 8, by increasing the thickness of the interface anchoring sublayer to 5 μm and the amount of anchoring functional group compound to 15 parts by weight, showed an initial peel strength of 0.96 N / mm, higher than Example 1; however, its Dk increased to 2.88, Df increased to 0.0065, the absolute value of Sdd21 insertion loss increased to 1.18 dB / 100 mm, the maximum impedance deviation after damp heat increased to 7.8 Ω, and hardening and whitening occurred in the bending region. These results indicate that more anchoring functional groups and interface layers are not necessarily better; excessive thickness or quantity may introduce more polar structures and reduce high-frequency transmission and bending reliability.

[0145] In summary, the technical effect of this invention is not achieved by a single low-dissipation material, a single interface coating, a single grid reference, or a single linewidth compensation, but rather by the combined effect of the main low-dissipation cross-linked layer, the interface anchoring sublayer, the gradient grid reference in the bending region, and the coupling impedance compensation method. Example 1 demonstrates the balanced effect of the complete combination; Example 2 demonstrates further improvement of the preferred structure; Examples 3 and 4 demonstrate the feasibility of the claims' boundary range; and Example 5 demonstrates the contribution of the coupling compensation method to impedance consistency. Comparative Examples 1 to 8 respectively demonstrate the necessity and rationality of the interface anchoring sublayer, anchoring functional groups, thermal cross-linked structure, gradient grid reference, linewidth / spacing compensation segment, and the upper and lower limits of key parameters.

[0146] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

[0147] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to specific implementations. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A multilayer low dielectric loss flexible circuit board, characterized in that, It includes a bending region, a non-bending region, and at least one high-speed signal unit. The high-speed signal unit includes a differential signal line layer, at least one reference ground layer, and a low dielectric loss modified polymer dielectric layer located between the differential signal line layer and the reference ground layer. The differential signal line layer includes a pair of first signal lines and second signal lines, and the first signal lines, the second signal lines and the reference ground layer constitute a differential impedance transmission channel; The low dielectric loss modified polymer dielectric layer includes a main low dielectric loss layer and an interface anchoring sublayer disposed on the side of the main low dielectric loss layer near the copper foil. The main low dielectric loss layer is a continuous phase formed by curing fluorinated aryl ether imide prepolymer, polyaryl ether resin and thermally crosslinked monomer; The interface anchoring sublayer contains at least one anchoring functional group selected from phosphate ester group, benzotriazole group, imidazole group, catechol group and trialkoxysilyl group; The reference grounding layer within the bending region is a grid reference ground, and the opening ratio of the grid reference ground decreases from the bending center region to the non-bending region. The first and second signal lines within the bending zone have at least one of a line width compensation segment and a line spacing compensation segment relative to the non-bending zone.

2. The multilayer low dielectric loss flexible circuit board according to claim 1, characterized in that, The high-speed signal unit is a stripline structure or a microstripline structure; When the high-speed signal unit is a stripline structure, the reference ground layer is respectively provided on both sides of the differential signal line layer; When the high-speed signal unit is a microstrip line structure, a reference ground layer is provided on one side of the differential signal line layer, and a cover film or shielding film is provided on the other side.

3. The multilayer low dielectric loss flexible circuit board according to claim 1, characterized in that, The interface anchoring sublayer is disposed between the main low-dispersion layer and the differential signal line layer, between the main low-dispersion layer and the reference ground layer, or simultaneously disposed between the main low-dispersion layer and the differential signal line layer and between the main low-dispersion layer and the reference ground layer; The thickness of the main low dielectric loss layer is 5μm~45μm, and the thickness of the interface anchoring sublayer is 0.1μm~3μm; Based on the total amount of solid components in the interface anchoring sublayer, the raw materials of the interface anchoring sublayer include 50 to 95 parts by weight of low polarity film-forming resin, 0.5 to 10 parts by weight of anchoring functional group compound, 0.1 to 8 parts by weight of crosslinking aid, and 0 to 5 parts by weight of coupling agent.

4. The multilayer low dielectric loss flexible circuit board according to claim 1, characterized in that, Based on the total amount of solid components in the main low-dielectric-loss layer, the raw materials of the main low-dielectric-loss layer include: 40 to 80 parts by weight of fluorinated aryl ether imide prepolymer; 5 to 35 parts by weight of polyarylether resin; 3 to 20 parts by weight of thermally crosslinked monomer; Low dielectric loss inorganic packing: 0-10 parts by weight; Additives: 0.1 to 3 parts by weight.

5. The multilayer low dielectric loss flexible circuit board according to claim 4, characterized in that, The fluorinated aryl ether imide prepolymer is obtained by reacting a fluorinated aromatic diamine with an aromatic dianhydride. The polyarylene ether resin is selected from at least one of polyphenylene ether, allyl-terminated polyphenylene ether, vinyl-terminated polyphenylene ether, maleimide-terminated polyphenylene ether, polyarylene ether ketone and polyarylene ether sulfone. The thermal crosslinking monomer is selected from at least one of benzocyclobutene resin, aromatic monomers containing benzocyclobutene group, bismaleimide, norbornene imide and norbornene anhydride modified monomer; The low dielectric loss inorganic filler is selected from at least one of fluorinated hollow silica, fluorinated porous silica, cage-type silsesquioxane, fluorinated boron nitride, and surface-silanized silica.

6. The multilayer low dielectric loss flexible circuit board according to claim 1, characterized in that, The bending area includes a bending center area and transition areas located on both sides of the bending center area; The grid reference ground aperture ratio in the bending center area is 40%~80%, the grid reference ground aperture ratio in the transition area is 20%~60%, and the reference ground layer in the non-bending area is a continuous copper surface or a grid copper surface with an aperture ratio of no more than 30%; the line width compensation section and the line spacing compensation section are connected to the signal line in the non-bending area through a gradual transition section.

7. A method for fabricating a multilayer low dielectric loss flexible circuit board, characterized in that, Includes the following steps: S1. Mix the fluorinated aryl ether imide prepolymer, polyaryl ether resin, thermal crosslinking monomer, optional low dielectric loss inorganic filler, additives and organic solvent to obtain the main layer adhesive solution. S2. Mix a low-polarity film-forming resin, an anchoring functional group compound, a crosslinking aid, an optional coupling agent, and an organic solvent to obtain an interface layer adhesive, wherein the anchoring functional group compound contains at least one anchoring functional group selected from phosphate ester group, benzotriazole group, imidazolium group, catechol group, and trialkoxysilyl group. S3. Coat the interface layer adhesive on a low-profile copper foil or release carrier, pre-bake and then coat the main layer adhesive, and dry to obtain a B-order low-dielectric-loss modified polymer film including an interface anchoring sublayer and a main low-dielectric-loss layer. S4. Obtain the lamination thickness variation value and warp and weft dimension variation value of the B-order low dielectric loss modified polymer film, and obtain the copper foil thickness, copper foil surface treatment parameters and bending zone design radius. S5. Based on the target impedance design value, the laminate thickness variation value, the warp and weft dimension variation value, the copper foil thickness, the copper foil surface treatment parameters, and the bending area design radius, generate the differential signal line width compensation value, the line spacing compensation value, and the grid opening compensation value of the reference ground layer. S6. Fabricate a differential signal line layer and a reference ground layer according to the compensated line pattern, and stack and press the B-order low dielectric loss modified polymer film, the differential signal line layer and the reference ground layer together to obtain a multilayer circuit board. S7. Drilling, metallizing, covering film lamination, shaping, and impedance testing of the multilayer circuit board are performed on the multilayer circuit board to obtain a multilayer low dielectric loss flexible circuit board.

8. The method for fabricating a multilayer low dielectric loss flexible circuit board according to claim 7, characterized in that, In step S1, the fluorinated aryl ether imide prepolymer is first dissolved in an organic solvent, then polyaryl ether resin is added and stirred, followed by the addition of thermal crosslinking monomer, optional low dielectric loss inorganic filler and additives, and after dispersion, it is filtered and degassed to obtain the main layer adhesive solution. In step S2, the low-polarity film-forming resin is first dissolved in an organic solvent, then an anchoring functional group compound and a crosslinking aid are added, and finally an optional coupling agent is added. After stirring, the mixture is filtered to obtain the interface layer adhesive. The organic solvent is selected from at least one of N,N-dimethylacetamide, N-methylpyrrolidone, dimethylformamide, cyclohexanone, propylene glycol methyl ether acetate, toluene, and xylene.

9. A method for fabricating a multilayer low dielectric loss flexible circuit board according to claim 7, characterized in that, In step S3, the wet film thickness of the interface layer adhesive is 0.5μm~10μm, the pre-baking temperature is 70℃~130℃, and the pre-baking time is 1min~15min; The wet film thickness of the main layer adhesive is 10μm to 120μm. Drying is carried out by a stepped heating method, with a drying temperature of 80℃ to 170℃ and a drying time of 5min to 60min.

10. A method for fabricating a multilayer low dielectric loss flexible circuit board according to claim 7, characterized in that, In step S6, the lamination and pressing are performed using either rapid pressing or pressure transmission; when using rapid pressing, the pressing temperature is 150℃ to 210℃, and the pressure is 50 kgf / cm². 2 ~150kgf / cm 2 The pressing time is 60s~600s; when using pressure transmission, the pressing temperature is 150℃~190℃, and the pressure is 10kgf / cm. 2 ~80kgf / cm 2 The pressing time is 30 min to 240 min; After pressing, a post-curing treatment is performed at a temperature of 180℃~260℃ for a time of 20min~120min.

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