Method for manufacturing a circuit board and circuit board
Patent Information
- Application Number
- CN202510465256.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-14
- Publication Date
- 2026-10-20
AI Technical Summary
采用介电常数(Dk)和耗散因数(Df)较高的材质作为介质层会导致信号衰减严重，难以满足5G通信、毫米波雷达等高速系统的性能需求；采用具有低介电常数(Dk)和耗散因数(Df)的聚四氟乙烯(PTFE)作为介质层的材料，但其热塑性特性给加工工艺带来挑战
[0006]本申请实施例提供的电路板的制作方法，局部采用低Dk、低Df的第二介质层，在降低信号传输损耗的前提下，能够降低生产成本；另外，本申请设置支撑层，支撑层用于将高频信号传输层的至少部分与其他材质隔绝(例如第一胶层、第一介质层)，能够有效保护高频信号传输层的至少部分，以防高频信号传输层的至少部分被其他材质覆盖而增加信号传输损耗；再者，局部采用低Dk、低Df的第二介质层，剩余部分采用其他材质的介质层，在后续钻孔过程中，钻孔未贯穿第二介质层，则不会存在相关技术中产生铜瘤和孔破的问题，可加工性强。
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Abstract
Description
Technical Field
[0001] This application relates to the field of circuit board technology, and in particular to a method for manufacturing a circuit board and a circuit board. Background Technology
[0002] In high-frequency electronic circuit design, the choice of dielectric material has a significant impact on signal transmission performance and fabrication technology. The dielectric constant (D) is used as the dielectric constant. k and dissipation factor (D) f Using materials with high dielectric constants as the dielectric layer can lead to severe signal attenuation, making it difficult to meet the performance requirements of high-speed systems such as 5G communication and millimeter-wave radar; therefore, materials with low dielectric constants (Dk) are used. k and dissipation factor (D) f Polytetrafluoroethylene (PTFE) is used as the dielectric layer material, but its thermoplastic properties pose challenges to the processing technology. For example, during drilling, PTFE can easily produce residual adhesive or burrs in the hole, and during copper electroplating, problems such as copper nodules and hole breakage can easily occur. Summary of the Invention
[0003] In view of this, it is necessary to provide a method for manufacturing a circuit board that balances the low-loss characteristics and processability of the dielectric material in order to solve the above problems.
[0004] A method for manufacturing a circuit board includes: providing a first circuit substrate, including a first dielectric layer, a first circuit layer, and a support layer, wherein the support layer is located on the side of the first dielectric layer opposite to the first circuit layer; providing a second circuit substrate, including a high-frequency signal transmission layer, a second dielectric layer, and a third dielectric layer, wherein the second dielectric layer is filled in the third dielectric layer, and the high-frequency signal transmission layer is located on the surface of the second dielectric layer and corresponds to the second dielectric layer; pressing the first circuit substrate and the second circuit substrate together with the support layer and the high-frequency signal transmission layer facing inward, wherein the support layer is located in the projection area of the second dielectric layer along the pressing direction; and forming a via that connects the first circuit substrate and the second circuit substrate, wherein the via penetrates the third dielectric layer.
[0005] A circuit board includes a first circuit board, a second circuit board, and vias. The first circuit board includes a first dielectric layer, a first circuit layer, and a support layer, with the support layer located on the side of the first dielectric layer facing away from the first circuit layer. The second circuit board includes a high-frequency signal transmission layer, a second dielectric layer, and a third dielectric layer, with the second dielectric layer filling the third dielectric layer. The high-frequency signal transmission layer is located on the surface of the second dielectric layer and corresponds to the second dielectric layer. The support layer faces the high-frequency signal transmission layer, and along the stacking direction of the first and second circuit boards, the support layer is located within the projection area of the second dielectric layer. The vias connect the first and second circuit boards and penetrate the third dielectric layer.
[0006] The circuit board manufacturing method provided in this application embodiment uses low-D in certain areas. k Low D f The second dielectric layer reduces production costs while minimizing signal transmission loss. Furthermore, this application includes a support layer to isolate at least a portion of the high-frequency signal transmission layer from other materials (e.g., the first adhesive layer, the first dielectric layer), effectively protecting at least a portion of the high-frequency signal transmission layer from being covered by other materials, thus preventing increased signal transmission loss. Additionally, low-D materials are used locally. k Low D f The second dielectric layer is made of a different material, and the remaining part is made of a dielectric layer of other materials. In the subsequent drilling process, if the drill does not penetrate the second dielectric layer, there will be no copper nodules or hole breakage problems as in related technologies, and the process is highly machinable. Attached Figure Description
[0007] Figure 1 A cross-sectional flow diagram illustrating drilling and electroplating of a circuit board substrate, provided for related technologies.
[0008] Figure 2A This is a cross-sectional schematic diagram of the first dielectric layer and the first copper layer provided in the embodiments of this application.
[0009] Figure 2B In order to be in Figure 2A The diagram shows a cross-sectional view of the groove formed on the first dielectric layer.
[0010] Figure 2C In order to be in Figure 2B A cross-sectional schematic diagram of the first circuit board obtained by setting a support layer in the groove shown.
[0011] Figure 3A This is a cross-sectional schematic diagram showing a second dielectric layer disposed on the surface of the second copper layer, as provided in an embodiment of this application.
[0012] Figure 3B To be in accordance with the third copper layer, the third dielectric layer and Figure 3A The diagram shows a cross-section of the second dielectric layer and the second copper layer arranged in that order.
[0013] Figure 3C To be Figure 3B The diagram shows a cross-sectional view of the component after it has been pressed together.
[0014] Figure 3D To Figure 3C The diagram shows a cross-sectional view of the second circuit substrate obtained by fabricating circuitry on the third copper layer to form a high-frequency signal transmission layer.
[0015] Figure 4 In accordance with Figure 2C The first circuit board and the first adhesive layer shown Figure 3D The diagram shows a cross-sectional view of the second circuit board, the second adhesive layer, and the third circuit board arranged in that order.
[0016] Figure 5 To be Figure 4 The diagram shows a cross-sectional view of the component after it has been pressed together.
[0017] Figure 6 In order to be in Figure 5 A schematic cross-sectional view of the circuit board is shown, in which vias and a solder mask are formed on the structure shown.
[0018] Explanation of main component symbols
[0019]
[0020]
[0021] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation
[0022] To better understand the above-mentioned objectives, features, and advantages of this application, the application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Many specific details are set forth in the following description to provide a thorough understanding of this application; the described embodiments are merely some, not all, of the embodiments described in this application.
[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The term "and / or" as used herein includes all and any combination of one or more of the associated listed items.
[0024] In the various embodiments of this application, for ease of description and not limitation, the term "connection" used in the patent application specification and claims is not limited to physical or mechanical connections, whether direct or indirect. Terms such as "upper," "lower," "above," "below," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship also changes accordingly.
[0025] Please see Figure 1The related technology provides a method for manufacturing a circuit board 100', including the steps of: first, providing a circuit board 10, the circuit board 10 including a dielectric layer 13 and a circuit layer 14 stacked together, the dielectric layer 13 using a material with a low dielectric constant (D). k and dissipation factor (D) f The circuit board 100' uses polytetrafluoroethylene (PTFE) to reduce signal loss. During the drilling process of the circuit board 10, PTFE forms residual adhesive 11 and burr peaks 12 on the hole walls. Subsequently, the circuit board 10 undergoes plasma treatment and copper plating. During copper plating, the residual adhesive 11 adheres to the hole walls, and the copper plating coats the residual adhesive 11, forming copper nodules 111. Burr peaks 12 detach during plasma treatment, but they block the hole walls, preventing copper from being deposited on the holes, resulting in hole breakage 121. Both copper nodules 111 and hole breakage 121 reduce the yield of the circuit board 100'.
[0026] Please see Figures 2A to 6 This application provides a method for manufacturing a circuit board 100, which can balance the low-loss characteristics and processability of the dielectric material. The method for manufacturing the circuit board 100 may include the following steps:
[0027] Step S1: Please refer to Figures 2A to 2C A first circuit board 20 is provided. The first circuit board 20 includes a first dielectric layer 21, a first circuit layer 22 and a support layer 23. The support layer 23 is located on the side of the first dielectric layer 21 away from the first circuit layer 22. The support layer 23 has a receiving cavity 231. The opening of the receiving cavity 231 faces the surface away from the first dielectric layer 21.
[0028] The number of layers in the first dielectric layer 21 and the first circuit layer 22 is not limited. In this embodiment, both the first dielectric layer 21 and the first circuit layer 22 are single layers, with the first circuit layer 22 located on the surface of the first dielectric layer 21. The support layer 23 is located on the surface of the first dielectric layer 21 opposite to the first circuit layer 22. A portion of the support layer 23 is housed within the first dielectric layer 21, while another portion protrudes from the first dielectric layer 21.
[0029] The method for manufacturing the first circuit board 20 may include the following steps:
[0030] Step S11: Please refer to Figure 2A It provides a first dielectric layer 21 and a first copper layer 221 stacked together.
[0031] Step S12: Please refer to Figure 2B A groove 211 is formed on the first dielectric layer 21. The groove 211 is formed by a depression on the surface of the first dielectric layer 21 away from the first copper layer 221.
[0032] Step S13: Please refer to Figure 2C A support layer 23 is provided in the groove 211, a portion of the support layer 23 protrudes from the first medium layer 21, and the opening of the receiving cavity 231 faces the surface away from the first medium layer 21.
[0033] The first copper layer 221 is used to form the first circuit layer 22 in subsequent steps. The step of forming the circuit on the first copper layer 221 can be performed on the first circuit substrate 20 (see [link]). Figure 5 The first circuit substrate 20 can be laminated before the second circuit substrate 30 lamination step, or after the first circuit substrate 20 and the second circuit substrate 30 lamination step.
[0034] The support layer 23 has high rigidity and will not deform or collapse significantly during subsequent pressing. The support layer 23 can be made of metal, plastic, or other materials.
[0035] Step S2: Please refer to Figures 3A to 3D A second circuit board 30 is provided, which includes a third dielectric layer 31, a high-frequency signal transmission layer 32, and a second dielectric layer 33, wherein the high-frequency signal transmission layer 32 is located on the surface of the second dielectric layer 33.
[0036] The number of layers in the third dielectric layer 31 and the high-frequency signal transmission layer 32 is not limited. In this embodiment, the third dielectric layer 31 has one layer, and the high-frequency signal transmission layer 32 has two layers, located on opposite surfaces of the third dielectric layer 31. The second dielectric layer 33 penetrates the third dielectric layer 31. The high-frequency signal transmission layer 32 corresponds to the second dielectric layer 33, that is, the high-frequency signal transmission layer 32 is located within the projection area of the second dielectric layer 33 along the pressing direction.
[0037] The high-frequency signal transmission layer 32 may include a first part 321 and a second part 322, which are spaced apart and both are located on the surface of the second dielectric layer 33. The first part 321 may be a signal line and the second part 322 may be a ground line.
[0038] The method for manufacturing the second circuit board 30 may include the following steps:
[0039] Step S21: Please refer to Figure 3A A second copper layer 323 is provided, and a second dielectric layer 33 is disposed on the surface of the second copper layer 323.
[0040] Step S22: Please refer to Figure 3B They are arranged in the order of the third copper layer 324, the third dielectric layer 31, and the second copper layer 323 with the second dielectric layer 33.
[0041] Step S23: Please refer to Figure 3C The third copper layer 324, the third dielectric layer 31, and the second copper layer 323 having the second dielectric layer 33 are laminated together, with the second dielectric layer 33 penetrating the third dielectric layer 31.
[0042] After pressing, the third dielectric layer 31 and the second dielectric layer 33 deform and connect with each other.
[0043] Step S24: Please refer to Figure 3D The third copper layer 324 is fabricated to form a high-frequency signal transmission layer 32.
[0044] The high-frequency signal transmission layer 32 includes a first part 321 and a second part 322. The first part 321 is located on the surface of the second dielectric layer 33, and a portion of the second part 322 is located on the surface of the second dielectric layer 33. That is, along the direction in which the high-frequency signal transmission layer 32 and the second dielectric layer 33 are stacked, the projection of the second dielectric layer 33 covers the first part 321, and the projection of the second dielectric layer 33 coincides with a portion of the second part 322.
[0045] The second copper layer 323 is used to form another high-frequency signal transmission layer 32 in subsequent steps. The second copper layer 323 can be fabricated simultaneously during the fabrication of the third copper layer 324. The fabrication of the second copper layer 323 can also be performed after the lamination of the first circuit substrate 20 and the second circuit substrate 30.
[0046] Step S3: Please refer to Figure 4 The system provides a first adhesive layer 50, a second adhesive layer 60, and a third circuit board 40, arranged in the order of the first circuit board 20, the first adhesive layer 50, the second circuit board 30, the second adhesive layer 60, and the third circuit board 40.
[0047] The third circuit board 40 includes a fourth dielectric layer 41 and a third circuit layer 42. The number of layers for both the fourth dielectric layer 41 and the third circuit layer 42 is not limited. In this embodiment, both the fourth dielectric layer 41 and the third circuit layer 42 are single layers, with the third circuit layer 42 located on the surface of the fourth dielectric layer 41. In other embodiments, multiple third circuit layers 42 can be provided according to the actual circuit layer requirements, or the third circuit layer 42 can be omitted (i.e., the third circuit board 40 can be omitted).
[0048] The first adhesive layer 50 has a through hole 51, which penetrates the two opposite surfaces of the first adhesive layer 50.
[0049] Step S4: Please refer to Figure 5 ,Will Figure 4 The components arranged in the order shown are pressed together.
[0050] After arranging the first circuit board 20, the first adhesive layer 50, the second circuit board 30, the second adhesive layer 60 and the third circuit board 40 in that order, they are pressed together. The first adhesive layer 50 bonds the first circuit board 20 and the second circuit board 30, and the second adhesive layer 60 bonds the second circuit board 30 and the third circuit board 40.
[0051] During the pressing step, the portion of the support layer 23 protruding from the first dielectric layer 21 corresponds to and penetrates the through hole 51. The support layer 23 contacts the second part 322, and the first part 321 is located within the projection area of the receiving cavity 231 along the pressing direction. During the pressing step, the support layer 23 serves to support and isolate the first part 321. The support layer 23 and the first part 321 are spaced apart, and the support layer 23 isolates the first part 321 from the first adhesive layer 50 and the first dielectric layer 21. The first adhesive layer 50 and the first dielectric layer 21 will not cover the first part 321 during the flow process.
[0052] After pressing, the support layer 23 is located within the projection area of the second dielectric layer 33 along the pressing direction, and at least a portion of the high-frequency signal transmission layer 32 is located within the projection area of the support layer 23 along the pressing direction. In this embodiment, the support layer 23 is connected to the second part 322, and the support layer 23, the second part 322, and the second dielectric layer 33 enclose a cavity 232. The first part 321 is located in the cavity 232, and the cavity 232, except for the first part 321, is filled with air. The air has a D k =1, D f It is 0.
[0053] Step S5: Please refer to Figure 6 This forms a through hole 70 that connects the first circuit board 20, the second circuit board 30, and the third circuit board 40.
[0054] In this embodiment, a via 70 is formed to penetrate the first circuit board 20, the first adhesive layer 50, the second circuit board 30, the second adhesive layer 60, and the third circuit board 40 to electrically connect the first circuit board 20, the second circuit board 30, and the third circuit board 40; a solder resist layer 73 is formed on the surface of the first circuit board 20 and the third circuit board 40.
[0055] Forming the via 70 may specifically include the following steps: drilling the first circuit substrate 20, the first adhesive layer 50, the second circuit substrate 30, the second adhesive layer 60, and the third circuit substrate 40 to form a through hole 71, exposing the first circuit layer 22, the first dielectric layer 21, the first adhesive layer 50, the third dielectric layer 31, the second adhesive layer 60, the third circuit layer 42, and the fourth dielectric layer 41 through the through hole 71; plasma treating the hole wall of the through hole 71, followed by electroplating to form an electroplated layer, which is located on the hole wall, forming the via 70. The via 70 penetrates the first circuit layer 22, the first dielectric layer 21, the first adhesive layer 50, the third dielectric layer 31, the second adhesive layer 60, the third circuit layer 42, and the fourth dielectric layer 41, and electrically connects the first circuit layer 22, the high-frequency signal transmission layer 32, and the third circuit layer 42. The via 70 will not penetrate the second dielectric layer 33. In the process of forming the via 70, the generation of residual adhesive 11 and burr peak 12 in related technologies is fundamentally avoided, thereby avoiding the generation of copper nodules 111 and hole breaks 121.
[0056] The electroplated layer formed after the electroplating process can also be located on the surface of the first copper layer 221. A circuit is then fabricated on the first copper layer 221 and the electroplated layer located on the surface of the first copper layer 221 to form a first circuit layer 22. It is understood that in other embodiments, the steps for forming the first circuit layer 22 are not limited to this.
[0057] In other embodiments, the way in which the first circuit layer 22, the high-frequency signal transmission layer 32, and the third circuit layer 42 are connected is not limited to the via 70 described above. The via 70 can be a through hole or a blind hole. In other embodiments, if the third circuit substrate 40 is omitted, the step of setting the second adhesive layer 60 is also omitted, and the via 70 does not need to connect to the third circuit substrate 40.
[0058] D of the second dielectric layer 33 k D smaller than the first dielectric layer 21 k D of the second dielectric layer 33 f D smaller than the first dielectric layer 21 f ;D of the second dielectric layer 33 k D smaller than the third dielectric layer 31 k D of the second dielectric layer 33 f D smaller than the third dielectric layer 31 f ;D of the second dielectric layer 33 k D smaller than the fourth dielectric layer 41 k D of the second dielectric layer 33 f D smaller than the fourth dielectric layer 41 fThe first dielectric layer 21, the third dielectric layer 31, and the fourth dielectric layer 41 can all be selected from polypropylene (PP), epoxy resin fiberglass board (FR4), liquid crystal polymer (LCP), and low-loss substrates (such as BT resin or composite substrates). The material of the second dielectric layer 33 includes polytetrafluoroethylene (PTFE). The table below lists the D values of the above materials. k and D f Summarize the results.
[0059] Material <![CDATA[D k ]]> <![CDATA[D f ]]> PP 2.0～2.6 Approximately 0.001 FR4 4.2～4.4 0.018～0.022 LCP 3.9～4.5 0.018～0.034 Low loss substrate 3.5～4.0 0.003～0.0065 PTFE 2.1～2.3 0.0009～0.001 Air 1 0
[0060] The method for manufacturing the circuit board 100 provided in this application embodiment uses low-D in certain areas. k Low D f The second dielectric layer 33 reduces production costs while minimizing signal transmission loss. Furthermore, this application includes a support layer 23, which isolates at least a portion of the high-frequency signal transmission layer 32 from other materials (e.g., the first adhesive layer 50, the first dielectric layer 21), effectively protecting at least a portion of the high-frequency signal transmission layer 32 from being covered by other materials, thus preventing increased signal transmission loss. Additionally, low-D materials are used locally. k Low D f The second dielectric layer 33 is used, and the remaining part is a dielectric layer of other materials. In the subsequent drilling process, if the drill does not penetrate the second dielectric layer 33, the problems of copper nodules 111 and hole breaks 121 in the related technologies will not exist, and the processability is strong.
[0061] Please refer to it again. Figure 6 This application provides a circuit board 100, which may include a first circuit board 20, a first adhesive layer 50, a second circuit board 30, a second adhesive layer 60 and a third circuit board 40 stacked together. The first adhesive layer 50 bonds the first circuit board 20 and the second circuit board 30, and the second adhesive layer 60 bonds the second circuit board 30 and the third circuit board 40.
[0062] The first circuit board 20 may include a first dielectric layer 21, a first circuit layer 22, and a support layer 23. The support layer 23 is located on the side of the first dielectric layer 21 opposite to the first circuit layer 22. The support layer 23 has a receiving cavity 231, the opening of which faces the surface opposite to the first dielectric layer 21. A portion of the support layer 23 is located in the first dielectric layer 21, and the remaining portion of the support layer 23 penetrates the first adhesive layer 50 and is connected to the first circuit board 20. The second circuit board 30 may include a third dielectric layer 31, a high-frequency signal transmission layer 32, and a second dielectric layer 33. The second dielectric layer 33 penetrates the third dielectric layer 31. The high-frequency signal transmission layer 32 is located on the surface of the second dielectric layer 33 and corresponds to the second dielectric layer 33, i.e., the high-frequency signal transmission layer 32 is located within the projection area of the second dielectric layer 33 along the pressing direction. The high-frequency signal transmission layer 32 can be connected to the support layer 23, which is located within the projection area of the second dielectric layer 33 along the pressing direction. At least a portion of the high-frequency signal transmission layer 32 is located within the projection area of the support layer 23 along the pressing direction.
[0063] The third circuit board 40 may include a fourth dielectric layer 41 and a third circuit layer 42, with the third circuit layer 42 located on the surface of the fourth dielectric layer 41. The circuit board 100 may also include a via 70, which penetrates the first circuit board 20, the first adhesive layer 50, the second circuit board 30, the second adhesive layer 60, and the third circuit board 40 to electrically connect the first circuit board 20, the second circuit board 30, and the third circuit board 40.
[0064] D of the second dielectric layer 33 k D smaller than the first dielectric layer 21 k D of the second dielectric layer 33 f D smaller than the first dielectric layer 21 f ;D of the second dielectric layer 33 k D smaller than the third dielectric layer 31 k D of the second dielectric layer 33 f D smaller than the third dielectric layer 31 f ;D of the second dielectric layer 33 k D smaller than the fourth dielectric layer 41 k D of the second dielectric layer 33 f D smaller than the fourth dielectric layer 41 f Choose low D k Low D f The second dielectric layer 33 helps to reduce signal transmission loss of the circuit board 100.
[0065] The high-frequency signal transmission layer 32 may include a first portion 321 and a second portion 322, which are spaced apart and both are located on the surface of the second dielectric layer 33. The opening of the receiving cavity 231 faces the high-frequency signal transmission layer 32, and the support layer 23 is in contact with the second portion 322. Along the direction in which the first circuit board 20 and the second circuit board 30 are stacked, the first portion 321 is located within the projection area of the receiving cavity 231. The support layer 23 isolates the first portion 321 from the first dielectric layer 21 and the first adhesive layer 50.
[0066] The support layer 23 and the first part 321 are spaced apart, and the surface of the support layer 23 facing the first part 321 can be curved. The support layer 23, the second part 322, and the second dielectric layer 33 enclose a cavity 232, in which the first part 321 is located, and the cavity 232 is also filled with air. The air's D... k and D f The values are all relatively small, which helps to further reduce signal transmission loss.
[0067] The circuit board 100 may also include a solder resist layer 73 located on the surfaces of the first circuit board 20 and the third circuit board 40. In other embodiments, the third circuit board 40 and the second adhesive layer 60 may be omitted.
[0068] The circuit board 100 provided in this embodiment of the application uses low-D in some parts. k Low D f The second dielectric layer 33 can reduce production costs while reducing signal transmission loss; the support layer 23 can isolate the first part 321 from other materials to further reduce signal transmission loss; the circuit board 100 does not have the problems of copper nodules 111 and holes 121 in related technologies.
[0069] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the scope of the technical solutions of this application.
Claims
1. A method for manufacturing a circuit board, characterized in that, include: A first circuit board is provided, including a first dielectric layer, a first circuit layer and a support layer, wherein the support layer is located on the side of the first dielectric layer opposite to the first circuit layer; A second circuit board is provided, including a high-frequency signal transmission layer, a second dielectric layer and a third dielectric layer, wherein the second dielectric layer is filled in the third dielectric layer, and the high-frequency signal transmission layer is located on the surface of the second dielectric layer and corresponds to the second dielectric layer. The first circuit board and the second circuit board are pressed together with the support layer and the high-frequency signal transmission layer facing inward, and the support layer is located in the projection area of the second dielectric layer along the pressing direction; as well as A via is formed to connect the first circuit substrate and the second circuit substrate, and the via penetrates the third dielectric layer.
2. The method for manufacturing a circuit board according to claim 1, characterized in that, The high-frequency signal transmission layer includes a first part and a second part. The support layer and the first part are spaced apart. The support layer, the second part, and the second dielectric layer surround to form a cavity. The first part is located in the cavity, and the cavity is also filled with air.
3. The method for manufacturing a circuit board according to claim 1, characterized in that, D of the second dielectric layer k D smaller than the first dielectric layer k The second dielectric layer D f D smaller than the first dielectric layer f ; D of the second dielectric layer k D is smaller than that of the third dielectric layer k The second dielectric layer D f D is smaller than that of the third dielectric layer f .
4. The method for manufacturing a circuit board according to any one of claims 1 to 3, characterized in that, The support layer protrudes from the first dielectric layer, and prior to the step of pressing the first circuit board and the second circuit board together, the manufacturing method further includes: A first adhesive layer is provided, wherein the first adhesive layer has through holes; and After being arranged in the order of the first circuit board, the first adhesive layer and the second circuit board, they are pressed together, and the support layer passes through the through hole.
5. The method for manufacturing a circuit board according to any one of claims 1-3, characterized in that, The support layer protrudes from the first dielectric layer, and prior to the step of pressing the first circuit board and the second circuit board together, the manufacturing method further includes: A first adhesive layer and a second adhesive layer are provided, wherein the first adhesive layer has a through hole; Provide a third circuit board; The first circuit board, the first adhesive layer, the second circuit board, the second adhesive layer and the third circuit board are arranged in that order and then pressed together, with the support layer passing through the through hole; After the lamination step, the via is formed through the first circuit board, the first adhesive layer, the second circuit board, the second adhesive layer and the third circuit board to electrically connect the first circuit board, the second circuit board and the third circuit board.
6. A circuit board, characterized in that, include: A first circuit board includes a first dielectric layer, a first circuit layer, and a support layer, wherein the support layer is located on the side of the first dielectric layer opposite to the first circuit layer. as well as The second circuit board includes a high-frequency signal transmission layer, a second dielectric layer, and a third dielectric layer. The second dielectric layer is filled in the third dielectric layer. The high-frequency signal transmission layer is located on the surface of the second dielectric layer and corresponds to the second dielectric layer. The support layer faces the high-frequency signal transmission layer and is located in the projection area of the second dielectric layer along the direction in which the first circuit board and the second circuit board are stacked. as well as A via is provided to connect the first circuit board and the second circuit board, and the via penetrates the third dielectric layer.
7. The circuit board according to claim 6, characterized in that, The high-frequency signal transmission layer includes a first part and a second part. The support layer and the first part are spaced apart. The support layer, the second part, and the second dielectric layer surround to form a cavity. The first part is located in the cavity, and the cavity is also filled with air.
8. The circuit board according to claim 6, characterized in that, D of the second dielectric layer k D smaller than the first dielectric layer k The second dielectric layer D f D smaller than the first dielectric layer f ; D of the second dielectric layer k D is smaller than that of the third dielectric layer k The second dielectric layer D f D is smaller than that of the third dielectric layer f .
9. The circuit board according to any one of claims 6-8, characterized in that, The circuit board further includes a first adhesive layer with a through hole, the first adhesive layer being located between the first circuit substrate and the second circuit substrate; the support layer protrudes from the first dielectric layer and penetrates through the through hole.
10. The circuit board according to claim 9, characterized in that, The circuit board further includes a second adhesive layer and a third circuit board. The second adhesive layer is located between the second circuit board and the third circuit board. The via penetrates the first circuit board, the first adhesive layer, the second circuit board, the second adhesive layer, and the third circuit board to electrically connect the first circuit board, the second circuit board, and the third circuit board.