A method and apparatus for stacking communication circuit boards

Abstract

This invention relates to a method and apparatus for stacking communication circuit boards. By employing a multi-level positioning hole system and optimized drilling, copper plating, and hole plugging processes, this invention ensures precise alignment between layers and structural stability, has high-precision positioning and pressing capabilities, effectively reduces the risk of hole wall cracks and dielectric layer peeling, and improves the reliability and heat dissipation performance of the circuit board under extreme temperature cycling.

Description

Technical Field

[0001] This invention relates to the field of PCB manufacturing technology, specifically to a method and apparatus for stacking communication circuit boards. Background Technology

[0002] Commercial spaceflight and the low-altitude economy have risen to the level of national strategic emerging industries. The demand for equipment such as low-altitude drones and low-orbit satellites has grown dramatically, directly driving the expansion of the market for supporting printed circuit boards (PCBs). However, the operating environment of these aircraft is extremely harsh. Their electronic systems must simultaneously withstand the severe mechanical vibrations during launch / recovery, the extreme temperature fluctuations in space or high altitudes (e.g., the surface temperature of low-orbit satellites cyclically between -200°C and +150°C), and the low-loss transmission requirements of high-frequency radio frequency signals inside and outside the atmosphere. At the same time, airborne equipment is evolving towards miniaturization and multi-functional integration, forcing PCBs to achieve high-layer (typically more than twenty layers) stacking and multi-level blind via interconnections within a limited area to support high-density pin devices, and employing resin-filled via technology to ensure board surface flatness and interlayer crack resistance. The local heat flux density of high-power transceiver components and processor chips is extremely high. If heat cannot be effectively dissipated through a thermally conductive medium or metal substrate, it will directly threaten soldering reliability and long-term service life. While conventional FR-4 substrates or low- to mid-level high-density interconnect boards have proven mature in the consumer electronics field, they struggle to simultaneously achieve low dielectric loss, high heat resistance, and process compatibility with multi-level blind via fabrication. They often exhibit hole wall cracks or dielectric layer peeling after extreme temperature cycling tests, or fail due to localized overheating caused by simple heat dissipation structures.

[0003] Therefore, there is an urgent need to develop a new circuit board solution that can fully meet multiple performance requirements such as high multilayer, multi-level blind vias, resin filling, low loss, weather resistance and efficient heat dissipation, in order to break through the current technical bottlenecks and ensure the reliable engineering deployment of commercial aerospace and low-altitude equipment. Summary of the Invention

[0004] In view of the above problems, the present invention provides a communication circuit board stacking method and apparatus to solve the problem that although existing conventional FR-4 substrates or low-to-medium-density interconnect boards have mature performance in the consumer electronics field, they are difficult to simultaneously achieve low dielectric loss, high heat resistance and process compatibility of multi-level blind via processing. They often experience hole wall cracks or dielectric layer peeling after extreme temperature cycling tests, or local overheating failure due to simple heat dissipation structure.

[0005] According to one aspect of the present invention, a method for stacking communication circuit boards is provided, the method comprising: A first multilayer board is obtained, and a first drilling process is performed on the first multilayer board to create a first communication hole. The first communication hole is then copper plated, plugged, and subjected to a first outer layer circuit process. A second drilling process is performed on the first multilayer board to create a first positioning hole. Obtain the first outer layer board, and perform a third drilling process on the first outer layer board to create the second communication hole. Then, perform copper plating, hole plugging, and a second outer layer circuit on the second communication hole. Perform a fourth drilling process on the first outer layer board to create the second positioning hole. Obtain the second outer layer board, perform the first inner layer circuit processing on the second outer layer board, and perform the fifth drilling process on the second outer layer board to create the third positioning hole; Obtain the third outer layer board, perform a second inner layer circuit processing on the third outer layer board, and perform a sixth drilling process on the third outer layer board to create the fourth positioning hole; Based on the first positioning hole, the second positioning hole, the third positioning hole, and the fourth positioning hole, the first multilayer board, the first outer layer board, the second outer layer board, and the third outer layer board are positioned and pressed together to form the second multilayer board. The second multilayer board is then subjected to a seventh drilling process to create the third communication hole. Finally, the second multilayer board is post-processed to create the target PCB board.

[0006] In some implementations, obtaining the first multilayer board specifically includes: The raw material board is cut into core boards using a slitting device; The core board is subjected to inner layer circuit processing and inner layer AOI processing to fabricate inner layer circuits on the core board. Multiple core boards are pressed together to form a first multilayer board, and after the first multilayer board is cut and browned, it proceeds to the next process.

[0007] In some embodiments, the first multilayer board is subjected to a first drilling process to create a first communication hole, specifically including: A first communication hole is made in the first multilayer board by laser drilling, embedded drilling and mechanical drilling, wherein the first communication hole is a blind hole or a through hole. The first multilayer board is cleaned by high-pressure water washing and plasma desmearing, and then proceeds to the next process after AOI inspection of the first communication hole.

[0008] In some embodiments, the first communication hole undergoes copper plating, via plugging, and a first outer layer circuit processing, specifically including: The first communication hole is subjected to a hole-filling electroplating process to create a first copper plating layer in the first communication hole; After applying a dry film to the first communication hole, pattern electroplating is performed to create a second copper plating layer on the first copper plating layer, and excess dry film is removed. Back-drill the first communication hole of the first multilayer board to make the target layers of the first multilayer board connected, and perform AOI inspection after high-pressure water washing of the first multilayer board. The first multilayer board is subjected to a first resin plugging process from its first surface, a second resin plugging process from its second surface, and a baking process and a resin grinding process. The first multilayer board is subjected to a third resin plugging process from its first surface, a fourth resin plugging process from its second surface, and a baking process and a resin grinding process. After the first multilayer board is subjected to board electrical processing, the outer layer circuitry and outer layer AOI inspection are performed on the first multilayer board. After completion, the next process begins.

[0009] In some embodiments, a first outer layer board is obtained, and a third drilling process is performed on the first outer layer board to create a second communication hole. The second communication hole is then copper-plated, plugged, and subjected to a second outer layer circuit. A fourth drilling process is then performed on the first outer layer board to create a second positioning hole. Specifically, this includes: The raw material board is cut into the first outer layer board using a slitting device; The first outer layer board is drilled and then cleaned by high-pressure water washing and plasma descaling. The first multilayer board is subjected to pulse flash plating to thicken the copper plating layer of the first multilayer board. After the second communication hole is plated with a dry film, pattern electroplating is performed to thicken the copper plating layer of the first multilayer board a second time, and excess dry film is removed. The first outer layer plate is drilled a fourth time to create a second positioning hole, and the second positioning hole matches the first positioning hole.

[0010] In some embodiments, after the second outer layer plate is drilled a fifth time to create the third positioning hole, the method further includes: The second outer layer is first grooved using a roughing method, and then the second multilayer board is second grooved using a fine grinding method to form grooves in the second outer layer for pressing PP film.

[0011] In some embodiments, non-grooved areas are provided in the second and third outer layers, and PTH holes are provided in the non-grooved areas to improve the bonding force; NPTH holes are provided in the enlarged area of ​​the second outer layer, and a groove is provided on the side of the second outer layer adjacent to the first outer layer, the groove communicating with the NPTH holes for heat dissipation.

[0012] In some embodiments, post-processing of the second multilayer board to fabricate the target PCB board specifically includes: The second multilayer board undergoes board electrical processing, a third outer layer circuit processing, and AOI inspection to fabricate the outer layer circuitry on the second multilayer board. The second multilayer board is sequentially subjected to solder resist treatment, text processing, electroless gold treatment, forming treatment, pressure baking inspection hole treatment, and step hole drilling treatment to obtain the target PCB board.

[0013] In some embodiments, the first positioning hole, the second positioning hole, the third positioning hole, and the fourth positioning hole all include round holes and square slot holes. The round holes are located at the four corners of the first multilayer plate, the first outer layer plate, the second outer layer plate, the third outer layer plate, or the fourth outer layer plate, and the square slot holes are located between adjacent round holes to improve the pressing and positioning accuracy.

[0014] According to another aspect of the present invention, a communication circuit board stacking apparatus is provided, the apparatus being used to perform the above-described communication circuit board stacking method.

[0015] The beneficial effects of the communication circuit board stacking method and apparatus of the present invention are as follows: The present invention obtains a first multilayer board, performs a first drilling process on the first multilayer board to create a first communication hole, and performs copper plating, hole plugging, and a first outer layer circuit processing on the first communication hole; then performs a second drilling process on the first multilayer board to create a first positioning hole; obtains a first outer layer board, performs a third drilling process on the first outer layer board to create a second communication hole, and performs copper plating, hole plugging, and a second outer layer circuit processing on the second communication hole; then performs a fourth drilling process on the first outer layer board to create a second positioning hole; obtains a second outer layer board, performs a first inner layer circuit processing on the second outer layer board, and performs a fifth drilling process on the second outer layer board to create a third positioning hole; obtains a third... The outer layer board undergoes a second inner layer circuit processing, followed by a sixth drilling process to create the fourth positioning hole. Based on the first, second, third, and fourth positioning holes, the first multilayer board, first outer layer board, second outer layer board, and third outer layer board are positioned and pressed together to form the second multilayer board. The second multilayer board undergoes a seventh drilling process to create the third communication hole. The second multilayer board is then post-processed to create the target PCB board. By employing a multi-level positioning hole system and optimized drilling, copper plating, and via plugging processes, precise interlayer alignment and structural stability are ensured. This provides high-precision positioning and pressing capabilities, effectively reducing the risk of hole wall cracks and dielectric layer peeling, and improving the reliability and heat dissipation performance of the circuit board under extreme temperature cycling.

[0016] The above description is merely an overview of the technical solutions of the embodiments of the present invention. In order to better understand the technical means of the embodiments of the present invention and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0017] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 A flowchart illustrating the communication circuit board stacking method according to an embodiment of the present invention is shown; Figure 2 A flowchart illustrating step S1 of an embodiment provided by the present invention is shown; Figure 3 A flowchart illustrating step S2 of an embodiment provided by the present invention is shown; Figure 4 A flowchart illustrating step S5 of an embodiment provided by the present invention is shown; Figure 5 A schematic diagram of the structure of the target PCB board according to an embodiment of the present invention is shown; Figure 6 A schematic diagram of the structure of the first positioning hole according to an embodiment of the present invention is shown. Detailed Implementation

[0018] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0019] Example 1: Figure 1 This illustration shows a first embodiment of a communication circuit board stacking method provided by the present invention, offering a novel circuit board solution capable of comprehensively meeting multiple performance requirements such as high multilayer construction, multi-level blind vias, resin filling, low loss, weather resistance, and efficient heat dissipation. The method includes: S1, Obtain the first multilayer board, perform a first drilling process on the first multilayer board to create the first communication hole, and perform copper plating, hole plugging and first outer layer circuit processing on the first communication hole, and perform a second drilling process on the first multilayer board to create the first positioning hole. S2, obtain the first outer layer board, and perform a third drilling process on the first outer layer board to create the second communication hole, and perform copper plating, hole plugging and a second outer layer circuit on the second communication hole, and perform a fourth drilling process on the first outer layer board to create the second positioning hole. S3, obtain the second outer layer board, perform the first inner layer circuit processing on the second outer layer board, and perform the fifth drilling process on the second outer layer board to create the third positioning hole; S4, obtain the third outer layer board, perform the second inner layer circuit processing on the third outer layer board, and perform the sixth drilling process on the third outer layer board to create the fourth positioning hole; S5, based on the first positioning hole, the second positioning hole, the third positioning hole and the fourth positioning hole, the first multilayer board, the first outer layer board, the second outer layer board and the third outer layer board are positioned and pressed together to form the second multilayer board, and the second multilayer board is subjected to a seventh drilling process to make the third communication hole, and the second multilayer board is post-processed to make the target PCB board.

[0020] In steps S1-S5, the specific implementation process may include the following steps: Obtaining a first multilayer board. This first multilayer board can be formed by conventional lamination processes of several pre-treated core boards and prepreg sheets, or by directly purchasing pre-fabricated multilayer board substrates. Performing a first drilling process on the first multilayer board to create a first communication hole. This drilling process can use mechanical drilling equipment to form holes in the first multilayer board, for example, by drilling with a conventional drill bit. Performing copper plating, hole plugging, and a first outer layer circuit processing on the first communication hole. Specifically, the copper plating process can use conventional chemical copper plating or electroplating to form a conductive layer on the hole wall; the hole plugging process can use a single resin filling and curing process; the first outer layer circuit processing can use a traditional etching process to create the outer layer circuitry. Performing a second drilling process on the first multilayer board to create a first positioning hole. The creation of this positioning hole can be performed at a designated location on the first multilayer board using mechanical drilling equipment.

[0021] Obtain the first outer layer board. This first outer layer board can be a prefabricated single-layer or double-layer copper-clad laminate as the substrate. Perform a third drilling process on the first outer layer board to create the second communication hole. This drilling process can use mechanical drilling equipment to form holes in the first outer layer board. Perform copper plating, hole plugging, and a second outer layer circuit on the second communication hole. The copper plating can use conventional chemical copper plating or electroplating processes to form a conductive layer on the hole wall; the hole plugging can use a single resin filling and curing process; the second outer layer circuit can use a traditional etching process to create the outer layer circuit. Perform a fourth drilling process on the first outer layer board to create the second positioning hole. The positioning hole can be created at a designated location on the first outer layer board using mechanical drilling equipment.

[0022] Obtain the second outer layer board. This second outer layer board can be a prefabricated single-layer or double-layer copper-clad laminate as the substrate. Perform the first inner layer circuit processing on the second outer layer board. This inner layer circuit processing can be performed using traditional etching processes. Then, perform a fifth drilling process on the second outer layer board to create the third positioning holes. These positioning holes can be created at designated locations on the second outer layer board using mechanical drilling equipment.

[0023] Obtain the third outer layer board. This third outer layer board can be a prefabricated single-layer or double-layer copper-clad laminate as the substrate. Perform a second inner layer circuit processing on this third outer layer board. This inner layer circuit processing can be done using traditional etching processes. Then, perform a sixth drilling process on the third outer layer board to create the fourth positioning hole. This positioning hole can be created at designated locations on the third outer layer board using mechanical drilling equipment.

[0024] Based on the first, second, third, and fourth positioning holes, the first multilayer board, the first outer layer board, the second outer layer board, and the third outer layer board are positioned and pressed together to form the second multilayer board. This positioning and pressing process can be achieved manually or through simple mechanical alignment, aligning the positioning holes of each layer board, followed by a conventional hot-pressing process. A seventh drilling process is then performed on the second multilayer board to create the third communication hole. This drilling process can be carried out using mechanical drilling equipment to form holes in the pressed second multilayer board. Post-processing is then performed on the second multilayer board to fabricate the target PCB board. This post-processing may include conventional surface treatment, solder resist printing, text printing, and shaping and cutting processes.

[0025] The communication circuit board stacking method proposed in this application effectively achieves the stacking of high-multilayer circuit boards by performing drilling, copper plating, via plugging, and circuit processing on each layer in stages, and using positioning holes for precise lamination. This provides support for the integration of high-density pin devices. This method helps improve the reliability of interlayer connections on the circuit board and lays the foundation for subsequent optimization of heat dissipation structures and low-loss transmission performance, thereby meeting the basic performance requirements of commercial aerospace and low-altitude equipment for circuit boards in complex environments.

[0026] Example 2: Based on Embodiment 1, the present invention provides a second embodiment of a communication circuit board stacking method to further describe the communication circuit board stacking method.

[0027] In some embodiments of step S1, obtaining the first multilayer board specifically includes: cutting the raw material board into a core board using a slitting device; performing inner layer circuit processing and inner layer AOI processing on the core board to fabricate inner layer circuits on the core board; pressing multiple core boards together to form the first multilayer board, and then proceeding to the next process after performing cutting and grinding processing and browning processing on the first multilayer board.

[0028] Through the above technical solution, in the process of obtaining the first multilayer board, this application specifies in detail a series of refined steps, from the blanking of the raw material board to the core board, the fabrication and testing of the inner layer circuitry of the core board, and the lamination, grinding, and browning treatment of multiple core boards. This strict control over the first multilayer board preparation process ensures the accuracy of its internal circuitry, the reliability of interlayer bonding, and the stability of the overall structure. Through inner layer AOI processing, circuit defects can be detected and corrected in a timely manner, preventing the introduction of substandard semi-finished products into subsequent processes. At the same time, the browning treatment significantly improves the interlayer bonding strength, effectively reducing the risk of delamination. Therefore, this solution provides a high-quality, high-reliability base material for subsequent complex processes such as drilling, copper plating, and plugging of the first communication holes, as well as the processing of outer layer circuitry, thereby significantly improving the manufacturing accuracy of the entire communication circuit board stacking method and the performance stability of the final product.

[0029] In some embodiments of step S1, a first drilling process is performed on the first multilayer board to create a first communication hole, specifically including: The first communication hole is created on a multilayer board using laser drilling, subsurface drilling, and mechanical drilling. This first communication hole can be a blind hole or a through hole. Laser drilling is a non-contact processing method that uses a high-energy laser beam to ablate, melt, or vaporize the material surface to form a hole. Its advantages include the ability to achieve extremely small hole diameters, high-precision positioning, and the creation of blind holes, making it particularly suitable for creating micro-vias in high-density interconnect (HDI) boards. Subsurface drilling is mainly used to achieve electrical connections between inner layers, helping to increase wiring density and save board space. It is typically achieved using specialized subsurface drilling equipment to precisely control the drilling depth, ensuring that the hole penetrates only the target inner layer. Mechanical drilling is a traditional drilling method that uses a high-speed rotating drill bit to cut the material to form a hole. Mechanical drilling is suitable for creating through holes with larger diameters and is characterized by relatively low cost and high efficiency.

[0030] The first multilayer board is cleaned through high-pressure water washing and plasma desmearing, and then proceeds to the next process after AOI inspection of the first communication hole. High-pressure water washing aims to rinse the first multilayer board after drilling with high-pressure water jets to effectively remove mechanical impurities such as debris, dust, and cutting fluid residue generated during drilling. By adjusting the water pressure, temperature, and spray angle, thorough cleaning of the hole walls and board surface is ensured, providing a clean surface for subsequent copper plating. Plasma desmearing is a method that uses plasma to chemically treat the hole walls. Its main purpose is to remove residual resin residue (such as epoxy resin) from the hole walls, activate the hole wall surface, and thus improve the adhesion between the subsequent copper plating layer and the hole walls.

[0031] Through the aforementioned technical solution, when performing the first drilling process on the first multilayer board to create the first communication via, a combination of laser drilling, subsurface drilling, and mechanical drilling is employed. This allows for the flexible and efficient fabrication of high-precision blind or through-hole communication vias, tailored to different design requirements and hole diameter specifications. Laser drilling ensures the fabrication of small-diameter and high-precision blind vias, subsurface drilling achieves tight connections between inner layers, and mechanical drilling meets the needs for through-holes and larger diameters, thereby significantly improving the wiring density and functional integration of the first multilayer board. Simultaneously, after drilling, high-pressure water washing thoroughly removes mechanical debris, and plasma desmearing effectively removes residual resin from the hole walls, activating the hole wall surface and greatly improving its cleanliness and roughness. This provides an ideal substrate for subsequent copper plating, ensuring good adhesion of the copper plating layer and reliable electrical connections. In addition, AOI inspection before proceeding to the next process can promptly identify and remove unqualified first communication holes, effectively controlling product quality, avoiding the accumulation of defects, and improving the overall manufacturing yield and reliability of communication circuit boards.

[0032] In some embodiments of step S1, the first communication hole undergoes copper plating, hole plugging, and the first outer layer circuit processing; see [link to relevant documentation]. Figure 2 Specifically, it includes: S11, A hole-filling electroplating process is performed on the first communication hole to create a first copper plating layer. The aim is to completely fill the blind or through hole with conductive material (typically copper), rather than merely covering the hole walls. This process forms a solid, void-free conductive pillar inside the first communication hole, i.e., the first copper plating layer, thereby significantly improving the electrical connection reliability, thermal conductivity, and mechanical strength of the hole. This process is typically achieved through precise control of the electroplating solution composition, current density, and additives to promote copper growth from the bottom of the hole upwards until it is completely filled.

[0033] S12, after applying a dry film to the first communication hole, pattern electroplating is performed to create a second copper plating layer from the first copper plating layer, removing excess dry film. This dry film is a photosensitive polymer film laminated onto the surface of the first multilayer board, including the first communication hole where the first copper plating layer has already formed. After exposure and development, the dry film forms a specific pattern, exposing areas requiring further electroplating. The pattern electroplating performed on this basis involves depositing copper further on top of the first copper plating layer within the area defined by the dry film, forming a second copper plating layer to achieve the required line thickness and in-hole copper thickness. After electroplating, excess dry film is removed by chemical stripping.

[0034] S13, back-drill the first communication hole of the first multilayer board to connect the target layers of the first multilayer board, and perform AOI inspection after high-pressure water washing of the first multilayer board. Back-drilling is a drilling process with precise depth control, used to remove portions of plated through holes that exceed the actual connection requirements. Its purpose is to eliminate "residual stubs" in the high-speed signal transmission path, thereby effectively reducing signal reflection, reducing impedance discontinuity, and significantly improving signal integrity, which is crucial for high-frequency communication circuit boards. After back-drilling, high-pressure water washing thoroughly removes debris and chemical residues generated during the drilling process, ensuring the cleanliness of the board surface and the inside of the hole. The subsequent AOI inspection is used to check the back-drilling quality, hole wall integrity, and board surface cleanliness to ensure that the process meets the requirements.

[0035] S14, the first multilayer board is subjected to a first resin plugging process from the first surface of the first multilayer board, the first multilayer board is subjected to a second resin plugging process from the second surface of the first multilayer board, and the first multilayer board is subjected to baking and resin grinding processes. S15, a third resin plugging process is performed on the first surface of the first multilayer board, and a fourth resin plugging process is performed on the second surface of the first multilayer board. The first multilayer board is then baked and resin-polished. This application employs a multi-stage, double-sided plugging strategy, alternating between the first and second surfaces of the first multilayer board, i.e., first, second, third, and fourth resin plugging processes. This strategy ensures that the resin fully penetrates and completely fills the pores, effectively avoiding voids or air bubbles that may occur with a single plugging process. After each plugging, a baking process is performed to cure the resin, and resin polishing is performed to remove excess resin, resulting in a highly flat board surface. This meticulous plugging and polishing process is crucial for the refined fabrication of subsequent outer layer circuitry.

[0036] S16. After performing board electrical processing on the first multilayer board, perform outer layer circuit fabrication and outer layer AOI testing on the first multilayer board. After completion, proceed to the next process.

[0037] By employing the aforementioned technical solutions, the via-filling electroplating and patterned electroplating processes on the first communication hole ensure the formation of a dense and uniform first and second copper plating layers within the hole. This effectively avoids voids and uneven plating issues that may occur in traditional copper plating processes, significantly improving the reliability and conductivity of electrical connections. Furthermore, by back-drilling the first communication hole on the first multilayer board, unnecessary hole segments are precisely removed, greatly reducing signal reflection and impedance discontinuities, thereby optimizing the transmission quality of high-frequency signals, which is crucial for the performance of the communication circuit board. In addition, multiple resin-filling processes are performed on the first and second surfaces of the first multilayer board, combined with baking and resin polishing, ensuring that the communication hole is thoroughly filled and the surface is highly flat. This provides an ideal substrate for subsequent fine outer layer circuit fabrication, effectively avoiding circuit defects caused by surface unevenness, and improving product yield and overall reliability.

[0038] In some embodiments of step S2, a first outer layer board is obtained, and a third drilling process is performed on the first outer layer board to create a second communication hole. The second communication hole is then copper-plated, plugged, and subjected to a second outer layer circuit. A fourth drilling process is performed on the first outer layer board to create a second positioning hole. (See [link to previous section]). Figure 3 Specifically, it includes: S21, The raw material board is cut into the first outer layer board by a board splitting equipment; S22, the first outer layer board undergoes buried drilling, and the first multilayer board is cleaned through high-pressure water washing and plasma desmearing. Buried drilling involves creating blind or buried vias on the first outer layer board that do not penetrate all layers. These vias are typically used to achieve electrical connections between internal layers, saving board space and increasing wiring density. After drilling, high-pressure water washing and plasma desmearing are required to ensure the cleanliness of the hole walls and the reliability of subsequent copper plating. High-pressure water washing uses high-pressure water to flush the inside of the holes and the board surface, effectively removing copper shavings, dust, and debris generated during drilling. Plasma desmearing uses plasma to bombard the hole walls, removing resin residue (i.e., "drill sludge") generated during drilling, exposing the glass fiber bundles and copper foil edges on the hole walls, forming a rough microstructure, thereby enhancing the adhesion between the subsequent copper plating layer and the hole walls. Although described here as "cleaning the first multilayer board," this cleaning operation is performed on the "first outer layer board" that has just undergone drilling to ensure that its hole walls and surface meet the requirements for copper plating.

[0039] S23, pulse flash plating is performed on the first multilayer board to thicken the copper plating layer. After dry film plating of the second communication hole, pattern electroplating is performed to further thicken the copper plating layer of the first multilayer board, removing excess dry film. Pulse flash plating is then performed on the first outer layer board. This is an electroplating technique that periodically changes the direction and magnitude of the current, uniformly depositing a thin and dense copper layer on the hole wall of the second communication hole as a basis for subsequent pattern electroplating and initially thickening the copper plating layer. Subsequently, a photosensitive dry film is applied to the surface of the first outer layer board using a dry film plating process, and the second communication hole is exposed and developed to expose the inner wall of the hole and the area where the circuitry needs to be formed. Pattern electroplating is then performed, depositing a thicker copper layer on the exposed inner wall of the second communication hole and the circuitry area, achieving a second thickening of the copper plating layer to ensure sufficient conductivity and mechanical strength for the second communication hole. Finally, excess dry film is removed, revealing the complete copper circuitry and copper-plated holes. In this process, although it is described here as “pulse flash plating on the first multilayer board” and “a second thickening of the copper plating layer on the first multilayer board”, these operations are performed on the “first outer layer board” being processed, with the aim of optimizing the conductivity of its second communication hole.

[0040] S24, A fourth drilling process is performed on the first outer layer board to create second positioning holes, which match the first positioning holes. These positioning holes are key features used to accurately align the first outer layer board with other layers during subsequent lamination. To ensure the accuracy of the stack-up, the design and fabrication of the second positioning holes must be highly compatible with the previously fabricated first positioning holes (located on the first multilayer board) in position, size, and shape. This compatibility is typically achieved by using high-precision CNC drilling equipment and programming the drilling according to unified CAD design data, thereby ensuring precise alignment of each layer during lamination, avoiding interlayer misalignment, and ensuring the electrical connection reliability of the final PCB board.

[0041] Through the above technical solution, the raw material board is precisely cut, ensuring the dimensional accuracy and substrate integrity of the first outer layer board. After the embedded drilling process, high-pressure water washing and plasma desmearing effectively remove residual adhesive and drilling debris from the hole walls, providing a clean surface for subsequent copper plating and ensuring the conductivity reliability of the second communication hole. Furthermore, the copper plating layer is thickened twice through pulse flash plating and patterned electroplating, significantly improving the conductivity and mechanical strength of the second communication hole. In addition, a fourth drilling process is specially performed to create a second positioning hole that matches the first positioning hole, greatly improving the alignment accuracy of the first outer layer board with other layers, effectively avoiding interlayer misalignment, and thus ensuring the overall quality and electrical performance stability of the communication circuit board stack.

[0042] In some embodiments, after the fifth drilling process is performed on the second outer layer to create the third positioning hole, the method further includes: The second outer layer is grooved for the first time using a roughing method, and then the second multilayer board is grooved for the second time using a fineing method, so as to form grooves in the second outer layer for pressing PP film.

[0043] Specifically, the first milling of the second outer layer plate using rough milling refers to the rapid cutting of a preliminary, relatively large groove shape in a designated area of ​​the second outer layer plate using a rough milling process. The main purpose of this step is to efficiently remove most of the material, laying the foundation for subsequent fine processing and initially forming a space to guide the flow of the PP film. Rough milling typically uses a larger diameter tool and a faster feed rate to improve processing efficiency.

[0044] Subsequently, a second rounding process is performed on the second multilayer board using a precision milling method. This refers to a precise machining process performed on the second multilayer board after its formation. This step aims to refine the grooves previously formed on the second outer layer board using a rough milling method, or to form new, precisely sized grooves in specific areas of the second multilayer board. This ensures that the final grooves formed on the second outer layer board for laminating the PP film have the required geometry, depth, and surface quality. This precision milling process typically employs a high-precision CNC milling machine, coupled with small-diameter cutting tools and fine machining parameters, to achieve high-precision grooving.

[0045] Finally, grooves for laminating the PP film are formed on the second outer layer. This refers to the process of creating grooves with specific dimensions, shapes, and positions on the surface of the second outer layer through a combination of rough and fine milling. These grooves serve as storage and flow channels for the PP film (prepreg) resin during the subsequent lamination process. When heat and pressure are applied, the resin in the PP film can flow sufficiently into these pre-designed grooves, thereby ensuring the uniformity and integrity of the interlayer filling.

[0046] Following the fifth drilling process on the second outer layer to create the third positioning hole, a phased grooving process was introduced using the aforementioned technical solution. First, a rough grooving method quickly forms preliminary grooves on the second outer layer, improving material removal efficiency. Subsequently, after the second multilayer board is formed, a fine grooving method precisely refines the existing grooves or creates new grooves, ensuring dimensional accuracy and surface quality, allowing for precise containment and guidance of the PP film resin flow. This refined grooving process effectively solves the problems of uneven PP film filling, void formation, or insufficient bonding strength during traditional lamination processes. The grooving provides ample flow space and anchoring points for the PP film resin, enabling uniform filling during lamination, reducing air bubbles and voids, and significantly enhancing the bonding strength and reliability between the second outer layer and adjacent layers. This is of great significance for improving the overall structural stability and electrical performance of communication circuit boards, especially signal integrity in high-frequency signal transmission.

[0047] In some embodiments, non-grooved areas are provided in the second and third outer layers, and PTH holes are provided in the non-grooved areas to improve the bonding force; NPTH holes are provided in the enlarged area of ​​the second outer layer, and a groove is provided on the side of the second outer layer adjacent to the first outer layer, and the groove communicates with the NPTH holes for heat dissipation.

[0048] Specifically, the non-riveted areas refer to specific areas reserved on the second and third outer layers that are not milled or slotted. These areas are planned during the circuit board design phase to maintain material integrity, aiming to provide a solid foundation for subsequent PTH holes, thereby ensuring structural strength and the reliability of electrical connections.

[0049] Plating PTH vias in the non-routed areas refers to creating plated through-holes in these areas where no routing has been performed. The fabrication of PTH vias typically involves drilling followed by chemical and electroless copper plating processes to form a continuous conductive copper layer on the hole walls. These plated through-holes not only enable electrical interconnection between different layers, but more importantly, the mechanical bonding between the internal copper layer and the hole walls, as well as the anchoring effect with the interlayer dielectric, significantly enhances the bonding strength between the second and third outer layers during lamination, effectively preventing interlayer delamination and improving the overall structural stability of the communication circuit board.

[0050] The enlarged hole area of ​​the second outer layer refers to a region on the second outer layer where holes larger than the conventional hole diameter are formed at specific locations through a drilling process. These enlarged hole areas are designed to provide sufficient space for subsequent NPTH holes and to offer flexibility in the design of the heat dissipation structure.

[0051] Setting NPTH holes in the enlarged hole area refers to creating unplated through holes within the enlarged hole area of ​​the second outer layer board. Unlike PTH holes, the walls of NPTH holes are not coated with conductive plating; their main function is to provide mechanical support, positioning, or as a heat conduction channel. In this design, NPTH holes are designed as vertical paths for heat conduction from the inside of the circuit board to the outside.

[0052] The grooves are provided on the side of the second outer layer plate adjacent to the first outer layer plate. This means that a groove structure with a certain depth and width is formed on the surface of the second outer layer plate facing the first outer layer plate by milling, etching, or other mechanical processing methods. These grooves serve as horizontal heat diffusion channels, capable of collecting and guiding heat conducted from the NPTH holes.

[0053] The groove communicating with the NPTH hole for heat dissipation refers to ensuring, through precise design and manufacturing, that the groove on the second outer layer board and the NPTH hole in the enlarged hole area are spatially connected. This interconnected structure forms an efficient heat dissipation path: heat generated inside the circuit board is first vertically conducted to the surface of the second outer layer board through the NPTH hole, then enters the groove communicating with it, and is horizontally diffused within the groove or further dissipated to the adjacent first outer layer board or the external environment through convection or conduction.

[0054] By employing the aforementioned technical solution, PTH vias are placed in the non-grooved areas of the second and third outer layers, significantly improving the bonding strength between the layers and enhancing the overall structural strength and reliability of the communication circuit board. This effectively avoids interlayer delamination issues that may occur under complex stacking structures and high-density interconnections. Simultaneously, NPTH vias are placed in the enlarged via area of ​​the second outer layer and connected to a recess on the adjacent side, constructing an integrated thermal management system. This system effectively guides heat generated inside the circuit board to the recess through the NPTH vias, where it is diffused and dissipated, thus preventing localized hotspot accumulation, reducing the operating temperature of the circuit board, and ensuring the stability and performance of the communication circuit board during long-term operation. This system is particularly suitable for high-power, highly integrated communication equipment.

[0055] In some embodiments of step S5, the second multilayer board undergoes post-processing to fabricate the target PCB board, see [link to relevant documentation]. Figure 4 Specifically, it includes: S51, perform board electrical processing, third outer layer circuit processing and AOI inspection on the second multilayer board in order to fabricate the outer layer circuit on the second multilayer board; S52 sequentially performs solder mask treatment, text processing, electroless gold treatment, forming treatment, pressure baking inspection hole treatment, and step hole drilling treatment on the second multilayer board to obtain the target PCB board.

[0056] Through the aforementioned technical solutions, after the formation of the second multilayer board, comprehensive post-processing can be performed, transforming it from a semi-finished product into a fully functional and reliable target PCB board. Specifically, the combination of board electrical treatment, third outer layer circuit processing, and AOI inspection ensures the precise formation and quality control of the outer layer circuitry, guaranteeing effective signal transmission. Subsequently, solder mask treatment effectively protects the circuitry, preventing environmental corrosion and soldering short circuits; text processing provides necessary labeling information for subsequent operations; and electroless gold treatment significantly improves the solderability and reliability of the pads, ensuring a stable connection of components. Finally, molding processing gives the PCB board precise physical dimensions and shape, while pressure testing and stepped hole drilling further verify and improve the hole structure on the board, ensuring the reliability of interlayer connections and the installation requirements of special components. Overall, this series of meticulous post-processing steps not only guarantees the electrical performance and mechanical strength of the target PCB board but also greatly improves its long-term stability and reliability in complex communication circuits, enabling it to meet high-standard application requirements.

[0057] In some embodiments, the first positioning hole, the second positioning hole, the third positioning hole, and the fourth positioning hole all include round holes and square slot holes. The round holes are located at the four corners of the first multilayer plate, the first outer layer plate, the second outer layer plate, the third outer layer plate, or the fourth outer layer plate, and the square slot holes are located between adjacent round holes to improve the pressing and positioning accuracy.

[0058] See Figure 6 By employing the aforementioned technical solution, a positioning structure combining round holes and square slots is used in the positioning and pressing stage of communication circuit board stacking. This effectively solves the problem of insufficient positioning accuracy that may occur with single-shaped positioning holes in multilayer board stacking. Specifically, the round holes first provide rapid and coarse alignment, allowing each layer of board material to quickly reach a roughly aligned state. Based on this, the square slots, through their non-circular geometric features, closely cooperate with positioning pins or positioning posts, effectively limiting the rotation and minute translation of the board material in the plane, thereby eliminating or significantly reducing the cumulative error of interlayer alignment. Placing the round holes at the four corners of the board material provides a stable reference for overall positioning; while the square slots, placed between adjacent round holes, provide additional fine positioning constraints in critical areas. This composite positioning structure ensures high-precision alignment of each layer of board material during the positioning and pressing of the first multilayer board, the first outer layer board, the second outer layer board, and the third outer layer board, thereby significantly improving the interlayer alignment accuracy and product quality of the final second multilayer board and reducing the scrap rate caused by misalignment.

[0059] Example 3: Based on Embodiment 1 or Embodiment 2, the present invention provides an embodiment of a communication circuit board stacking device, which is used to execute the communication circuit board stacking method of Embodiment 1 or Embodiment 2.

[0060] Specifically, see Figure 5 L1-L10 are the first multilayer boards, L11-L12 are the first outer layer boards, L13-L14 are the second outer layer boards, L15-L16 are the third outer layer boards, 11 is the first communication hole; 12 is the back drill hole; 13 is the third communication hole; 14 is the router hole; 15 is the stepped hole; 16 is the round hole; 17 is the square slot hole.

[0061] The manufacturing process of the target PCB board is as follows: L1L10: L2L3 / L4L5 / L6L7 / L8L9 core board cutting → inner layer → internal inspection → lamination → grinding → browning (before laser drilling) → laser drilling → embedded drilling → mechanical drilling → high-pressure water washing → plasma desmearing → second outer layer AOI2 → hole filling → hole plating dry film → patterned hole plating → film removal → high-pressure water washing → back drilling → high-pressure water washing II → back drilling AOI → resin hole plugging I → resin hole plugging II → resin hole plugging III → resin III hole plugging IV → board electrode → second outer layer 2 → second outer layer AOI2 (II) → grinding II → mechanical drilling II (drilling the positioning holes required for Pin-lam) → waiting to be pressed; L111L12: Material cutting → Embedded drilling → High-pressure water washing → Plasma desmearing → Board electrode → Resin hole plugging → Second outer layer 2 → Grinding → Mechanical drilling of hole 2 (drilling positioning holes required for Pin-lam) → Waiting for pressing; L13L14: Material preparation → Inner layer → Inner layer AOI → Grinding → Embedded drilling (drilling positioning holes required for Pin-lam) → Grooving (spinning core board and PP sheet) → Ready for pressing; L15L16: Material preparation → Inner layer → Inner layer AOI → Grinding → Embedded drilling (drilling the positioning holes required for Pin-lam) → Ready for pressing; L1L16: L1L10 / L11L12 / L13L14 / L15L16 lamination - PINLAM → cutting and grinding → resin grinding → mechanical drilling → high-pressure water washing → plasma desmearing → board electrode → outer layer → outer layer AOI → solder mask → text → chemical gold → molding → press baking inspection hole → drilling step hole → testing → FQC → packaging.

[0062] Specifically, see Figure 5 The overall thickness of the laminated plate is 4.54±0.25mm, and the special design features include: The core board thickness of L13 and L14 is 1.524mm (excluding copper). Its main function is to improve the warping of asymmetrical structure boards (the copper thickness of L4, L5, L6, L7, L8, and L9 is 2OZ, and that of L10, L11, and L12 is 0.5OZ). The materials selected are: core board S1190GB + synamic6 (to ensure low loss during signal transmission, meeting ≤1.3db / 50GHz) \PP synamic6B + S1190GB + SP168GN (low flow rate, ensuring that PP will not seep into the voids after high temperature during lamination, ensuring uniformity of dielectric thickness and board thickness).

[0063] After the L1L10 layers are filled, the via thickness is only about 0.6mil, which cannot meet the average requirement of 1mil. The surface copper is controlled at 1-1.4mil. In order to ensure that the surface copper thickness exceeds the standard, which is not conducive to the fabrication of outer layer circuits, it is necessary to make a dry film data for plating (develop the 15mil diameter blind vias of L1L3 and the window opening of the vias, and cover all other positions, including the 5mil filling of the blind vias of L1L2 to meet the copper thickness and recess requirements). The copper thickness of the blind vias and vias of L1L3 is increased by electroplating according to the required thickness.

[0064] After the patterned holes are plated, back drilling is performed on the through holes, starting from L10 and drilling through the L9 layer, but not reaching the L8 layer. The depth is controlled at 0.65±0.05mm.

[0065] Its main function is to drill through layers that are not necessary to connect, ensuring that signal transmission is free from interference.

[0066] L1L10 Resin Pluging Hole 1 (back-drilling + through-hole plugging simultaneously, plugging from L10 side), Resin Pluging Hole 2 (blind hole + through-hole plugging simultaneously, plugging from L1 side). After Resin Pluging Hole 2 is completed, baking and resin polishing are performed. Resin Pluging Holes 3 and 4 repeat the steps of Resin Pluging Holes 1 and 2. After polishing, the copper surface thickness is controlled at 0.8-1.2mil. After resin plugging is completed, copper plating and capping are performed, with a cap thickness of 0.4mil and a surface copper surface thickness controlled at 1.3-1.7mil.

[0067] When fabricating the outer layer circuitry of L1L10, only L10 is fabricated. The L1 layer needs to be protected to facilitate the fabrication of the outer layer of L1L12.

[0068] For L1L10 plates with a thickness exceeding 1mm, target holes need to be drilled using a CCD drill in the second stage of cutting and grinding. Then, in the third stage of mechanical drilling, a CCD machine is used to drill the required positioning holes (round holes and square slot holes, as shown below) for the Pin-lam. Figure 4 This design combines circular holes with square slots for positioning, which improves positioning accuracy and reduces layer misalignment.

[0069] The L11L12 board uses pulse flash plating to thicken the copper to 0.5-0.8mil, followed by dry film plating of the holes and patterned hole plating, mainly to thicken the copper of the through holes to 1mil.

[0070] L11L12 mechanical drilling is a back-drilling process for through holes, drilling from layer L12 without drilling to layer L11, with a depth control of 0.14±0.05mm. Its main function is to drill through layers that are not necessary to connect, ensuring that signal transmission is not interfered with.

[0071] L11L12 resin plugging / two is mainly for plugging through holes and back drilled holes.

[0072] When fabricating the outer layers L11 and L12, only L12 needs to be fabricated. The L1 layer needs to be protected to facilitate the fabrication of the outer layers L1 and L16.

[0073] Slotted core boards and P-sheets (L13 and L14) are produced using mass production milling machines, employing a rough milling followed by a fine finishing process. The rough milling cutter has a 5-minute lifespan, while the fine finishing cutter has a 2-minute lifespan. The slotting clearance size is controlled to 10mm x 10mm. The PP slotting between L12-13 and L14-15 is done using a Han's UV laser cutting machine. The PP slotting area is extended outwards by 0.1mm on each side, resulting in a 9.9mm x 9.9mm slot size, to reduce PP resin flow exceeding the 10mm x 10mm area during lamination. Note: Each PP sheet should be placed on a sheet of white paper of the same size during processing to prevent resin flow at the PP slot edges due to the high temperature of the laser when multiple sheets are stacked together.

[0074] When fabricating the inner layer circuitry of L15 and L16, only L16 needs to be fabricated. The L15 layer needs to be protected to facilitate the fabrication of the outer layer of L1 and L16.

[0075] The L1L16 lamination process employs a Pin-lam positioning method to ensure that the layer misalignment after lamination is controlled within ±0.075mm, preventing short circuits caused by layer misalignment.

[0076] In the L1L16 stack, layers L13, L14, and L15 are etched as a smooth copper board. Within the PCS, there are nine non-routed open areas with dimensions of 13mm*13mm and four non-routed open areas with dimensions of 13mm*18mm (including PP for layers L12, L13, L14, and L15). 5mm diameter PTH holes are designed in the non-routed open areas (which can connect all layers from L2 to L12) to improve the bonding strength and prevent delamination and board breakage issues from layers L12 to L16.

[0077] When fabricating the L16 layer circuitry, a copper pad of the same size was designed in the L13 and L14 router empty areas. After testing, a 0.6mm NPTH hole was drilled in the center of the copper pad (as shown below). Figure 5 , 6In the L13-L14 core board, a groove 3mm wide and 0.5mm deep is spun out on the surface of the L13 layer at the connection position of the non-spun area. Through the connection between the 0.6mm hole in the center of the L16 layer copper PAD and the groove in the L13 layer, an air tube is inserted into the two holes between them. By using an inlet and outlet method, the heat generated by the circuit board when it is used on the aircraft can be effectively circulated out through the punched area to achieve the function of heat dissipation and cooling.

[0078] The hot pressing cooling period for L1L12 and L1L16 was extended by 30 minutes, and the cold pressing period was extended by 90 minutes to ensure the bonding strength of the overall stack after pressing. After 6 tests of thermal stress at 288℃*10S, the L1L12 layer did not delaminate or burst, meeting the requirements for high reliability.

[0079] For the special stacked structure design and manufacturing process of low-orbit communication satellite circuit boards, by using low-loss, high-speed, high-TG special materials, extending hot-pressing and cold-pressing time, blind via design, resin plugging of buried vias and large blind vias, adjusting the thickness of L13 and L14 core boards, back-drilling design, router gap design, and L16 stepped via design, it can meet high-performance requirements such as multi-level circuit interconnection, high bonding strength, high-speed signal transmission, asymmetric structure without board warping, and special heat dissipation requirements.

[0080] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several systems, several of these systems may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be construed as limiting the order of execution.

Claims

1. A method for stacking communication circuit boards, characterized in that, The method includes: A first multilayer board is obtained, and a first drilling process is performed on the first multilayer board to create a first communication hole. The first communication hole is then copper plated, plugged, and subjected to a first outer layer circuit process. A second drilling process is performed on the first multilayer board to create a first positioning hole. Obtain the first outer layer board, and perform a third drilling process on the first outer layer board to create the second communication hole. Then, perform copper plating, hole plugging, and a second outer layer circuit on the second communication hole. Perform a fourth drilling process on the first outer layer board to create the second positioning hole. Obtain the second outer layer board, perform the first inner layer circuit processing on the second outer layer board, and perform the fifth drilling process on the second outer layer board to create the third positioning hole; Obtain the third outer layer board, perform a second inner layer circuit processing on the third outer layer board, and perform a sixth drilling process on the third outer layer board to create the fourth positioning hole; Based on the first positioning hole, the second positioning hole, the third positioning hole, and the fourth positioning hole, the first multilayer board, the first outer layer board, the second outer layer board, and the third outer layer board are positioned and pressed together to form the second multilayer board. The second multilayer board is then subjected to a seventh drilling process to create the third communication hole. Finally, the second multilayer board is post-processed to create the target PCB board.

2. The communication circuit board stacking method according to claim 1, characterized in that, Obtaining the first multilayer board specifically includes: The raw material board is cut into core boards using a slitting device; The core board is subjected to inner layer circuit processing and inner layer AOI processing to fabricate inner layer circuits on the core board. Multiple core boards are pressed together to form a first multilayer board, and after the first multilayer board is cut and browned, it proceeds to the next process.

3. The communication circuit board stacking method according to claim 1, characterized in that, The first multilayer board is drilled to create the first communication hole, specifically including: A first communication hole is made in the first multilayer board by laser drilling, embedded drilling and mechanical drilling, wherein the first communication hole is a blind hole or a through hole. The first multilayer board is cleaned by high-pressure water washing and plasma desmearing, and then proceeds to the next process after AOI inspection of the first communication hole.

4. The communication circuit board stacking method according to claim 1, characterized in that, The first communication hole undergoes copper plating, via plugging, and the first outer layer circuit processing, specifically including: The first communication hole is subjected to a hole-filling electroplating process to create a first copper plating layer in the first communication hole; After applying a dry film to the first communication hole, pattern electroplating is performed to create a second copper plating layer on the first copper plating layer, and excess dry film is removed. Back-drill the first communication hole of the first multilayer board to make the target layers of the first multilayer board connected, and perform AOI inspection after high-pressure water washing of the first multilayer board. The first multilayer board is subjected to a first resin plugging process from its first surface, a second resin plugging process from its second surface, and a baking process and a resin grinding process. The first multilayer board is subjected to a third resin plugging process from its first surface, a fourth resin plugging process from its second surface, and a baking process and a resin grinding process. After the first multilayer board is subjected to board electrical processing, the outer layer circuitry and outer layer AOI inspection are performed on the first multilayer board. After completion, the next process begins.

5. The communication circuit board stacking method according to claim 1, characterized in that, Obtain the first outer layer board, and perform a third drilling process on the first outer layer board to create the second communication hole. Then, perform copper plating, hole plugging, and a second outer layer circuit on the second communication hole. Finally, perform a fourth drilling process on the first outer layer board to create the second positioning hole. Specifically, this includes: The raw material board is cut into the first outer layer board using a slitting device; The first outer layer board is drilled and then cleaned by high-pressure water washing and plasma descaling. The first multilayer board is subjected to pulse flash plating to thicken the copper plating layer of the first multilayer board. After the second communication hole is plated with a hole dry film, pattern electroplating is performed to thicken the copper plating layer of the first multilayer board a second time, and excess dry film is removed. The first outer layer plate is drilled a fourth time to create a second positioning hole, and the second positioning hole matches the first positioning hole.

6. The communication circuit board stacking method according to claim 1, characterized in that, After drilling the second outer layer plate for the fifth time to create the third positioning hole, the process also includes: The second outer layer is first grooved using a roughing method, and then the second multilayer board is second grooved using a fine grinding method to form grooves in the second outer layer for pressing PP film.

7. The communication circuit board stacking method according to claim 1, characterized in that, Non-grooved areas are provided in the second and third outer layers, and PTH holes are provided in the non-grooved areas to improve the bonding force. NPTH holes are provided in the enlarged hole area of ​​the second outer layer, and a groove is provided on the side of the second outer layer adjacent to the first outer layer. The groove communicates with the NPTH holes for heat dissipation.

8. The communication circuit board stacking method according to claim 1, characterized in that, Post-processing of the second multilayer board to fabricate the target PCB board specifically includes: The second multilayer board undergoes board electrical processing, a third outer layer circuit processing, and AOI inspection to fabricate the outer layer circuitry on the second multilayer board. The second multilayer board is sequentially subjected to solder resist treatment, text processing, electroless gold treatment, forming treatment, pressure baking inspection hole treatment, and step hole drilling treatment to obtain the target PCB board.

9. The communication circuit board stacking method according to claim 1, characterized in that, The first positioning hole, the second positioning hole, the third positioning hole, and the fourth positioning hole all include round holes and square slot holes. The round holes are located at the four corners of the first multilayer plate, the first outer layer plate, the second outer layer plate, the third outer layer plate, or the fourth outer layer plate, and the square slot holes are located between adjacent round holes to improve the pressing and positioning accuracy.

10. A communication circuit board stacking device, characterized in that, The apparatus is used to perform the communication circuit board stacking method according to any one of claims 1-9.

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