High multilayer mixed pressure back drilling system HDI board for high speed switch and manufacturing method thereof

Abstract

This invention discloses a high-multilayer hybrid back-drilling HDI board for high-speed switches and its manufacturing method, including: preliminary preparation and data processing; inner layer fabrication and browning; lamination and expansion / contraction management, using X-ray measurement of layer offset data, grouping according to predetermined expansion / contraction differences and performing dynamic expansion / contraction compensation; mechanical drilling and back-drilling, using a CCD full-thickness measurement device to perform C-side through-hole drilling and S-side back-drilling respectively, the through-hole drilling adopts a depth-expanding drilling method combining short and long drills, and the drilling depth is dynamically calculated based on the actual measured board thickness during back-drilling; laser blind vias and electroplating, setting corresponding laser drilling parameters for blind vias of different depths; POFV and polishing, using differentiated polishing parameters for the BGA area and the large copper surface; outer layer patterning and quality inspection; molding, testing, and shipping. The method of this invention can control the interlayer alignment accuracy within ±1 mil, significantly improving the signal integrity and manufacturing yield of the high-multilayer hybrid back-drilling HDI board. This invention also provides a high-multilayer hybrid back-drilling HDI board for high-speed switches manufactured by the above method.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board (PCB) manufacturing technology, specifically to a high-multilayer hybrid back-drilling system HDI board for high-speed switches and its manufacturing method. Background Technology

[0002] With the rapid development of 5G communication, cloud computing, and big data technologies, the data throughput of core switches has evolved to the terabits per second (Tbps) level. To support such ultra-high bandwidth requirements, the core interconnect backplane inside the switch must simultaneously possess comprehensive performance characteristics such as ultra-high multilayer (e.g., 22-30 layers), high-density interconnect (HDI), extremely low signal loss, and high reliability. To meet these requirements, PCB design typically employs the following integrated technical solutions to achieve the manufacturing of such high-end backplanes:

[0003] 1. Hybrid Pressing Structure Design. To balance signal transmission performance and manufacturing costs, existing technologies employ a hybrid pressing structure. Specifically, in the same backplane, different signal layers use different types of prepreg (PP) and core board materials for mixing and laminating. For example, high-frequency materials with low dielectric loss (Df≤0.005) (such as the EM-891EMC series) are used for high-frequency signal layers, while ordinary FR-4 materials (such as the EM-827EMC series) are used for non-critical power / ground layers. The hybrid pressing structure design typically allocates materials based on signal integrity (SI) simulation results, forming an alternating stack of "high-frequency material layers + ordinary material layers".

[0004] 2. System HDI Arbitrary Layer Interconnection and High Aspect Ratio Extreme Drilling. To achieve high-density wiring, existing technologies employ arbitrary layer HDI designs, which involve creating cross-layer blind vias (such as L1-L2, L1-L3, and L26-L25 in a 26-layer hybrid HDI board) through multiple lamination and laser drilling. Typically, for backplanes with more than 26 layers, the board thickness (e.g., 3.958mm ± 6% after lamination) and the minimum mechanical drill diameter (e.g., 0.175mm) create an extremely high aspect ratio (approximately 22.6:1). Existing technologies achieve the metallization of such ultra-high aspect ratio holes by employing TAC-coated superhard drill bits, segmented pecking drilling, and horizontal pulse electroplating processes.

[0005] 3. Back-drilling process eliminates the stub effect. To reduce the reflection and attenuation of high-speed signals by via stubs, existing technologies perform back-drilling on all signal vias. Back-drilling technology uses a controlled-depth drilling method, employing a two-stage drilling approach to remove unused copper layers from the vias. This eliminates the parasitic capacitance effect caused by the via stub, ensuring that the impedance at the via in the channel link is consistent with the trace, reducing signal reflection, and thus improving signal quality.

[0006] 4. POFV process and surface flatness control. To meet the high-density mounting requirements of BGA (Ball Grid Array) packaging, existing technology performs resin-filled vias (POFV) on all through-holes, blind vias, and back-drilled vias, and then uses abrasive belt grinding to reduce the copper thickness of the board surface to the target value to ensure the flatness of the BGA area.

[0007] 5. Strict layer misalignment control. Multilayer mixing, multiple pressing, and expansion and contraction effects can easily cause the inner and outer layer patterns to shift, compromising signal integrity. Therefore, the requirements for interlayer alignment are extremely high (e.g., ≤6mil alignment Coupon design).

[0008] Therefore, existing technologies have effectively integrated processes such as mixed-material bonding, arbitrary-layer HDI blind vias, back-drilling, ultra-high aspect ratio mechanical vias, and POFV polishing, attempting to manufacture system-level HDI backplanes that meet the requirements of high-speed switches through an integrated process. However, when these processes are highly integrated onto the same product, existing processes reveal the following systemic defects, leading to low product yield and difficulty in guaranteeing signal integrity:

[0009] (1) Interlayer alignment failure and signal quality risk. In the prior art, the product needs to undergo more than two laminations, more than three drillings (including laser blind holes, through holes, and back drilling), and multiple electroplating and grinding processes. During the multiple laminations, drilling and electroplating processes, the uneven release of stress in the board leads to inconsistent expansion and contraction coefficients, which eventually causes the layer misalignment to exceed the standard, causing the blind holes and the target pads to be misaligned and open circuit, or causing damage to the signal layer during back drilling, which seriously affects the signal integrity.

[0010] (2) High aspect ratio blind vias have poor copper reliability. For structures with a board thickness of more than 3.5 mm, blind vias that are required to span multiple layers (such as L1-L3) and have extremely small diameters (<0.2 mm), conventional laser drilling and horizontal copper plating processes cannot guarantee the uniformity and integrity of the copper thickness on the via wall. This can easily lead to fatal defects such as no copper on the via wall or cracks, causing the product to fail under high temperature and humidity or high current (HCT test).

[0011] (3) Insufficient precision in back-drilling depth control. Back-drilling depth control is the core difficulty of the back-drilling process. Drilling too shallow will leave residual stubs, while drilling too deep will sever the connection of the target layer. Existing technologies usually set the back-drilling depth by subtracting a fixed back-drilling allowance from a fixed theoretical plate thickness. When the actual plate thickness fluctuates due to expansion and contraction of the mixed-pressure plate (e.g., ±6% tolerance), back-drilling at a fixed depth will result in two outcomes: drilling too deep will damage the target signal layer, while drilling too shallow will result in an excessively long residual stub, leading to excessive signal insertion loss. In addition, the existing process does not distinguish between "requires back-drilling" and "does not require back-drilling" for through holes of the same diameter, and uses the same drill strip for processing. This increases the number of back-drilling cuts, affecting efficiency, and makes it impossible to independently optimize the stub length.

[0012] (4) Conflict between process compatibility and signal insertion loss control. The existing process lacks global optimization for signal insertion loss control when handling processes such as back drilling, resin-filled via (POFV, Plating Over Filled Via), and outer layer patterning. For example, inappropriate browning, rework, or polishing can lead to uneven dielectric layer thickness or excessive copper foil surface roughness, thereby increasing high-frequency signal transmission loss (insertion loss) and failing to meet the stringent requirements of SI Coupon (signal integrity test strip).

[0013] (5) Local flatness loss after POFV polishing. In the POFV process, the existing technology uses the same polishing parameters for large copper surfaces (Cu≥70%) and BGA dense via areas. However, due to the huge difference in copper area and resin filling amount between the two types of areas, BGA vias often show depressions or protrusions after polishing, exceeding the surface mount tolerance window of high-end chips, causing short circuits or poor soldering.

[0014] Therefore, the purpose of this invention is to provide a manufacturing process for a high-multilayer hybrid back-drilling system HDI board for high-speed switches to solve the above-mentioned technical problems. Summary of the Invention

[0015] The purpose of this invention is to provide a manufacturing method for a high-multilayer hybrid back-drilling system HDI board for high-speed switches, which can solve the problems of alignment, signal integrity and reliability caused by multiple complex processes such as hybrid voltage, ultra-high multilayer, high aspect ratio micro blind via, back drilling, and strict layer offset during integration.

[0016] The technical solution of this invention is:

[0017] A method for manufacturing a high-multilayer hybrid back-drilling system HDI board for high-speed switches includes the following steps:

[0018] Step S1, Preliminary preparation and data processing: Generate data including independent drill lines and optical plotting based on the client's design;

[0019] Step S2, Inner Layer Fabrication and Browning: Complete the inner layer circuitry and AOI inspection, and perform low-roughness browning;

[0020] Step S3, lamination and expansion / contraction management: The Pin-Lam system is used for stacking and fusion; after lamination, the first piece is taken to confirm the board thickness, dielectric layer thickness and missing adhesive. The layer deviation data is measured using an X-RAY drilling machine. Based on the measurement results, the panels are stacked according to the predetermined expansion / contraction difference. An X-RAY drilling machine is used to generate independent drilling programs for different batches to perform dynamic expansion / contraction compensation, and the compensation data is synchronized to the outer layer LDI exposure and back drilling process.

[0021] Step S4, Mechanical drilling and back drilling: Through hole drilling uses a TAC coated drill bit to deepen the small diameter through hole by combining short and long drills. CCD full board thickness measurement equipment is used to drill through holes on the C-side and back drill on the S-side. During back drilling, the drilling depth is dynamically calculated based on the actual measured board thickness to control the drilling depth.

[0022] Step S5, Laser Blind Hole and Electroplating: Blind holes are drilled using laser drilling technology, and corresponding laser drilling parameters are set according to the thickness of the dielectric layer spanned by the blind hole; after drilling, low-temperature baking and dehumidification, slag removal and copper plating, and pulse electroplating are performed in sequence; wherein, the laser drilling parameters include laser energy, pulse width and number of pulses;

[0023] Step S6, POFV and Grinding: Resin plugs are applied to all through holes, blind holes and back drill holes, and coarse and fine grinding is performed using a multi-axis grinding line. Different grinding parameters are used for the BGA area and the large copper surface to make the copper thickness of the BGA area different from that of the large copper surface, and then POFV electroplating is performed.

[0024] Step S7, Outer layer pattern and quality inspection: Perform copper reduction, LDI exposure, etching and AOI, create solder mask and text, and check for pores in the predetermined area during the solder mask and circuit fabrication stage.

[0025] Step S8: Molding, Testing and Shipping.

[0026] Furthermore, in step S1, the independent drill strip data includes S-face through holes, C-face through holes, S-face back drill holes, C-face back drill holes, and drilling data of enlarged drills with different hole diameters.

[0027] Further, in step S3, the predetermined expansion / contraction difference is ±1mil, and the dynamic expansion / contraction compensation includes stacking the panels according to the expansion / contraction difference of ±1mil, and using the Pluritec X-RAY drilling machine to generate independent drilling programs for different batches to automatically compensate for the stretching or shrinkage ratio.

[0028] Furthermore, in step S4, the diameter range of the small-diameter through hole is 0.175mm to 0.225mm; during back drilling, the drilling depth is dynamically calculated based on the actual plate thickness. After the first piece is debugged, three additional holes are measured for each tool to confirm the Stub length, and the T-segment is adjusted according to the results.

[0029] Furthermore, in step S5, after drilling, the material is baked at a low temperature to remove moisture. The baking temperature is 125°C and the baking time is 2 hours.

[0030] Further, in step S6, the grinding target is to grind the copper thickness to 35.0±5um, the hole thickness to 25.0±4um, the depression to be less than 7.62um, and the protrusion to be less than 7.62um.

[0031] POFV electroplating employs selective electroplating. After electroplating, the target copper size for the BGA area is 57±5um, and for the large copper area it is 67±5um.

[0032] Furthermore, rework is prohibited in the browning, pressing, and electroplating processes to control ion contamination levels.

[0033] Furthermore, in step S8, the SI Coupon is transferred synchronously with the product board and undergoes insertion loss testing, HCT testing, four-wire testing, and RVC testing.

[0034] The present invention also provides a high-multilayer hybrid back-drilling system HDI board for high-speed switches, which is manufactured using the above-described manufacturing method.

[0035] Compared with the prior art, the HDI board for high-speed switches and its manufacturing method provided by the present invention have the following advantages:

[0036] I. The high-multilayer hybrid back-drilling HDI board for high-speed switches and its manufacturing method significantly improve interlayer alignment accuracy. Through dynamic expansion and contraction compensation and refined stacking (stacked at ±1mil), this invention reduces the expansion and contraction differences caused by hybrid voltage and ultra-thick boards from the industry average of ±3-4mil to within ±1mil, effectively avoiding blind via misalignment and open circuits, and ensuring the wiring density and reliability of the system HDI board.

[0037] II. The high-multilayer hybrid back-drilling system HDI board and its manufacturing method for high-speed switches of the present invention ensure the electrical connection reliability of blind vias with high aspect ratios. By setting corresponding laser drilling parameters such as laser energy, pulse width, and number of pulses according to the thickness of the dielectric layer spanned by the blind via, the problems of laser drilling energy attenuation and poor hole shape are solved. Combined with copper plating / electroplation parameters, even blind vias with an aspect ratio reaching the industry limit (AR≥2.5) can obtain a uniform, continuous, and standard-compliant (average hole copper >25.4um) hole wall copper layer, ultimately passing the stringent HCT high-current test (resistance change rate ≤5%).

[0038] III. The high-multilayer hybrid back-drilling system HDI board for high-speed switches and its manufacturing method of the present invention reduce signal reflection by precisely controlling the back-drilling quality. The integrated full-test board thickness control deep drilling method ensures stable control of the residual stub length after back-drilling, avoiding damage to the effective signal layer; and by adopting differentiated drilling strategies for holes of the same diameter for different purposes, both electrical performance and production efficiency are taken into account.

[0039] IV. The high-multilayer hybrid back-drilling system HDI board and its manufacturing method for high-speed switches of the present invention ensure low insertion loss characteristics under high-frequency signals. The "no rework" process (browning, lamination, electroplating, etc.) and key control point inspections (hole inspection, SI Coupon on-the-job flow) of the present invention maximize the protection of the low loss characteristics of high-frequency materials. The full-process tracking and control of SI Coupon ensures that the signal integrity of the product is measurable, controllable, and reproducible.

[0040] V. The present invention relates to a high-multilayer hybrid back-drilling system HDI board for high-speed switches and its manufacturing method, which meets the requirements of high-end BGA packaging. The present invention's targeted POFV electroplating and polishing process (differentiated copper targets for the BGA area and the large copper surface, multi-level polishing) achieves a flatness of better than 3mil (76.2um) in the BGA area and precise control of the copper thickness (57±5um in the BGA area), which greatly improves the mounting yield and long-term reliability of advanced chip packages (such as ultra-large 65×65mm BGA). Detailed Implementation

[0041] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, and to make the above-mentioned objectives, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below.

[0042] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein.

[0043] Example 1

[0044] This embodiment uses a 26-layer hybrid HDI board (model number 26H25XXXA0) as an example to illustrate the manufacturing method of the present invention in detail.

[0045] A method for manufacturing a high-multilayer hybrid back-drilling system HDI board for high-speed switches includes the following steps:

[0046] Step S1, Preliminary Preparation and Data Processing:

[0047] Based on the customer's design, the system generates independent drill strips and photoplotting data. The independent drill strip data includes S-face through holes, C-face through holes, S-face back drill holes, C-face back drill holes, and drilling data for enlarged drills of different diameters.

[0048] Define the hybrid lamination structure: L1 / L26 uses 0.5OZ HTE copper foil, and the inner core board and PP material are EM-891EMC and EM-827EMC hybrid lamination, with a total board thickness of 3.958mm ± 6% after lamination.

[0049] Step S2, Inner Layer Fabrication and Browning:

[0050] Complete the inner layer circuitry (including LDI QR code) and AOI inspection. Perform low-roughness browning, and strictly prohibit rework during the browning process, controlling ion contamination (target ≤6.45ug / inch² NaCl).

[0051] Step S3, Compression and Expansion / Contraction Management:

[0052] The Pin-Lam system is used for stacking and fusion, with 4.0mm solid rivets at the four corners. Scrap boards or dummy boards are used to supplement the number of layers. Hot melt parameters: hot melt temperature 220°C, hot melt time 25±5 seconds, cooling time 15 seconds;

[0053] After lamination, the first piece is taken for confirmation of board thickness, dielectric layer thickness, and adhesive shortage. Layer misalignment data is measured using an X-ray drilling machine. Based on the measurement results, the panels (PNL) are stacked according to a ±1 mil expansion / contraction difference. A Pluritec X-ray drilling machine is used to generate independent drilling programs for different batches, automatically compensating for stretching or shrinkage ratios. This data is synchronized to the outer layer LDI exposure and back-drilling processes.

[0054] Step S4, Mechanical drilling and back drilling:

[0055] Perform through-hole drilling (DRL1) using a TAC-coated drill bit. For holes with diameters of 0.175mm, 0.2mm, and 0.225mm, use the "short drill + long drill" method to deepen the hole (drilling one hole twice). Use the S-side drill to drill the edge holes and the test board coupon first. The essential principle and process of the "short drill + long drill" method is: first, use a short-bladed drill bit with good rigidity and less tendency to deviate to accurately "guide the way", and then use a long-bladed drill bit to continue drilling through along the "guide way".

[0056] Step 1: Short drill "pilot hole" (pre-drilling). Its purpose is to create a highly precise pilot hole with a short chip flute and good rigidity, providing a precise path for subsequent long drilling. The drilling depth is typically 10%–30% of the board thickness. Recommended parameters: high speed, low feed rate to ensure accurate positioning. The drill bit has a relatively short overall length and good rigidity.

[0057] Step 2: Long-drill "deepening" (main drilling), its purpose is to use the channel opened by the short drill to finally drill through the hole. To avoid difficulties in chip removal, a "pecking drill" method (multi-step drilling) is often used; Layer ratio: When using multi-step drilling, the feed is usually in the ratio of 1 / d:2 / d:3 / d:4 / d (d is the total hole depth), and the feed amount per step is smaller as the depth increases; Decreasing pecking drill: As the depth increases, the depth of each peck decreases from 3mm → 2mm → 1.5mm → 1mm to improve chip removal; Rotation speed adjustment: When the drilling depth exceeds 5 times the hole diameter, the rotation speed can be reduced by 10% to 15% as needed to prevent overheating.

[0058] For these three extremely small apertures, the specific parameters are set as follows, taking into account the thickness-to-diameter ratio:

[0059] For a hole diameter of 0.175mm: the short drill bit is typically 2.5-3.0mm long, while the long drill bit is responsible for the remaining depth; the short drill bit rotates at 120-150krpm and feeds at 8-12 mm / s.

[0060] Hole diameter 0.200mm: short drill bit length 3.0-3.5mm, long drill bit relay; drill rotation speed 100-130 krpm, feed 10-15mm / s;

[0061] Hole diameter 0.225mm: short drill bit length 3.5-4.0mm, rotation speed 90-120 krpm, feed 12-18 mm / s.

[0062] Do not use abrasive belts when deburring to avoid damage; wash away pressure-sensitive ink.

[0063] C-face and back drilling were performed using a CCD full-thickness measurement device for through-hole drilling on the C-face and back drilling on the S-face. The depth of controlled drilling was dynamically calculated based on the measured board thickness. After the first piece was tested, three additional holes were drilled for each drill bit to confirm the stub length, and the T-screw plan was adjusted according to the results. The back drill bit specifications were 0.45 × 6.5 mm (total length), with an effective cutting length ≥ 4.0 mm.

[0064] Step S5, laser blind hole and electroplating:

[0065] Laser drilling is used to drill blind holes, and the laser drilling parameters, such as laser energy, pulse width, and number of pulses, are set according to the thickness of the dielectric layer spanned by the blind hole. For example, different laser energy, pulse width, and number of pulses are set for blind holes with thin dielectric layers (such as L1-L2 / L26-L25) and blind holes with thick dielectric layers (such as L1-L3 / L26-L24).

[0066] In this embodiment, laser drilling parameters are set for different dielectric layer thicknesses. For example, for thin dielectric layer blind holes (e.g., L1-L2, dielectric layer thickness approximately 60-80 μm), the target blind hole diameter is 75-100 μm. Using a CO2 laser, the optimized typical parameters are: pulse energy 12-14 mJ, pulse width 10-12 μs, 1-2 pulses, and mask size 2.0 mm. For thick dielectric layer blind holes (e.g., L1-L3, dielectric layer thickness approximately 120-160 μm), the target blind hole diameter is 100-125 μm. Due to the thicker dielectric layer and the greater drilling depth required, higher laser energy and a longer pulse width are needed to ensure complete resin vaporization at the bottom of the hole without residual resin residue. The optimized typical parameters are: pulse energy 14-16 mJ, pulse width 13-15 μs, 2-3 pulses, and mask size 2.2 mm. It should be noted that there is a corresponding relationship between the thickness of the dielectric layer and the target aperture of the blind hole in the design. The thicker the dielectric layer, the more severe the laser energy attenuation. The aperture must be increased accordingly to ensure the exchange capacity of the electroplating solution. Therefore, in practice, different laser parameters are set for different apertures, which simultaneously takes into account the influence of the dielectric layer thickness.

[0067] In this embodiment, the blind hole thickness-to-diameter ratio reaches the industry limit (AR≥2.5), and the hole shape integrity is ensured by optimizing the laser parameters.

[0068] After drilling, the process involves low-temperature baking for dehumidification, slag removal, copper plating, and pulse electroplating. The baking temperature is 125°C for 2 hours. Plasma treatment is applied to improve the hole walls. A horizontal copper plating line is fabricated, with particular attention paid to plating control. After copper plating, the board is immersed in a curing tank, awaiting entry into the gantry electroplating line. Full-board pulse electroplating is then performed to ensure uniform copper plating in high aspect ratio through-holes and blind holes. The target copper thickness after pre-plating is 12±2µm.

[0069] Step S6, POFV and grinding:

[0070] Using a vacuum plugging machine, plug the holes from the S-side and C-side separately (using different tools), using Bairou PHF-9000-3F-ST ink. The plugging targets included all through holes, blind holes, and back-drilled holes.

[0071] Two grinding processes were performed using a 12-axis grinding line:

[0072] (a) Coarse grinding (copper reduction stage):

[0073] Objective: To quickly thin the copper surface to near the target thickness and remove excess adhesive from vias and excess copper layer on the surface.

[0074] 400# mesh sander belt;

[0075] Platform speed 500-600 rpm

[0076] Carrier head pressure: 3.0-4.0 psi;

[0077] Applicable area: The entire board is subjected to uniform rough grinding. At this stage, the BGA area and the large copper surface are not distinguished.

[0078] (II) Fine grinding (refinement stage):

[0079] Objective: To precisely control the final copper thickness and flatness, and to perform differentiated grinding for the different characteristics of BGA areas and large copper surfaces.

[0080] Abrasive belt mesh size 800#;

[0081] BGA area finishing parameters (dense holes, small copper area, high flatness requirements):

[0082] Carrier head pressure: 0.5-0.8 psi (this is "lower pressure"), to prevent the copper layer at the orifice from being excessively polished, which could lead to orifice collapse or excessive depression.

[0083] Platform speed: 400-600 rpm;

[0084] Vehicle head rotation speed: 300-500 rpm;

[0085] Grinding mode: Low pressure + high oscillation mode to ensure the flatness of BGA orifices.

[0086] Parameters for fine grinding of large copper surfaces (large copper area, fast heat dissipation, and need for efficient thinning):

[0087] Carrier head pressure: 1.5-2.5 psi (this is "slightly higher pressure") to improve copper surface thinning efficiency;

[0088] Platform speed: 300-500 rpm;

[0089] Vehicle head rotation speed: 200-400 rpm;

[0090] Grinding mode: Normal mode.

[0091] By employing the two-stage grinding process of coarse grinding and fine grinding, and by controlling the differentiated parameters during the fine grinding stage, the following can be achieved:

[0092] The copper thickness on the surface is ground to 35.0±5um;

[0093] The copper thickness at the orifice is 25.0±4um;

[0094] Dimple < 7.62um;

[0095] Bump < 7.62um.

[0096] Finally, POFV electroplating is performed using selective electroplating (BGA dry film masking) to achieve a copper target size of 57±5µm on the BGA area and 67±5µm on the large copper area.

[0097] Step S7, Outer Layer Pattern and Quality Inspection:

[0098] Copper Reduction and Dry Film: To obtain fine circuitry, a two-stage copper reduction process (chemical copper reduction + micro-etching) was employed, with the total copper reduction controlled to ≤15µm. After copper reduction, the target copper area in the BGA region was 42±5µm. LDI exposure was used, with compensation based on expansion and contraction data.

[0099] Etching and AOI: Strict control over etching factor and lateral etching amount, and strict repair rules are implemented for outer layer AOI (impedance lines, high frequency areas, and SI Coupon areas are prohibited from repair).

[0100] Solder mask and text: Use Haitian HSR-200GK31M matte green solder mask. Perform 100% inspection for pinholes near the varistor area. Use inkjet printing to create QR codes and text on the board.

[0101] Step S8, Molding, Testing and Shipping:

[0102] Forming: Mill the outer shape; the impedance strip and SI Coupon strip need to be milled out along with the product board and retained.

[0103] Perform the following tests:

[0104] (1) HCT test: Under the conditions of 125°C and 2.6A, the current carrying capacity of PTH vias and laser blind holes was tested, and the resistance change rate was ≤ 5%; In addition, a reflow soldering simulation test was conducted: peak temperature 260°C, 3 times in the furnace, to confirm that there was no cracking of the copper in the hole;

[0105] (2) Four-wire test: 100% four-wire low resistance test is performed on holes ≤6mil and areas with line width / spacing less than 8mil;

[0106] (3) Insertion loss test: Perform insertion loss test on the SI Coupon on the work order, and retain and compare the FA data;

[0107] (4) RVC test: Perform 100% open and short circuit test on the residual coupling structure (RVC) designed in the board to ensure that there is no short circuit at a specific spacing (e.g., D2M≥4.5mil).

[0108] In this invention, rework is prohibited in the browning, pressing, and electroplating processes in order to control the degree of ion contamination.

[0109] The 26-layer hybrid back-drilled HDI board fabricated in this embodiment has an interlayer alignment accuracy controlled within ±1 mil, a blind via aspect ratio reaching the industry limit (AR≥2.5), an average via copper thickness greater than 25.4 μm, a BGA area flatness better than 3 mil, and a BGA area surface copper thickness of 57±5 μm. The product passed HCT testing (resistance change rate ≤5%), insertion loss testing, and four-wire testing, meeting the stringent signal integrity requirements of high-speed switches.

[0110] The manufacturing method of the high-multilayer hybrid back-drilling system HDI board for high-speed switches of the present invention establishes a closed-loop control system for the entire process from design → lamination → expansion and contraction compensation → drilling → electroplating → final inspection.

[0111] The embodiments of the present invention have been described in detail above, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions, and variations made to these embodiments without departing from the principles and spirit of the present invention still fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a high-multilayer hybrid back-drilling system HDI board for high-speed switches, characterized in that, Includes the following steps: Step S1, Preliminary preparation and data processing: Generate data including independent drill lines and optical plotting based on the client's design; Step S2, Inner Layer Fabrication and Browning: Complete the inner layer circuitry and AOI inspection, and perform low-roughness browning; Step S3, lamination and expansion / contraction management: The Pin-Lam system is used for stacking and fusion; after lamination, the first piece is taken to confirm the board thickness, dielectric layer thickness and missing adhesive. The layer deviation data is measured using an X-RAY drilling machine. Based on the measurement results, the panels are stacked according to the predetermined expansion / contraction difference. An X-RAY drilling machine is used to generate independent drilling programs for different batches to perform dynamic expansion / contraction compensation, and the compensation data is synchronized to the outer layer LDI exposure and back drilling process. Step S4, Mechanical drilling and back drilling: Through hole drilling uses a TAC coated drill bit to deepen the small diameter through hole by combining short and long drills. CCD full board thickness measurement equipment is used to drill through holes on the C-side and back drill on the S-side. During back drilling, the drilling depth is dynamically calculated based on the actual measured board thickness to control the drilling depth. Step S5, Laser Blind Hole and Electroplating: Blind holes are drilled using laser drilling technology, and corresponding laser drilling parameters are set according to the thickness of the dielectric layer spanned by the blind hole; after drilling, low-temperature baking and dehumidification, slag removal and copper plating, and pulse electroplating are performed in sequence; wherein, the laser drilling parameters include laser energy, pulse width and number of pulses; Step S6, POFV and Grinding: Resin plugs are applied to all through holes, blind holes and back drill holes, and coarse and fine grinding is performed using a multi-axis grinding line. Different grinding parameters are used for the BGA area and the large copper surface to make the copper thickness of the BGA area different from that of the large copper surface, and then POFV electroplating is performed. Step S7, Outer layer pattern and quality inspection: Perform copper reduction, LDI exposure, etching and AOI, create solder mask and text, and check for pores in the predetermined area during the solder mask and circuit fabrication stage. Step S8: Molding, Testing and Shipping.

2. The manufacturing method of the high-multilayer hybrid back-drilling system HDI board for high-speed switches according to claim 1, characterized in that, In step S1, the independent drill strip data includes S-face through holes, C-face through holes, S-face back drill holes, C-face back drill holes, and drilling data of enlarged drills with different diameters.

3. The manufacturing method of the high-multilayer hybrid back-drilling system HDI board for high-speed switches according to claim 1, characterized in that, In step S3, the predetermined expansion / contraction difference is ±1mil, and the dynamic expansion / contraction compensation includes stacking the panels according to the expansion / contraction difference of ±1mil, and using the Pluritec X-RAY drilling machine to generate independent drilling programs for different batches to automatically compensate for the stretching or shrinkage ratio.

4. The manufacturing method of the high-multilayer hybrid back-drilling system HDI board for high-speed switches according to claim 1, characterized in that, In step S4, the diameter range of the small-diameter through hole is 0.175mm to 0.225mm; during back drilling, the drilling depth is dynamically calculated based on the actual plate thickness. After the first piece is debugged, three additional holes are measured for each tool to confirm the Stub length, and the T-segment is adjusted according to the results.

5. The method for manufacturing a high-multilayer hybrid back-drilling system HDI board for a high-speed switch according to claim 1, characterized in that, In step S5, after drilling, the material is baked at a low temperature to remove moisture. The baking temperature is 125°C and the baking time is 2 hours.

6. The method for manufacturing a high-multilayer hybrid back-drilling system HDI board for a high-speed switch according to claim 5, characterized in that, In step S6, the grinding target is to grind the copper thickness to 35.0±5um, the hole thickness to 25.0±4um, the depression to be less than 7.62um, and the protrusion to be less than 7.62um. After POFV electroplating, the target copper content on the BGA area is 57±5µm, and the copper content on the large copper area is 67±5µm.

7. The method for manufacturing a high-multilayer hybrid back-drilling system HDI board for a high-speed switch according to any one of claims 1-6, characterized in that, Rework is prohibited in the browning, pressing, and electroplating processes to control ion contamination levels.

8. The method for manufacturing a high-multilayer hybrid back-drilling system HDI board for a high-speed switch according to claim 1, characterized in that, In step S8, the SI Coupon is transferred synchronously with the product board and undergoes insertion loss testing, HCT testing, four-wire testing, and RVC testing.

9. A high-multilayer hybrid back-drilling system HDI board for high-speed switches, characterized in that, It is prepared by the manufacturing method according to any one of claims 1 to 8.