Memory array, static random access memory, semiconductor package structure, and electronic device

Abstract

This application discloses a memory array, a static random access memory (SRAM), a semiconductor packaging structure, and an electronic device, relating to the field of semiconductor technology. The memory array includes multiple memory cells, multiple first bit lines, and multiple second bit lines. The leakage channels of the FETs in the memory cells extend along a first direction, while the first and second bit lines extend along a second direction. In the multiple memory cells arranged along the second direction, the channel of each first access FET is connected to a first bit line, and the channel of each second access FET is connected to a second bit line. The proportion of leakage channels in the memory cells connected by the first and second bit lines is small, resulting in a low overall leakage current flowing into the first and second bit lines, or even a negligible increase in leakage current. This reduces the leakage current flowing into the first and second bit lines, thereby reducing read / write errors, improving read speed, and enhancing reliability.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to memory arrays, static random access memory, semiconductor packaging structures, and electronic devices. Background Technology

[0002] Static random access memory (SRAM) is a type of memory device that allows for static access without requiring a refresh circuit. It is widely used in digital and various electronic circuit designs. Typically, an SRAM array has multiple cells, each containing a field-effect transistor (FET). However, because the channel material of FETs often has leakage current, and the bit lines connect to a large number of cells, leakage current flowing into the bit lines due to these leakage currents increases significantly. This causes noticeable voltage fluctuations on the bit lines, which can lead to read / write errors, slow down read speeds, and reduce reliability. Summary of the Invention

[0003] This application provides a storage array, static random access memory, semiconductor packaging structure, and electronic device to reduce leakage current inrushing into bit lines due to leakage channels, thereby reducing read / write errors, improving read speed, and enhancing reliability.

[0004] In a first aspect, this application provides a memory array comprising a substrate and a plurality of memory cells, a plurality of first bit lines, and a plurality of second bit lines located on the substrate. Each memory cell includes a plurality of FETs, the channel of which comprises a semiconductor material having a leakage channel extending along a first direction. Furthermore, the plurality of first bit lines and the plurality of second bit lines extend along a second direction. The plurality of FETs includes first access FETs and second access FETs, and in the plurality of memory cells arranged along the second direction, the channel of each first access FET is connected to a first bit line, and the channel of each second access FET is connected to a second bit line. The first direction and the second direction are parallel to the substrate and intersect each other. This configuration ensures that the first bit line and the second bit line intersect the extension direction of the leakage current path of the channel they are connected to. Based on this, if some of the channels of the multiple memory cells arranged along the second direction have leakage current paths, while the channels of the remaining memory cells do not, then not all channels in the memory cells connected to the first bit line and the second bit line have leakage current paths. This results in a very small proportion of leakage current paths connected to the first bit line and the second bit line, thus keeping the overall leakage current flowing into the first bit line and the second bit line low, or even negligible. This reduces the leakage current flowing into the first bit line and the second bit line due to leakage current paths, reduces voltage fluctuations on the first bit line and the second bit line, and consequently reduces read / write errors, improves read speed, and enhances reliability. In one possible implementation, the semiconductor material may include carbon nanotubes (CNTs), where the extension direction of the CNTs intersects the extension directions of the first bit line and the second bit line. If some of the memory cells arranged along the second direction have metallic CNTs, while the CNTs of the remaining memory cells do not, then not all CNTs in the memory cells connected to the first bit line and the second bit line have metallic CNTs. Typically, the proportion of metallic CNTs is very small, thus keeping the overall leakage current flowing into the first bit line and the second bit line low, or even negligible. This reduces the leakage current flowing into the first bit line and the second bit line caused by metallic CNTs, reduces voltage fluctuations on the first bit line and the second bit line, and consequently reduces read / write errors, improves read speed, and enhances reliability.

[0005] In one possible implementation, the semiconductor material may also include a two-dimensional material with conductive grain boundaries, Si, Ge, III-V group semiconductor materials, or oxide semiconductor materials. Since the first bit line and the second bit line intersect the extension direction of the channel they are connected to, when the semiconductor material may include a two-dimensional material with conductive grain boundaries, Si, Ge, III-V group semiconductor materials, or oxide semiconductor materials, leakage current flowing into the first bit line and the second bit line due to leakage channels can be reduced, voltage fluctuations on the first bit line and the second bit line can be reduced, thereby reducing read / write errors, increasing read speed, and improving reliability.

[0006] In one possible implementation, the orthographic projection of the gate of the first access FET onto the substrate and the orthographic projection of the gate of the second access FET onto the substrate are located between the orthographic projection of the first bit line onto the substrate and the orthographic projection of the second bit line onto the substrate, which can optimize wiring and layout.

[0007] In one possible implementation, the orthographic projection of the first bit line onto the substrate and the orthographic projection of the second bit line onto the substrate are located between the orthographic projection of the gate of the first access FET onto the substrate and the orthographic projection of the gate of the second access FET onto the substrate, which can optimize wiring and layout.

[0008] In one possible implementation, the plurality of FETs further includes: a first pull-down FET, a second pull-down FET, a first pull-up FET, and a second pull-up FET, wherein the first pull-down FET, the second pull-down FET, the first pull-up FET, and the second pull-up FET include a first portion FET and a second portion FET. The channel of the first portion FET and the first bit line of the second portion FET have an overlapping region when projected onto the substrate, and the channel of the second portion FET and the second bit line of the second portion FET have an overlapping region when projected onto the substrate. This reduces the area occupied by the planar layout and improves the integration density.

[0009] In one possible implementation, the first terminals of the first pull-up FET, the first terminals of the first pull-down FET, and the first terminal of the first access FET are connected via a first electrode interconnect, and the first terminals of the second access FET, the second pull-up FET, and the second pull-down FET are connected via a second electrode interconnect. Furthermore, the first electrode interconnect and the second electrode interconnect extend along a second direction, respectively. This ensures that the first electrode interconnect, the second electrode interconnect, the first bit line, and the second bit line extend in the same direction, preventing short circuits.

[0010] In one possible implementation, the first access FET, the second access FET, the first pull-down FET, and the second pull-down FET are arranged along a first direction, with the first pull-down FET and the second pull-down FET located between the first access FET and the second access FET. Furthermore, the regions containing the first access FET and the first pull-down FET are arranged along a second direction, as are the regions containing the first pull-up FET and the second access FET and the second pull-down FET. This allows for a more regular layout of the FETs in any memory cell, making full use of space and reducing design complexity. Moreover, based on this arrangement, the first portion of the FETs includes the first pull-up FET, and the second portion of the FETs includes the second pull-up FET, which further optimizes wiring and layout.

[0011] For example, the gates of the first pull-up FET and the first pull-down FET are arranged along a second direction, which can further optimize the layout. As an example, the gates of the first pull-up FET and the first pull-down FET are integrated into a single structure, which can shorten the signal transmission path, reduce latency, and simplify the manufacturing process.

[0012] For example, the gates of the second pull-up FET and the second pull-down FET are arranged along a second direction, which can further optimize the layout. As an example, the gates of the second pull-up FET and the second pull-down FET are integrated into a single structure, which can shorten the signal transmission path, reduce latency, and simplify the manufacturing process.

[0013] In one possible implementation, the memory array further includes word lines extending along a first direction, the word lines being connected to the gates of a first access FET and a second access FET. Furthermore, the orthographic projection of the word lines onto the substrate lies between the orthographic projections of the first access FET and the first pull-up FET onto the substrate. This optimizes the word line routing and layout.

[0014] In one possible implementation, the memory array further includes a first power line and a second power line. The first power line is connected to a first pull-up FET and a second pull-up FET, and the second power line is connected to a first pull-down FET and a second pull-down FET. Furthermore, the orthographic projection of the first power line onto the substrate is located on the side where the orthographic projection of the first pull-up FET onto the substrate faces away from the orthographic projection of the first access FET onto the substrate, and the orthographic projection of the second power line onto the substrate is located on the side where the orthographic projection of the first access FET onto the substrate faces away from the orthographic projection of the first pull-up FET onto the substrate. Therefore, fewer power lines can be used to transmit the first and second power supply voltages, reducing wiring complexity.

[0015] In one possible implementation, the first access FET, the first pull-down FET, and the first pull-up FET are arranged along a second direction. This allows for a more regular layout of the FETs in any memory cell, making full use of space and reducing design complexity. Furthermore, based on this arrangement, the first portion of the FETs includes the first pull-up FET and the first pull-down FET, which can further optimize wiring and layout.

[0016] For example, in the second direction, the first pull-down FET is located between the first access FET and the first pull-up FET. For instance, the orthogonal projection of the channel of the first pull-down FET onto the substrate is located between the orthogonal projection of the channel of the first access FET onto the substrate and the orthogonal projection of the channel of the first pull-up FET onto the substrate, which can further optimize the layout.

[0017] For example, the gates of the first access FET, the first pull-down FET, and the first pull-up FET are arranged along the second direction, which can further optimize the layout. As an example, the gates of the first pull-down FET and the first pull-up FET are integrated into a single structure, which can shorten the signal transmission path, reduce latency, and simplify the manufacturing process.

[0018] In one possible implementation, the second access FET, the second pull-down FET, and the second pull-up FET are arranged along a second direction. This allows for a more regular layout of the FETs in any memory cell, making full use of space and reducing design complexity. Furthermore, based on this arrangement, the second part of the FETs includes a second pull-up FET and a second pull-down FET, which can further optimize wiring and layout.

[0019] For example, in the second direction, the second pull-down FET is located between the second access FET and the second pull-up FET. For instance, the orthogonal projection of the channel of the second pull-down FET onto the substrate may be located between the orthogonal projections of the channel of the second access FET and the channel of the second pull-up FET onto the substrate, which may further optimize the layout.

[0020] For example, the gates of the second access FET, the second pull-down FET, and the second pull-up FET are arranged along a second direction, which can further optimize the layout. As an example, the gates of the second pull-down FET and the second pull-up FET are integrated into a single structure, which can shorten the signal transmission path, reduce latency, and simplify the manufacturing process.

[0021] In one possible implementation, the memory array further includes word lines extending along a first direction, the word lines being connected to the gates of the first access FET and the second access FET. Furthermore, the orthographic projection of the word lines onto the substrate is located on the side where the orthographic projection of the first access FET onto the substrate faces away from the orthographic projection of the first pull-down FET onto the substrate. This optimizes the word line routing and layout.

[0022] In one possible implementation, the memory array further includes a second power line connected to both the first and second pull-down FETs. Furthermore, the orthographic projection of the second power line onto the substrate is located on the side where the orthographic projection of the word line onto the substrate faces away from the orthographic projection of the first access FET onto the substrate. This allows for the transmission of the second power supply voltage using fewer power lines, reducing wiring complexity.

[0023] In one possible implementation, the memory array further includes a second power line connected to both the first and second pull-down FETs. Furthermore, the orthographic projection of the second power line onto the substrate lies between the orthographic projections of the first access FET and the first pull-down FET onto the substrate. This allows for the transmission of the second power supply voltage using fewer power lines, reducing wiring complexity.

[0024] In one possible implementation, the memory array further includes a first power line connected to a first pull-up FET and a second pull-up FET. Furthermore, the orthographic projection of the first power line onto the substrate is located on the side where the orthographic projection of the first pull-up FET onto the substrate faces away from the orthographic projection of the first access FET onto the substrate. This allows for the transmission of the first power supply voltage using fewer power lines, reducing wiring complexity.

[0025] In one possible implementation, the first access FET, the second pull-up FET, and the second pull-down FET are arranged along a second direction. This allows for a more regular layout of the FETs in any memory cell, making full use of space and reducing design complexity. Furthermore, based on this arrangement, the first part of the FETs includes the second pull-up FET and the second pull-down FET, which can further optimize wiring and layout.

[0026] For example, in the second direction, the second pull-up FET is located between the first access FET and the second pull-down FET. For instance, the orthogonal projection of the channel of the second pull-up FET onto the substrate is between the orthogonal projection of the channel of the first access FET onto the substrate and the channel of the second pull-down FET onto the substrate.

[0027] For example, the gates of the first access FET, the second pull-up FET, and the second pull-down FET are arranged along a second direction, which can further optimize the layout. As an example, the gates of the second pull-down FET and the second pull-up FET are integrated into a single structure, which can shorten the signal transmission path, reduce latency, and simplify the manufacturing process.

[0028] In one possible implementation, the second access FET, the first pull-up FET, and the first pull-down FET are arranged along a second direction. This allows for a more regular layout of the FETs in any memory cell, making full use of space and reducing design complexity. Furthermore, based on this arrangement, the second part of the FETs includes the first pull-up FET and the first pull-down FET, which can further optimize wiring and layout.

[0029] For example, in the second direction, the first pull-up FET is located between the second access FET and the first pull-down FET. For instance, the orthogonal projection of the channel of the first pull-up FET onto the substrate is located between the orthogonal projection of the channel of the second access FET onto the substrate and the orthogonal projection of the channel of the first pull-down FET onto the substrate, which can further optimize the layout.

[0030] For example, the gates of the second access FET, the first pull-down FET, and the first pull-up FET are arranged along a second direction, which can further optimize the layout. As an example, the gates of the first pull-down FET and the first pull-up FET are integrated into a single structure, which can shorten the signal transmission path, reduce latency, and simplify the manufacturing process.

[0031] In one possible implementation, the memory array further includes word lines extending along a first direction, the word lines being connected to the gates of a first access FET and a second access FET. Furthermore, the orthographic projection of the word lines onto the substrate lies between the orthographic projections of the first and second access FETs onto the substrate. This optimizes the word line routing and layout.

[0032] In one possible implementation, the memory array further includes a first power line, a second power line, and a third power line. The first power line is connected to a first pull-up FET and a second pull-up FET, the second power line is connected to a first pull-down FET, and the third power line is connected to a second pull-down FET. Furthermore, the orthographic projection of the first power line onto the substrate lies between the orthographic projections of the second power line and the third power line onto the substrate. Therefore, fewer power lines can be used to transmit the first and second power supply voltages, reducing wiring complexity.

[0033] Secondly, this application provides a static random access memory (SRAM), comprising: a controller and at least one memory array, wherein the controller is electrically connected to any memory array. The memory array is the memory array described in the first aspect or in various embodiments of the first aspect. Because the memory array in the embodiments of this application has good performance, the SRAM including this memory array also has good performance.

[0034] Thirdly, this application provides a semiconductor package structure, which includes a package substrate and a static random access memory (SRAM), wherein the SRAM is packaged on the package substrate. The SRAM is the SRAM described in the second aspect or in the embodiments of the second aspect. Because the SRAM in the embodiments of this application has better performance, the semiconductor package structure including the SRAM also has better performance.

[0035] Fourthly, this application provides an electronic device, comprising: a circuit board and a semiconductor package structure, wherein the semiconductor package structure is electrically connected to the circuit board. The semiconductor package structure is the semiconductor package structure described in the third aspect. Because the semiconductor package structure in the embodiments of this application has better performance, the electronic device incorporating this semiconductor package structure also has better performance.

[0036] Furthermore, the technical effects of the corresponding solutions in the second to fourth aspects can be referred to the technical effects that can be obtained by the corresponding solutions in the first aspect, and the repetitions will not be detailed. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the structure of an electronic device in an embodiment of this application;

[0038] Figure 2A This is a schematic diagram of a semiconductor packaging structure in an embodiment of this application;

[0039] Figure 2B A structural block diagram of a storage array provided in an embodiment of this application;

[0040] Figure 3 A circuit diagram of a storage unit provided in an embodiment of this application;

[0041] Figure 4 This is a top view of a storage array in an embodiment of this application.

[0042] Figure 5 This is a schematic diagram of a storage array structure in related technologies;

[0043] Figure 6 This is a top view schematic diagram of another storage array structure in the embodiments of this application;

[0044] Figure 7A for Figure 6 A top view of the semiconductor device layer in the diagram;

[0045] Figure 7B for Figure 6 A top view of the first wiring layer in the diagram;

[0046] Figure 7C for Figure 6 A top view of the second wiring layer in the diagram;

[0047] Figure 7D for Figure 6 A top view of the third wiring layer in the diagram;

[0048] Figure 8A for Figure 6 A schematic diagram of the cross-sectional structure along the AA' direction;

[0049] Figure 8B for Figure 6 A schematic diagram of the cross-sectional structure along the BB' direction;

[0050] Figure 8C for Figure 6 A schematic diagram of the cross-sectional structure along the CC' direction;

[0051] Figure 8D for Figure 6 A schematic diagram of the cross-sectional structure along the DD' direction;

[0052] Figure 8E for Figure 6 A schematic diagram of the cross-sectional structure along the EE' direction;

[0053] Figure 9 This is a top view schematic diagram of another storage array structure in the embodiments of this application;

[0054] Figure 10A for Figure 9 A top view of the semiconductor device layer in the diagram;

[0055] Figure 10B for Figure 9 A top view of the first wiring layer in the diagram;

[0056] Figure 10C for Figure 9 A top view of the second wiring layer in the diagram;

[0057] Figure 10D for Figure 9 A top view of the third wiring layer in the diagram;

[0058] Figure 11A for Figure 9 A schematic diagram of the cross-sectional structure along the AA' direction;

[0059] Figure 11B for Figure 9 A schematic diagram of the cross-sectional structure along the BB' direction;

[0060] Figure 11C for Figure 9 A schematic diagram of the cross-sectional structure along the CC' direction;

[0061] Figure 12 This is a top view schematic diagram of another storage array structure in the embodiments of this application;

[0062] Figure 13 This is a top view schematic diagram of another storage array structure in the embodiments of this application;

[0063] Figure 14A for Figure 13 A top view of the semiconductor device layer in the diagram;

[0064] Figure 14B for Figure 13 A top view of the first wiring layer in the diagram;

[0065] Figure 14C for Figure 13 A top view of the second wiring layer in the diagram;

[0066] Figure 14D for Figure 13 A top view of the third wiring layer in the diagram;

[0067] Figure 15 This is a top view schematic diagram of another storage array structure in the embodiments of this application;

[0068] Figure 16A for Figure 15 A top view of the semiconductor device layer in the diagram;

[0069] Figure 16B for Figure 15 A top view of the first wiring layer in the diagram;

[0070] Figure 16C for Figure 15 A top view of the second wiring layer in the diagram;

[0071] Figure 16D for Figure 15 A top view of the third wiring layer.

[0072] Figure label:

[0073] 1-Electronic device; 2-Semiconductor package structure; 3-Circuit board; 4-Housing; 10-Substrate; 11-First dielectric layer; 12-Second dielectric layer; 13-Third dielectric layer; 20-Semiconductor device layer; 30-First wiring layer; 31-First power line; 32-Second power line; 33-Third power line; 40-Second wiring layer; 41-First electrode interconnect; 42-Second electrode interconnect; 43 / 43a / 43b-First power interconnect; 44 / 44a / 44b-Second power interconnect; 45-Third electrode interconnect; 46-Fourth electrode interconnect; 47-First word line interconnect; 48-Second word line interconnect; 50-Third wiring layer; MA1-First access FET; MA2-Second access FET; MP1-First upper... Pull-up FET; MP2 - Second pull-up FET; MN1 - First pull-down FET; MN2 - Second pull-down FET; CA1 - First electrode contact hole; CA2 - Second electrode contact hole; CA3 - Third electrode contact hole; CA4 - Fourth electrode contact hole; CA5 - Fifth electrode contact hole; CA6 - Sixth electrode contact hole; CA7 - Seventh electrode contact hole; CA8 - Eighth electrode contact hole; CA9 - Ninth electrode contact hole; CA10 - Tenth electrode contact hole; CB1 - First bit line contact hole; CB2 - Second bit line contact hole; CD1 - First word line contact hole; CD2 - Second word line contact hole; CD3 - Third word line contact hole; CD4 - Fourth word line contact hole; CD5 - Fifth word line contact hole; CD6 - Sixth word line contact hole; 212 A1 / 212 A2 / 212 P1 / 212 P2 / 212 N1 / 212 N2 - Gate; 211a A2 / 211a N2 / 211a P2 / 211a A1 / 211a N1 / 211a P1 -First section; 211b N2 / 211b N1 / 211b P2 / 211b P1 / 211b A2 / 211b A1 - Second part area; 100 - Memory cell; BL1 - First bit line; BL2 - Second bit line; F1 - First direction; F2 - Second direction. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0075] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0076] To facilitate understanding of the storage array, static random access memory (SRAM), and electronic device provided in the embodiments of this application, their application scenarios will be introduced first below.

[0077] The storage array provided in this application embodiment can be applied to electronic devices with storage functions, such as SRAM in electronic devices. Electronic devices include, but are not limited to, terminal devices, communication devices, and electronic components. Terminal devices include, but are not limited to, mobile phones, computers, televisions, set-top boxes, watches, personal computers (PCs), wearable devices, workstations, etc. Communication devices include, but are not limited to, wireless networks, fixed networks, servers, and smart broadband. Electronic components include, but are not limited to, memory (e.g., SRAM), processing chips (e.g., central processing unit (CPU), graphics processing unit (GPU), artificial intelligence (AI) processors, digital signal processors (DSPs), and neural network processors), system-on-chips (SoCs), etc., which are not listed here. It is understood that the specific implementation of the storage array can be determined according to the actual application scenario and is not limited here.

[0078] The memory array, SRAM, semiconductor packaging structure, and electronic device provided in the embodiments of this application are described below with reference to the accompanying drawings.

[0079] Figure 1 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. (Refer to...) Figure 1 The electronic device 1 may include a semiconductor package structure 2 and a circuit board 3, which are electrically connected. For example, the semiconductor package structure 2 may be fixed to the circuit board 3 using bonding or other connection methods to achieve an electrical connection between them, thereby transmitting signals.

[0080] For example, the electronic device 1 may also include a housing 4 having an accommodating space, in which the circuit board 3 is disposed and fixed to the housing 4. Furthermore, the circuit board 3 includes, but is not limited to, a printed circuit board (PCB).

[0081] Figure 2A This is a schematic diagram of a semiconductor packaging structure according to an embodiment of this application. (Refer to...) Figure 2A The semiconductor packaging structure 2 may include a packaging substrate ( Figure 2A (Not shown) and SRAM, with the SRAM packaged on a package substrate. Exemplarily, the SRAM may include a controller and a memory array, the controller being electrically connected to the memory array so that the controller can access the memory array. The SRAM may include one or more memory arrays. Furthermore, the electronic device may also include a processor, a cache, etc., wherein the SRAM may be integrated into the processor or disposed independently on a circuit board. Exemplarily, the processor may be a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor, or a neural network processor, etc. The circuit board includes, but is not limited to, a printed circuit board (PCB).

[0082] Figure 2B This is a structural block diagram of a storage array provided in an embodiment of this application. (Refer to...) Figure 2B The storage array may include multiple storage cells 100 arranged in an N-row, M-column array, where M and N are both integers greater than or equal to 1. For example, the multiple storage cells 100 may be arranged along a second direction F2 as multiple storage cell rows (e.g., row 1 to row N), each storage cell row (e.g., row 1 to row N) including multiple storage cells 100 arranged along a first direction F1. Furthermore, the multiple storage cells 100 may also be arranged along the first direction F1 as multiple storage cell columns (e.g., column 1 to column M), each storage cell column (e.g., column 1 to column M) including multiple storage cells 100 arranged along the second direction F2.

[0083] Figure 3 This is a circuit diagram of a storage unit provided in an embodiment of this application. (Refer to...) Figure 3 The memory cell 100 can be configured as a 6T structure. For example, the memory cell 100 may include: a first access FETMA1, a second access FETMA2, a first pull-up FETMP1, a second pull-up FETMP2, a first pull-down FETMN1, and a second pull-down FETMN2. The gates of the first access FETMA1 and the second access FETMA2 are connected to the same word line (WL), and the signal transmitted through the WL drives the first access FETMA1 and the second access FETMA2 to turn on and off. The second terminal of the first access FETMA1 is connected to the first bit line BL1, through which data is transmitted. The second terminal of the second access FETMA2 is connected to the second bit line BL2, through which data is transmitted. The first terminals of the first access FETMA1, the first terminals of the first pull-up FETMP1 and the first pull-down FETMN1, the gates of the second pull-up FETMP2 and the second pull-down FETMN2 are interconnected to form a memory node QB. The first terminals of the second access FETMA2, the second pull-up FETMP2, and the second pull-down FETMN2, as well as the gates of the first pull-up FETMP1 and the first pull-down FETMN1, are interconnected to form a storage node Q. The second terminals of the first pull-up FETMP1 and the second pull-up FETMP2 are used to receive the first power supply voltage VDD, and the second terminals of the first pull-down FETMN1 and the second pull-down FETMN2 are used to receive the second power supply voltage VSS.

[0084] For example, refer to Figure 3 The first pull-up FET MP1 and the second pull-up FET MP2 are both P-type FETs, and the first pull-down FET MN1 and the second pull-down FET MN2 are both N-type FETs. Therefore, the first pull-up FET MP1 and the first pull-down FET MN1 constitute the first inverter, and the second pull-up FET MP2 and the second pull-down FET MN2 constitute the second inverter. The output of the first inverter is electrically connected to the input of the second inverter, forming a storage node QB. The output of the second inverter is connected to the input of the first inverter, forming a storage node Q. Because the first and second inverters are cross-coupled, a latching circuit is formed, so that when one storage node is pulled down to a low potential, the other storage node is pulled up to a high potential. Furthermore, the first access FET MA1 and the second access FET MA2 can both be N-type FETs.

[0085] Combination Figure 1In the prior art, since the first bit line BL1 is connected to the first access FETMA1 in a row of memory cells, and the second bit line BL2 is typically connected to the second access FETMA2 in the same row of memory cells, the extension directions of the CNTs of the first access FETMA1 and the second access FETMA2 in the same row of memory cells are the same as the extension directions of the first bit line BL1 and the second bit line BL2. If there are metallic CNTs in the CNTs of the first access FETMA1 and the first access FETMA2 in the row of memory cells, a leakage current path will exist in the channel of the first access FETMA1 and the first access FETMA2, causing a large amount of leakage current to surge into the first bit line BL1 and the second bit line BL2, which can easily cause read / write errors, slow down the read speed, and reduce reliability. To improve this problem, the embodiments of this application redesign the layout of the memory array to reduce the leakage current surging into the bit lines due to metallic CNTs, thereby reducing read / write errors, improving read speed, and improving reliability.

[0086] Figure 4 This is a top view schematic diagram of a storage array in an embodiment of this application, with reference to... Figure 4In this embodiment, the memory array may include a substrate 10 and a plurality of memory cells 100, a plurality of first bit lines BL1, and a plurality of second bit lines BL2 located on the substrate 10. Each memory cell 100 includes a plurality of FETs, the channel of which includes a semiconductor material with a leakage channel extending along a first direction. Furthermore, the plurality of FETs in the memory cell 100 may include a first access FET MA1 and a second access FET MA2, i.e., the first access FET MA1 and the second access FET MA2 are respectively configured as CNTFETs. To improve the leakage current problem of the first access FET MA1 and the second access FET MA2 due to the leakage channel, the plurality of first bit lines BL1 and the plurality of second bit lines BL2 are extended along a second direction F2 and arranged along a first direction F1, such that the extension directions of the first bit lines BL1 and the second bit lines BL2 intersect (e.g., perpendicularly) the extension directions of the leakage channels of the first access FET MA1 and the second access FET MA2. Furthermore, among the plurality of memory cells 100 arranged along the second direction F2, the channel of each first access FETMA1 is connected to a first bit line BL1, and the channel of each second access FETMA2 is connected to a second bit line BL2, such that the first bit line BL1 and the second bit line BL2 respectively intersect (e.g., perpendicularly) the extension direction of the leakage current path of the channel to which they are connected. For example, if some of the storage cells 100 arranged along the second direction have leakage paths in their channels, while the channels of the remaining storage cells 100 do not, then not all the channels in the storage cells 100 connected to the first bit line BL1 and the second bit line BL2 have leakage paths. This results in a very small proportion of leakage paths connected to the first bit line BL1 and the second bit line BL2, thus keeping the overall leakage current flowing into the first bit line BL1 and the second bit line BL2 low, or even negligible. This reduces the leakage current flowing into the first bit line BL1 and the second bit line BL2 due to leakage paths, reduces voltage fluctuations on the first bit line BL1 and the second bit line BL2, thereby reducing read / write errors, improving read speed, and improving reliability.

[0087] In one embodiment of this application, reference is made to... Figure 4 The semiconductor material forming the channel of the FET can be a CNT, allowing the FET in the memory cell 100 to be configured as a CNTFET. This leverages the advantages of CNTFETs, such as high mobility and good gate control, to improve read / write time and noise margin. The CNT extends along a first direction F1, meaning the axial direction of the CNT is the first direction F1. Furthermore, the CNT includes semiconductor-type CNTs.

[0088] Understandably, due to limitations in current semiconductor CNT fabrication processes, the purity of the formed semiconductor CNT material cannot reach 100%, and it will still contain a small amount of metallic CNTs. This makes it easy to introduce a small amount of metallic CNTs into the channel of the CNTFET. Since metallic CNTs have better conductivity, the presence of these metallic CNTs increases the leakage current of the CNTFET. For example, when the semiconductor material is CNT, its leakage channel can be a metallic CNT. For instance, refer to... Figure 5 In related technologies, the first bit line BL1 is connected to the first access FETMA1 in a row of memory cells, and the second bit line BL2 is typically connected to the second access FETMA2 in the same row of memory cells. Furthermore, the extension directions of the CNTs of the first access FETMA1 and the second access FETMA2 in a row of memory cells are the same as the extension directions of the first bit line BL1 and the second bit line BL2. For example, if there are metallic CNTs in the CNTs of the first access FETMA1 and the first access FETMA2 in the row of memory cells, a leakage current path may exist in the channels of the first access FETMA1 and the first access FETMA2. This will cause a significant increase in the leakage current of each first access FETMA1 and each first access FETMA2 in the row of memory cells. This will result in a large amount of leakage current flowing into the first bit line BL1 and the second bit line BL2, which can easily cause read / write errors, slow down the read speed, and reduce reliability.

[0089] In the embodiments of this application, reference is made to Figure 4Taking columns 1, 2, and 3 of the memory cell columns, and rows 1 to N of the memory cell rows as examples, the first bit line BL1 is connected to the first access FETMA1 CNT of each memory cell 100 in column 1 (i.e., memory cells 100 in rows 1 to N in column 1), and the first second bit line BL2 is connected to the second access FETMA2 CNT of each memory cell 100 in column 1 (i.e., memory cells 100 in rows 1 to N in column 1). The second bit line BL1 is connected to the first access FETMA1 CNT of each memory cell 100 in column 2 (i.e., memory cells 100 in rows 1 to N in column 2), and the second second bit line BL2 is connected to the second access FETMA2 CNT of each memory cell 100 in column 2 (i.e., memory cells 100 in rows 1 to N in column 2). The third bit line BL1 is connected to the CNT of the first access FETMA1 of each memory cell 100 in column 3 (i.e., memory cells 100 in rows 1 to N in column 3), and the third bit line BL2 is connected to the CNT of the second access FETMA2 of each memory cell 100 in column 3 (i.e., memory cells 100 in rows 1 to N in column 3). Taking the first bit line BL1 and column 1 as an example, if the CNT of the first access FETMA1 in row 1 has a metallic CNT, and the CNT of the first access FETMA1 in rows 2 to N does not have a metallic CNT, then when the first access FETMA1 is in the off state, because the leakage current of the first access FETMA1 in row 1 is higher, and the leakage current of the first access FETMA1 in rows 2 to N is lower or negligible, there is an increase in the leakage current of the first access FETMA1 in row 1 to the first bit line BL1. However, since the first access FETMA1 in row 1 accounts for a small proportion of all the first access FETMA1s connected to the first bit line BL1, the overall leakage current flowing into the first bit line BL1 remains low. In fact, the increase in leakage current flowing into the first bit line BL1 caused by the first access FETMA1 in row 1 is negligible. This reduces the leakage current flowing into the first bit line BL1 caused by the metal-type CNT, thus reducing voltage fluctuations on the first bit line BL1. Similarly, it also reduces the leakage current flowing into the first second bit line BL2 caused by the metal-type CNT, reducing voltage fluctuations on the first second bit line BL2. Furthermore, the method for reducing the leakage current flowing into the remaining first bit lines BL1 and second bit lines BL2 caused by the metal-type CNT can be deduced in the same way, and will not be elaborated here. Therefore, by setting the extension directions of the first bit line BL1 and second bit line BL2 to intersect with the extension directions of the CNTs of their corresponding first access FETMA1 and second access FETMA1, read / write errors can be reduced, read speed improved, and reliability enhanced.

[0090] Understandably, in order to clearly illustrate the relationship between the extension directions of CNT and the first bit line BL1 and the second bit line BL2 in the embodiments of this application, Figure 4 and Figure 5 The diagram illustrates the relationship between the CNTs of the first access FETMA1 and the second access FETMA2 and the extension directions of the first bit line BL1 and the second bit line BL2, respectively. It does not focus on the specific locations of the first access FETMA1 and the second access FETMA2 in the layout; their locations can be flexibly designed based on the actual layout of the memory cell. Furthermore, the first direction F1 and the second direction F2 are parallel to the substrate 10, but they intersect; for example, the first direction F1 is perpendicular to the second direction F2.

[0091] It is worth mentioning that during the fabrication of memory arrays, when forming the CNTs in the FET channels of each memory cell, one or more elongated CNTs extending along the first direction F1 are typically laid. Then, etching is performed at the locations where the laid CNTs need to be truncated. Alternatively, these elongated CNTs can be shared directly to form the channels of the FETs in each memory cell row. Based on this, at least the following structures exist in the memory array: the first structure is a structure where the first access FETMA1 and the second access FETMA2 in any memory cell row share a CNT; the second structure is a structure where the CNTs of the first access FETMA1 and the second access FETMA2 in any memory cell row are independent of each other. Since the CNTs in any memory cell row are formed from elongated CNTs, if a metallic CNT is present in the elongated CNTs of a certain memory cell row, the leakage current of the first access FETMA1 and the second access FETMA2 in that memory cell row will increase significantly. Based on this, the relationship between the extension direction of the CNT and the first bit line BL1 and the second bit line BL2 in the embodiments of this application can be applied not only to the first structure described above, but also to the second structure described above. For these structures, the leakage current that surges into the first bit line BL1 and the second bit line BL2 due to the metal CNT can be reduced, and the voltage fluctuation on the first bit line BL1 and the second bit line BL2 can be reduced.

[0092] It is understood that the arrangement and technical effects of the first and second bit lines in the embodiments of this application can also be applied when forming the FET channel using other semiconductor materials with leakage channels. For example, semiconductor materials with leakage channels include, but are not limited to, two-dimensional materials with conductive grain boundaries, Si, Ge, and III-V group semiconductor materials using large-particle polycrystalline substrates, and oxide semiconductor materials with long leakage channels. Furthermore, the implementation methods and technical effects of forming FET channels using other semiconductor materials with leakage channels can be referred to the implementation methods and technical effects of forming FET channels using CNTs, and the repetitions will not be discussed.

[0093] The structure of the storage array in the embodiments of this application will be described in detail below with reference to the embodiments and accompanying drawings.

[0094] Figure 6 This is a top view schematic diagram of another storage array structure in an embodiment of this application. Figure 7A for Figure 6 A top view of the semiconductor device layer in the diagram. Figure 7B for Figure 6 A top view of the first wiring layer in the diagram. Figure 7C for Figure 6 A top view of the second wiring layer in the diagram. Figure 7D for Figure 6 A top view of the third wiring layer in the diagram. Figure 8A for Figure 6 A schematic diagram of the cross-sectional structure along the AA' direction. Figure 8B for Figure 6 A schematic diagram of the cross-sectional structure along the BB' direction. Figure 8C for Figure 6 A schematic diagram of the cross-sectional structure along the CC' direction. Figure 8D for Figure 6 A schematic diagram of the cross-sectional structure along the DD' direction. Figure 8E for Figure 6 A schematic cross-sectional view of the structure along the EE' direction. (Refer to...) Figures 6 to 8E In the memory cell 100, the CNTs of each FET extend along a first direction F1, and the first bit line BL1 and the second bit line BL2 extend along a second direction F2 and are arranged along the first direction F1. Specifically, the orthographic projections of the CNTs of the first access FET MA1 onto the substrate 10 overlap with the orthographic projections of the first bit line BL1 onto the substrate 10, and the orthographic projections of the CNTs of the second access FET MA2 onto the substrate 10 overlap with the orthographic projections of the second bit line BL2 onto the substrate 10. This optimizes the wiring and layout.

[0095] In one embodiment of this application, reference is made to... Figure 6 and Figure 7AIn any memory cell 100, the gate 212 of the first access FETMA1 A1 Orthogonal projection of substrate 10 and gate 212 of second access FET MA2 A2 In the orthographic projection of the substrate 10, the first bit line BL1 connected to the memory cell 100 is located between the orthographic projection of the substrate 10 and the second bit line BL2 connected to the memory cell 100. This allows for optimized routing and layout.

[0096] In one embodiment of this application, reference is made to... Figure 6 The memory cell 100 further includes multiple FETs: a first pull-down FET MN1, a second pull-down FET MN2, a first pull-up FET MP1, and a second pull-up FET MP2. Each of the first pull-down FET MN1, second pull-down FET MN2, first pull-up FET MP1, and second pull-up FET MP2 comprises a first portion FET and a second portion FET. The orthogonal projection of the CNT of the first portion FET onto the substrate 10 overlaps with the orthogonal projection of the first bit line BL1 onto the substrate 10, and the orthogonal projection of the CNT of the second portion FET onto the substrate 10 overlaps with the orthogonal projection of the second bit line BL2 onto the substrate 10. This reduces the area occupied by the planar layout and improves the integration density.

[0097] In one embodiment of this application, the first FET and the second FET are different, which can further optimize the layout. As an example, see [reference]. Figure 6 and Figure 7AIn any memory cell, the first access FET MA1, the second access FET MA2, the first pull-down FET MN1, and the second pull-down FET MN2 are arranged along a first direction F1. Furthermore, the first pull-down FET MN1 and the second pull-down FET MN2 are located between the first access FET MA1 and the second access FET MA2. Additionally, the regions containing the first access FET MA1 and the first pull-down FET MN1 are arranged along a second direction F2, as are the regions containing the first pull-up FET MP1, and the regions containing the second access FET MA2 and the second pull-down FET MN2 are arranged along a second direction F2. This allows for a more regular layout of the FETs in any memory cell 100, making full use of space and reducing design complexity. Furthermore, based on this arrangement, the first FET portion can include a first pull-up FET MP1, and the second FET portion can include a second pull-up FET MP2. That is, the orthogonal projection of the CNT of the first pull-up FET MP1 onto the substrate 10 overlaps with the orthogonal projection of the first bit line BL1 onto the substrate 10, and the orthogonal projection of the CNT of the second pull-up FET MP2 onto the substrate 10 overlaps with the orthogonal projection of the second bit line BL2 onto the substrate 10. This further optimizes the wiring and layout. In other embodiments of this application, the first FET portion and the second FET portion can also have some FETs that are the same and some that are different; details will not be elaborated here.

[0098] For example, refer to Figure 6 and Figure 7A In any memory cell 100, the CNTs in the channel of the first pull-up FETMP1 and the channel of the second pull-up FETMP2 are shared. Furthermore, the CNTs in the channel of the first access FETMA1, the channel of the first pull-down FETMN1, the channel of the second pull-down FETMN2, and the channel of the second access FETMA2 are shared. Further, in some or all of the adjacent memory cells in any row of memory cells, the CNTs in the channel of the first pull-up FETMP1 and the channel of the second pull-up FETMP2 are shared, and the CNTs in the channel of the first access FETMA1, the channel of the first pull-down FETMN1, the channel of the second pull-down FETMN2, and the channel of the second access FETMA2 are shared. That is, the CNTs extend along the first direction F1 to form the channels of the FETs in the memory cell 100.

[0099] For example, refer to Figure 6 and Figure 7A The gate 212 of the first pull-up FETMP1 P1 With the gate 212 of the first pull-down FET MN1 N1Arranging the components along the second direction F2 allows for further optimization of the layout. As an example, the gate 212 of the first pull-up FET MP1... P1 With the gate 212 of the first pull-down FET MN1 N1 As a single integrated structure, the gate 212 of the first pull-down FET MN1 can be... N1 With the gate 212 of the first pull-up FETMP1 P1 Direct electrical connection shortens the signal transmission path and reduces latency. Furthermore, the gate 212 of the first pull-down FET MN1 can be fabricated using the same process. N1 With the gate 212 of the first pull-up FETMP1 P1 This simplifies the manufacturing process. In other embodiments of this application, the gate 212 of the first pull-up FETMP1... P1 With the gate 212 of the first pull-down FET MN1 N1 They can also be independent and connected at points through the connection lines of other wiring layers.

[0100] For example, refer to Figure 6 and Figure 7A The gate 212 of the second pull-up FETMP2 P2 With the gate 212 of the second pull-down FETMN2 N2 Arranging the FETs along the second direction F2 allows for further optimization of the layout. As an example, the gate 212 of the second pull-up FET MP2... P2 With the gate 212 of the second pull-down FETMN2 N2 As a single integrated structure, the gate 212 of the second pull-down FET MN2 can be... N2 With the gate 212 of the second pull-up FETMP2 P2 Direct electrical connection shortens the signal transmission path and reduces latency. Furthermore, the gate 212 of the second pull-down FET MN2 can be fabricated using the same process. N2 With the gate 212 of the second pull-up FETMP2 P2 This simplifies the manufacturing process. In other embodiments of this application, the gate 212 of the second pull-up FETMP2... P2 With the gate 212 of the second pull-down FETMN2 N2 They can also be independent and connected at points through the connection lines of other wiring layers.

[0101] In one embodiment of this application, reference is made to... Figure 6 and Figure 7D The memory array 100 also includes WL, which is connected to the gate 212 of the first access FET MA1. A1 Second access FETMA2 gate 212 A2The connection is established. Furthermore, the orthographic projection of WL onto substrate 10 lies between the orthographic projections of the first access FETMA1 onto substrate 10 and the first pull-up FETMP1 onto substrate 10. This allows for optimization of the routing of WL and improved layout.

[0102] For example, refer to Figure 6 and Figure 7D The WL extends along the first direction F1. Furthermore, the memory array can have multiple WLs, with one WL corresponding to one row of memory cells. The first access FETMA1 and the second access FETMA2 in one row of memory cells are connected to one WL to simplify wiring, save memory array area, and improve integration density. Moreover, the orthographic projection of the WL corresponding to any row of memory cells onto the substrate 10 lies between the orthographic projection of the first access FETMA1 and the first pull-up FETMP1 onto the substrate 10.

[0103] In one embodiment of this application, reference is made to... Figure 6 and Figure 7B The storage array also includes a first power line 31 and a second power line 32. The first power line 31 is connected to a first pull-up FETMP1 and a second pull-up FETMP2 to transmit a first power supply voltage VDD to the first pull-up FETMP1 and the second pull-up FETMP2. The second power line 32 is connected to a first pull-down FETMN1 and a second pull-down FETMN2 to transmit a second power supply voltage VSS to the first pull-down FETMN1 and the second pull-down FETMN2. Therefore, fewer power lines can be used to transmit the first power supply voltage VDD and the second power supply voltage VSS, reducing wiring complexity.

[0104] For example, refer to Figure 6 and Figure 7B The first power line 31 and the second power line 32 are arranged sequentially along the first direction F1 and extend along the second direction F2 respectively. The orthographic projection of the first power line 31 onto the substrate 10 is located on the side opposite to the orthographic projection of the first pull-up FETMP1 onto the substrate 10, and the orthographic projection of the second power line 32 onto the substrate 10 is located on the side opposite to the orthographic projection of the first pull-up FETMP1 onto the substrate 10. This allows for further optimization of the layout.

[0105] For example, the storage array has multiple first power lines 31 and multiple second power lines 32. One storage cell row corresponds to one first power line 31 and one second power line 32. Each first pull-up FETMP1 and each second pull-up FETMP2 in a storage cell row is connected to one first power line 31, and each second pull-down FETMN2 and each first pull-down FETMN1 in a storage cell row is connected to one second power line 32. This can simplify wiring, save storage array area, and improve integration.

[0106] In one embodiment of this application, the structure of two adjacent memory cells 100 along the second direction F2 can be optimized in terms of layout, simplifying the design, improving reliability, and reducing manufacturing costs. Exemplarily, the structure of two adjacent memory cells 100 along the second direction F2 can be mirror-symmetrical about the axis of symmetry along the first direction F1. Further, when the first power line 31 is located between a first portion of adjacent memory cells 100 arranged along the second direction F2, the first portion of adjacent memory cells 100 can share a single first power line 31. When the second power line 32 is located between a second portion of adjacent memory cells 100 arranged along the second direction F2, the second portion of adjacent memory cells 100 can share a single second power line 32. This further simplifies wiring, further saves memory array area, and further improves integration. In other embodiments of this application, the structures of two adjacent storage cells 100 along the second direction F2 can also be the same, that is, the structure of one storage cell 100 is translated along the second direction F2 to form the structure of another storage cell 100. In this case, the first power line 31 and the second power line 32 can also not be shared in the two storage cells 100, that is, the first power line 31 and the second power line 32 connected to different storage cells 100 are independent of each other.

[0107] In one embodiment of this application, the structures of two adjacent memory cells 100 along the first direction F1 are symmetrical, which can optimize the layout, simplify the design, improve reliability, and reduce manufacturing costs. Exemplarily, the structures of two adjacent memory cells 100 along the first direction F1 can be mirror-symmetrical about the axis of symmetry along the second direction F2. In other embodiments of this application, the structures of two adjacent memory cells 100 along the first direction F1 can also be identical, that is, the structure of one memory cell 100 is translated along the first direction F1 to form the structure of the other memory cell 100.

[0108] In one embodiment of this application, during the fabrication process, a front-end of-line (FEOL) process can be used to form the structure of each FET in the memory cell, and a back-end of-line (BEOL) process can be used to realize the metal interconnection, ultimately forming a complete memory array structure on the substrate. The structures of each FET in the memory cell include, but are not limited to, Gate All Around (GAA) FETs, planar FETs, dual-gate FETs, and fin FETs. The following description uses a GAA FET as an example to illustrate the structure of the memory array in this embodiment.

[0109] Reference Figures 6 to 8E The memory array includes a semiconductor device layer 20 located on a substrate 10. A first access FET MA1, a second access FET MA2, a first pull-up FET MP1, a second pull-up FET MP2, a first pull-down FET MN1, and a second pull-down FET MN2 are located on the semiconductor device layer 20. It is understood that, to clearly illustrate the structure of each FET in the memory cell 100 in this embodiment, when illustrating each FET as a GAAFET, a gate dielectric layer 21 is also present between the gate and the CNT in each FET.

[0110] For example, to improve the driving capability of each FET in the memory cell 100, the widths of the channels of the first access FET MA1, the second access FET MA2, the first pull-down FET MN1, and the second pull-down FET MN2 are respectively greater than the widths of the channels of the first pull-up FET MP1 and the second pull-up FET MP2. For example, the widths of the channels of the first access FET MA1, the second access FET MA2, the first pull-down FET MN1, and the second pull-down FET MN2 are the same, and the widths of the channels of the first pull-up FET MP1 and the second pull-up FET MP2 are the same. It is understood that the width of the channel of each FET can be the width of the channel in its gate coverage region in the second direction F2.

[0111] For example, the channel width can be adjusted by changing the number of CNTs in the channel of the FET; that is, a larger channel width results in a larger number of CNTs, and a smaller channel width results in a smaller number of CNTs. For example, refer to... Figure 6 and Figure 7AThe number of CNTs in the first access FETMA1, the number of CNTs in the second access FETMA2, the number of CNTs in the first pull-down FETMN1, and the number of CNTs in the second pull-down FETMN2 are all greater than the number of CNTs in the first pull-up FETMP1 and the number of CNTs in the second pull-up FETMP2. For example, the number of CNTs in the first access FETMA1, the number of CNTs in the second access FETMA2, the number of CNTs in the first pull-down FETMN1, and the number of CNTs in the second pull-down FETMN2 are the same, and the number of CNTs in the first pull-up FETMP1 and the number of CNTs in the second pull-up FETMP2 are the same.

[0112] It is understood that the similarities described in the embodiments of this application are those within the allowable error range, and repeated details will not be elaborated upon. Furthermore, in order to clearly demonstrate the structure of the CNT in the embodiments of this application, Figure 6 and Figure 7A The following diagram illustrates a single-layer CNT structure. In a single-layer CNT structure, there can be one or more CNTs. When there are multiple CNTs, they can be arranged in an array, a grid, or other feasible arrangements; the specific arrangement is not limited here. Furthermore, the exact number of CNTs can be flexibly designed according to the needs of the actual application scenario; this is also not limited here.

[0113] In one embodiment of this application, reference is made to... Figure 6 , Figure 7B , Figures 8A to 8D The memory array further includes a first dielectric layer 11 located on the side of the semiconductor device layer 20 facing away from the substrate 10 and a first wiring layer 30 located on the side of the first dielectric layer 11 facing away from the substrate 10. A first power line 31 and a second power line 32 may be located on the first wiring layer 30. Furthermore, to achieve electrical connection between the first power line 31 and the first pull-up FETMP1 and the second pull-up FETMP2, exemplarily, referring to… Figure 6 , Figure 7B , Figure 7C , Figures 8A to 8D The memory array further includes: a second dielectric layer 12 located on the side of the first wiring layer 30 facing away from the substrate 10, and a second wiring layer 40 located on the side of the second dielectric layer 12 facing away from the substrate 10. The second wiring layer 40 may include a first power interconnect 43. The first power line 31 is connected to the first power interconnect 43 through a first power contact hole CC1. The first power interconnect 43 is connected to the second portion region 211b of the channel of the first pull-up FETMP1 through a second power contact hole CC2. P1 The second part of the channel 211b of CNT and the second pull-up FETMP2 P2 CNT connection in the second part of region 211b P1The CNT in the first pull-up FETMP1 can be used as the second electrode, and the second part of region 211b P2 The CNT in the first power line 31 can be used as the second pole of the second pull-up FETMP2 to achieve electrical connection between the first power line 31 and the first pull-up FETMP1 and the second pull-up FETMP2.

[0114] To achieve the electrical connection between the second power line 32 and the first pull-down FETMN1 and the second pull-down FETMN2, exemplarily, refer to... Figure 6 , Figure 7B , Figure 7C , Figure 8A and Figure 8B The second wiring layer 40 may include a second power interconnect 44, the second power line 32 is connected to the second power interconnect 44 through a third power contact hole CC3, and the second power interconnect 44 is connected to the second portion region 211b of the channel of the first pull-down FETMN1 through a fourth power contact hole CC4. N1 The second part of the channel 211b of CNT and the second pull-down FETMN2 N2 CNT connection in the second part of region 211b N1 The CNT in the middle can serve as the second electrode of the first pull-down FETMN1, and the second part of region 211b N2 The CNT in the second pull-down FETMN2 can be used as the second terminal of the second pull-down FETMN2 to realize the electrical connection between the second power line 32 and the first pull-down FETMN1 and the second pull-down FETMN2.

[0115] Furthermore, the first power contact hole CC1 and the third power contact hole CC3 penetrate the second dielectric layer 12, and the second power contact hole CC2 and the fourth power contact hole CC4 penetrate the second dielectric layer 12 and the first dielectric layer 11. Exemplarily, during fabrication, conductive material can be filled into the first power contact hole CC1 to the fourth power contact hole CC4 to form a conductive portion, thereby achieving electrical connection. Exemplarily, this conductive portion can be a single-layer or multi-layer conductive film structure. For example, a single-layer conductive film structure can be a metallic material, and a multi-layer conductive film structure includes a combination structure of metal nitrides and metals, such as TiN / Cu, TaN / Cu, etc. It is understood that the conductive portions described below can be formed similarly, and repeated details will not be elaborated further.

[0116] For example, refer to Figure 6 , Figure 7A , Figure 8C and Figure 8D In any memory cell 100, the CNT of the first pull-up FETMP1 and the CNT of the second pull-up FETMP2 can be shared, therefore the second part of region 211b P1 CNT and the second part of region 211bP2 The CNTs in the memory cells are interconnected. This not only shortens the interconnect length between the two P-type FETs, reducing parasitic capacitance and resistance, and reducing signal transmission delay, but also optimizes the memory cell layout and reduces wiring complexity.

[0117] For example, refer to Figure 6 , Figure 7A , Figure 8A and Figure 8B In any memory cell 100, the CNT of the first pull-down FETMN1 and the CNT of the second pull-down FETMN2 can be shared, therefore the second part of region 211b N1 CNT and the second part of region 211b N2 The CNTs in the memory cells are interconnected. This not only shortens the interconnect length between the two N-type FETs, reducing parasitic capacitance and resistance, and signal transmission delay, but also optimizes memory cell layout and reduces wiring complexity.

[0118] For example, when the first group of adjacent storage cells 100 share a first power line 31, the first group of adjacent storage cells 100 may also share a first power interconnect 43. When the second group of adjacent storage cells 100 share a second power line 32, the second group of adjacent storage cells 100 may also share a second power interconnect 44. This further optimizes the storage cell layout and reduces wiring complexity.

[0119] In one embodiment of this application, reference is made to... Figure 6 and Figure 7C The first terminals of the first pull-up FETMP1, the first terminals of the first pull-down FETMN1, and the first terminal of the first access FETMA1 are connected through the first electrode interconnect 41, thereby realizing the electrical connection between the first terminals of the first pull-up FETMP1, the first terminals of the first pull-down FETMN1, and the first terminals of the first access FETMA1, and achieving signal transmission. For example, refer to... Figure 6 , Figure 7C , Figure 8A and Figure 8C The first electrode interconnect 41 passes through the first electrode contact hole CA1 and the first portion region 211a of the channel of the first pull-up FETMP1. P1 In the CNT connection, the first electrode interconnect 41 is also connected to the first portion region 211a of the channel of the first pull-down FET MN1 through the second electrode contact hole CA2. N1 The first portion of the channel 211a of the CNT and the first access FETMA1 is located in the CNT. A1 The CNT connection in the middle. Among them, the first part region 211a P1The CNT in the first region can be used as the first electrode of the first pull-up FETMP1, and the first part of region 211a N1 The CNT in the first pull-down FETMN1 can be used as the first electrode, the first part of region 211a A1 The CNT in the circuit can be used as the first electrode of the first access FETMA1, thus enabling them to be electrically connected to each other and realize signal transmission.

[0120] For example, refer to Figure 6 , Figure 7A and Figure 8A In any memory cell 100, the CNT of the first access FETMA1 and the CNT of the first pull-down FETMN1 can be shared, therefore the first part of region 211a A1 CNT and the first part of region 211a N1 The CNTs in the memory cells are interconnected. This not only shortens the interconnect length between the two N-type FETs, reducing parasitic capacitance and resistance, and signal transmission delay, but also optimizes memory cell layout and reduces wiring complexity.

[0121] In one embodiment of this application, reference is made to... Figure 6 and Figure 7C The first terminals of the second access FETMA2, the second pull-up FETMP2, and the second pull-down FETMN2 are connected via the second electrode interconnect 42, thereby achieving electrical connection between the first terminals of the second access FETMA2, the second pull-up FETMP2, and the second pull-down FETMN2, and realizing signal transmission. For example, refer to... Figure 6 , Figure 7C , Figure 8B and Figure 8D The second electrode interconnect 42 passes through the third electrode contact hole CA3 and the first portion region 211a of the channel of the second pull-up FETMP2. P2 The CNT connection in the middle, the second electrode interconnect 42 also connects to the first part region 211a of the channel of the second pull-down FET MN2 through the fourth electrode contact hole CA4. N2 The first portion of the channel 211a of the CNT and the second access FETMA2 in the CNT. A2 The CNT connection in the middle. Among them, the first part region 211a P2 The CNT in the first part can be used as the first electrode of the second pull-up FETMP2, the first part region 211a N2 The CNT in the middle can be used as the first electrode of the second pull-down FETMN2, in the first part of region 211a A2 The CNT in the circuit can serve as the first electrode of the second access FETMA2, thus enabling them to be electrically connected to each other and transmit signals.

[0122] For example, refer to Figure 6 , Figure 7A and Figure 8B In any memory cell 100, the CNT of the second access FETMA2 and the CNT of the second pull-down FETMN2 can be shared, therefore the first part of region 211a A2 CNT and the first part of region 211a N2 The CNTs in the memory cells are interconnected. This not only shortens the interconnect length between the two N-type FETs, reducing parasitic capacitance and resistance, and signal transmission delay, but also optimizes memory cell layout and reduces wiring complexity.

[0123] For example, refer to Figure 6 and Figure 7A In any memory cell 100, the CNTs of the first access FETMA1, the first pull-down FETMN1, the second access FETMA2, and the second pull-down FETMN2 can be shared, which can optimize the memory cell layout. For example, multiple CNTs of the first access FETMA1, multiple CNTs of the first pull-down FETMN1, multiple CNTs of the second access FETMA2, and multiple CNTs of the second pull-down FETMN2 arranged along the first direction F1 can be shared, which can further optimize the memory cell layout.

[0124] For example, refer to Figure 6 and Figure 7C The first electrode interconnect 41 and the second electrode interconnect 42 extend along the second direction F2, that is, the first electrode interconnect 41, the second electrode interconnect 42, the first bit line BL1, and the second bit line BL2 extend in the same direction to avoid short circuits. Furthermore, the first electrode interconnect 41 and the second electrode interconnect 42 are arranged along the first direction F1. For example, the orthogonal projection of the first electrode interconnect 41 onto the substrate 10 is located at the gate 212 of the first pull-down FET MN1. N1 The orthogonal projection of substrate 10 and the gate 212 of the first access FET MA1 A1 Between the orthogonal projections of the substrate 10. Furthermore, the orthogonal projection of the second electrode interconnect 42 onto the substrate 10 lies at the gate 212 of the second pull-down FET MN2. N2 The orthogonal projection of substrate 10 and the gate 212 of the second access FET MA2 A2 Between the orthographic projections of substrate 10.

[0125] For example, refer to Figure 6 , Figure 7C , Figures 8A to 8DThe first electrode interconnect 41 and the second electrode interconnect 42 can be located in the second wiring layer 40, and the first electrode contact holes CA1 to the fourth electrode contact holes CA4 all penetrate the first dielectric layer 11 and the second dielectric layer 12. Alternatively, the first electrode interconnect 41 and the second electrode interconnect 42 can also be located in the first wiring layer 30, and the first electrode contact holes CA1 to the fourth electrode contact holes CA4 all penetrate the first dielectric layer 11. Furthermore, during the fabrication process, conductive material can be filled into the first electrode contact holes CA1 to the fourth electrode contact holes CA4 to form conductive portions, thereby achieving electrical connection.

[0126] In one embodiment of this application, reference is made to... Figure 6 and Figure 7C The first electrode interconnect 41 is connected to the gate 212 of the second pull-up FET MP2 via the third electrode interconnect 45. P2 Gate 212 of the second pull-down FETMN2 N2 The interconnections are interconnected to electrically connect the first terminal of the first pull-up FETMP1, the first terminal of the first pull-down FETMN1, the first terminal of the first access FETMA1, the gate of the second pull-up FETMP2, and the gate of the second pull-down FETMN2, thereby enabling signal transmission. Exemplarily, the third electrode interconnect 45 can be located in the second wiring layer 40. For example, the third electrode interconnect 45 is an integral structure with the first electrode interconnect 41. The third electrode interconnect 45 is also connected to the gate 212 of the second pull-up FETMP2 through the fifth electrode contact hole CA5. P2 Gate 212 of the second pull-down FETMN2 N2 The fifth electrode contact hole CA5 connects to the first dielectric layer 11 and the second dielectric layer 12. Alternatively, the third electrode interconnect 45 can also be located in the first wiring layer 30.

[0127] In one embodiment of this application, reference is made to... Figure 6 and Figure 7C The second electrode interconnect 42 is connected to the gate 212 of the first pull-up FET MP1 via the fourth electrode interconnect 46. P1 and the gate 212 of the first pull-down FET MN1 N1 The interconnections are interconnected to electrically connect the first terminals of the second pull-up FETMP2, the second pull-down FETMN2, the second access FETMA2, the gate of the first pull-up FETMP1, and the gate of the first pull-down FETMN1, thereby enabling signal transmission. Exemplarily, the fourth electrode interconnect 46 can be located in the second wiring layer 40. For example, the fourth electrode interconnect 46 and the second electrode interconnect 42 are integrally structured. The fourth electrode interconnect 46 is also connected to the gate 212 of the first pull-up FETMP1 via the sixth electrode contact hole CA6. P1 and the gate 212 of the first pull-down FET MN1N1 The sixth electrode contact hole CA6 connects through the first dielectric layer 11 and the second dielectric layer 12. Alternatively, the fourth electrode interconnect 46 can also be located in the first wiring layer 30.

[0128] For example, the third electrode interconnect 45 and the fourth electrode interconnect 46 extend along the first direction F1, facilitating wiring and layout design. Furthermore, during fabrication, conductive material can be filled into the fifth electrode contact hole CA5 and the sixth electrode contact hole CA6 to form conductive portions, thereby achieving electrical connection.

[0129] For example, refer to Figure 6 The orthographic projection of WL onto substrate 10 lies between the orthographic projections of the third electrode interconnect 45 and the fourth electrode interconnect 46 onto substrate 10, which can further optimize the word line routing and layout. Alternatively, the orthographic projection of WL onto substrate 10 may overlap with the orthographic projections of the third electrode interconnect 45 and the fourth electrode interconnect 46 onto substrate 10, respectively, which can also optimize the layout and reduce the occupied area of ​​the memory array.

[0130] In one embodiment of this application, reference is made to... Figure 6 , Figure 7C , Figures 8A to 8D The first line BL1 can be located in the second wiring layer 40. Specifically, the first line BL1 connects to the second portion region 211b of the channel of the first access FETMA1 via the first line contact hole CB1. A1 CNT connection in the second part of region 211b A1 The CNT in the first access FETMA1 serves as the second electrode, thereby achieving an electrical connection between the first bit line BL1 and the CNT of the first access FETMA1.

[0131] In one embodiment of this application, reference is made to... Figure 6 , Figure 7C , Figures 8A to 8D The second bit line BL2 can be located in the second wiring layer 40, and the second bit line BL2 passes through the second bit line contact hole CB2 and the second portion region 211b of the channel of the second access FETMA2. A2 CNT connection in the second part of region 211b A2 The CNT in the second access FETMA2 serves as the second pole, thereby enabling the connection between the second bit line BL2 and the CNT of the second access FETMA2.

[0132] For example, refer to Figure 6 and Figure 7CIn any memory cell 100, the orthographic projections of the first electrode interconnect 41, the second electrode interconnect 42, the third electrode interconnect 45, the fourth electrode interconnect 46, the first power interconnect 43, and the second power interconnect 44 on the substrate 10 are located between the orthographic projections of the first bit line BL1 connected to the memory cell 100 on the substrate 10 and the second bit line BL2 connected to the memory cell 100 on the substrate 10.

[0133] In one embodiment of this application, reference is made to... Figure 6 , Figure 7D , Figures 8A to 8E The memory array also includes a third dielectric layer 13 located on the side of the second wiring layer 40 facing away from the substrate 10, and a third wiring layer 50 located on the side of the third dielectric layer 13 facing away from the substrate 10. The bit line WL can be located on the third wiring layer 50. Therefore, the layers containing the first bit line BL1 and the second bit line BL2 can be different from the layer containing WL, and WL can be interleaved with the first bit line BL1 and the second bit line BL2. This simplifies addressing, improves integration density, reduces wiring length, enhances stability, optimizes read / write speed, reduces power consumption, and simplifies manufacturing processes. Alternatively, WL can also be located on the first wiring layer 30, thereby saving one wiring layer process and improving production efficiency.

[0134] For example, refer to Figure 6 , Figure 7D , Figure 8E WL is connected to the first word line interconnect 47 through the first word line contact hole CD1, and the first word line interconnect 47 is connected to the gate 212 of the first access FETMA1 through the second word line contact hole CD2. A1 In addition, WL is also connected to the second word line interconnect 48 via the third word line contact hole CD3, and the second word line interconnect 48 is connected to the gate 212 of the second access FETMA2 via the fourth word line contact hole CD4. A2 Connection. Thus, WL can be connected to the gate 212 of the first access FETMA1. A1 Second access FETMA2 gate 212 A2 Electrical connection between them.

[0135] For example, the first word line interconnect 47 and the second word line interconnect 48 are located in the second wiring layer 40, the first word line contact hole CD1 and the third word line contact hole CD3 both penetrate the third dielectric layer 13, and the second word line contact hole CD2 and the fourth word line contact hole CD4 both penetrate the first dielectric layer 11 and the second dielectric layer 12. Alternatively, the first word line interconnect 47 and the second word line interconnect 48 are located in the first wiring layer 30, the first word line contact hole CD1 and the third word line contact hole CD3 both penetrate the third dielectric layer 13 and the second dielectric layer 12, and the second word line contact hole CD2 and the fourth word line contact hole CD4 both penetrate the first dielectric layer 11. Alternatively, WL is directly connected to the gate of the first access FETMA1 through the fifth word line contact hole, and WL is directly connected to the gate of the second access FETMA2 through the sixth word line contact hole, then the fifth word line contact hole and the sixth word line contact hole both penetrate the first dielectric layer 11, the second dielectric layer 12 and the third dielectric layer 13. For example, during the manufacturing process, conductive material can be filled into the first letter contact hole CD1 to the sixth letter contact hole to form a conductive part to achieve electrical connection.

[0136] For example, refer to Figure 6 , Figures 7B to 7D The shapes of the first power line 31, the second power line 32, the first bit line BL1, the second bit line BL2, and WL are all linear, which can simplify design and manufacturing, reduce parasitic effects, optimize layout density, improve read and write speed, reduce power consumption, enhance reliability and stability, and facilitate expansion and optimization.

[0137] Figure 9 This is a top view schematic diagram of another storage array structure in the embodiments of this application. Figure 10A for Figure 9 A top view of the semiconductor device layer in the diagram. Figure 10B for Figure 9 A top view of the first wiring layer in the diagram. Figure 10C for Figure 9 A top view of the second wiring layer in the diagram. Figure 10D for Figure 9 A top view of the third wiring layer in the diagram. Figure 11A for Figure 9 A schematic diagram of the cross-sectional structure along the AA' direction. Figure 11B for Figure 9 A schematic diagram of the cross-sectional structure along the BB' direction. Figure 11C for Figure 9 A schematic cross-sectional view of the structure along the CC' direction. (Refer to...) Figures 9 to 11CThe memory array includes a semiconductor device layer 20, a first dielectric layer 11, a first wiring layer 30, a second dielectric layer 12, a second wiring layer 40, a third dielectric layer 13, and a third wiring layer 50. Each FET in the memory cell is located on the semiconductor device layer 20. The first power line 31 and the second power line 32 are located on the first wiring layer 30. The first bit line BL1, the second bit line BL2, the first electrode interconnect 41, the second electrode interconnect 42, the first power interconnects 43a and 43b, and the second power interconnects 44a and 44b are located on the second wiring layer 40. The WL is located on the third wiring layer 50. Furthermore, this embodiment is aimed at… Figure 6 The embodiments shown have been modified. The differences between this embodiment and the above embodiments will only be described below; the similarities will not be repeated here.

[0138] In yet another embodiment of this application, reference is made to... Figure 9 and Figure 10A This changes the arrangement of FETs in the memory cell 100. For example, in any memory cell 100, the first access FET MA1, the first pull-down FET MN1, and the first pull-up FET MP1 are arranged along the second direction F2. This allows for a more regular layout of the FETs in any memory cell 100, making full use of space and reducing design complexity. Furthermore, based on this arrangement, the first part of the FETs can include the first pull-up FET MP1 and the first pull-down FET MN1. That is, the orthogonal projections of the CNTs of the first pull-up FET MP1 and the first pull-down FET MN1 on the substrate 10 overlap with the orthogonal projection of the first bit line BL1 on the substrate 10, thereby further optimizing the wiring and layout.

[0139] For example, refer to Figure 9 and Figure 10A In any memory cell 100, in the second direction F2, the first pull-down FETMN1 is located between the first access FETMA1 and the first pull-up FETMP1. For example, in any memory cell 100, the orthographic projection of the CNT of the first pull-down FETMN1 onto the substrate 10 is located between the orthographic projection of the CNT of the first access FETMA1 onto the substrate 10 and the orthographic projection of the CNT of the first pull-up FETMP1 onto the substrate 10, which can further optimize the layout.

[0140] For example, refer to Figure 9 and Figure 10A In any memory cell 100, the gate 212 of the first access FETMA1 A1 Gate 212 of the first pull-down FETMN1 N1 and the gate 212 of the first pull-up FETMP1 P1 Arranging along the second direction F2 can further optimize the map layout.

[0141] For example, refer to Figure 9 and Figure 10A In any memory cell 100, the gate 212 of the first pull-down FETMN1 N1 and the gate 212 of the first pull-up FETMP1 P1 It is a single integrated structure. This allows the gate 212 of the first pull-down FET MN1 to be integrated. N1 With the gate 212 of the first pull-up FETMP1 P1 Direct electrical connection shortens the signal transmission path and reduces latency. Furthermore, the gate 212 of the first pull-down FET MN1 can be fabricated using the same process. N1 With the gate 212 of the first pull-up FETMP1 P1 This simplifies the manufacturing process. In other embodiments of this application, the gate 212 of the first pull-up FETMP1... P1 With the gate 212 of the first pull-down FET MN1 N1 They can also be independent and connected at points through the connection lines of other wiring layers.

[0142] In yet another embodiment of this application, reference is made to... Figure 9 and Figure 10A In any memory cell 100, the second access FET MA2, the second pull-down FET MN2, and the second pull-up FET MP2 are arranged along the second direction F2. This allows for a more regular layout of the FETs in any memory cell 100, making full use of space and reducing design complexity. Furthermore, based on this arrangement, the second part of the FETs can include the second pull-up FET MP2 and the second pull-down FET MN2. That is, the orthographic projection of the CNT of the second pull-up FET MP2 onto the substrate 10 and the orthographic projection of the CNT of the second pull-down FET MN2 onto the substrate 10 overlap with the orthographic projection of the second bit line BL2 onto the substrate 10, thereby further optimizing wiring and layout.

[0143] For example, refer to Figure 9 and Figure 10A In any memory cell 100, in the second direction F2, the second pull-down FETMN2 is located between the second access FETMA2 and the second pull-up FETMP2. For example, in any memory cell 100, the orthogonal projection of the CNT of the second pull-down FETMN2 onto the substrate 10 is located between the orthogonal projection of the CNT of the second access FETMA2 onto the substrate 10 and the orthogonal projection of the CNT of the second pull-up FETMP2 onto the substrate 10, which can further optimize the layout.

[0144] For example, refer to Figure 9 and Figure 10AIn any memory cell 100, the gate 212 of the second access FETMA2 A2 Gate 212 of the second pull-down FETMN2 N2 Gate 212 of the second pull-up FETMP2 P2 Arranging along the second direction F2 can further optimize the map layout.

[0145] For example, refer to Figure 9 and Figure 10A In any memory cell 100, the gate 212 of the second pull-down FET MN2 N2 Gate 212 of the second pull-up FETMP2 P2 It is a single integrated structure. This allows the gate 212 of the second pull-down FET MN2 to be integrated. N2 With the gate 212 of the second pull-up FETMP2 P2 Direct electrical connection shortens the signal transmission path and reduces latency. Furthermore, the gate 212 of the second pull-down FET MN2 can be fabricated using the same process. N2 With the gate 212 of the second pull-up FETMP2 P2 This simplifies the manufacturing process. In other embodiments of this application, the gate 212 of the second pull-up FETMP2... P2 With the gate 212 of the second pull-down FETMN2 N2 They can also be independent and connected at points through the connection lines of other wiring layers.

[0146] In yet another embodiment of this application, reference is made to... Figure 9 and Figure 10A In any memory cell 100, the first access FETMA1 and the second access FETMA2 are arranged along the first direction F1, and the CNTs of the first access FETMA1 and the second access FETMA2 are independent of each other. That is, during the fabrication process, the long strip CNTs are etched to obtain the channels of the first access FETMA1 and the second access FETMA2 in the same memory cell, so that the CNTs of the first access FETMA1 and the second access FETMA2 are not directly connected.

[0147] For example, refer to Figure 9 and Figure 10A In the plurality of memory cells 100 arranged along the first direction F1, the CNT of the first access FETMA1 and the CNT of the second access FETMA2 are also independent of each other. That is, during the fabrication process, the long strip CNT is etched to obtain the channels of the first access FETMA1 and the second access FETMA2 in the plurality of memory cells, so that the plurality of CNTs of the first access FETMA1 and the second access FETMA2 are not directly connected.

[0148] In yet another embodiment of this application, reference is made to... Figure 9 and Figure 10A In any memory cell 100, the first pull-down FETMN1 and the second pull-down FETMN2 are arranged along the first direction F1, and the CNTs of the first pull-down FETMN1 and the second pull-down FETMN2 are independent of each other. That is, during the fabrication process, the elongated CNTs are etched to obtain the channels of the first pull-down FETMN1 and the second pull-down FETMN2, so that the CNTs of the first pull-down FETMN1 and the second pull-down FETMN2 are not directly connected.

[0149] For example, refer to Figure 9 and Figure 10A In the case where the structures of two adjacent memory cells 100 along the first direction F1 are symmetrical, the CNTs of the first pull-down FETMN1 and the first pull-up FETMP1 in some adjacent memory cells can be shared, and the CNTs of the second pull-down FETMN2 and the second pull-up FETMP2 in other adjacent memory cells can be shared. In other embodiments of this application, in any two adjacent memory cells 100 along the first direction F1, the CNTs of the first pull-down FETMN1, the first pull-up FETMP1, the second pull-down FETMN2, and the second pull-up FETMP2 can also be made independent of each other and not shared.

[0150] In yet another embodiment of this application, reference is made to... Figure 9 and Figure 10A In any memory cell 100, the first pull-up FETMP1 and the second pull-up FETMP2 are arranged along the first direction F1, and the CNTs of the first pull-up FETMP1 and the second pull-up FETMP2 are independent of each other. That is, during the fabrication process, the elongated CNTs are etched to obtain the channels of the first pull-up FETMP1 and the second pull-up FETMP2, so that the CNTs of the first pull-up FETMP1 and the second pull-up FETMP2 are not directly connected.

[0151] For example, to improve the driving capability of each FET in the memory cell 100, the width of the channel of the first access FET MA1 and the width of the channel of the second access FET MA2 are greater than the width of the channel of the first pull-down FET MN1 and the width of the channel of the second pull-down FET MN2, and the width of the channel of the first pull-down FET MN1 and the width of the channel of the second pull-up FET MN2 are respectively greater than the width of the channel of the first pull-up FET MP1 and the width of the channel of the second pull-up FET MP2. For example, the width of the channel of the first access FET MA1 and the width of the channel of the second access FET MA2 are the same, the width of the channel of the first pull-down FET MN1 and the width of the channel of the second pull-down FET MN2 are the same, and the width of the channel of the first pull-up FET MP1 and the width of the channel of the second pull-up FET MP2 are the same. It is understood that the width of the channel of each FET can be the width of the channel in its gate coverage region in the second direction F2.

[0152] For example, the channel width can be adjusted by changing the number of CNTs in the channel; that is, a FET with a wider channel has a larger number of CNTs, and a FET with a narrower channel has a smaller number of CNTs. For example, refer to... Figure 9 The number of CNTs in the first access FETMA1 and the number of CNTs in the second access FETMA2 are greater than the number of CNTs in the first pull-down FETMN1 and the second pull-down FETMN2. The number of CNTs in the first pull-down FETMN1 and the second pull-down FETMN2 are also greater than the number of CNTs in the first pull-up FETMP1 and the second pull-up FETMP2. For example, the number of CNTs in the first access FETMA1 and the second access FETMA2 are the same, the number of CNTs in the first pull-down FETMN1 and the second pull-down FETMN2 are the same, and the number of CNTs in the first pull-up FETMP1 and the second pull-up FETMP2 are the same.

[0153] In yet another embodiment of this application, reference is made to... Figure 9 , Figure 10A , Figure 10C , Figure 11B and Figure 11C The first electrode interconnect 41 passes through the first electrode contact hole CA1 and the first portion region 211a of the channel of the first pull-up FETMP1. P1 In the CNT connection, the first electrode interconnect 41 also connects to the first portion region 211a of the channel of the first pull-down FET MN1 through the second electrode contact hole CA2a. N1In the CNT connection, the first electrode interconnect 41 also connects to the first portion region 211a of the channel of the first access FETMA1 through the second electrode contact hole CA2b. A1 The CNTs in the circuit are connected to each other electrically to enable signal transmission.

[0154] For example, refer to Figure 9 and Figure 10A In any memory cell 100, the first electrode interconnect 41 is connected to the gate 212 of the second pull-up FET MP2 via the third electrode interconnect 45. P2 Gate 212 of the second pull-down FETMN2 N2 The interconnections are designed to electrically connect the first electrode of the first pull-up FETMP1, the first electrode of the first pull-down FETMN1, the first electrode of the first access FETMA1, the gate of the second pull-up FETMP2, and the gate of the second pull-down FETMN2, thereby enabling signal transmission. For example, for structures at some process nodes (e.g., earlier than 28nm), the area of ​​the memory cell 100 can be larger. Based on this, the third electrode interconnect 45 can be located in the semiconductor device layer. For example, the third electrode interconnect 45 is connected to the gate 212 of the second pull-up FETMP2. P2 Gate 212 of the second pull-down FETMN2 N2 It can be a single integrated structure. Alternatively, as process nodes shrink (e.g., later than 28nm), the area of ​​the memory cell 100 is further compressed, and based on this, the third electrode interconnect 45 can also be located in the first wiring layer 30 or the third wiring layer 50.

[0155] In yet another embodiment of this application, reference is made to... Figure 9 , Figure 10A , Figure 10C , Figure 11B and Figure 11C The second electrode interconnect 42 passes through the third electrode contact hole CA3 and the first portion region 211a of the channel of the second pull-up FETMP2. P2 The CNT connection in the second electrode interconnect 42 also connects to the first portion region 211a of the channel of the second pull-down FET MN2 through the fourth electrode contact hole CA4a. N2 The CNT connection in the second electrode interconnect 42 also connects to the first portion region 211a of the channel of the second access FETMA2 via the fourth electrode contact hole CA4b. A2 The CNTs in the circuit are connected to each other electrically to enable signal transmission.

[0156] For example, refer to Figure 9 and Figure 10A In any memory cell, the second electrode interconnect 42 is connected to the gate 212 of the first pull-up FET MP1 via the fourth electrode interconnect 46.P1 and the gate 212 of the first pull-down FET MN1 N1 The interconnections are configured to electrically connect the first terminals of the second pull-up FETMP2, the second pull-down FETMN2, the second access FETMA2, the gate of the first pull-up FETMP1, and the gate of the first pull-down FETMN1, thereby enabling signal transmission. For example, for structures at some process nodes (e.g., earlier than 28nm), the area of ​​the memory cell 100 can be larger. Based on this, the fourth electrode interconnect 46 can be located in the semiconductor device layer 20. For example, the fourth electrode interconnect 46 is connected to the gate 212 of the first pull-up FETMP1. P1 and the gate 212 of the first pull-down FET MN1 N1 It can be a single integrated structure. Alternatively, as process nodes shrink (e.g., later than 28nm), the area of ​​the memory cell 100 is further compressed, and based on this, the fourth electrode interconnect 46 can also be located in the first wiring layer 30 or the third wiring layer 50.

[0157] For example, refer to Figure 9 , Figure 10A , Figure 10C , Figure 11B and Figure 11C The orthographic projection of the first electrode interconnect 41 onto the substrate 10 and the orthographic projection of the second electrode interconnect 42 onto the substrate 10 are respectively located at the gate 212 of the first pull-down FET MN1. N1 The orthogonal projection of substrate 10 and the gate 212 of the second pull-down FET MN2 N2 Between the orthographic projections of substrate 10.

[0158] It is understood that the second electrode contact holes CA2a and CA2b in this embodiment are basically the same as the second electrode contact hole CA2 in the above embodiment, and the fourth electrode contact holes CA4a and CA4b in this embodiment are basically the same as the fourth electrode contact hole CA4 in the above embodiment. The specific details will not be elaborated here.

[0159] In yet another embodiment of this application, reference is made to... Figure 9 The orthographic projection of WL onto substrate 10 is located on the side opposite to the orthographic projection of the first access FETMA1 onto substrate 10. Similarly, the orthographic projection of WL onto substrate 10 is located on the side opposite to the orthographic projection of the second access FETMA2 onto substrate 10. This allows for optimized routing and layout.

[0160] For example, refer to Figure 9 , Figure 10A , Figure 10D and Figure 11AWL directly connects to the gate 212 of the first access FETMA1 via the fifth word line contact hole CD5. A1 The connection is made directly through the sixth word line contact hole CD6 to the gate 212 of the second access FETMA2. A2 When connected, both the fifth digit contact hole CD5 and the sixth digit contact hole CD6 penetrate the first dielectric layer 11, the second dielectric layer 12, and the third dielectric layer 13. Other embodiments of this application may also refer to this. Figure 6 In the embodiment shown, by providing a first word line interconnect 47 and a second word line interconnect 48, WL is connected to the gate 212 of the first access FETMA1 via the first word line interconnect 47. A1 The connection, and the connection of WL to the gate 212 of the second access FETMA2 via the second word line interconnect 48. A2 The specific connection is not limited here.

[0161] In yet another embodiment of this application, reference is made to... Figure 9 The orthographic projection of the first power line 31 onto the substrate 10 is located on the side opposite to the orthographic projection of the first pull-up FETMP1 onto the substrate 10. Similarly, the orthographic projection of the first power line 31 onto the substrate 10 is located on the side opposite to the orthographic projection of the second pull-up FETMP2 onto the substrate 10. This optimizes wiring and layout. For example, in the case where the structures of two adjacent memory cells 100 along the second direction F2 are symmetrical, the first portion of adjacent memory cells 100 share a first power line 31, a first power interconnect 43a, and a first power interconnect 43b.

[0162] For example, refer to Figure 9 , Figures 10A to 10C , Figure 11B The first power line 31 is connected to the first power interconnect 43a through the first power contact hole CC1a, and the first power interconnect 43a is connected to the second part region 211b of the channel of the first pull-up FETMP1 through the second power contact hole CC2a. P1 The CNT connection is used to establish an electrical connection between the first power line 31 and the first pull-up FETMP1. Furthermore, the first power line 31 is also connected to the first power interconnect 43b via the first power contact hole CC1b, and the first power interconnect 43b is connected to the second portion region 211b of the channel of the second pull-up FETMP2 via the second power contact hole CC2b. P2 The CNT connection is used to establish an electrical connection between the first power line 31 and the second pull-up FETMP2.

[0163] For example, refer to Figure 9The orthogonal projection of the first power interconnect 43a onto the substrate 10 is located at the orthogonal projection of the first line BL1 onto the substrate 10 and the gate 212 of the first pull-up FET MP1. P1 Between the orthographic projections of substrate 10, the first power interconnect 43b is located in the orthographic projection of substrate 10, and the second bit line BL2 is located in the orthographic projection of substrate 10, and the gate 212 of the second pull-up FET MP2 is located in the second pull-up FET MP2. P2 Between the orthographic projections of substrate 10.

[0164] In yet another embodiment of this application, reference is made to... Figure 9 The orthographic projection of the second power line 32 onto the substrate 10 lies between the orthographic projections of the first access FET MA1 and the first pull-down FET MN1 onto the substrate 10. Similarly, the orthographic projection of the second power line 32 onto the substrate 10 lies between the orthographic projections of the second access FET MA2 and the second pull-down FET MN2 onto the substrate 10. This allows for optimized routing and layout.

[0165] For example, refer to Figure 9 , Figures 10A to 10C , Figure 11C The second power line 32 is connected to the second power interconnect 44a through the third power contact hole CC3a, and the second power interconnect 44a is connected to the second portion region 211b of the channel of the first pull-down FETMN1 through the fourth power contact hole CC4a. N1 The CNT connection is used to establish an electrical connection between the second power line 32 and the first pull-down FET MN1. Furthermore, the second power line 32 is also connected to the second power interconnect 44b via the third power contact hole CC3b, and the second power interconnect 44b is connected to the second portion region 211b of the channel of the second pull-down FET MN2 via the fourth power contact hole CC4b. N2 The CNT connection is used to establish an electrical connection between the second power line 32 and the second pull-down FETMN2.

[0166] For example, refer to Figure 9 The orthogonal projection of the second power interconnect 44a onto the substrate 10 is located at the orthogonal projection of the first line BL1 onto the substrate 10 and the gate 212 of the first pull-down FET MN1. N1 Between the orthographic projections of substrate 10, the second power interconnect 44b is located at the orthographic projection of the second bit line BL2 on substrate 10 and the gate 212 of the second pull-down FET MN2. N2 Between the orthographic projections of substrate 10.

[0167] For example, refer to Figure 9 and Figure 10CThe first power interconnects 43a and 43b and the second power interconnects 44a and 44b extend along the second direction F2, respectively. The first power interconnects 43a and 44a are arranged along the first direction F1, and the first power interconnects 43b and 44b are arranged along the first direction F1. For example, arranging the first power interconnects 43a and 44a along the second direction F2, and arranging the first power interconnects 43b and 44b along the second direction F2, can optimize wiring and reduce wiring design complexity.

[0168] Figure 12 This is a top view schematic diagram of another storage array structure in the embodiments of this application, referring to... Figure 12 The memory array includes a semiconductor device layer 20, a first dielectric layer 11, a first wiring layer 30, a second dielectric layer 12, a second wiring layer 40, a third dielectric layer 13, and a third wiring layer 50. Each FET in the memory cell 100 is located on the semiconductor device layer 20. The first power line 31 and the second power line 32 are located on the first wiring layer 30. The first bit line BL1, the second bit line BL2, the first electrode interconnect 41, the second electrode interconnect 42, the first power interconnects 43a and 43b, and the second power interconnects 44a and 44b are located on the second wiring layer 40. The WL is located on the third wiring layer 50. Furthermore, this embodiment is aimed at… Figure 9 The embodiments shown have been modified. The differences between this embodiment and the above embodiments will only be described below; the similarities will not be repeated here.

[0169] In yet another embodiment of this application, reference is made to... Figure 12 This changes the position of the second power line 32. The orthographic projection of the second power line 32 onto the substrate 10 is located on the side where the orthographic projection of WL onto the substrate 10 is opposite to the orthographic projection of the first access FETMA1 onto the substrate 10, which can further optimize the layout. For example, when the second power line 32 is located between adjacent memory cells 100 in the second portion, the adjacent memory cells 100 in the second portion can share one second power line 32, one second power interconnect 44a, and one second power interconnect 44b. This further simplifies wiring, saves memory array area, and improves integration density.

[0170] Figure 13 This is a top view schematic diagram of another storage array structure in the embodiments of this application. Figure 14A for Figure 13 A top view of the semiconductor device layer in the diagram. Figure 14B for Figure 13 A top view of the first wiring layer in the diagram. Figure 14C for Figure 13 A top view of the second wiring layer in the diagram. Figure 14Dfor Figure 13 A top view of the third wiring layer, see diagram below. Figures 13 to 14D The memory array includes a semiconductor device layer 20, a first dielectric layer 11, a first wiring layer 30, a second dielectric layer 12, a second wiring layer 40, a third dielectric layer 13, and a third wiring layer 50. Each FET in the memory cell 100 is located on the semiconductor device layer 20. The first power line 31 and the second power line 32 are located on the first wiring layer 30. The first bit line BL1, the second bit line BL2, the first electrode interconnect 41, the second electrode interconnect 42, the first power interconnect 43, and the second power interconnect 44 are located on the second wiring layer 40. The WL is located on the third wiring layer 50. Furthermore, this embodiment is aimed at… Figure 9 The embodiments shown have been modified. The differences between this embodiment and the above embodiments will only be described below; the similarities will not be repeated here.

[0171] In yet another embodiment of this application, reference is made to... Figure 13 and Figure 14A The positions of the first bit line BL1 and the second bit line BL2 were adjusted so that the orthographic projection of the first bit line BL1 onto the substrate 10 and the orthographic projection of the second bit line BL2 onto the substrate 10 are located between the orthographic projection of the gate of the first access FETMA1 onto the substrate 10 and the orthographic projection of the gate of the second access FETMA2 onto the substrate 10. This simplifies the wiring and optimizes the layout.

[0172] For example, refer to Figure 13 and Figure 14A It can be based on Figure 9 The first portion region 211a of the channel of the first access FETMA1 in the embodiment shown A1 Second part of region 211b A1 By swapping the positions, the first portion region 211a of the channel for the first access FETMA1 in this embodiment is obtained. A1 Second part of region 211b A1 For the implementation where the first access FETMA1 is connected to the first bit line BL1, refer to... Figure 9 The specific descriptions in the illustrated embodiments will not be repeated here.

[0173] Similarly, it can also be based on the following: Figure 9 The first portion region 211a of the channel of the second access FETMA2 in the illustrated embodiment A2 Second part of region 211b A2 By swapping the positions, the first portion region 211a of the channel for the second access FETMA2 in this embodiment is obtained. A2 Second part of region 211b A2For the implementation of connecting the second access FETMA2 and the second bit line BL2, refer to the following: Figure 9 The specific descriptions in the illustrated embodiments will not be repeated here.

[0174] In yet another embodiment of this application, reference is made to... Figure 13 and Figure 14A In any memory cell 100, the CNT of the first pull-down FETMN1 and the CNT of the second pull-down FETMN2 are shared. Furthermore, the CNTs of the first pull-down FETMN1 and the second pull-down FETMN2 in two adjacent memory cells along the first direction F1 are not shared. For example, in any memory cell 100, the second portion region 211b of the channel of the first pull-down FETMN1... N1 The second portion region 211b of the channel between the orthogonal projection of substrate 10 and the second pull-down FET MN2. N2 In the orthogonal projection of substrate 10, the gate 212 of the first pull-down FET MN1 is located. N1 The orthogonal projection of substrate 10 and the gate 212 of the second pull-down FET MN2 N2 Between the orthogonal projections of substrate 10, and the second portion region 211b of the channel of the first pull-down FET MN1. N1 The second part of the channel 211b of the CNT and the second pull-down FETMN2 is connected. N2 If the CNTs in the circuit can be directly interconnected, then the first pull-down FETMN1 and the second pull-down FETMN2 can share the second power interconnect 44. Furthermore, in this embodiment, the way the first pull-down FETMN1 and the second pull-down FETMN2 are connected to the second power line 32 via the second power interconnect 44 can be referred to... Figure 6 The descriptions in the illustrated embodiments will not be repeated here.

[0175] For example, refer to Figure 13 and Figure 14C The orthographic projection of the first bit line BL1 onto the substrate 10 and the orthographic projection of the second bit line BL2 onto the substrate 10 are located between the orthographic projections of the first electrode interconnect 41 onto the substrate 10 and the second electrode interconnect 42 onto the substrate 10. Furthermore, the orthographic projections of the first bit line BL1 and the second bit line BL2 onto the substrate 10 overlap with the orthographic projections of the third electrode interconnect 45 and the fourth electrode interconnect 46 onto the substrate 10, respectively.

[0176] For example, refer to Figure 13 and Figure 14A It can be based on Figure 9 The first portion region 211a of the channel of the first pull-down FETMN1 in the embodiment shown N1 Second part of region 211bN1 By swapping the positions, the first portion region 211a of the channel of the first pull-down FETMN1 in this embodiment is obtained. N1 Second part of region 211b N1 For the embodiment where the first pull-down FETMN1 is connected to the first electrode interconnect 41, please refer to... Figure 9 The descriptions in the illustrated embodiments will not be repeated here.

[0177] Similarly, it can also be based on the following: Figure 9 The first portion region 211a of the channel of the second pull-down FETMN2 in the embodiment shown N2 Second part of region 211b N2 By swapping the positions, the first portion region 211a of the channel of the second pull-down FETMN2 in this embodiment is obtained. N2 Second part of region 211b N2 For the implementation where the second pull-down FETMN2 is connected to the second electrode interconnect 42, please refer to... Figure 9 The descriptions in the illustrated embodiments will not be repeated here.

[0178] In yet another embodiment of this application, reference is made to... Figure 13 and Figure 14A In any memory cell 100, the CNT of the first pull-up FETMP1 and the CNT of the second pull-up FETMP2 are shared. Furthermore, the CNTs of the first pull-up FETMP1 and the second pull-up FETMP2 in two adjacent memory cells along the first direction F1 are not shared. Exemplarily, in any memory cell 100, the second portion region 211b of the channel of the first pull-up FETMP1... P1 The second portion region 211b of the channel of the second pull-up FET MP2 is projected onto the substrate 10. P2 In the orthogonal projection of substrate 10, the gate 212 of the first pull-up FETMP1 is located. P1 The orthogonal projection of substrate 10 and the gate 212 of the second pull-up FET MP2 P2 Between the orthographic projections of substrate 10, and the second portion region 211b of the channel of the first pull-up FETMP1 P1 The second part of the channel 211b of CNT and the second pull-up FETMP2 is connected. P2 If the CNTs in the circuit can be directly interconnected, then the first pull-up FETMP1 and the second pull-up FETMP2 can share the first power interconnect 43. Furthermore, in this embodiment, the way the first pull-up FETMP1 and the second pull-up FETMP2 are connected to the first power line 31 via the first power interconnect 43 can be referred to... Figure 6 The descriptions in the illustrated embodiments will not be repeated here.

[0179] For example, refer to Figure 13 and Figure 14A It can be based on Figure 9 The first portion region 211a of the channel of the first pull-up FETMP1 in the embodiment shown P1 Second part of region 211b P1 By swapping the positions, the first portion region 211a of the channel of the first pull-up FETMP1 in this embodiment is obtained. P1 Second part of region 211b P1 For the embodiment where the first pull-up FETMP1 is connected to the first electrode interconnect 41, please refer to... Figure 9 The descriptions in the illustrated embodiments will not be repeated here.

[0180] Similarly, it can also be based on the following: Figure 9 The first portion region 211a of the channel of the second pull-up FETMP2 in the illustrated embodiment P2 Second part of region 211b P2 By swapping the positions, the first portion region 211a of the channel of the second pull-up FETMP2 in this embodiment is obtained. P2 Second part of region 211b P2 For the implementation where the second pull-up FETMP2 is connected to the second electrode interconnect 42, please refer to... Figure 9 The descriptions in the illustrated embodiments will not be repeated here.

[0181] In yet another embodiment of this application, reference is made to... Figure 13 , Figure 14A and Figure 14D The layers containing the third electrode interconnect 45 and the fourth electrode interconnect 46 are different from the layers containing the first bit line BL1 and the second bit line BL2. The third electrode interconnect 45 is connected to the first electrode interconnect 41 through the seventh electrode contact hole CA7, and the third electrode interconnect 45 is also connected to the gate 212 of the second pull-up FET MP2 through the eighth electrode contact hole CA8. P2 Gate 212 of the second pull-down FETMN2 N2 Connection. Furthermore, the fourth electrode interconnect 46 is connected to the second electrode interconnect 42 via the ninth electrode contact hole CA9, and the fourth electrode interconnect 46 is also connected to the gate 212 of the first pull-up FET MP1 via the tenth electrode contact hole CA10. P1 and the gate 212 of the first pull-down FET MN1 N1Connection. Exemplarily, the third electrode interconnect 45 and the fourth electrode interconnect 46 may be located in the third wiring layer 50, with the seventh electrode contact hole CA7 to the tenth electrode contact hole CA10 penetrating the first dielectric layer 11, the second dielectric layer 12, and the third dielectric layer 13. Alternatively, the third electrode interconnect 45 and the fourth electrode interconnect 46 may be located in the first wiring layer 30, with the seventh electrode contact hole CA7 and the ninth electrode contact hole CA9 penetrating the second dielectric layer 12, and the eighth electrode contact hole CA8 and the tenth electrode contact hole CA10 penetrating the first dielectric layer 11.

[0182] Figure 15 This is a top view schematic diagram of another storage array structure in the embodiments of this application. Figure 16A for Figure 15 A top view of the semiconductor device layer in the diagram. Figure 16B for Figure 15 A top view of the first wiring layer in the diagram. Figure 16C for Figure 15 A top view of the second wiring layer in the diagram. Figure 16D for Figure 15 A top view of the third wiring layer, see diagram below. Figures 13 to 16D The memory array includes a semiconductor device layer 20, a first dielectric layer 11, a first wiring layer 30, a second dielectric layer 12, a second wiring layer 40, a third dielectric layer 13, and a third wiring layer 50. Each FET in the memory cell 100 is located on the semiconductor device layer 20. The first bit line BL1, the second bit line BL2, the first electrode interconnect 41, the second electrode interconnect 42, the first power interconnect 43, and the second power interconnect 44 are located on the second wiring layer 40. The WL is located on the third wiring layer 50. Furthermore, this embodiment is aimed at… Figure 9 The embodiments shown have been modified. The differences between this embodiment and the above embodiments will only be described below; the similarities will not be repeated here.

[0183] In yet another embodiment of this application, reference is made to... Figure 15 and Figure 16A This changes the arrangement of FETs in the memory cell 100. For example, in any memory cell 100, the first access FET MA1, the second pull-up FET MP2, and the second pull-down FET MN2 are arranged along the second direction F2. This allows for a more regular layout of the FETs in any memory cell 100, making full use of space and reducing design complexity. Furthermore, based on this arrangement, the first part of the FETs can include the second pull-up FET MP2 and the second pull-down FET MN2. That is, the orthographic projection of the CNT of the second pull-up FET MP2 onto the substrate 10 and the orthographic projection of the CNT of the second pull-up FET MN2 onto the substrate 10 overlap with the orthographic projection of the first line BL1 onto the substrate 10, thereby further optimizing the wiring and layout.

[0184] For example, refer to Figure 15 and Figure 16A In any memory cell 100, in the second direction F2, the second pull-up FETMP2 is located between the first access FETMA1 and the second pull-down FETMN2. For example, the orthogonal projection of the CNT of the second pull-up FETMP2 onto the substrate 10 is between the orthogonal projection of the CNT of the first access FETMA1 onto the substrate 10 and the CNT of the second pull-down FETMN2 onto the substrate 10.

[0185] For example, refer to Figure 15 and Figure 16A In any memory cell 100, the gate 212 of the first access FETMA1 A1 The gate 212 of the second pull-up FETMP2 P2 Gate 212 of the second pull-down FETMN2 N2 Arranging along the second direction F2 can further optimize the map layout.

[0186] For example, refer to Figure 15 and Figure 16A In any memory cell 100, the gate 212 of the second pull-down FET MN2 N2 Gate 212 of the second pull-up FETMP2 P2 It is a single integrated structure. This allows the gate 212 of the second pull-down FET MN2 to be integrated. N2 With the gate 212 of the second pull-up FETMP2 P2 Direct electrical connection shortens the signal transmission path and reduces latency. Furthermore, the gate 212 of the second pull-down FET MN2 can be fabricated using the same process. N2 With the gate 212 of the second pull-up FETMP2 P2 This simplifies the manufacturing process. In other embodiments of this application, the gate of the second pull-up FETMP2 and the gate of the second pull-down FETMN2 can also be the same and independent, and can be point-connected through the connection lines of other wiring layers.

[0187] In yet another embodiment of this application, reference is made to... Figure 15 and Figure 16AIn any memory cell 100, the second access FET MA2, the first pull-up FET MP1, and the first pull-down FET MN1 are arranged along the second direction F2. This allows for a more regular layout of the FETs in any memory cell 100, making full use of space and reducing design complexity. Furthermore, based on this arrangement, the second part of the FETs can include the first pull-up FET MP1 and the first pull-down FET MN1. That is, the orthographic projections of the CNTs of the first pull-up FET MP1 and the first pull-down FET MN1 onto the substrate 10 overlap with the orthographic projection of the second bit line BL2 onto the substrate 10, thereby further optimizing wiring and layout.

[0188] For example, refer to Figure 15 and Figure 16A In any memory cell 100, in the second direction F2, the first pull-up FETMP1 is located between the second access FETMA2 and the first pull-down FETMN1. For example, in any memory cell 100, the orthographic projection of the CNT of the first pull-up FETMP1 onto the substrate 10 is located between the orthographic projection of the CNT of the second access FETMA2 onto the substrate 10 and the orthographic projection of the CNT of the first pull-down FETMN1 onto the substrate 10, which can further optimize the layout.

[0189] For example, refer to Figure 15 and Figure 16A In any memory cell 100, the gate 212 of the second access FETMA2 A2 Gate 212 of the first pull-down FETMN1 N1 and the gate 212 of the first pull-up FETMP1 P1 Arranging along the second direction F2 can further optimize the map layout.

[0190] For example, refer to Figure 15 and Figure 16A In any memory cell 100, the gate 212 of the first pull-down FETMN1 N1 and the gate 212 of the first pull-up FETMP1 P1 It is a single integrated structure. This allows the gate 212 of the first pull-down FET MN1 to be integrated. N1 With the gate 212 of the first pull-up FETMP1 P1 Direct electrical connection shortens the signal transmission path and reduces latency. Furthermore, the gate 212 of the first pull-down FET MN1 can be fabricated using the same process. N1 With the gate 212 of the first pull-up FETMP1 P1This simplifies the manufacturing process. In other embodiments of this application, the gate of the first pull-up FETMP1 and the gate of the first pull-down FETMN1 can also be the same and independent, and can be point-connected through the connection lines of other wiring layers.

[0191] In yet another embodiment of this application, reference is made to... Figure 15 and Figure 16A In any memory cell 100, the first access FETMA1 and the first pull-down FETMN1 are arranged along the first direction F1, and the CNTs of the first access FETMA1 and the first pull-down FETMN1 are shared. The implementation of the CNTs in the first access FETMA1 and the first pull-down FETMN1 in this embodiment can be referred to... Figure 6 The specific descriptions in the illustrated embodiments will not be repeated here.

[0192] In yet another embodiment of this application, reference is made to... Figure 15 and Figure 16A In any memory cell 100, the second access FETMA2 and the second pull-down FETMN2 are arranged along the first direction F1, and the CNTs of the second access FETMA2 and the second pull-down FETMN2 are shared. The implementation of the CNTs in the second access FETMA2 and the second pull-down FETMN2 in this embodiment can be referred to... Figure 6 The specific descriptions in the illustrated embodiments will not be repeated here.

[0193] In yet another embodiment of this application, reference is made to... Figure 15 and Figure 16A In any memory cell 100, the first pull-up FETMP1 and the second pull-up FETMP2 are staggered along the first direction F1, meaning that the first pull-up FETMP1 and the second pull-up FETMP2 are not arranged along the first direction F1. Furthermore, the CNT of the first pull-up FETMP1 and the CNT of the second pull-up FETMP2 are not shared. For example, in the second direction F2, the first pull-up FETMP1 is located between the second pull-up FETMP2 and the first pull-down FETMN1, and the second pull-up FETMP2 is located between the first pull-up FETMP1 and the second pull-down FETMN2. This allows two FETs that require direct gate connection to be closer together, saving area, optimizing signal transmission, and simplifying wiring.

[0194] To achieve the gate 212 of the first pull-down FETMN1 N1 The gate 212 of the first pull-up FET MP1 P1 And the connection of the first terminal of the second pull-up FETMP2, exemplarily, refer to Figure 15 and Figure 16A The gate 212 of the first pull-down FET MN1 N1Extending along the second direction F2, located in the channel of the second pull-up FETMP2, and adjacent to the first portion region 211a of the channel of the second pull-up FETMP2. P2 The CNT connection in the layout can further optimize the layout and realize its electrical connection.

[0195] To achieve the gate 212 of the second pull-down FET MN2 N2 The gate 212 of the second pull-up FETMP2 P2 And the connection of the first terminal of the first pull-up FETMP1, exemplarily, refer to Figure 15 and Figure 16A The gate 212 of the second pull-down FETMN2 N2 Extending along the second direction F2, it is located in the channel of the first pull-up FETMP1 and is adjacent to the first portion region 211a of the channel of the first pull-up FETMP1. P1 The CNT connection in the layout can further optimize the layout and realize its electrical connection.

[0196] In yet another embodiment of this application, reference is made to... Figure 15 and Figure 16D The orthographic projection of WL onto substrate 10 lies between the orthographic projections of the first access FETMA1 onto substrate 10 and the second access FETMA2 onto substrate 10, which can further optimize the layout. For example, referring to... Figure 15 and Figure 16D To facilitate the electrical connection between WL and the first access FETMA1 and the second access FETMA2 respectively, WL can be shaped into a bent form, thereby simplifying design and manufacturing and facilitating expansion and optimization of the layout. For example, the shape of WL can be rectangular wave-shaped. This application does not limit the shape of WL; for example, it can also be wavy, sawtooth, etc.

[0197] For example, refer to Figure 15 and Figure 16A It can be based on Figure 9 The positions of the first access FETMA1 and the second access FETMA2 in the illustrated embodiment are changed to obtain the first access FETMA1 and the second access FETMA2 in this embodiment. Therefore, for the embodiments in which the first access FETMA1 is connected to the first bit line BL1, the second access FETMA2 is connected to the second bit line BL2, and the first access FETMA1 and the second access FETMA2 are respectively connected to WL, please refer to... Figure 9 The specific descriptions in the illustrated embodiments will not be repeated here.

[0198] In yet another embodiment of this application, reference is made to... Figure 15 , Figure 16A and Figure 16C In this embodiment, the first electrode of the first pull-up FETMP1, the first electrode of the first pull-down FETMN1, and the first electrode of the first access FETMA1 are connected through the first electrode interconnect 41. This can be referred to in the following implementation. Figure 6 The specific descriptions in the illustrated embodiments will not be repeated here. Similarly, in this embodiment, the implementation in which the first electrode of the second access FETMA2, the first electrode of the second pull-up FETMP2, and the first electrode of the second pull-down FETMN2 are connected through the second electrode interconnect 42 can be referred to... Figure 6 The specific descriptions in the illustrated embodiments will not be repeated here.

[0199] In yet another embodiment of this application, reference is made to... Figure 15 and Figure 16B The memory array also includes a first power line 31, a second power line 32, and a third power line 33. The first power line 31 is connected to a first pull-up FETMP1 and a second pull-up FETMP2 to transmit a first power supply voltage VDD to the first pull-up FETMP1 and the second pull-up FETMP2. The second power line 32 is connected to a first pull-down FETMN1 to transmit a second power supply voltage VSS to the first pull-down FETMN1. The third power line 33 is connected to a second pull-down FETMN2 to transmit the second power supply voltage VSS to the second pull-down FETMN2.

[0200] For example, refer to Figures 15 to 16B It can be based on Figure 9 The positions of the first pull-up FETMP1 and the second pull-up FETMP2 in the illustrated embodiment are changed to obtain the first pull-up FETMP1 and the second pull-up FETMP2 in this embodiment. Therefore, for the embodiment in which the first pull-up FETMP1 and the second pull-up FETMP2 are connected to the first power line 31, refer to... Figure 9 The specific descriptions in the illustrated embodiments will not be repeated here.

[0201] Similarly, it can also be based on the following: Figure 9 The position of the first pull-down FETMN1 in the illustrated embodiment is changed to obtain the first pull-down FETMN1 in this embodiment. Therefore, for the implementation where the first pull-down FETMN1 is connected to the second power line 32, refer to... Figure 9 The specific descriptions in the illustrated embodiments will not be repeated here.

[0202] For example, refer to Figure 15 and Figure 16BThe third power line 33 is connected to the second pull-down FET MN2 via the second power interconnect 44b. Furthermore, in this embodiment, the implementation of the connection between the third power line 33 and the second pull-down FET MN2 can be referred to... Figure 9 The specific details of the embodiment in which the second power line 32 is connected to the second pull-down FETMN2 are not repeated here.

[0203] In yet another embodiment of this application, reference is made to... Figure 15 and Figure 16B The orthographic projection of the first power line 31 onto the substrate 10 lies between the orthographic projections of the second power line 32 onto the substrate 10 and the orthographic projections of the third power line 33 onto the substrate 10.

[0204] For example, refer to Figure 15 and Figure 16B The orthographic projection of the first power line 31 onto the substrate 10 is located between the orthographic projections of the first pull-up FETMP1 and the second pull-up FETMP2 onto the substrate 10, optimizing the layout. For example, the orthographic projection of the first power line 31 onto the substrate 10 may be located between the orthographic projections of the CNTs of the first pull-up FETMP1 and the second pull-up FETMP2 onto the substrate 10. Alternatively, the orthographic projection of the first power line 31 onto the substrate 10 may also have an overlapping area with the orthographic projections of the CNTs of the first pull-up FETMP1 and the second pull-up FETMP2 onto the substrate 10, optimizing the layout.

[0205] For example, refer to Figure 15 and Figure 16B The first power line 31 has an overlapping area in the orthographic projection on the substrate 10 with the WL in the orthographic projection on the substrate 10, which can optimize the layout.

[0206] For example, refer to Figure 15 and Figure 16B The orthographic projection of the second power line 32 onto the substrate 10 is located on the side opposite to the orthographic projection of the first access FET MA1 onto the substrate 10. For example, the orthographic projection of the second power line 32 onto the substrate 10 is located on the side opposite to the orthographic projection of the CNT of the first access FET MA1 onto the substrate 10, which can optimize the layout.

[0207] For example, refer to Figure 15 and Figure 16BThe orthographic projection of the third power line 33 onto the substrate 10 is located on the side where the orthographic projection of the second access FETMA2 onto the substrate 10 is opposite to the orthographic projection of the first pull-down FETMN1 onto the substrate 10. For example, the orthographic projection of the third power line 33 onto the substrate 10 is located on the side where the orthographic projection of the CNT of the second access FETMA2 onto the substrate 10 is opposite to the orthographic projection of the CNT of the first pull-down FETMN1 onto the substrate 10, which can optimize the layout.

[0208] The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A storage array, characterized in that, Includes a substrate and multiple memory cells, multiple first bit lines, and multiple second bit lines located on the substrate; Each of the memory cells includes a plurality of field-effect transistors (FETs), the channels of which include a semiconductor material having a leakage channel extending along a first direction; The plurality of first bit lines and the plurality of second bit lines extend along a second direction, the first direction and the second direction being parallel to the substrate, and the first direction and the second direction intersecting each other; The plurality of FETs includes a first access FET and a second access FET. In the plurality of memory cells arranged along the second direction, the channel of each first access FET is connected to a first bit line, and the channel of each second access FET is connected to a second bit line.

2. The storage array according to claim 1, characterized in that, The semiconductor materials include: carbon nanotubes, two-dimensional materials with conductive grain boundaries, Si, Ge, III-V group semiconductor materials, or oxide semiconductor materials.

3. The storage array according to claim 1 or 2, characterized in that, The orthographic projection of the gate of the first access FET on the substrate and the orthographic projection of the gate of the second access FET on the substrate are located between the orthographic projection of the first bit line on the substrate and the orthographic projection of the second bit line on the substrate. or, The orthographic projection of the first bit line onto the substrate and the orthographic projection of the second bit line onto the substrate are located between the orthographic projection of the gate of the first access FET onto the substrate and the orthographic projection of the gate of the second access FET onto the substrate.

4. The storage array according to any one of claims 1-3, characterized in that, The plurality of FETs further includes: a first pull-down FET, a second pull-down FET, a first pull-up FET, and a second pull-up FET; The first pull-down FET, the second pull-down FET, the first pull-up FET, and the second pull-up FET include a first part FET and a second part FET. The channel of the first part FET has an overlapping region when projected onto the substrate and the first bit line has an overlapping region when projected onto the substrate. The channel of the second part FET has an overlapping region when projected onto the substrate and the second bit line has an overlapping region when projected onto the substrate.

5. The storage array according to claim 4, characterized in that, The first terminals of the first pull-up FET, the first terminals of the first pull-down FET, and the first terminals of the first access FET are connected through a first electrode interconnect, and the first terminals of the second access FET, the first terminals of the second pull-up FET, and the first terminals of the second pull-down FET are connected through a second electrode interconnect. The first electrode interconnect and the second electrode interconnect extend along the second direction, respectively.

6. The storage array according to claim 4 or 5, characterized in that, The first access FET, the second access FET, the first pull-down FET, and the second pull-down FET are arranged along the first direction, with the first pull-down FET and the second pull-down FET located between the first access FET and the second access FET. The regions where the first access FET and the first pull-down FET are located are arranged along the second direction with the region where the first pull-up FET is located; the regions where the second access FET and the second pull-down FET are located are arranged along the second direction with the region where the second pull-up FET is located. The first part of the FET includes the first pull-up FET, and the second part of the FET includes the second pull-up FET.

7. The storage array according to claim 6, characterized in that, The memory array further includes word lines extending along a first direction, the word lines being connected to the gates of the first access FET and the second access FET; The word line's orthogonal projection onto the substrate lies between the orthogonal projections of the first access FET onto the substrate and the first pull-up FET onto the substrate.

8. The storage array according to claim 6 or 7, characterized in that, The memory array further includes a first power line and a second power line, the first power line being connected to the first pull-up FET and the second pull-up FET, and the second power line being connected to the first pull-down FET and the second pull-down FET. The orthogonal projection of the first power line on the substrate is located on the side opposite to the orthogonal projection of the first pull-up FET on the substrate, and the orthogonal projection of the second power line on the substrate is located on the side opposite to the orthogonal projection of the first access FET on the substrate.

9. The storage array according to claim 4 or 5, characterized in that, The first access FET, the first pull-down FET, and the first pull-up FET are arranged along the second direction, and the first portion of the FET includes the first pull-up FET and the first pull-down FET; and / or, The second access FET, the second pull-down FET, and the second pull-up FET are arranged along the second direction, and the second part of the FET includes the second pull-up FET and the second pull-down FET.

10. The storage array according to claim 9, characterized in that, The memory array further includes word lines extending along a first direction, the word lines being connected to the gates of the first access FET and the second access FET; The word line's orthogonal projection onto the substrate is located on the side opposite to the orthogonal projection of the first access FET onto the substrate.

11. The storage array according to claim 10, characterized in that, The memory array further includes a second power line, which is connected to the first pull-down FET and the second pull-down FET. The orthographic projection of the second power line on the substrate is located on the side of the orthographic projection of the word line on the substrate opposite to the orthographic projection of the first access FET on the substrate; or, the orthographic projection of the second power line on the substrate is located between the orthographic projection of the first access FET on the substrate and the orthographic projection of the first pull-down FET on the substrate.

12. The storage array according to any one of claims 9-11, characterized in that, The memory array further includes a first power line, which is connected to the first pull-up FET and the second pull-up FET. The orthogonal projection of the first power line onto the substrate is located on the side opposite to the orthogonal projection of the first pull-up FET onto the substrate.

13. The storage array according to claim 4 or 5, characterized in that, The first access FET, the second pull-up FET, and the second pull-down FET are arranged along the second direction, and the first portion of the FET includes the second pull-up FET and the second pull-down FET; and / or, The second access FET, the first pull-up FET, and the first pull-down FET are arranged along the second direction, and the second part of the FET includes the first pull-up FET and the first pull-down FET.

14. The storage array according to claim 13, characterized in that, The memory array further includes word lines extending along a first direction, the word lines being connected to the gates of the first access FET and the second access FET; The word line's orthogonal projection onto the substrate lies between the orthogonal projections of the first access FET onto the substrate and the orthogonal projections of the second access FET onto the substrate.

15. The storage array according to claim 13 or 14, characterized in that, The storage array further includes a first power line, a second power line and a third power line, wherein the first power line is connected to the first pull-up FET and the second pull-up FET, the second power line is connected to the first pull-down FET, and the third power line is connected to the second pull-down FET. The orthographic projection of the first power line onto the substrate lies between the orthographic projections of the second power line onto the substrate and the orthographic projection of the third power line onto the substrate.

16. A static random access memory, characterized in that, include: The controller and at least one storage array as described in any one of claims 1-15, wherein the controller is electrically connected to any one of the storage arrays.

17. A semiconductor packaging structure, characterized in that, include: The package substrate and the static random access memory as described in claim 16, wherein the static random access memory is packaged on the package substrate.

18. An electronic device, characterized in that, include: The circuit board and the semiconductor package structure as described in claim 17, wherein the semiconductor package structure is electrically connected to the circuit board.

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