Memory array, semiconductor structure, and method of forming the same

Abstract

The semiconductor structure includes a device layer and an interconnect structure. The device layer includes a first active region of a first cell, a first transistor and a second transistor sharing the first active region, a second active region of a second cell adjacent to the first cell, and a third transistor and a fourth transistor sharing the second active region. The interconnect structure includes a first bonding pad extending along a second direction and electrically coupled to the source / drain regions of the second and fourth transistors, a second bonding pad electrically coupled to the source / drain regions of the first transistor, a first metal line extending along a first direction over the second cell and electrically coupled to the first bonding pad, and a second metal line extending along the first direction over the first cell and electrically coupled to the source / drain regions of the second bonding pad and the third transistor. Embodiments of this disclosure also provide memory arrays and methods for forming semiconductor structures.

Description

Technical Field

[0001] Embodiments of this disclosure relate to memory arrays, semiconductor structures, and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] Semiconductor memory is an electronic data storage device implemented on semiconductor integrated circuits and has access times much faster than other types of data storage technologies. For example, static random access memory (SRAM) devices are commonly used in integrated circuits. SRAM devices are popular in high-speed communications, image processing, and system-on-a-chip (SoC) applications. Bits can be read from or written to SRAM cells in nanoseconds, while the access time of spinning storage devices such as hard disks is in the millisecond range.

[0004] With the advent of the deep submicron era, SRAM devices have become increasingly favored due to their photolithography-friendly layout of active regions, gate lines, and interconnect layers. However, the continuous shrinking of SRAM cells not only presents complex manufacturing processes but also introduces specific challenges to signal routing design and functionality. For example, multilayer interconnect structures with multiple interconnect layers provide signal routing for memory cells in the underlying memory array. Because wiring resources are limited in the lower interconnect layers, some signal lines (e.g., bit lines) face challenges of increased wiring resistance and parasitic capacitance due to limited line width and pitch. Accordingly, with the continuous advancement of process nodes, there is a need to improve the signal routing in multilayer interconnect structures of memory arrays. Summary of the Invention

[0005] Some embodiments of this disclosure provide a semiconductor structure comprising: a device layer including: a first active region of a first unit extending longitudinally in a first direction; a first transistor and a second transistor sharing the first active region; a second active region of a second unit adjacent to the first unit, extending longitudinally in the first direction and spaced apart from the first active region in a second direction different from the first direction; a third transistor and a fourth transistor sharing the second active region, the first transistor, the second transistor, the third transistor, and the fourth transistor including titanium-containing gate electrodes; an isolation structure intersecting the sidewalls of the first and second active regions, the top surface of the isolation structure being uneven; and a multilayer interconnect structure disposed above the device layer, the multilayer interconnect structure including: a first A bonding pad extends along a second direction and passes through the boundary line between the first and second units. The first bonding pad is electrically coupled to the source / drain regions of the second transistor and the source / drain regions of the fourth transistor. A first metal line extends along a first direction and is located above the second unit. The first metal line is electrically coupled to the first bonding pad. A second bonding pad is electrically coupled to the source / drain regions of the first transistor. A second metal line extends along the first direction and is located above the first unit. The second metal line is electrically coupled to the second bonding pad and also electrically coupled to the source / drain regions of the third transistor. The first and second bonding pads are located in the first interconnect layer of the multilayer interconnect structure, the first and second metal lines are located in the second interconnect layer of the multilayer interconnect structure, and the first interconnect layer is located below the second interconnect layer.

[0006] Other embodiments of this disclosure provide a memory array comprising: a first plurality of cells arranged in a first row of the memory array, wherein the cells in the first row share a first active region extending longitudinally along a first direction; a second plurality of cells arranged in a second row of the memory array, wherein the cells in the second row share a second active region extending longitudinally along the first direction, wherein the second row is adjacent to the first row along a second direction different from the first direction; and a multilayer interconnect structure disposed above the cells in the first and second rows, wherein the multilayer interconnect structure includes a plurality of interconnect layers, wherein each interconnect layer includes a metal line disposed in a dielectric layer, wherein... The thickness of the bottommost interconnect layer is less than the thickness of at least one interconnect layer above the bottommost interconnect layer, wherein the multilayer interconnect structure includes: a first signal line located in the first interconnect layer of the interconnect layer, wherein the first signal line extends along a first direction and is located above a cell in a first row, wherein the first signal line is electrically coupled to a cell in a first row and a second row; and a second signal line located in the first interconnect layer of the interconnect layer, wherein the second signal line extends along the first direction and is located above a cell in a second row, wherein the second signal line is electrically coupled to a cell in a first row and a second row, wherein the first signal line and the second signal line carry a pair of complementary signals.

[0007] Further embodiments of this disclosure provide a method for forming a semiconductor structure, the method comprising: forming a first active region and a second active region extending longitudinally in a first direction; forming a first gate structure and a second gate structure bonded to the first active region to form a first transistor and a second transistor, respectively; forming a third gate structure and a fourth gate structure bonded to the second active region to form a third transistor and a fourth transistor, respectively, wherein the first gate structure, the second gate structure, the third gate structure and the fourth gate structure extend longitudinally in a second direction different from the first direction, wherein the first gate structure, the second gate structure, the third gate structure and the fourth gate structure include a gate dielectric layer and a gate electrode disposed on the gate dielectric layer; and depositing along the sidewalls of the first gate structure, the second gate structure, the third gate structure and the fourth gate structure. A gate spacer, wherein the thickness of the gate spacer is greater than the thickness of the gate dielectric layer, and wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer; a first interconnect layer is formed on a first transistor, a second transistor, a third transistor, and a fourth transistor, the first interconnect layer including a first bonding pad and a second bonding pad, the first bonding pad extending along a second direction and electrically coupled to the source / drain regions of the first transistor and the third transistor, the second bonding pad extending along a second direction and electrically coupled to the source / drain regions of the second transistor and the fourth transistor; and a second interconnect layer is formed on the first interconnect layer, the second interconnect layer including a first metal line and a second metal line, the first metal line extending along a first direction and electrically coupled to the first bonding pad, the second metal line extending along a first direction and electrically coupled to the second bonding pad. Attached Figure Description

[0008] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1A and Figure 1B Perspective and top views of portions of a memory device according to some embodiments of the present disclosure are shown respectively.

[0010] Figure 2 Cross-sectional views of various layers of a memory device according to some embodiments of the present disclosure are shown.

[0011] Figure 3 A circuit diagram of a dual-port static random access memory (SRAM) cell according to some embodiments of the present disclosure is shown.

[0012] Figure 4 Examples of embodiments according to this disclosure are shown. Figure 3The layout of the device layer of the dual-port SRAM cell.

[0013] Figure 5 and Figure 6 Examples of embodiments according to this disclosure are shown. Figure 4 The layout of the contact layer, via zero layer and metal zero layer of the multilayer interconnect structure of the dual-port SRAM cell.

[0014] Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 Some embodiments according to this disclosure are shown, based on, as Figure 4 The layout of the device layer, contact layer, via zero layer, metal zero layer, via one layer, metal one layer, via two layer, and metal two layer in the multilayer interconnect structure of the SRAM array of the dual-port SRAM cell.

[0015] Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 19 Some embodiments according to this disclosure are shown, based on, as Figure 4 An optional embodiment of the layout of a multilayer interconnect structure of a dual-port SRAM cell SRAM array, comprising a through-hole layer, a metal layer, a through-hole layer, and a metal layer.

[0016] Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 Some embodiments according to this disclosure are shown, based on, as Figure 4 The layout of the multilayer interconnect structure of the SRAM array of the dual-port SRAM cell in the SRAM array includes contact layer, via zero layer, metal zero layer, via one layer, metal one layer, via two layers, metal two layers, via three layers, and metal three layers.

[0017] Figure 25 A flowchart illustrating an exemplary method for manufacturing a memory device according to some embodiments of the present disclosure is shown. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples of various components for implementing this application. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or above a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact.

[0019] Additionally, reference numerals and / or characters may be repeated in various instances of this disclosure. This repetition is for clarity and simplicity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Furthermore, in the following disclosure, a component formed on, connected to, and / or coupled to another component may include embodiments where the components are in direct contact, and may also include embodiments where additional components can be inserted between components so that the components are not in direct contact. Additionally, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “under,” “below,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to facilitate understanding of the relationship between one component and another in this disclosure. Spatially relative terms are intended to cover different orientations of the device including the component. Further still, when numerical values ​​or ranges are described using terms such as “about,” “approximately,” etc., unless otherwise stated, the term is intended to cover values ​​including + / - 10% of the described value. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0020] As smaller geometries are implemented (e.g., by reducing the transmission distance of electrical signals) to achieve semiconductor devices with faster operating speeds, resistance-capacitance (RC) delay and IR drop have become significant challenges, offsetting some of the advantages gained by scaling down and limiting further scaling of ICs. Therefore, it is desirable to reduce both resistance and parasitic capacitance to decrease RC delay and IR drop, and to optimize the performance of scaled-down ICs. In some integrated circuits (ICs) (e.g., memory devices), multilayer interconnect structures are formed to couple transistors to memory cells. These multilayer interconnect structures include power lines located between and within the memory cells of the memory device (e.g., coupled to a power supply V). DD The power supply line is coupled to the reference voltage V. SSPower lines, signal lines (e.g., bit lines, word lines), and other conductors used to interconnect power lines and / or signal lines (e.g., vias, bonding wires, bonding pads, source / drain contacts, butt contacts). Multilayer interconnect structures that physically and / or electrically connect transistor components and / or parts contribute to RC delay and IR drop. For example, as memory cell heights decrease to accommodate advanced process nodes, the available layout area within a single memory cell may no longer provide sufficient routing space. Consequently, some signal lines either have to have reduced line widths and / or line pitches to accommodate the limited routing area, or they have to be routed to higher interconnect layers where additional routing space is available, increasing routing resistance and parasitic capacitance, and consequently degrading RC performance.

[0021] This disclosure provides memory devices including arrays of memory cells and corresponding multilayer interconnect structures. In some embodiments, adjacent memory cells may share one or more signal lines, rather than providing a dedicated set of signal lines (e.g., read port bit lines and / or write port bit lines) for each memory cell. By sharing one or more signal lines among adjacent memory cells, the demand for wiring resources in a given interconnect layer (e.g., M0 or M2 level) is reduced, allowing signal lines to have relatively larger linewidths and / or larger line pitches. Implementing such an interconnect structure can effectively reduce wiring resistance and parasitic capacitance associated with signal lines.

[0022] Some exemplary embodiments relate to, but are not otherwise limited to, static random access memory (SRAM) cells. Furthermore, some exemplary embodiments relate to, but are not otherwise limited to, multi-gate devices. Multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). One such multi-gate device that has been introduced is the FinFET (Fin Field-Effect Transistor). The name FinFET comes from the fin structure that extends from the substrate (on which the fin structure is formed) and is used to form the FET channel. Another multi-gate device is the Gate All-Around (GAA) transistor, which was introduced in part to address the performance challenges associated with FinFETs. The name GAA transistor comes from the gate structure that can extend around the channel region (e.g., a stack of nanosheets), thereby providing access to the channel on all four sides. GAA transistors are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their structure allows for large-scale scaling while maintaining gate control and mitigating SCE. The following disclosure describes various embodiments using SRAM cells with GAA transistors as exemplary examples. However, it should be understood that, unless expressly stated in the claims, the application should not be limited to a particular type of device or transistor. For example, aspects of this disclosure can also be applied to memory devices other than SRAM, and to implementations based on FinFETs or planar FETs instead of GAA transistors.

[0023] Figure 1A and Figure 1B Perspective and top views of portions of an integrated circuit (IC) device 10 (such as an SRAM device) implemented using GAA transistors are shown, respectively. Reference Figure 1AThe IC device 10 includes a substrate 12. The substrate 12 may comprise elemental (single-element) semiconductors such as silicon, germanium, and / or other suitable materials; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 12 may be a monolayer material with a uniform composition. Optionally, the substrate 12 may include multiple material layers having similar or different compositions suitable for IC device fabrication. In one example, the substrate 12 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 12 may include conductive layers, semiconductor layers, dielectric layers, other layers, or combinations thereof. Various doped regions, such as source / drain (S / D) regions, may be formed in or on the substrate 12. Depending on design requirements, the doped regions can be doped with n-type dopants (such as phosphorus or arsenic) and / or p-type dopants (such as boron). The doped regions can be formed directly on the substrate 12, in a p-well structure, in an n-well structure, in a double-well structure, or using a bump structure. The doped regions can be formed by dopant atom implantation, in-situ doped epitaxial growth, and / or other suitable techniques.

[0024] Three-dimensional active regions 14 are formed on substrate 12. The active region of a transistor refers to the region forming the source region, drain region, and channel region below the transistor gate structure. In this context, the active region is also referred to as an "oxide-bounded (OD) region." Each active region 14 includes elongated nanostructures 26 (e.g., Figure 2 As shown, nanostructure 26 is vertically stacked in the channel region defined in the active region and situated above the fin base. The fin base protrudes upward beyond the substrate 12. Source / drain components 16 are formed in the source / drain region defined in the active region and situated above the fin base. The source / drain components 16 are abutted against the two opposite ends of the nanostructure 26. The source / drain components 16 may include an epitaxial layer epitaxially grown on the fin base.

[0025] The IC device 10 also includes an isolation structure (or isolation component) 18 formed over the substrate 12. The isolation structure 18 electrically isolates the various components of the IC device 10. The isolation structure 18 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric material, and / or other suitable materials. In some embodiments, the isolation structure 18 may include a shallow trench isolation (STI) component. In one embodiment, the isolation structure 18 is formed by etching trenches in the substrate 12 during the formation of the active region 14. The trenches can then be filled with the aforementioned isolation material, followed by a chemical mechanical planarization (CMP) process. Other isolation structures, such as field oxide, localized oxidation of silicon (LOCOS), and / or other suitable structures, may also be implemented as the isolation structure 18. Optionally, the isolation structure 18 may include a multilayer structure, for example, having one or more thermal oxide pad layers. In some embodiments, the top surface of the isolation structure 18 intersects with the opposing sidewalls of two adjacent fin bases and is not flat.

[0026] IC device 10 also includes a gate structure (or gate stack) 20 formed over and bonded to active region 14. Gate structure 20 may be a dummy gate structure (e.g., containing an oxide gate dielectric and a polysilicon gate electrode), or it may be a high-k metal gate (HKMG) structure containing a high-k gate dielectric and a metal gate electrode, wherein the HKMG structure is formed by replacing the dummy gate structure. Although not shown herein, gate structure 20 may include additional material layers, such as interface layers, cap layers, other suitable layers, or combinations thereof.

[0027] refer to Figure 1B Multiple active regions 14 are longitudinally oriented along the X direction, and multiple gate structures 20 are longitudinally oriented along the Y direction, i.e., substantially perpendicular to the active regions 14. Transistors are formed at the intersections of the active regions 14 and the gate structures 20. In many embodiments, the IC device 10 includes additional components, such as gate spacers extending along the sidewalls of the gate structures 20, and numerous other components.

[0028] Figure 2 It is based on the various aspects of this disclosure. Figure 1A A partial schematic cross-sectional view along centerline AA shows the various layers (layers) that can be fabricated above substrate 12. Figure 2In this configuration, each layer includes a device layer DL and a metal interconnect structure (also collectively referred to as a multilayer interconnect structure MLI) disposed above the device layer DL. The device layer DL includes devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or device components (e.g., doped wells, gate structures, and / or source / drain components). In some embodiments, the device layer DL includes a substrate 12, doped regions 15 (e.g., n-wells and / or p-wells) disposed in the substrate 12, isolation components 18, and a transistor T. In the illustrated embodiment, the transistor T includes a suspended nanostructure (channel layer) 26 disposed on a finned base and a gate structure 20 disposed between the source / drain components 16, wherein the gate structure 20 surrounds each suspended nanostructure 26. The nanostructure 26 may include nanosheets, nanotubes, or nanowires, or some other type of nanostructure extending horizontally in the X direction. Each gate structure 20 has a metal gate structure and a gate spacer 25 extending along the sidewall of the metal gate structure, the metal gate structure being formed by a gate electrode 22 disposed above a gate dielectric layer 24. In some embodiments, the gate electrode 22 comprises a titanium-containing material. In some embodiments, the dielectric constant of the gate dielectric layer 24 is greater than the dielectric constant of the gate spacer 25. In some embodiments, the thickness of the gate spacer 25 is greater than the thickness of the gate dielectric layer 24.

[0029] A multilayer interconnect structure (MLI) electrically couples the individual devices and / or components of a device layer (DL) so that the individual devices and / or components can operate as specified in the memory design requirements. In the illustrated embodiment, the MLI includes a contact layer (CO level), a via zero layer (V0 level), a metal zero layer (M0) level, a via one layer (V1 level), a metal one layer (M1 level), a via two layer (V2 level), a metal two layer (M2 level), a via three layer (V3 level), a metal three layer (M3 level), and so on. This disclosure contemplates multilayer interconnect structures (MLI) with more or fewer layers and / or levels, for example, a multilayer interconnect structure (MLI) with a total of N metal layers (levels), where N is an integer ranging from 2 to 20. Each level of the MLI includes conductive components (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., interlayer dielectric (ILD) layers and contact etch stop layers (CESL)). In some embodiments, conductive components at the same level (such as the M0 level) of the multilayer interconnect structure MLI are formed simultaneously. In some embodiments, conductive components at the same level of the multilayer interconnect structure MLI have top surfaces that are substantially flat to each other and / or bottom surfaces that are substantially flat to each other. The CO level includes source / drain contacts (MD) disposed in dielectric layer 28; the V0 level includes gate vias VG, source / drain contact vias (referred to as contact vias) VD and mating contacts disposed in dielectric layer 28; the M0 level includes M0 metal lines disposed in dielectric layer 28, wherein the gate via VG connects the gate structure to the M0 metal line, the contact via VD connects the source / drain contacts MD to the M0 metal line, and the mating contacts connect the gate structure and the source / drain. Together; the V1 layer includes a V1 via disposed in the dielectric layer 28, wherein the V1 via connects the M0 metal line to the M1 metal line; the M1 layer includes the M1 metal line disposed in the dielectric layer 28; the V2 layer includes a V2 via disposed in the dielectric layer 28, wherein the V2 via connects the M1 metal line to the M2 metal line; the M2 layer includes the M2 metal line disposed in the dielectric layer 28; the V3 layer includes a V3 via disposed in the dielectric layer 28, wherein the V3 via connects the M2 metal line to the M3 metal line.

[0030] In some embodiments, the thickness of the bottommost interconnect layer (e.g., M0 level) is less than the thickness of at least one interconnect layer (e.g., M1 level, M2 level, or M3 level) disposed above the bottommost interconnect layer. In some embodiments, the thickness of the bottommost metal line (e.g., M0 metal line) is less than the thickness of at least one metal line (e.g., M1 metal line, M2 metal line, or M3 metal line) disposed above the bottommost metal line. In the illustrated embodiment, a silicide layer 30 is inserted between the source / drain contact (MD) and the source / drain component 16. The silicide layer 30 reduces the contact resistance between the source / drain contact (MD) and the source / drain component 16. In some embodiments, the conductivity of the silicide layer 30 is higher than the conductivity of the source / drain component 16, and the conductivity of the source / drain contact (MD) is higher than the conductivity of the silicide layer 30. In some embodiments, the silicide layer 30 has an uneven profile.

[0031] For clarity, it has been simplified. Figure 2 To better understand the inventive concept of this disclosure. Additional components may be added to the various layers of the memory, and in other embodiments of the memory, some of the described components may be replaced, modified, or eliminated. Figure 2 This is merely an example and may not reflect the actual cross-sectional view of the IC device 10 and / or SRAM cell 100, which are discussed in further detail below.

[0032] refer to Figure 3 An exemplary circuit diagram of a dual-port SRAM cell 100 is shown. The dual-port SRAM cell 100 includes a write port 100W and a read port 100R. The write port 100W includes pull-up transistors PU-1 and PU-2, pull-down transistors PD-1 and PD-2, and pass-gate transistors PG-1 and PG-2. In the illustrated embodiment, transistors PU-1, PU-2, PG-1, and PG-2 are p-type transistors, and transistors PD-1 and PD-2 are n-type transistors. The read port 100R includes a read port pass-gate transistor R-PG. In the illustrated embodiment, the pass-gate transistor R-PG is an n-type transistor. That is, in the dual-port SRAM cell 100, the pass-gate transistor in the write port is a p-type transistor, and the pass-gate transistor in the read port is an n-type transistor.

[0033] The drains of pull-up transistor PU-1 and pull-down transistor PD-1 are coupled together, and the drains of pull-up transistor PU-2 and pull-down transistor PD-2 are also coupled together. Transistors PU-1 and PD-1 are cross-coupled with transistors PU-2 and PD-2 to form a data latch. The gates of transistors PU-2 and PD-2 are coupled together and connected to the common drain of transistors PU-1 and PD-1 to form a memory node SN. The gates of transistors PU-1 and PD-1 are coupled together and connected to the common drain of transistors PU-2 and PD-2 to form a complementary memory node SNB. The sources of pull-up transistors PU-1 and PU-2 are coupled to the power supply voltage V. DD Furthermore, the sources of pull-down transistors PD-1 and PD-2 are coupled to the reference voltage V. SS In some embodiments, the reference voltage V SS It can be electrical grounding.

[0034] The data latch's storage node SN is coupled to the write port bit line (denoted as WBL) of write port 100W via the transfer gate transistor PG-1, and the complementary storage node SNB is coupled to the complementary write port bit line (denoted as WBLB) of write port 100W via the transfer gate transistor PG-2. Storage node SN and complementary storage node SNB are complementary nodes that are often at opposite logic levels (logic high or logic low). The gates of transfer gate transistors PG-1 and PG-2 are coupled to the write port word line (denoted as WWL) of write port 100W.

[0035] In the read port 100R of SRAM cell 100, the read port transfer gate transistor R-PG is coupled between the read port bit line (denoted as RBL) of read port 100R and the memory node SN (or coupled to the gates of transistors PU-1 and PD-1). The gate of the read port transfer gate transistor R-PG is coupled to the read port word line (denoted as RWL) of read port 100R.

[0036] Figure 4 A simplified schematic layout of the device layer DL of a dual-port SRAM cell 100 is shown. The dual-port SRAM cell 100 includes a write port 100W and a read port 100R. The write port 100W includes transistors PG-1, PG-2, PU-1, PU-2, PD-1, and PD-2. The read port 100R includes transistors R-PG. For visual clarity and simplicity, the layout includes the active regions and gate structures of those transistors in the SRAM cell 100, while numerous other components in or above the device layer DL, such as gate cutouts, contacts, vias, and metal lines, are not shown.

[0037] The dual-port SRAM cell 100 includes active regions 102 and 104. Both active regions 102 and 104 extend longitudinally in the X direction. In the illustrated embodiment, active regions 102 and 104 may both include (or be implemented as) those discussed above. Figure 2 Nanostructure 26. In other embodiments, active regions 102 and 104 may also include fin structures. Active region 102 is a component of write port 100W, and active region 104 has a side portion as a component of read port 100R, and the remaining portion as a component of write port 100W. In other words, active region 104 is shared by read port 100R and write port 100W. In the illustrated embodiment, active region 104 belongs to transistors PD-1, PD-2, and R-PG, which are NMOS devices. Thus, active region 104 is formed above a p-well (or p-type substrate). Meanwhile, active region 102 belongs to transistors PG-1, PU-1, PU-2, and PG-2, which are PMOS devices. Thus, active region 102 is formed above an n-well. In the illustrated embodiment, active region 102 extends across opposite edges of cell boundary 140 of SRAM cell 100 and continues into adjacent cells on both sides. In contrast, active region 104 extends into adjacent cells across only one edge of cell boundary 140, while its opposite longitudinal edge remains within cell boundary 140. This configuration can be achieved by an active region dicing process (e.g., fin dicing) that truncates active region 104.

[0038] The dual-port SRAM cell 100 also includes gate structures 112, 114, 116, 118, and 120, and a non-functional gate structure 122. Gate structures 112-122 all extend longitudinally in the Y direction. Gate structures 112-122 may all include (or be implemented as) those discussed above. Figure 2Gate structure 20. Gate structures 112, 114, 116, and 120 are components of write port 100W. Gate structure 118 is a component of read port 100R. Gate structures 114 and 116 both extend through two active regions 102 and 104. Thus, gate structure 114 is shared by transistors PD-1 and PU-1, and gate structure 116 is shared by transistors PD-2 and PU-2. Gate structures 118 and 120 are aligned in their longitudinal direction but spaced apart from each other. This configuration can be produced by a gate dicing process (e.g., a diced metal gate process, also known as a CMG process), which cuts the originally continuous gate structure line into two isolated segments corresponding to gate structures 118 and 120. Similarly, gate structures 112 and 122 are aligned along their longitudinal direction but spaced apart from each other. This can be achieved using the same gate dicing process, which cuts the originally continuous gate structure line into two isolated segments corresponding to gate structures 112 and 122. It is noteworthy that gate structure 122 is a non-functional gate because it is located above the longitudinal edge of the active region 104, and no source / drain regions are formed on either side of gate structure 122. Accordingly, no functional transistor is formed at the intersection of gate structure 122 and active region 104.

[0039] Still referencing Figure 4 The boundary 140 of the dual-port SRAM cell 100 is longer in the X direction than in the Y direction. In other words, the boundary 140 can be rectangular. Let the first dimension of the boundary 140 in the X direction be denoted as the cell width W, and the second dimension of the boundary 140 in the Y direction be denoted as the cell height H. The cell size of the dual-port SRAM cell 100 is defined as W × H, where the cell width W is approximately four times the polysilicon pitch (i.e., the center-to-center distance between two adjacent gate structures in the X direction), and the cell height H is approximately twice the isolation pitch (i.e., the center-to-center distance between two adjacent STI components in the Y direction). A unit area is defined as the product of one polysilicon pitch and one isolation pitch, each unit area including the intersection of the gate structure and the active region. Therefore, the dual-port SRAM cell 100 occupies a cell size of approximately eight unit areas to accommodate seven functional transistors, namely transistors PG-1, PG-2, PU-1, PU-2, PD-1, PD-2, and R-PG. Since only one unit area is not used to form a functional transistor, the device layer area utilization of the SRAM cell 100 is considered efficient. In the memory array, dual-port SRAM cells 100 are repeated along both the X and Y directions. Accordingly, at the array level, the cell width W can be referred to as the memory cell pitch along the X direction, and the cell height H can be referred to as the memory cell pitch along the Y direction.

[0040] For reference Figure 5 , Figure 5 A simplified schematic layout of conductive components at the contact (CO) level and via zero (VO) level of a multilayer interconnect structure located above the device layer DL of an SRAM cell 100, according to one embodiment of the present disclosure, is depicted. Similarly, for visual clarity, Figure 5 The image reproduces some components in the device layer DL, such as active regions 102, 104 and gate structures 112-122.

[0041] Gate via 150A electrically connects the gate of the read port transfer gate transistor R-PG (formed by gate structure 118) to the read port word line (RWL). Gate via 150C electrically connects the gate of the write port transfer gate transistor PG-1 (formed by gate structure 112) to the write port word line (WWL). Gate via 150D electrically connects the gate of the write port transfer gate transistor PG-2 (formed by gate structure 120) to the write port word line (WWL). Gate via 150E electrically connects the gate of the write port pull-up transistor PU-1 (formed by gate structure 114) and the gate of the write port pull-down transistor PD-1 (also formed by gate structure 114) to the complementary memory node (SNB). Gate via 150F electrically connects the gate of the write port pull-up transistor PU-2 (formed by gate structure 116) and the gate of the write port pull-down transistor PD-2 (also formed by gate structure 116) to the memory node (SN).

[0042] Source / drain contact 160A and source / drain contact via 170A thereon electrically connect the source region of read port transfer gate transistor R-PG to the read port bit line (RBL). Source / drain contact 160B is bonded to an STI component located outside the longitudinal end of active region 104, and because it does not have a corresponding source / drain contact via bonded thereon, source / drain contact 160B remains electrically suspended. Source / drain contact 160C and source / drain contact via 170C thereon electrically connect the source region of write port transfer gate transistor PG-1 to the write port bit line (WBL). Source / drain contact 160D and source / drain contact via 170D thereon electrically connect the source region of write port transfer gate transistor PG-2 to the write port complementary bit line (WBLB). Source / drain contact 160E and source / drain contact via 170E thereon electrically connect the common drain region of write port transfer gate transistor PG-1 and write port pull-up transistor PU-1 together with the drain region of write port pull-down transistor PD-1 to the memory node (SN). Source / drain contact 160F and source / drain contact via 170F thereon electrically connect the common drain region of write port transfer gate transistor PG-2 and write port pull-up transistor PU-2 together with the common drain region of write port pull-down transistor PD-2 and read port transfer gate transistor R-PG to the complementary memory node (SNB). Source / drain contact 160G and source / drain contact via 170G thereon electrically connect the common source region of write port pull-up transistor PU-1 and write port pull-up transistor PU-2 to the power supply V. DD The source / drain contact 160H and the source / drain contact via 170H bonded thereon electrically connect the common source region of the write port pull-down transistors PD-1 and PD-2 to the electrical ground node Vss. In the illustrated embodiment, the source / drain contacts 160A-160H are all elongated and have a longitudinal direction in the Y direction, which is parallel to the extension direction of the gate structure.

[0043] like Figure 5As shown, the complementary memory node SNB includes a gate via 150E and a source / drain contact via 170F located on two opposite sides of the gate structure 116. As will be discussed in further detail below, a metal line at the M0 level extends across the gate structure 116 in the X direction and connects the gate via 150E and the source / drain contact via 170F. In other words, the M0 metal line is suspended above the gate structure 116 and provides cross-coupling functionality between the gate via 150E and the source / drain contact via 170F. Thus, in the layout shown, the gate via 150E and the source / drain contact via 170F are located at the same horizontal position in the Y direction, so that the metal line extending in the X direction can connect the two. Similarly, the memory node SN includes a gate via 150F and a source / drain contact via 170E located on two opposite sides of the gate structure 114. As will be discussed in further detail below, another metal line at the M0 level extends across the gate structure 114 in the X direction and connects the gate via 150F and the source / drain contact via 170E. In other words, another M0 metal line is suspended above the gate structure 114 and provides cross-coupling functionality between the gate via 150F and the source / drain contact via 170E. Thus, in the layout shown, the gate via 150F and the source / drain contact via 170E are located at the same horizontal position in the Y direction, so that the metal line extending in the X direction can connect the two.

[0044] Now for reference Figure 6 According to one embodiment of this disclosure, Figure 6 A simplified schematic layout of conductive components in the metal zero (M0) level of the multilayer interconnect structure located above the device layer DL of the SRAM cell 100 is depicted. Furthermore, for visual clarity, Figure 6 It is reproduced in Figure 5 The diagram shows the contact vias (VD) and gate vias (VG) in the via zero (V0) level. The M0 level includes a plurality of metal traces arranged in parallel. Specifically, in the embodiment with the layout shown, the SRAM cell 100 includes seven metal traces arranged sequentially along the Y direction from the first (M0 trace 1) to the seventh (M0 trace 7). The distance between the center lines of adjacent metal traces is denoted as the metal trace pitch.

[0045] A metal trace may include a single metal line extending along the X direction through the entire SRAM cell 100. Such a metal line is referred to as a global metal line. Alternatively, a metal trace may include one or more metal lines that do not extend through the entire SRAM cell 100. Such metal lines are referred to as local metal lines, or called islands, pads, bonding lines, or bonding pads. In the illustrated layout, the first metal trace "M0 trace 1" includes a global metal line 180A, which is electrically coupled to the V-channel of the source / drain contact via 170G. DD Line. V DD Line 180A is disposed on the upper edge of SRAM cell 100 and can be shared with adjacent SRAM cells. A second metal trace "M0 trace 2" includes a local metal line 180B, which serves as a pad for the write port word line (WWL). Local metal line 180B is entirely within SRAM cell 100 and is electrically connected to gate vias 150C and 150D. A third metal trace "M0 trace 3" includes three local metal lines 180C, 180D, and 180E. Local metal line 180C provides a pad for the write port bit line (WBL). Local metal line 180C extends beyond the left edge of SRAM cell 100 and can be shared with adjacent SRAM cells. Local metal line 180D is entirely within SRAM cell 100, belongs to a complementary memory node (SNB), and provides cross coupling between gate via 150E and source / drain contact via 170F. As described above, local metal line 180D crosses over gate structure 116. Local metal line 180E provides pads for write port complementary bit lines (WBLBs). Local metal line 180E extends beyond the right edge of SRAM cell 100 and can be shared with adjacent SRAM cells. A fourth metal trace "M0 trace 4" includes local metal line 180F, which belongs to a memory node (SN). Local metal line 180F is entirely within SRAM cell 100 and provides cross coupling between gate via 150F and source / drain contact via 170E. As described above, local metal line 180F crosses over gate structure 114. The fifth metal trace, "M0 trace 5", includes global metal line 180G, which is electrically coupled to the read port bit line (RBL) of source / drain contact via 170A. The sixth metal trace, "M0 trace 6", includes local metal line 180H. Local metal line 180H is entirely located within SRAM cell 100 and provides pads for the read port word line (RWL). The seventh metal trace, "M0 trace 7", includes global metal line 180I, which is electrically coupled to the V... SS Line. V SSLine 180I is located on the lower edge of SRAM cell 100 and can be shared with adjacent SRAM cells.

[0046] V DD The width of line 180A is denoted as w1. Half of w1 is located within an SRAM cell, and the other half of w1 is located within an adjacent SRAM cell. V SS The width of line 180I can be compared with V DD Line 180A is essentially the same, with half of w1 located within an SRAM cell and the other half located within an adjacent SRAM cell. The other M0 metal lines 180B-180H can all have the same width, denoted as w2. The spacing between two adjacent M0 metal lines can be uniform and denoted as s1. Therefore, the SRAM cell height H is equal to w1 + 5 * w2 + 6 * s1.

[0047] like Figure 6 As shown, within cell boundary 140, the layout space at level M0 accommodates two power lines (dedicated to V). DD and V SS A write port bit line (WBL) and a signal line (dedicated to the RBL in the illustrated embodiment) are provided within the cell boundary 140 of the SRAM cell 100. Other signal routing, such as write port bit lines (WBL) and write port complementary bit lines (WBLB), are provided in the form of bonding pads rather than signal lines. Accordingly, the signal lines other than the RBL are routed to higher interconnect layers.

[0048] refer to Figure 7 This diagram illustrates a simplified schematic layout of the device layer DL of an SRAM array (or simply array) 200. The array 200 is formed by repeating dual-port SRAM cells 100 in both the X and Y directions. Specifically, Figure 7 The layout corresponding to the eight SRAM cells is shown in two rows and four columns. The first row is designated as SRAM cells (or simply cells) 100A1, 100A2, 100A3, and 100A4, and the second row is designated as SRAM cells 100B1, 100B2, 100B3, and 100B4. For visual clarity and simplicity, only the active regions and gate structures in the device layer DL are shown.

[0049] Each cell in array 200 can be used as follows Figure 4The layout of unit 100 is shown. In some embodiments, two adjacent units in the Y direction are line-symmetric about their common boundary, and two adjacent units in the X direction are also line-symmetric about their common boundary. In the illustrated embodiment of array 200, unit 100B1 is a copy of unit 100A1, but mirrored across the X-axis; unit 100B2 is a copy of unit 100A2, but mirrored across the X-axis; unit 100B3 is a copy of unit 100A3, but mirrored across the X-axis; unit 100B4 is a copy of unit 100A4, but mirrored across the X-axis; unit 100A2 is a copy of unit 100A1, but mirrored across the X-axis. Arrayed along the Y-axis; Element 100A3 is a copy of Element 100A2, but mirrored across the Y-axis; Element 100A4 is a copy of Element 100A3, but mirrored across the Y-axis; Element 100B2 is a copy of Element 100B1, but mirrored across the Y-axis; Element 100B3 is a copy of Element 100B2, but mirrored across the Y-axis; Element 100B4 is a copy of Element 100B3, but mirrored across the Y-axis. Furthermore, the relationship between Element 100A3 and Element 100A1 corresponds to a translation of two element widths (2W) along the X-axis; the relationship between Element 100A4 and Element 100A2 corresponds to a translation of two element widths (2W) along the X-axis; the relationship between Element 100B3 and Element 100B1 corresponds to a translation of two element widths (2W) along the X-axis; the relationship between Element 100B4 and Element 100B2 corresponds to a translation of two element widths (2W) along the X-axis.

[0050] like Figure 7 As shown, in the first row, units 100A1-100A4 share the same active region 102 extending through the first row; units 100A1 and 100A2 share the same active region 104 extending through the boundary between them; and units 100A3 and 100A4 share the same active region 104 extending through the boundary between them. In the second row, units 100B1-100B4 share the same active region 102 extending through the second row; units 100B1 and 100B2 share the same active region 104 extending through the boundary between them; and units 100B3 and 100B4 share the same active region 104 extending through the boundary between them.

[0051] Now for reference Figure 8 According to one embodiment of this disclosure, Figure 8 A simplified schematic layout of conductive components at the contact (CO) level and via zero (V0) level of the multilayer interconnect structure disposed above the device layer DL of array 200 is depicted. For visual clarity, Figure 8The diagram reproduces some components of the device layer DL, such as the active region and gate structure, while only the gate vias and source / drain contacts of cells 100A1 and 100B1 are labeled with reference numerals. In each of cells 100A1-100A4 and 100B1-100B4, the diagram is repeated. Figure 5 The layout of the CO and V0 levels shown remains consistent with the above-mentioned... Figure 7 The cells have the same mirror arrangement and translation relationship. It is worth noting that the source / drain contact via 170A (electrically coupled to RBL) is located in the first row, but is not mirrored in the second row.

[0052] Two adjacent cells can share a common source / drain contact that extends longitudinally across their common boundary. Taking cells 100A and 100B as examples, cells 100A and 100B share a source / drain contact 160H electrically coupled to Vss, with a corresponding source / drain contact via 170H located at the common boundary between the two cells. Cells 100A and 100B also share a source / drain contact 160A electrically coupled to the read port bit line (RBL). In the illustrated embodiment, a corresponding source / drain contact via 170A is located within the boundary of cell 100A but not within cell 100B. The arrangement of contact vias 170H and 170A allows cells 100A and 100B to share a common Vss power line disposed above the common boundary between cells 100A and 100B, and to share a common RBL signal line disposed above cell 100A.

[0053] Figure 9 The conductive components at the metal zero (M0) level and via one (V1) level of the multilayer interconnect structure are shown. In each of cells 100A1-100A4 and 100B1-100B4, the following is repeated... Figure 6 The layout of the M0 level shown remains consistent with the above regarding... Figure 7 The units have the same mirror arrangement and translation relationship. For visual clarity, Figure 9 The gate via (VG) and contact via (VD) at the via zero (V0) level are reproduced, while only the M0 metal lines above cells 100A1 and 100B1 are marked with reference numerals.

[0054] Above the first and second rows, there are five global metal lines, including two V-shaped lines. DD Power cord, one V SS A power line, an RBL signal line, and a pseudo-metallic line. Cells in the first row share the first V with cells in the immediately preceding row. DD The power supply is 180A. The cells in the second row share the second voltage with the cells in the row immediately below. DDPower supply 180A. Cells in the first and second rows share V. SS Power line 180I. Cells in the first and second rows share the RBL signal line 180G, which is located above the first row and spaced apart from the second row. Cells in the second row are electrically coupled to the RBL signal line 180G above the first row via source / drain contacts 160A at the CO layer. Meanwhile, another metal line 180G above the second row is a pseudo-metal line because it lacks a corresponding source / drain contact via 170A located in the second row for its electrical connection. The pseudo-metal line is electrically floating, but it improves the uniformity of the metal lines at the M0 layer. The via at the V1 layer connects the V at the M0 layer... DD Power line 180A, WWL bonding pad 180B, WBL bonding pad 180C, WBLB bonding pad 180E, and RBL bonding pad 180H are electrically coupled to higher intermediate conductive components at the M1 level.

[0055] Figure 10 The conductive components at the metal layer (M1) and via layer (V2) of the multilayer interconnect structure are shown. For visual clarity, Figure 10 The vias at level V1 are reproduced, while only the M1 metal lines above cells 100A1 and 100B1 are shown using reference numerals. As previously described, the remaining M1 metal lines and V2 vias above cells 100A2-100A4 and 100B2-100B4 exhibit the same mirror arrangement and translational relationship relative to the corresponding metal lines and V2 vias above cells 100A1 and 100B1.

[0056] Taking cells 100A and 100B as examples, at the M1 level, bonding pad (or local metal line) 185A is electrically connected to the WBL via at the V1 level of the first and second rows, and bonding pad 185F is electrically connected to the WBLB via at the V1 level of the first and second rows. As will be discussed further below, by bonding pads 185A and 185F, the WBL and WBLB nodes in the first and second rows are electrically connected, thereby ensuring that the cells in the first and second rows can share common WBL and WBLB signal lines. Also at the M1 level, WWL signal line 185B is electrically connected to the WWL via at the V1 level of the cell in the first row, and WWL signal line 185C is electrically connected to the WWL via at the V1 level of the cell in the second row. In other words, one WWL signal line provides a first control signal that activates the write port in the cells of odd-numbered rows (e.g., the first row); another WWL signal line provides a second control signal that activates the write port in the cells of even-numbered rows (e.g., the second row). In this way, the write ports in the cells of odd-numbered and even-numbered rows can be controlled separately. Also at the M1 level, the bonding pad 185D is electrically connected to the V1 level. DD The via connects pad 185E to the RWL via at level V1. The via at level V2 connects pad 185A (WBL) to pad 185F (WBLB). DD The bonding pads 185D and 185E are further electrically coupled to higher intermediate conductive components at the M2 level.

[0057] Figure 11 The conductive components at the M2 layer of the multilayer interconnect structure are shown. For visual clarity, Figure 11 The vias at the V2 level are reproduced, while only the M2 metal lines above cells 100A1 and 100B1 are shown using reference numerals. As previously mentioned, the remaining M2 metal lines above cells 100A2-100A4 and 100B2-100B4 exhibit the same mirror arrangement and translational relationship relative to the corresponding metal lines above cells 100A1 and 100B1.

[0058] Above the first and second rows, there are seven global metal lines, including two VDD power lines, two WBL signal lines, two WBLB signal lines, and one pseudo-metal line. Cells in the first row share the first VDD power line with cells in the immediately above row. DD Power supply 190A. The cells in the second row share the second voltage with the cells in the row immediately below. DDPower line 190A. A pseudo-metal line 190E is positioned above the common boundary between cells in the first and second rows. The pseudo-metal line 190E is electrically floating but improves the uniformity of the metal lines at the M2 level. Above the first row, a first WBL signal line 190B is electrically connected to the WBL node in the cell of the first row and is also electrically coupled to the WBL node in the cell of the second row via bonding pad 185A at the M1 level. Above the first row, a first WBLB signal line 190C is electrically connected to the WBLB node in the cell of the first row and is also electrically coupled to the WBLB node in the cell of the second row via bonding pad 185F at the M1 level. Above the second row, a second WBL signal line 190B is electrically connected to the WBL node in the cell of the second row and is also electrically coupled to the WBL node in the cell of the first row via bonding pad 185A at the M1 level. Above the second row, the second WBLB signal line 190C is electrically connected to the WBLB node in the cell of the second row, and is also electrically coupled to the WBLB node in the cell of the first row via the bonding pad 185F at the M1 level. In other words, although each of the first and second rows includes its own set of WBL and WBLB signal lines, each row is also electrically coupled to the corresponding set of WBL and WBLB signal lines in the adjacent row via the bonding pad at the M1 level. As a result, each cell is electrically coupled to two WBL signal lines 190B of the two rows, and electrically coupled to two WBLB signal lines 190C of the two rows. Thus, the wiring resistance of the write port signal lines is reduced because two write port signal lines distributed across the two rows are used, instead of a single write port signal line located above a single row. Also at the M2 level, the RWL bonding pad 190D in each cell electrically couples the corresponding RWL via at the V2 level to an intermediate conductive component at a higher interconnect level. In the illustrated embodiment, the width of the WBL and WBLB signal lines is greater than V DD Width of the power lines. In some embodiments, the width of the WBL and WBLB signal lines is greater than the width of the metal line 190E. In some embodiments, the width of the WBL and WBLB signal lines is equal to the width of the metal line 190E.

[0059] Now for reference Figure 12 and Figure 13 . Figure 12 and Figure 13 Alternative implementations of the layout at the V2 and M2 levels are shown. Figure 12 and Figure 13 Many aspects of the conductive components at the V2 and M2 layers are similar to those described above. Figure 10 and Figure 11 The conductive components described are omitted here for the sake of brevity. Differences are discussed below. Figure 12As shown, the two WBL vias on WBL bonding pad 185A at the V2 level are both located above the first row, and the two WBLB vias on WBLB bonding pad 185F at the V2 level are both located above the second row. In other words, the WBL vias previously located above the second row have now moved to the first row, and the WBLB vias previously located above the first row have now moved to the second row. Figure 13 As shown, due to the relocation of the WBL and WBLB vias at the V2 level, metal line 190C in the first row is now electrically coupled to the WBL node instead of the WBLB node, and metal line 190B in the second row is now electrically coupled to the WBLB node instead of the WBL node. In other words, both WBL signal lines are located on the first row, but are still shared by cells in the first and second rows via the bonding pad 185A at the M1 level, and both WBLB signal lines are located on the second row, but are still shared by cells in the first and second rows via the bonding pad 185F at the M1 level.

[0060] For reference Figure 14 and Figure 15 . Figure 14 and Figure 15 Alternative implementations of the layout at the V2 and M2 levels are shown. Figure 14 and Figure 15 Many aspects of the conductive components at the V2 and M2 layers are similar to those described above. Figure 12 and Figure 13 The conductive components described are omitted here for brevity. The differences are discussed below. At the M2 level, relative to... Figure 13 The embodiment shown, Figure 15 The two adjacent WBL signal lines shown are now merged into a wider WBL signal line 190B, and the two adjacent WBLB signal lines are now merged into a wider WBLB signal line 190C. The wider WBL signal line 190B remains shared by the cells of the first and second rows via the bonding pad 185A at the M1 level, and the wider WBLB signal line 190C remains shared by the cells of the first and second rows via the bonding pad 185F at the M1 level. Using wider WBL and WBLB signal lines further reduces wiring resistance. The V2 level can remain as... Figure 12 The same as, or alternatively, can be as follows Figure 14 The V2 layer is shown, in which the number of WBL and WBLB vias can be reduced by half.

[0061] Now for reference Figure 16 and Figure 17 . Figure 16 and Figure 17Alternative embodiments of the layout at the V1, M1, V2, and M2 levels are shown. Figure 16 and Figure 17 Many aspects of the conductive components at the V1, M1, V2, and M2 layers are similar to those described above. Figure 10 and Figure 11 The conductive components described are omitted here for the sake of brevity. Differences are discussed below. Figure 16 As shown, the Vss via at the V1 level is located on the Vss metal line 180I at the M0 level, and the Vss bonding pad 185G is located on the common boundary between the first and second rows and is electrically coupled to the Vss via at the V1 level. Some WBL bonding pads (such as...) Figure 10 As shown, these WBL bonding pads, which previously extended across the common boundary between the first and second rows but now conflict with the location of the additional Vss bonding pad 185G, have been replaced by two separate WBL bonding pads 185A', one above the first row and the other above the second row. Similarly, some WBLB bonding pads (such as...) Figure 10 As shown, these WBLB bonding pads, which previously extended across the common boundary between the first and second rows (but now conflict with the location of the additional Vss bonding pad 185G), have been replaced by two separate WBLB bonding pads 185A'', one above the first row and the other above the second row. Figure 16 In the illustrated embodiment, a WBLB bonding pad 185F located between the first and second columns is retained and electrically connected to the WBLB signal line 190C at the M2 layer; and a WBL bonding pad 185A located between the second and third columns is retained and electrically connected to the WBL signal line 190B at the M2 layer. Figure 17 As shown, global metalline 190E is electrically connected to Vss bonding pad 185G. Accordingly, WBL signal lines 190B and WBLB signal lines 190C continue to be shared by the cells of both the first and second rows, while Vss power distribution is enhanced by an additional dedicated global metalline 190E.

[0062] For reference Figure 18 and Figure 19 . Figure 18 and Figure 19 Alternative embodiments of the layout at the V1, M1, V2, and M2 levels are shown. Figure 18 and Figure 19 Many aspects of the conductive components at the V1, M1, V2, and M2 layers are similar to those described above. Figure 16 and Figure 17The conductive components described are omitted here for the sake of brevity. Differences are discussed below. Figure 18 As shown, all WBL vias at the V2 level are located in the first row, and all WBLB vias at the V2 level are located in the second row. This allows the two WBL signal lines above the first row to now merge into a single wider WBL signal line 190B, and the two WBLB signal lines above the second row to now merge into a single wider WBLB signal line 190C. The wider WBL signal line 190B and the wider WBLB signal line 190C continue to be shared by the cells in both the first and second rows, while Vss power distribution is enhanced by an additional dedicated global metal line 190E.

[0063] like Figures 7 to 19 As shown in the embodiment, bonding pads 185A and 185F at the M1 level electrically connect the WBL and WBLB nodes of cells in two adjacent rows, thereby ensuring that cells in two adjacent rows can share the WBL and WBLB signal lines at the M2 level. This reduces the resistance on the write port bit lines (e.g., WBL and WBLB). Return to Reference Figure 8 and Figure 9 The RBL nodes of two adjacent rows of cells are electrically connected via source / drain contacts 160A, eliminating the need for M1 level bonding pads. Similarly, source / drain contacts can be used to provide electrical connections for the WBL and WBLB nodes of two adjacent rows of cells. Figures 20 to 24 This method is shown in more detail.

[0064] Now for joint reference Figures 20 to 24 .exist Figures 20 to 24 The diagram shows a simplified schematic layout of a portion of array 200, corresponding to four cells in a column of array 200, wherein the dual-port SRAM cell 100 is repeated four times along the Y direction. The four cells in this column are designated as cells 100A, 100B, 100C, and 100D. In some embodiments, cells 100A and 100B may correspond to... Figure 7 The array 200 shown contains cells 100A1 and 100B1. Each cell in array 200 can be configured as follows: Figure 4The layout of the device layer of the SRAM cell 100 is shown. In the illustrated embodiment of the columns in the array 200, the second cell 100B is a copy of the first cell 100A, but arranged in a mirror image across the X-axis. Similarly, the third cell 100C is a copy of the second cell 100B, arranged in a mirror image across the X-axis, and the fourth cell 100D is a copy of the third cell 100C, arranged in a mirror image across the X-axis. Furthermore, the third cell 100C corresponds to the first cell 100A translated two cell heights (2H) along the Y-direction, and the fourth SRAM cell 100D corresponds to the second cell 100B translated two cell heights (2H) along the Y-direction.

[0065] According to one embodiment of this disclosure, Figure 20 A simplified schematic layout of conductive components at the contact (CO) level and via zero (V0) level of the multilayer interconnect structure above the device layer DL of cells 100A-100D is shown. Figure 21 The conductive components at the metal zero (M0) level and via one (V1) level of the multilayer interconnect structure are shown. For visual clarity, Figure 21 The gate via (VG) and contact via (VG) at the via zero (V0) level are reproduced. Figure 22 The conductive components at the metal layer (M1) and via layer (V2) of the multilayer interconnect structure are shown. For visual clarity, Figure 22 The through-hole at level one (V1) is reproduced in the image. Figure 23 Conductive components at the metal layer two (M2) and via three (V3) levels of a multilayer interconnect structure are shown. For visual clarity, Figure 23 The through-hole at level two (V2) is reproduced in the image. Figure 24 Conductive components at the metal third (M3) layer of a multilayer interconnect structure are shown. For visual clarity, Figure 24 The through-hole at level three (V3) is reproduced. Similar to... Figures 9 to 19 As explained, metal traces in two adjacent Mx layers can be perpendicular. For example, in the illustrated embodiment, the metal traces in metal zero (M0) layer extend vertically in the X direction, the metal traces in metal one (M1) layer extend vertically in the Y direction, the metal traces in metal two (M2) layer extend vertically in the X direction, and the metal traces in metal three (M3) layer extend vertically in the Y direction.

[0066] exist Figure 20 and Figure 21In this context, many aspects of the conductive components at the contact (CO) level, via zero (V0) level, and metal zero (MO) level in each SRAM cell 100A-100D, as well as the active regions and gate structures in the device layer DL, are similar to those concerning... Figures 4 to 6 The corresponding structures in the SRAM cell 100 are described, and therefore, for the sake of brevity, their description is omitted here. The differences are discussed below. Figure 20 As shown, the electrical coupler is connected to V SS The source / drain contact via 170H is disposed on the boundary between two adjacent cells (e.g., the boundary between cells 100A and 100B, and the boundary between cells 100C and 100D). The source / drain contact via 170A electrically coupled to the read port bit line (RBL) is disposed above a cell (e.g., cells 100A and 100C) and is not located on the common boundary between two adjacent cells. Correspondingly, as... Figure 21 As shown, the global metal line 180I set on the boundary between two adjacent cells is V SS The global metal line 180G, extending through SRAM cells 100A or 100C, is electrically coupled to the source / drain contact via 170A and now serves as the read port bit line (RBL). Because the source / drain contact 160A still extends across the boundary between the two adjacent cells and is electrically coupled to both active regions, the global metal line 180G, serving as the RBL, is still shared by the two adjacent cells. It is worth noting that another global metal line 180G extending through SRAM cells 100B or 100C is electrically floating and becomes a pseudo-metal line. Figure 20 As shown, the source / drain contact 160C, electrically coupled to the write port bit line (WBL) via source / drain contact via 170C, extends across the boundary between two adjacent cells and is shared by the two adjacent cells. The source / drain contact 160D, electrically coupled to the write port complementary bit line (WBLB) via source / drain contact via 170D, extends across the boundary between two adjacent cells and is shared by the two adjacent cells. The source / drain contact vias 170C (electrically coupled to WBL) and 170D (electrically coupled to WBLB) are separately positioned above two different cells of the adjacent cells and are not aligned in the X or Y direction. This allows the two adjacent cells to share the WBL signal line and the WBLB signal line (e.g., in a...). Figure 23 (As shown in the M2 level).

[0067] like Figure 22As shown, at the metal one (M1) level, metal line 290A electrically connects to pad 180B at the metal zero (M0) level in units 100A and 100C for WWL, and metal line 290B electrically connects to pad 180B at the metal zero (M0) level in units 100B and 100D for WWL. This allows a column of cells to have two WWL signal lines 290A and 290B, enabling separate control of the write port word lines for even rows (e.g., units 100A and 100C) and odd rows (e.g., units 100B and 100D). The metal one (M1) level also includes a V-type connection at the metal zero (M0) level. DD The power cord is 180A and connected to V. DD The pad 290C will be placed at the V level of the metal zero (M0) layer. SS Power cord 180I is electrically connected to V SS The pad 290D is electrically connected to the pad 180H at the metal zero (M0) level to the pad 290E of the RWL, the pad 180C at the metal zero (M0) level is electrically connected to the pad 290F of the WBL, and the pad 180E at the metal zero (M0) level is electrically connected to the pad 290G of the WBLB.

[0068] like Figure 23 As shown, at the metal level 2 (M2), global metal line 295A extends above cell 100A and is shared as a WBLB signal line by cell 100A and adjacent cells above cell 100A. Global metal line 295B extends on the boundary between cells 100A and 100B and serves as a V SS The power supply line is shared by units 100A and 100B. Global metal line 295C extends above unit 100B and is shared by units 100B and 100C as a WBLB signal line. Global metal line 295D extends above unit 100C and is shared by units 100B and 100C as a WBL signal line. Global metal line 295E extends at the boundary between units 100C and 100D and serves as a V... SS The power lines are shared by cells 100C and 100D. A global metal line 295F extends above cell 100D and is shared by cell 100D and the adjacent cell immediately below cell 100D as a WBL signal line. Each of metal lines 295A through 295F is shared by two adjacent cells in the column. By sharing the signal lines for WBL and WBLB, the number of metal lines at the metal level (M2) can be reduced, allowing each metal line to have a larger width and a larger line-to-line spacing, thus contributing to reduced resistance and parasitic capacitance. In the illustrated embodiment, the width of metal lines 295A, 295C, 295D, and 295F can be approximately 1 / 3 to approximately 2 / 3 of the cell height H, and greater than V. SSLines 295B and 295E are wider. The Metal II (M2) layer also includes additional metal lines for electrical coupling to other nodes, including V... DD Power line 295G and RWL bonding pads 295H-295K. A via at the V3 level further electrically couples the RWL bonding pads 295H-295K to the intermediate conductive component at the M3 level.

[0069] Taking cells 100B and 100C as examples, the two cells 100B and 100C share a global metalline 295C as a common WBLB signal line and a global metalline 295D as a common WBL signal line. The global metalline 295C is disposed above cell 100B and spaced apart from the boundary of cell 100C, but is still electrically coupled to cell 100C through the lower interconnect layer, specifically through the source / drain contact 160D and source / drain contact via 170D shared by the two cells. Similarly, the global metalline 295D is disposed above cell 100C and spaced apart from the boundary of cell 100B, but is still electrically coupled to cell 100B through the lower interconnect layer, specifically through the source / drain contact 160C and source / drain contact via 170C. It is worth noting that, as... Figure 23 In the illustrated embodiment, units 100B and 100C share common WBL and WBLB signal lines at the M2 level, and a V signal line is provided between the common WBL and WBLB signal lines. DD The power supply line, while units 100B and 100A share the RBL signal line at the M1 level, and units 100C and 100D share the RBL signal line at the M1 level. In contrast, as Figures 8 to 19 In the illustrated embodiment, two adjacent cells in two adjacent rows share not only the WBL and WBLB signal lines at the M2 level, but also the RBL signal line at the M1 level. Furthermore, at the M2 level, what is stacked between the common WBL and WBLB metal lines is a Vss power line (or pseudo-metal line), instead of a V... DD Power cord.

[0070] like Figure 24As shown, at the M3 level, metal lines 298A and 298B extend through cells 100A-100D and are electrically coupled to RWL vias at the V3 level. The arrangement of the RWL vias at the V3 level allows metal line 298A to be electrically coupled to RWL nodes in cells 100A and 100C, and allows metal line 298B to be electrically coupled to RWL nodes in cells 100B and 100D. In other words, one RWL signal line provides a first control signal that activates the read ports in cells in odd-numbered rows (e.g., the first row), and another RWL signal line provides a second control signal that activates the read ports in cells in even-numbered rows (e.g., the second row), thereby ensuring separate control of the read ports in cells in odd-numbered and even-numbered rows.

[0071] Figure 25 A flowchart of an exemplary method 300 for manufacturing a memory device (such as an SRAM array 200) according to various embodiments of the present disclosure is shown. Method 300 includes block 302, where a precursor structure is received. The precursor structure may include a plurality of transistors. For example, the precursor structure may include transistors PU-1, PU-2, PD-1, PD-2, PG-1, PG-2, and R-PG for forming Figures 7 to 19 SRAM cells 100A1-A4 and 100B1-B4, and / or Figures 20 to 24The method 300 includes SRAM cells 100A-100D and other SRAM cells in SRAM array 200. Method 300 also includes block 304, where a contact interconnect layer (e.g., a CO layer) is formed over the precursor structure. The CO layer includes source / drain contacts (e.g., the aforementioned source / drain contacts 160A-160H). Method 300 also includes block 306, where a gate via is formed over the precursor structure. The gate via may include the aforementioned gate vias 150A-150F. Method 300 also includes block 308, where a source / drain contact via (e.g., source / drain contact vias 170A-170H) is formed over the corresponding source / drain contacts. Method 300 also includes block 310, where other interconnect layers of the multilayer interconnect structure MLI are formed above the front side of the substrate (e.g., metal zero (M0) interconnect layer (M0 level), via one (V1) interconnect layer (V1 level), metal one (M1) interconnect layer (M1 level), via two (V2) interconnect layer (V2 level), metal two (M2) interconnect layer (M2 level), via three (V3) interconnect layer (V3 level), metal three (M3) interconnect layer (M3 level)). In some embodiments, method 300 in forming one of the interconnect layers (e.g., at the M0 level) includes setting a read port bit line that extends over a cell but is shared by two adjacent cells in two adjacent rows. In some embodiments, method 300 in forming one of the interconnect layers (e.g., at the M1 level) includes setting a bonding pad that electrically connects the WBL and WBLB nodes of two cells in two adjacent rows. In a further embodiment, method 300 in forming one of the interconnect layers (e.g., at the M2 level) includes setting WBL and WBLB signal lines, which are electrically coupled to underlying WBL and WBLB bonding pads, respectively, such that the WBL and WBLB signal lines are shared by cells in two adjacent rows. In a further embodiment, vias for connecting the WBL and WBLB signal lines to the underlying interconnect layer are misaligned, thus allowing cells in two adjacent rows to share a common WBL and a common WBLB signal line. Method 300 is merely an example and is not intended to limit this disclosure to what is explicitly shown therein. Additional steps may be provided before, during, and / or after method 300, and some described steps may be replaced, eliminated, or moved for additional embodiments of the method. For brevity, not all steps are described in detail herein.

[0072] While not intended to be limiting, one or more embodiments of this disclosure provide numerous advantages for semiconductor devices and their fabrication. For example, this disclosure provides a memory array comprising memory cells arranged in rows and columns, together with a multilayer interconnect structure disposed above the memory array, to provide power and signal routing. In some embodiments, adjacent groups of memory cells may share one or more signal lines, thereby reducing routing requirements in the underlying interconnect layer and allowing signal lines, particularly bit lines, to have greater widths and / or greater line-to-line spacing. This arrangement can reduce the resistance and parasitic capacitance of the signal lines and improve the RC performance of the memory array.

[0073] In one exemplary aspect, this disclosure relates to a semiconductor structure. The semiconductor structure includes a device layer and a multilayer interconnect structure. The device layer includes a first active region of a first cell extending longitudinally in a first direction, wherein a first transistor and a second transistor share the first active region; a second active region of a second cell adjacent to the first cell, extending longitudinally in the first direction and spaced apart from the first active region in a second direction different from the first direction; a third transistor and a fourth transistor sharing the second active region; the first transistor, second transistor, third transistor, and fourth transistor include titanium-containing gate electrodes and an isolation structure intersecting the sidewalls of the first and second active regions, the top surface of the isolation structure being non-flat. The multilayer interconnect structure is disposed above the device layer. The multilayer interconnect structure includes: a first bonding pad extending along a second direction and passing through the boundary line between a first cell and a second cell, the first bonding pad being electrically coupled to the source / drain regions of a second transistor and a fourth transistor; a first metal line extending along a first direction and located above the second cell, the first metal line being electrically coupled to the first bonding pad; a second bonding pad being electrically coupled to the source / drain regions of the first transistor; and a second metal line extending along the first direction and located above the first cell, the second metal line being electrically coupled to the second bonding pad and also electrically coupled to the source / drain regions of a third transistor. The first and second bonding pads are located in a first interconnect layer of the multilayer interconnect structure, the first and second metal lines are located in a second interconnect layer of the multilayer interconnect structure, and the first interconnect layer is located below the second interconnect layer. In some embodiments, the second bonding pad is electrically coupled to the source / drain regions of the third transistor. In some embodiments, the multilayer interconnect structure further includes a third metal line extending along the first direction and located above the boundary line between the first cell and the second cell, and the third metal line is electrically floating. In some embodiments, the multilayer interconnect structure further includes a third bonding pad electrically coupled to the source / drain region of a third transistor. A second metal line is electrically coupled to the third bonding pad, and the third bonding pad is located in the first interconnect layer. In some embodiments, the multilayer interconnect structure further includes a third metal line extending along a first direction and located above the boundary line between the first cell and the second cell. The first metal line and the second metal line are signal lines, and the third metal line is a power line. In some embodiments, the widths of the first and second metal lines are greater than the width of the third metal line. In some embodiments, the first and second metal lines are signal lines carrying pairs of complementary signals. In some embodiments, the first cell and the second cell are dual-port memory cells, and the first and second metal lines are signal lines for the write ports of the first and second cells. In some embodiments, the first transistor, the second transistor, the third transistor, and the fourth transistor are pass-gate transistors.In some embodiments, the multilayer interconnect structure further includes a third metal line extending along a first direction and located above the first cell, the third metal line being electrically coupled to the first bonding pad; and a fourth metal line extending along the first direction and located above the second cell, the fourth metal line being electrically coupled to the source / drain region of the third transistor.

[0074] In another exemplary aspect, this disclosure relates to a memory array. The memory array includes: a first plurality of cells arranged in a first row of the memory array; a second plurality of cells arranged in a second row of the memory array; and a multilayer interconnect structure disposed above the cells in the first and second rows. Cells in the first row share a first active region extending longitudinally along a first direction. Cells in the second row share a second active region extending longitudinally along the first direction. The second row is adjacent to the first row along a second direction different from the first direction. The multilayer interconnect structure includes a plurality of interconnect layers. Each interconnect layer includes a metal line disposed in a dielectric layer. The thickness of the bottommost interconnect layer is less than the thickness of at least one interconnect layer above the bottommost interconnect layer. The multilayer interconnect structure includes a first signal line located in a first interconnect layer of the interconnect layer, wherein the first signal line extends along a first direction and is located above the cells in the first row; and a second signal line located in the first interconnect layer of the interconnect layer. The first signal line is electrically coupled to the cells in the first and second rows. The second signal line extends along the first direction and is located above the cells in the second row. The second signal line is electrically coupled to the cells in the first and second rows. The first signal line and the second signal line carry pairs of complementary signals. In some embodiments, the first signal line is a bit line, and the second signal line is a complementary bit line. In some embodiments, the cell is a two-port cell, and the first and second signal lines are signal lines for the write port of the cell. In some embodiments, the first interconnect layer of the interconnect layer is located above the bottommost interconnect layer of the interconnect layer. In some embodiments, the multilayer interconnect structure further includes a first plurality of bonding pads located in a second interconnect layer of the interconnect layer, and a second plurality of bonding pads located in the second interconnect layer of the interconnect layer. The first plurality of bonding pads extend along a second direction and cross the boundary between the first and second rows. The first plurality of bonding pads are electrically coupled to the cells in the first and second rows and electrically coupled to the first signal line. The second plurality of bonding pads extend along a second direction and cross the boundary between the first and second rows. The second plurality of bonding pads are electrically coupled to the cells in the first and second rows and electrically coupled to the second signal line. The second interconnect layer of the interconnect layer is located below the first interconnect layer of the interconnect layer. In some embodiments, the multilayer interconnect structure further includes a metal line located in the first interconnect layer of the interconnect layer. The metal line extends along a first direction and is located above the boundary between the first and second rows. The metal line is a power line or an electrically floating line. In some embodiments, the multilayer interconnect structure further includes a third signal line located in a first interconnect layer of the interconnect layer, and a fourth signal line located in the first interconnect layer of the interconnect layer. The third signal line extends along a first direction and is located above the cells in the second row. The third signal line is electrically coupled to the cells in the first and second rows. The first and third signal lines carry a first signal of a pair of complementary signals. The fourth signal line extends along the first direction and is located above the cells in the first row. The fourth signal line is electrically coupled to the cells in the first and second rows.The second and fourth signal lines carry a pair of complementary signals.

[0075] In another exemplary aspect, this disclosure relates to a method. The method includes: forming a first active region and a second active region extending longitudinally in a first direction; forming a first gate structure and a second gate structure bonded to the first active region to form a first transistor and a second transistor, respectively; and forming a third gate structure and a fourth gate structure bonded to the second active region to form a third transistor and a fourth transistor, respectively. The first gate structure, the second gate structure, the third gate structure, and the fourth gate structure extend longitudinally in a second direction different from the first direction. The first gate structure, the second gate structure, the third gate structure, and the fourth gate structure include a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The method further includes: depositing gate spacers along the sidewalls of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure. The thickness of the gate spacers is greater than the thickness of the gate dielectric layer. The dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacers. The method further includes: forming a first interconnect layer over the first transistor, the second transistor, the third transistor, and the fourth transistor. The first interconnect layer includes a first bonding pad extending along a second direction and electrically coupled to the source / drain regions of a first transistor and a third transistor, and a second bonding pad extending along the second direction and electrically coupled to the source / drain regions of a second transistor and a fourth transistor. The method also includes a second interconnect layer located above the first interconnect layer. The second interconnect layer includes a first metal line extending along a first direction and electrically coupled to the first bonding pad, and a second metal line extending along the first direction and electrically coupled to the second bonding pad. In some embodiments, the first metal line and the second metal line are signal lines carrying pairs of complementary signals. In some embodiments, the second interconnect layer further includes a third metal line disposed between the first metal line and the second metal line, and the widths of the first and second metal lines are greater than the width of the third metal line.

[0076] According to some embodiments of this disclosure, a semiconductor structure is disclosed, the semiconductor structure comprising: a device layer, the device layer comprising: a first active region of a first unit, the first active region extending longitudinally in a first direction; a first transistor and a second transistor sharing the first active region; a second active region of a second unit adjacent to the first unit, the second active region extending longitudinally in the first direction and spaced apart from the first active region in a second direction different from the first direction; a third transistor and a fourth transistor sharing the second active region, the first transistor, the second transistor, the third transistor, and the fourth transistor comprising a titanium-containing gate electrode; an isolation structure intersecting the sidewalls of the first active region and the second active region, the top surface of the isolation structure being uneven; and a multilayer interconnect structure disposed above the device layer, the multilayer interconnect structure comprising: a first... A bonding pad extends along a second direction and crosses the boundary line between the first and second units, electrically coupled to the source / drain regions of the second transistor and the source / drain regions of the fourth transistor; a first metal line extends along a first direction and is located above the second unit, electrically coupled to the first bonding pad; a second bonding pad is electrically coupled to the source / drain regions of the first transistor; and a second metal line extends along the first direction and is located above the first unit, electrically coupled to the second bonding pad and also electrically coupled to the source / drain regions of the third transistor, wherein the first and second bonding pads are located in the first interconnect layer of the multilayer interconnect structure, the first and second metal lines are located in the second interconnect layer of the multilayer interconnect structure, and the first interconnect layer is located below the second interconnect layer. In some embodiments, the second bonding pad is electrically coupled to the source / drain regions of the third transistor. In some embodiments, the multilayer interconnect structure further includes: a third metal line extending along the first direction and located above the boundary line between the first and second units, wherein the third metal line is electrically floating. In some embodiments, the multilayer interconnect structure further includes: a third bonding pad electrically coupled to the source / drain region of a third transistor, wherein a second metal line is electrically coupled to the third bonding pad, wherein the third bonding pad is located in the first interconnect layer. In some embodiments, the multilayer interconnect structure further includes: a third metal line extending along a first direction and located above the boundary line between the first cell and the second cell, wherein the first metal line and the second metal line are signal lines, and the third metal line is a power line. In some embodiments, the widths of the first and second metal lines are greater than the width of the third metal line. In some embodiments, the first and second metal lines are signal lines carrying pairs of complementary signals. In some embodiments, the first cell and the second cell are dual-port memory cells, and the first and second metal lines are signal lines for the write ports of the first and second cells. In some embodiments, the first transistor, the second transistor, the third transistor, and the fourth transistor are pass-gate transistors.In some embodiments, the multilayer interconnect structure further includes: a third metal line extending along a first direction and located above a first cell, the third metal line being electrically coupled to a first bonding pad; and a fourth metal line extending along a first direction and located above a second cell, the fourth metal line being electrically coupled to the source / drain region of a third transistor.

[0077] According to other embodiments of this disclosure, a memory array is disclosed, comprising: a first plurality of cells arranged in a first row of the memory array, wherein the cells in the first row share a first active region extending longitudinally along a first direction; a second plurality of cells arranged in a second row of the memory array, wherein the cells in the second row share a second active region extending longitudinally along the first direction, wherein the second row is adjacent to the first row along a second direction different from the first direction; and a multilayer interconnect structure disposed above the cells in the first and second rows, wherein the multilayer interconnect structure includes a plurality of interconnect layers, wherein each interconnect layer includes a metal line disposed in a dielectric layer, wherein... The thickness of the bottommost interconnect layer of the interconnect layer is less than the thickness of at least one interconnect layer above the bottommost interconnect layer of the interconnect layer. The multilayer interconnect structure includes: a first signal line located in the first interconnect layer of the interconnect layer, wherein the first signal line extends along a first direction and is located above cells in a first row, wherein the first signal line is electrically coupled to cells in the first and second rows; and a second signal line located in the first interconnect layer of the interconnect layer, wherein the second signal line extends along the first direction and is located above cells in a second row, wherein the second signal line is electrically coupled to cells in the first and second rows, wherein the first signal line and the second signal line carry a pair of complementary signals. In some embodiments, the first signal line is a bit line, and the second signal line is a complementary bit line. In some embodiments, the cell is a two-port cell, and the first and second signal lines are signal lines for the write port of the cell. In some embodiments, the first interconnect layer of the interconnect layer is located above the bottommost interconnect layer of the interconnect layer. In some embodiments, the multilayer interconnect structure further includes: a first plurality of bonding pads located in a second interconnect layer of the interconnect layer, wherein the first plurality of bonding pads extend along a second direction and cross the boundary between the first row and the second row, wherein the first plurality of bonding pads are electrically coupled to cells in the first row and the second row and electrically coupled to a first signal line; and a second plurality of bonding pads located in the second interconnect layer of the interconnect layer, wherein the second plurality of bonding pads extend along a second direction and cross the boundary between the first row and the second row, wherein the second plurality of bonding pads are electrically coupled to cells in the first row and the second row and electrically coupled to a second signal line, wherein the second interconnect layer of the interconnect layer is located below the first interconnect layer of the interconnect layer. In some embodiments, the multilayer interconnect structure further includes: a metal line located in the first interconnect layer of the interconnect layer, wherein the metal line extends along a first direction and is located above the boundary between the first row and the second row, wherein the metal line is a power line or an electrically floating line.In some embodiments, the multilayer interconnect structure further includes: a third signal line located in a first interconnect layer of the interconnect layer, wherein the third signal line extends along a first direction and is located above the cells of a second row, wherein the third signal line is electrically coupled to the cells in the first and second rows, wherein the first signal line and the third signal line carry a first signal of a pair of complementary signals; and a fourth signal line located in a first interconnect layer of the interconnect layer, wherein the fourth signal line extends along a first direction and is located above the cells of a first row, wherein the fourth signal line is electrically coupled to the cells in the first and second rows, wherein the second signal line and the fourth signal line carry a second signal of a pair of complementary signals.

[0078] According to further embodiments of this disclosure, a method for forming a semiconductor structure is disclosed. The method includes: forming a first active region and a second active region extending longitudinally in a first direction; forming a first gate structure and a second gate structure bonded to the first active region to form a first transistor and a second transistor, respectively; forming a third gate structure and a fourth gate structure bonded to the second active region to form a third transistor and a fourth transistor, respectively, wherein the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure extend longitudinally in a second direction different from the first direction, wherein the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure include a gate dielectric layer and a gate electrode disposed on the gate dielectric layer; and depositing along the sidewalls of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure. A gate spacer is formed, wherein the thickness of the gate spacer is greater than the thickness of the gate dielectric layer, and wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer; a first interconnect layer is formed on a first transistor, a second transistor, a third transistor, and a fourth transistor, the first interconnect layer including a first bonding pad and a second bonding pad, the first bonding pad extending along a second direction and electrically coupled to the source / drain regions of the first transistor and the third transistor, the second bonding pad extending along the second direction and electrically coupled to the source / drain regions of the second transistor and the fourth transistor; and a second interconnect layer is formed on the first interconnect layer, the second interconnect layer including a first metal line and a second metal line, the first metal line extending along a first direction and electrically coupled to the first bonding pad, the second metal line extending along the first direction and electrically coupled to the second bonding pad. In some embodiments, the first metal line and the second metal line are signal lines carrying pairs of complementary signals. In some embodiments, the second interconnect layer further includes a third metal line disposed between the first metal line and the second metal line, and the width of the first metal line and the second metal line is greater than the width of the third metal line.

[0079] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, comprising: A device layer comprising: a first active region of a first unit extending longitudinally in a first direction; a first transistor and a second transistor sharing the first active region; a second active region of a second unit adjacent to the first unit, extending longitudinally in the first direction and spaced apart from the first active region in a second direction different from the first direction; a third transistor and a fourth transistor sharing the second active region, the first transistor, the second transistor, the third transistor, and the fourth transistor comprising titanium-containing gate electrodes; and an isolation structure intersecting the sidewalls of the first active region and the second active region, the top surface of the isolation structure being non-flat; and A multilayer interconnect structure is disposed above the device layer. The multilayer interconnect structure includes: a first bonding pad extending along a second direction and passing through the boundary line between the first cell and the second cell, the first bonding pad being electrically coupled to the source / drain region of the second transistor and the source / drain region of the fourth transistor; a first metal line extending along the first direction and located above the second cell, the first metal line being electrically coupled to the first bonding pad; a second bonding pad being electrically coupled to the source / drain region of the first transistor; and a second metal line extending along the first direction and located above the first cell, the second metal line being electrically coupled to the second bonding pad and also electrically coupled to the source / drain region of the third transistor. The first bonding pad and the second bonding pad are located in the first interconnect layer of the multilayer interconnect structure, the first metal line and the second metal line are located in the second interconnect layer of the multilayer interconnect structure, and the first interconnect layer is located below the second interconnect layer.

2. The semiconductor structure according to claim 1, wherein, The second bonding pad is electrically coupled to the source / drain region of the third transistor.

3. The semiconductor structure according to claim 2, wherein, The multilayer interconnect structure further includes: A third metal wire extends along the first direction and is located above the boundary line between the first unit and the second unit, wherein the third metal wire is electrically levitated.

4. The semiconductor structure according to claim 1, wherein, The multilayer interconnect structure further includes: A third bonding pad is electrically coupled to the source / drain region of the third transistor, wherein the second metal line is electrically coupled to the third bonding pad, and wherein the third bonding pad is located in the first interconnect layer.

5. The semiconductor structure according to claim 4, wherein, The multilayer interconnect structure further includes: A third metal line extends along the first direction and is located above the boundary line between the first unit and the second unit, wherein the first metal line and the second metal line are signal lines and the third metal line is a power line.

6. The semiconductor structure according to claim 5, wherein, The widths of the first and second metal wires are greater than the width of the third metal wire.

7. The semiconductor structure according to claim 1, wherein, The first metal line and the second metal line are signal lines carrying pairs of complementary signals.

8. The semiconductor structure according to claim 7, wherein, The first unit and the second unit are dual-port memory units, and the first metal line and the second metal line are signal lines for the write ports of the first unit and the second unit, respectively.

9. A memory array, comprising: A plurality of cells are arranged in a first row of the memory array, wherein the cells in the first row share a first active region extending longitudinally along a first direction; A second plurality of cells are arranged in a second row of the memory array, wherein the cells in the second row share a second active region extending longitudinally along the first direction, wherein the second row is adjacent to the first row along a second direction different from the first direction; and A multilayer interconnect structure is disposed above the cells in the first and second rows, wherein the multilayer interconnect structure includes a plurality of interconnect layers, wherein each interconnect layer includes a metal line disposed in a dielectric layer, and wherein the thickness of the bottommost interconnect layer is less than the thickness of at least one interconnect layer above the bottommost interconnect layer. The multilayer interconnect structure includes: a first signal line located in a first interconnect layer of the interconnect layer, wherein the first signal line extends along the first direction and is located above the cell in the first row, wherein the first signal line is electrically coupled to the cell in the first row and the second row; and a second signal line located in the first interconnect layer of the interconnect layer, wherein the second signal line extends along the first direction and is located above the cell in the second row, wherein the second signal line is electrically coupled to the cell in the first row and the second row, wherein the first signal line and the second signal line carry a pair of complementary signals.

10. A method for forming a semiconductor structure, comprising: A first active region and a second active region are formed that extend longitudinally in the first direction; A first gate structure and a second gate structure are formed in conjunction with the first active region to form a first transistor and a second transistor, respectively; A third gate structure and a fourth gate structure are formed in conjunction with the second active region to form a third transistor and a fourth transistor, respectively. The first gate structure, the second gate structure, the third gate structure and the fourth gate structure extend longitudinally in a second direction different from the first direction. The first gate structure, the second gate structure, the third gate structure and the fourth gate structure include a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Gate spacers are deposited along the sidewalls of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure, wherein the thickness of the gate spacers is greater than the thickness of the gate dielectric layer, and wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacers. A first interconnect layer is formed over the first transistor, the second transistor, the third transistor, and the fourth transistor. The first interconnect layer includes a first bonding pad and a second bonding pad. The first bonding pad extends along a second direction and is electrically coupled to the source / drain regions of the first transistor and the third transistor. The second bonding pad extends along the second direction and is electrically coupled to the source / drain regions of the second transistor and the fourth transistor. A second interconnect layer is formed on top of the first interconnect layer. The second interconnect layer includes a first metal line and a second metal line. The first metal line extends along the first direction and is electrically coupled to the first bonding pad. The second metal line extends along the first direction and is electrically coupled to the second bonding pad.

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