Semiconductor structure and method of manufacturing the same, storage system

Abstract

This disclosure provides a semiconductor structure and its fabrication method, as well as a memory system, relating to the field of semiconductor technology, for improving leakage current in transistors within a semiconductor structure. The semiconductor structure includes: a semiconductor pillar array, gate structures, a first dielectric portion, and a first gap. The semiconductor pillars extend along a first direction. The first ends of a plurality of semiconductor pillars located in the same row are connected to each other. Along the row direction, two gate structures are located between two adjacent semiconductor pillars. Along the row direction, the first dielectric portion is located between two gate structures between two adjacent semiconductor pillars. The first gap is located between the first ends of two adjacent semiconductor pillars and the first dielectric portion. Along the first direction, the distance between the end face of the first dielectric portion near its first end and the end face of the gate structure near its first end is smaller than the distance between the end face of the first dielectric portion near its first end and the first end. The above semiconductor structure is used to implement data read and write operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, its fabrication method, and a memory system. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device that consists of multiple memory cells. A typical memory cell consists of a transistor and a capacitor. The capacitor stores data, and the transistor controls the reading of data from the capacitor.

[0003] With the development and advancement of technology, the size of semiconductor devices is becoming smaller and smaller. Semiconductor devices are constantly developing towards miniaturization and high integration, which also puts forward increasingly higher requirements for the storage performance of DRAM cells. Summary of the Invention

[0004] This disclosure provides a semiconductor structure, its fabrication method, and a memory system.

[0005] On one hand, a semiconductor structure is provided, comprising: a semiconductor pillar array, a plurality of gate structures, a plurality of first dielectric portions, and a plurality of first gaps. The semiconductor pillar array has each semiconductor pillar extending along a first direction. The first ends of the plurality of semiconductor pillars located in the same row are connected to each other. Along the row direction, two gate structures are located between two adjacent semiconductor pillars. The first direction intersects the row direction. Along the row direction, the first dielectric portions are located between two adjacent gate structures between two adjacent semiconductor pillars. The plurality of first gaps are located between the first ends of two adjacent semiconductor pillars and the first dielectric portions. Along the first direction, the distance between the end face of the first dielectric portion near its first end and the end face of the gate structure near its first end is less than the distance between the end face of the first dielectric portion near its first end and the first end.

[0006] In some embodiments, along the first direction, the distance between the end face of the first dielectric portion near the first end and the end face of the gate structure near the first end ranges from 0 nm to 20 nm.

[0007] In some embodiments, the gate structure includes a gate layer and a gate dielectric layer. Along the row direction, the gate dielectric layer is located between the gate layer and the semiconductor pillar. Along the first direction, the distance between the end face of the first dielectric portion near the first end and the end face of the gate layer near the first end is less than the distance between the end face of the first dielectric portion near the first end and the first end.

[0008] In some embodiments, along the first direction, the distance between the end face of the first dielectric portion near the first end and the end face of the gate layer near the first end ranges from 0 nm to 20 nm.

[0009] In some embodiments, the plane containing the end face of the gate layer near the first end is flush with the plane containing the end face of the gate dielectric layer near the first end.

[0010] In some embodiments, the system further includes: a plurality of first gaps. The first gaps are located between two adjacent rows of semiconductor pillars and on the side of the first dielectric portion near the first end. The first gaps communicate with the first voids.

[0011] In some embodiments, the semiconductor structure further includes a plurality of first insulating portions. The first insulating portions are located on the side of the gate structure near the first end. Along the row direction, the first insulating portions are also located between two adjacent semiconductor pillars and are disposed along the first ends of the adjacent two semiconductor pillars that are connected. The first gap is located between the first insulating portions and the first dielectric portion.

[0012] In some embodiments, along the first direction, the distance between the end face of the first dielectric portion near the first insulating portion and the end face of the gate structure near the first insulating portion is less than the distance between the end face of the first dielectric portion near the first insulating portion and the end face of the first insulating portion away from the gate structure.

[0013] In some embodiments, the semiconductor structure further includes a back gate and a second insulating portion. The back gate is located between two adjacent semiconductor pillars, and the back gate and the gate structures are arranged alternately in the row direction, with a semiconductor pillar disposed between an adjacent gate structure and the back gate. The second insulating portion is located on the side of the back gate near the first end.

[0014] In some embodiments, the system further includes a bit line located at the first end of a row of semiconductor pillars on the side away from the gate structure. The bit line extends along the row direction.

[0015] On the other hand, a method for fabricating a semiconductor structure is provided, comprising: forming a semiconductor pillar array, each of the semiconductor pillars extending along a first direction; first ends of a plurality of semiconductor pillars located in the same row being connected to each other; forming a plurality of gate structures, wherein the gate structures are located between two adjacent semiconductor pillars along the row direction; the first direction intersecting the row direction; forming a plurality of first dielectric portions, wherein the first dielectric portions are located between two adjacent gate structures between two adjacent semiconductor pillars along the row direction; and forming a plurality of first gaps, wherein the first gaps are located between the first ends of two adjacent semiconductor pillars and the first dielectric portions; and along the first direction, the distance between the end face of the first dielectric portion near the first end and the end face of the gate structure near the first end is less than the distance between the end face of the first dielectric portion near the first end and the first end.

[0016] In some embodiments, forming a plurality of gate structures, a plurality of first dielectric portions, and a plurality of first gaps includes: forming a first gate structure, which, along a row direction, is located between two adjacent semiconductor pillars and on one side of a first end where the two adjacent semiconductor pillars are connected; forming a second dielectric portion, one of which is located between the two adjacent semiconductor pillars and on the side of the first gate structure opposite to the semiconductor pillars; and forming a third dielectric portion, which is located between two adjacent rows of semiconductor pillars and on the side of the first gate structure away from the second dielectric portion.

[0017] In some embodiments, the fabrication method further includes: removing the portion of the third dielectric portion corresponding to the first end to expose the surface of the first gate structure; removing the portion of the first gate structure that contacts the first end connected to the two adjacent semiconductor pillars to expose the surface of the second dielectric portion near the first end; removing a portion of the second dielectric portion near the first end to form the first dielectric portion; and removing the portion of the first gate structure protruding from the first dielectric portion to form two gate structures and the first gap.

[0018] In some embodiments, the first gap is formed simultaneously during the formation of the first gap, the first dielectric portion, and the two gate structures. The first gap is located between two adjacent rows of semiconductor pillars and on the side of the first dielectric portion closer to the first end. The first gap communicates with the first gap.

[0019] In some embodiments, the fabrication method further includes forming a first insulating portion. The first insulating portion is located on the side of the gate structure near the first end. Along the row direction, the first insulating portion is also located between two adjacent semiconductor pillars and disposed along the first ends of the adjacent two semiconductor pillars that are connected. The first insulating portion and the first dielectric portion form the first gap. Two first insulating portions on the same side of two semiconductor pillars in two adjacent rows and located in the same column are separated by the first gap.

[0020] In some embodiments, during the formation of the first gate structure, the second dielectric portion, and the third dielectric portion, a plurality of back gates and a plurality of redundant portions are formed simultaneously. The back gates are located between two adjacent semiconductor pillars and between two adjacent first gate structures. The redundant portions are located on the side of the back gate closer to the first end and between two adjacent first gate structures. The redundant portions are removed simultaneously during the removal of the portion of the first gate structure protruding from the first dielectric portion.

[0021] In some embodiments, a second insulating portion is formed simultaneously during the formation of the first insulating portion. The second insulating portion is located on the side of the back gate near the first end. Two second insulating portions on the same side of two adjacent rows and in the same column of two back gates are separated by the first gap.

[0022] In another aspect, a semiconductor device is provided, comprising: a semiconductor structure, and peripheral devices. The semiconductor structure is the semiconductor structure described in any of the above embodiments. The peripheral devices are connected to the semiconductor structure.

[0023] In another aspect, a storage system is provided, comprising: a semiconductor device and a controller as described in the above embodiments. The controller is coupled to the semiconductor device to control the semiconductor device. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the products involved in the embodiments of this disclosure, the process of the manufacturing method, etc.

[0025] Figure 1 This is a structural diagram of an electronic device according to some embodiments of the present disclosure;

[0026] Figure 2 This is a structural diagram of a storage system according to some embodiments of the present disclosure;

[0027] Figure 3 This is a structural diagram of a semiconductor device according to some embodiments of the present disclosure;

[0028] Figure 4 This is a structural diagram of a semiconductor structure under different fabrication processes according to one implementation method;

[0029] Figure 5 This is a structural diagram of a semiconductor structure according to some embodiments of the present disclosure;

[0030] Figure 6 This is a flowchart illustrating the fabrication process of a semiconductor structure according to some embodiments of the present disclosure;

[0031] Figure 7 This is another fabrication flowchart of the semiconductor structure according to some embodiments of the present disclosure;

[0032] Figures 8-12 The following are cross-sectional views along the AA' direction of the semiconductor structures in some embodiments of this disclosure during different fabrication processes;

[0033] Figures 13-17 The following are cross-sectional views along the BB' direction of the semiconductor structures in some embodiments of this disclosure during different fabrication processes;

[0034] Figure 18 This is a graph showing the oxygen element detection results based on a semiconductor structure formed in one implementation method;

[0035] Figure 19 This is a graph showing the oxygen element detection results of a semiconductor structure according to some embodiments of the present disclosure. Detailed Implementation

[0036] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0037] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “horizontal,” “inner,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0038] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0039] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0040] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.

[0041] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0042] like Figure 1 As shown, some embodiments of this disclosure provide an electronic device 3000, which may include any device capable of storing data, such as a mobile phone, desktop computer, tablet computer, laptop computer, or server. The electronic device 3000 may include a storage system 1000 configured to implement data storage, as described below, and a circuit board 2000 electrically connected to the storage system. The circuit board 2000 is used to provide electrical signals, etc., to the storage system 1000.

[0043] like Figure 2As shown, some embodiments of this disclosure provide a storage system 1000. The storage system 1000 is used in the aforementioned electronic device 3000. The storage system 1000 includes a semiconductor device 100 and a controller 200. The controller 200 is coupled to the semiconductor device 100 and is used to control the semiconductor device 100 to store data.

[0044] The storage system 1000 can be integrated into various types of storage devices, for example, within the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other electronic device with memory.

[0045] In some examples, the storage system 1000 includes a controller 200 and a semiconductor device 100. The storage system 1000 may, for example, be integrated into a memory card. This memory card may include one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, Memory Stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0046] In other examples, such as Figure 2 As shown, the storage system 1000 includes a controller 200 and multiple semiconductor devices 100.

[0047] For example, the storage system 1000 includes a controller 200 and four semiconductor devices 100. The storage system 1000 may be integrated into a solid-state drive (SSD).

[0048] In some examples, in storage system 1000, controller 200 is configured to operate in low duty cycle environments, such as SD cards, CF cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0049] In other examples, in storage system 1000, controller 200 is configured to operate in high duty cycle environments using SSDs or eMMCs, which are used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0050] In some examples, controller 200 may be configured to manage data stored in semiconductor device 100 and communicate with external devices (e.g., a host).

[0051] In some examples, controller 200 can also be configured to control the operation of semiconductor device 100, such as read, erase, and program operations.

[0052] In some examples, controller 200 can also be configured to control semiconductor device 100 to store data.

[0053] In some examples, controller 200 may also be configured to manage various functions regarding data stored or to be stored in semiconductor device 100, including at least one of bad block management, garbage collection, logic-to-physical address translation, and wear leveling.

[0054] In some examples, controller 200 is also configured to process error correction codes for data read from or written to semiconductor device 100.

[0055] It is readily understood that controller 200 can also perform any other suitable function, such as formatting semiconductor device 100. For example, controller 200 can communicate with external devices (e.g., a host) via at least one of various interface protocols.

[0056] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0057] The controller 200 may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0058] In some examples, such as Figure 3 As shown, the semiconductor device 100 includes a semiconductor structure 10 and peripheral devices 20. The semiconductor structure 10 and peripheral devices 20 are interconnected. The semiconductor structure 10 can be a memory array.

[0059] For example, exemplarily, peripheral device 20 includes a substrate and a peripheral circuit layer. The peripheral circuit layer is located on the side of the substrate close to the semiconductor structure 10 and is electrically connected to the semiconductor structure 10; the peripheral circuit layer is configured to control and sense the memory array.

[0060] It should be noted that the types of the aforementioned peripheral circuit layers are diverse and can be selected according to actual needs. These peripheral circuit layers may include, for example, page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), or any active (or passive) components of the circuit (e.g., transistors, diodes, resistors, and capacitors).

[0061] The aforementioned peripheral circuit layer may include, for example, multiple transistors. Exemplarily, at least a portion of the transistors are formed in the substrate (e.g., below the top surface of the substrate), and / or directly on the substrate. The transistor may be a complementary metal-oxide-semiconductor (CMOS) transistor.

[0062] Furthermore, the aforementioned peripheral circuit layer may also include any other circuitry compatible with advanced logic processes. For example, the peripheral circuit layer may include logic circuitry (e.g., processors and programmable logic devices), and / or memory circuitry (e.g., static random access memory).

[0063] For example, the semiconductor device 100 further includes an interconnect layer. The interconnect layer is located between the peripheral device 20 and the semiconductor structure 10, and is used to realize the connection between the peripheral device 20 and the semiconductor structure 10.

[0064] In one implementation, such as Figure 4 As shown in (d), the semiconductor structure includes a gate structure 12' and a first dielectric portion 13' is provided in two adjacent gate structures 12'. The first dielectric portion 13' protrudes from the gate structure 12' and is located between two adjacent semiconductor pillars 11'. The first dielectric portion 13' has a large dimension along the first direction Z. Therefore, after the transistor composed of the gate structure and the semiconductor pillars is turned off, the charge accumulated on the first dielectric portion can easily migrate to the gate structure or migrate along the gate structure to the semiconductor pillars, causing leakage current in the transistor and easily affecting the storage performance of the semiconductor structure.

[0065] Based on this, such as Figure 5 , Figure 12 and Figure 18 As shown, an embodiment of this disclosure provides a semiconductor structure 10 including: a semiconductor pillar array, a plurality of gate structures 12, a plurality of first dielectric portions 13, and a plurality of first gaps 14.

[0066] like Figure 5 As shown, the semiconductor pillar array includes multiple semiconductor pillars 11, each extending along a first direction Z, and arranged in multiple rows and columns. For example, the multiple semiconductor pillars 11 are arranged in multiple rows along a second direction X and in multiple columns along a third direction Y. The row direction is the second direction X, and the column direction is the third direction Y. The first ends 110 of the multiple semiconductor pillars 11 located in the same row are connected to each other, forming a single structure.

[0067] The first direction Z, the second direction X, and the third direction Y intersect. For example, the first direction Z, the second direction X, and the third direction Y are perpendicular to each other.

[0068] For example, the material of semiconductor pillar 11 includes silicon, etc.

[0069] like Figure 5 and Figure 12 As shown, along the row direction X, two gate structures 12 are located between two adjacent semiconductor pillars 11. Along the row direction X, a first dielectric portion 13 is located between two adjacent gate structures 12 between two adjacent semiconductor pillars 11.

[0070] The material of the first dielectric portion 13 includes an insulating material, thereby isolating two adjacent gate structures 12 and preventing erroneous connections between them. For example, the material of the first dielectric portion 13 can be silicon oxide or the like.

[0071] For example, such as Figure 5As shown, semiconductor pillar 11 and adjacent gate structure 12 constitute transistor 101. Multiple transistors are arranged in multiple rows and columns. Multiple transistors 101 are arranged in multiple rows along a second direction X and in multiple columns along a third direction Y. Gate structures 12 in the same column of transistors 101 are connected to each other as a single structure. First dielectric portions 13 located between the gate structures 12 of two adjacent columns of transistors are connected to each other as a single structure, and the first dielectric portions 13 extend along a third direction Y.

[0072] like Figure 5 and Figure 12 As shown, the first gap 14 is located between the first ends 110 and the first dielectric portions 13 of two adjacent semiconductor pillars 11. The end face of the first dielectric portion 13 near the first end 110 forms the bottom wall of the first gap 14. For example, the distance between the end face of the first dielectric portion 13 near the first end 110 and the first end 110 is positively correlated with the size of the first gap 14 in the first direction Z. The greater the distance between the end face of the first dielectric portion 13 near the first end 110 and the first end 110, the larger the size of the first gap 14 in the first direction Z, and the larger the space occupied by the first gap 14.

[0073] For example, the end face of the first dielectric portion 13 near the first end 110 can be a plane, and the first end 110 of the semiconductor pillar 11 can also be a plane. Then, the distance between the end face of the first dielectric portion 13 near the first end 110 and the first end 110 is the dimension of the plane where the end face of the first dielectric portion 13 near the first end 110 is located and the plane where the first end 110 is located in the first direction Z.

[0074] For example, if one of the end face of the first dielectric portion 13 near the first end 110 and the first end 110 of the semiconductor pillar 11 is a non-planar surface (which can be a curved surface), and the other is a planar surface, then the distance between the end face of the first dielectric portion 13 near the first end 110 and the first end 110 is the distance between the lowest or highest point of the curved surface and the dimension of the planar surface in the first direction. If the first end 110 is a curved surface, and the curved surface is convex, then the distance between the end face of the first dielectric portion 13 near the first end 110 and the first end 110 is the distance between the highest point of the curved surface and the dimension of the planar surface in the first direction. If the first end 110 is a curved surface, and the curved surface is concave, then the distance between the end face of the first dielectric portion 13 near the first end 110 and the first end 110 is the distance between the lowest point of the curved surface and the dimension of the planar surface in the first direction.

[0075] For example, the end face of the first dielectric portion 13 near the first end 110 and the first end 110 of the semiconductor pillar 11 are both non-planar, and the non-planar can be curved. Then the distance between the end face of the first dielectric portion 13 near the first end 110 and the first end 110 is the minimum dimension of the two curved surfaces in the first direction.

[0076] Along the first direction Z, the distance between the end face of the first dielectric portion 13 near the first end 110 and the end face of the gate structure 12 near the first end 110 is smaller than the distance between the end face of the first dielectric portion 13 near the first end 110 and the first end 110.

[0077] Similarly, the spacing between the end face of the first dielectric portion 13 near the first end 110 and the end face of the gate structure 12 near the first end 110 can be defined with reference to the exemplary description of the spacing between the end face of the first dielectric portion 13 near the first end 110 and the first end 110 above, and will not be repeated here.

[0078] For example, the end face of the first dielectric portion 13 near the first end 110 may be flush or substantially flush with the end face of the gate structure 12 near the first end 110.

[0079] For example, the first dielectric portion 13 has a smaller size protruding from the gate structure 12 in the first direction Z near the end face of the first end 110.

[0080] Therefore, after the gate structure 12 receives the gate signal and controls the transistor 101 to turn off, due to the presence of the first gap 14, the distance between the end face of the first dielectric portion 13 near the first end 110 and the end face of the gate structure 12 near the first end 110 along the first direction Z is smaller than the distance between the end face of the first dielectric portion 13 near the first end 110 and the first end 110. This results in a smaller protrusion of the end face of the first dielectric portion 13 near the first end 110 out of the gate structure 12 in the first direction Z, resulting in less charge stored in the first dielectric portion 13. Furthermore, it makes it difficult for the charge stored in the first dielectric portion 13 to migrate to the gate structure or to the semiconductor pillar 11, making it difficult to form leakage current. This can improve the leakage phenomenon of the transistor after it is turned off, which is beneficial to reduce the impact of leakage current on the storage function of the semiconductor structure 10.

[0081] The embodiments of this disclosure provide a semiconductor structure 10 in which the first ends of a plurality of semiconductor pillars in the semiconductor structure 10 are connected to each other. Along the row direction X, a gate structure 12 is located between two adjacent semiconductor pillars 11, a first dielectric portion is located between two gate structures 12 between two adjacent semiconductor pillars, and a first gap 14 is provided between the first ends 110 of two adjacent semiconductor pillars 11 and the first dielectric portion 13. Along the first direction Z, the gap between the end face of the first dielectric portion 13 near the first end 110 and the end face of the gate structure 12 near the first end 110 is... The distance is smaller than the distance between the end face of the first dielectric portion 13 near the first end 110 and the first end 110. As a result, the size of the end face of the first dielectric portion 13 near the first end 110 protruding from the gate structure 12 in the first direction Z is smaller. This results in less charge stored in the first dielectric portion 13 and makes it difficult for the charge stored in the first dielectric portion 13 to migrate to the gate structure 12 or to the semiconductor pillar 11. This avoids leakage current when the transistor is turned off, thereby improving the leakage phenomenon of the transistor after it is turned off and improving the storage performance of the semiconductor structure 10.

[0082] For example, such as Figure 5 As shown, the semiconductor structure 10 also includes a bit line 15 located on the side of the first end 110 of a row of semiconductor pillars 11 away from the gate structure 12. The bit line 15 extends along the row direction X.

[0083] There are multiple bit lines 15, and these multiple bit lines 15 are arranged in a one-to-one correspondence with multiple rows of semiconductor pillars 11. The multiple bit lines 15 are arranged at intervals along the column direction Y. The bit lines 15 are electrically connected to the first end 110 of the semiconductor pillars 11. Thus, the first end 110 of the semiconductor pillars 11 can receive the electrical signals transmitted by the bit lines 15.

[0084] The presence of the first gap 14 reduces the capacitance of the parasitic capacitance between two adjacent bit lines 15, resulting in a smaller capacitance of the parasitic capacitance formed by the bit line 15 and the gate structure 12. Consequently, the electrical signal carried by the bit line 15 is less affected by the parasitic capacitance, leading to higher accuracy of the electrical signal carried by the bit line 15 and improved storage performance of the semiconductor structure 10.

[0085] In some examples, such as Figure 12 As shown, along the first direction Z, the distance between the end face of the first dielectric portion 13 near the first end 110 and the end face of the gate structure 12 near the first end 110 ranges from 0 nm to 20 nm.

[0086] For example, along the first direction Z, the distance between the end face of the first dielectric portion 13 near the first end 110 and the end face of the gate structure 12 near the first end 110 is in the range of 0nm to 5nm, 5nm to 12nm, 12nm to 18nm or 10nm to 20nm.

[0087] For example, along the first direction Z, the distance between the end face of the first dielectric portion 13 near the first end 110 and the end face of the gate structure 12 near the first end 110 is 0nm, 5nm, 10nm, 12nm, 18nm or 20nm.

[0088] like Figure 12 As shown, along the first direction Z, when the distance between the end face of the first dielectric portion 13 near the first end 110 and the end face of the gate structure 12 near the first end 110 is 0 nm, the end face of the first dielectric portion 13 near the first end 110 is flush with or approximately flush with the end face of the gate structure 12 near the first end 110.

[0089] By setting the aforementioned spacing range, the size of the first gap 14 in the first direction Z can be made larger, resulting in less charge stored in the first dielectric portion 13. This also makes it difficult for the charge stored in the first dielectric portion 13 to migrate to the gate structure 12 or the semiconductor pillar 11, preventing leakage current from forming when the transistor is turned off. This improves the leakage phenomenon after transistor turn-off and helps reduce the impact of leakage current on the storage function of the semiconductor structure 10. Furthermore, it allows for a smaller parasitic capacitance value between the bit line 15 and other structures (other structures can be other bit lines or gate structures, etc.). The electrical signal loaded on the bit line 15 is less affected by parasitic capacitance, resulting in higher accuracy of the electrical signal loaded on the bit line 15, which is beneficial for improving the storage performance of the semiconductor structure 10.

[0090] In some examples, such as Figure 5 As shown, the gate structure 12 includes a gate layer 121 and a gate dielectric layer 122. Along the row direction X, the gate dielectric layer 122 is located between the gate layer 121 and the semiconductor pillar 11.

[0091] For example, the material of the gate layer 121 can be a conductive material, such as a metal. Optionally, the material may include titanium nitride and tungsten.

[0092] For example, the material of the gate dielectric layer 122 can be an insulating material, such as silicon oxide.

[0093] For example, along the first direction Z, the size of the gate layer 121 is smaller than the size of the semiconductor pillar 11. Along the first direction Z, the size of the gate layer 121 is equal to or approximately equal to the size of the gate dielectric layer 122.

[0094] Along the first direction Z, the distance between the end face of the first dielectric portion 13 near the first end 110 and the end face of the gate layer 121 near the first end 110 is smaller than the distance between the end face of the first dielectric portion 13 near the first end 110 and the first end 110.

[0095] Therefore, the dimension of the end face of the first dielectric portion 13 protruding from the gate layer 121 in the first direction Z is smaller, resulting in less charge stored in the first dielectric portion 13. Furthermore, the charge stored in the first dielectric portion 13 is less likely to migrate to the gate layer 121 or to the semiconductor pillar 11, making leakage current less likely. This improves the leakage phenomenon of the transistor after turn-off, and helps reduce the impact of leakage current on the storage function of the semiconductor structure 10. Additionally, the electrical signal loaded on the bit line 15 is less affected by parasitic capacitance, which helps improve the storage performance of the semiconductor structure 10.

[0096] For example, such as Figure 5 As shown, along the first direction Z, the distance between the end face of the first dielectric portion 13 near the first end 110 and the end face of the gate layer 121 near the first end 110 ranges from 0 nm to 20 nm.

[0097] For example, along the first direction Z, the distance between the end face of the first dielectric portion 13 near the first end 110 and the end face of the gate layer 121 near the first end 110 is in the range of 0nm to 5nm, 5nm to 12nm, 12nm to 18nm or 10nm to 20nm.

[0098] For example, along the first direction Z, the distance between the end face of the first dielectric portion 13 near the first end 110 and the end face of the gate layer 121 near the first end 110 is 0nm, 5nm, 10nm, 12nm, 18nm or 20nm.

[0099] When the distance between the end face of the first dielectric portion 13 near the first end 110 and the end face of the gate layer 121 near the first end 110 along the first direction Z is 0 nm, the end face of the first dielectric portion 13 near the first end 110 is flush with or approximately flush with the end face of the gate layer 121 near the first end 110.

[0100] By setting the aforementioned spacing range, the size of the first gap 14 in the first direction Z can be made larger, resulting in less charge stored in the first dielectric portion 13. This also makes it difficult for the charge stored in the first dielectric portion 13 to migrate to the gate layer 121 or to the semiconductor pillar 11, preventing leakage current formation when the transistor is turned off. This improves the leakage phenomenon after transistor turn-off and helps reduce the impact of leakage current on the storage function of the semiconductor structure 10. Furthermore, it allows for a smaller parasitic capacitance value between the bit line 15 and other structures (other structures can be other bit lines or gate structures, etc.). The electrical signal loaded on the bit line 15 is less affected by parasitic capacitance, resulting in higher accuracy of the electrical signal loaded on the bit line 15, which is beneficial for improving the storage performance of the semiconductor structure 10.

[0101] For example, such as Figure 5 As shown, the plane of the end face of the gate layer 121 near the first end 110 is flush with the plane of the end face of the gate dielectric layer 122 near the first end 110.

[0102] Therefore, in the process of preparing the gate structure 12, the end face of the gate dielectric layer 122 near the first end 110 can be formed first, and then the end face of the gate layer 121 near the first end 110 can be formed based on this end face, thereby simplifying the preparation process of the gate structure 12.

[0103] In some embodiments, such as Figure 5 and Figure 12 As shown, the semiconductor structure 10 further includes a plurality of first insulating portions 16. The first insulating portions 16 are located on the side of the gate structure 12 near the first end 110. Along the row direction X, the first insulating portions 16 are also located between two adjacent semiconductor pillars 11 and are disposed along the first ends 110 connecting the two adjacent semiconductor pillars 11. For example, the first insulating portions 16 are disposed along two opposite sides of two adjacent semiconductor pillars 11 and the first ends 110 connecting the two adjacent semiconductor pillars 11. In the plane containing the second direction X and the first direction Z, the cross-sectional shape of the first insulating portion 16 is an inverted "U" shape or approximately an inverted "U" shape (see reference). Figure 12 ).

[0104] The aforementioned first gap 14 is located between the first insulating portion 16 and the first dielectric portion 13. For example, the end face of the first insulating portion 16 away from the semiconductor pillar 11 forms the top wall and side wall of the first gap 14, and the end face of the first dielectric portion 13 near the first end 110 forms the bottom wall of the first gap 14.

[0105] In some examples, along the first direction Z, the distance between the end face of the first dielectric portion 13 near the first insulating portion 16 and the end face of the gate structure 12 near the first insulating portion 16 is smaller than the distance between the end face of the first dielectric portion 13 near the first insulating portion 16 and the end face of the first insulating portion 16 away from the gate structure 12.

[0106] It is understood that the end face of the first dielectric portion 13 near the first insulating portion 16 can be planar or non-planar, and the non-planar surface can be curved. Similarly, the end face of the gate structure 12 near the first insulating portion 16 can be planar or non-planar, and the non-planar surface can be curved. The end face of the first insulating portion 16 away from the gate structure 12 can be planar or non-planar, and the non-planar surface can be curved.

[0107] Along the first direction Z, the distance between the end face of the first dielectric portion 13 near the first insulating portion 16 and the end face of the gate structure 12 near the first insulating portion 16 can be the minimum distance between two curved surfaces, the distance between two planes, or the minimum distance between a plane and a curved surface. Similarly, the distance between the end face of the first dielectric portion 13 near the first insulating portion 16 and the end face of the first insulating portion 16 away from the gate structure 12 can be the minimum distance between two curved surfaces, the distance between two planes, or the minimum distance between a plane and a curved surface.

[0108] This results in a larger size of the first gap 14 in the first direction Z, which reduces the amount of charge stored in the first dielectric portion 13 and makes it difficult for the charge stored in the first dielectric portion 13 to migrate to the gate structure 12 or to the semiconductor pillar 11. This avoids leakage current when the transistor is turned off, thereby improving the leakage phenomenon of the transistor after it is turned off and improving the storage performance of the semiconductor structure 10.

[0109] In some examples, such as Figure 5 As shown, the semiconductor structure 10 further includes a plurality of first gaps 17. The first gaps 17 are located between two adjacent rows of semiconductor pillars 11 and on the side of the first dielectric portion 13 near the first end 110. For example, the opposing sides of the two adjacent rows of semiconductor pillars 11 form the two sidewalls of the first gap 17, and the end face of the first dielectric portion 13 near the first end 110 forms the bottom wall of the first gap 17. The first gaps 17 extend along a second direction X.

[0110] The first gap 17 is connected to the first void 14. Therefore, the capacitance value of the parasitic capacitance formed by the adjacent bit line 15 or the bit line 15 and other structures can be further reduced by the first gap 17, so that the accuracy of the electrical signal loaded by the bit line 15 is higher, which is beneficial to improving the storage performance of the semiconductor structure 10.

[0111] In some embodiments, such as Figure 5 and Figure 12 As shown, the semiconductor structure 10 also includes a back gate 18 and a second insulating portion 19.

[0112] The back gate 18 is located between two adjacent semiconductor pillars 11. The back gate 18 and the two gate structures 12 are arranged alternately in the row direction X. A semiconductor pillar 11 is disposed between an adjacent gate structure 12 and the back gate 18. The second insulating portion 19 is located on the side of the back gate 18 near the first end 110.

[0113] Therefore, the threshold voltage of the transistor can be adjusted using the back gate 18. For example, a negative voltage can be applied to the back gate 18 to reduce the leakage current of the transistor in the off state, thereby improving the storage performance of the semiconductor structure 10.

[0114] In some examples, the semiconductor structure 10 also includes a storage capacitor. The storage capacitor is connected to the transistor described above, and the storage capacitor and the connected transistor constitute a storage cell of the semiconductor structure for receiving electrical signals transmitted from the peripheral circuit to realize the storage function.

[0115] In another implementation, such as Figure 4 As shown, the method for fabricating the semiconductor structure 10 includes: (Refer to...) Figure 4 In section (a), a first gate structure 120', a semiconductor pillar 11', and a second dielectric portion 131' are formed, as shown in reference. Figure 4 In section (b), along the location indicated by the dashed line, remove a portion of the third dielectric layer (located between two adjacent rows of semiconductor pillars, not shown in the figure), referring to... Figure 4 In section (c), a portion of the first gate structure 120' and a portion of the second dielectric portion 131' are removed, as shown in the reference section. Figure 4 In section (d), a gate structure 12' and a first dielectric portion 13' are formed. The first dielectric portion 13' protrudes from the gate structure 12' and is located between two adjacent semiconductor pillars 11'. The first dielectric portion 13' has a large dimension along the first direction Z. Therefore, after the transistor composed of the gate structure and semiconductor pillars is turned off, the charge accumulated on the first dielectric portion can easily migrate to the gate structure or migrate along the gate structure to the semiconductor pillars, causing leakage current in the transistor and easily affecting the storage function of the semiconductor structure.

[0116] Based on this, some embodiments of this disclosure also provide a method for preparing a semiconductor structure 10, for preparing the semiconductor structure 10 described in any of the above embodiments.

[0117] in, Figure 6 and Figure 7 Flowcharts showing two methods for fabricating the semiconductor structure 10 provided in some embodiments of this disclosure. Figures 8 to 17These are structural diagrams corresponding to each step in the fabrication method of the semiconductor structure 10 according to some embodiments. It should be understood that... Figure 6 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Furthermore, some steps may be performed simultaneously, or they may be performed in a sequence different from the steps described. Figure 6 The execution is carried out in the order shown. Similarly, Figure 7 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Furthermore, some steps may be performed simultaneously, or they may be performed in a sequence different from the steps described. Figure 7 The execution is performed in the order shown.

[0118] like Figure 6 As shown, the preparation method includes: A100 to A400.

[0119] A100, such as Figure 8 As shown, a semiconductor pillar array is formed, with each semiconductor pillar 11 extending along a first direction Z. The first ends 110 of the multiple semiconductor pillars 11 located in the same row are connected to each other.

[0120] A200, such as Figures 9-11 As shown, multiple gate structures 12 are formed along the row direction X, with each gate structure 12 located between two adjacent semiconductor pillars 11. The first direction Z intersects the row direction X.

[0121] A300, such as Figure 11 As shown, a plurality of first dielectric portions 13 are formed along the row direction X, and the first dielectric portions 13 are located between two adjacent gate structures 12 between two adjacent semiconductor pillars 11.

[0122] A400, such as Figure 11 and Figure 12 As shown, a plurality of first gaps 14 are formed, and the first gaps 14 are located between the first ends 110 and the first dielectric portions 13 of two adjacent semiconductor pillars 11. Along the first direction Z, the distance between the end face of the first dielectric portion 13 near the first end 110 and the end face of the gate structure 12 near the first end 110 is smaller than the distance between the end face of the first dielectric portion 13 near the first end 110 and the first end 110.

[0123] For example, the structure of the first gap 14, the first dielectric portion 13 and the two gate structures 12 can be referred to the description in some of the embodiments of this disclosure above, and will not be repeated here.

[0124] The embodiments of this disclosure provide a method for fabricating a semiconductor structure 10, including forming a first gap 14, a first dielectric portion 13, and two gate structures 12 in the semiconductor structure 10, such that the first ends 110 of a plurality of semiconductor pillars 11 in the semiconductor structure 10 are connected to each other. Along the row direction X, the gate structure 12 is located between two adjacent semiconductor pillars 11, the first dielectric portion 13 is located between two gate structures 12 between two adjacent semiconductor pillars 11, and the first gap 14 is located between the first ends 110 of two adjacent semiconductor pillars 11 and the first dielectric portion 13. Along the first direction Z, the end face of the first dielectric portion 13 near the first end 110 is close to the end face of the gate structure 12 near the first end 110. The spacing between the end faces on one side of the first end 110 is smaller than the spacing between the end face of the first dielectric portion 13 near the first end 110 and the first end 110. As a result, in the semiconductor structure 10 formed, the dimension of the end face of the first dielectric portion 13 near the first end 110 protruding from the gate structure 12 in the first direction Z is smaller. This results in less charge stored in the first dielectric portion 13 and makes it difficult for the charge stored in the first dielectric portion 13 to migrate to the gate structure 12 or to the semiconductor pillar 11. This avoids the formation of leakage current when the transistor is turned off, thereby improving the leakage phenomenon of the transistor after it is turned off and helping to reduce the impact of leakage current on the storage function of the semiconductor structure 10.

[0125] In some examples, the above fabrication method further includes forming multiple gate structures 12, multiple first dielectric portions 13, and multiple first voids 14, as well as:

[0126] A first gate structure 123 is formed along the row direction X. The first gate structure 123 is located between two adjacent semiconductor pillars 11 and on one side of the first end 110 where the two adjacent semiconductor pillars 11 are connected.

[0127] A second dielectric portion 131 is formed, which is located between two adjacent semiconductor pillars 11 and on the side of the first gate structure 123 away from the semiconductor pillars 11.

[0128] A third dielectric portion 132 is formed, which is located between two adjacent rows of semiconductor pillars 11 and on the side of the first gate structure 123 away from the second dielectric portion 131.

[0129] For example, in the plane containing the first direction Z and the row direction X, the cross-sectional shape of the first gate structure 123 is an inverted "U" shape or approximately an inverted "U" shape.

[0130] For example, the material of the second dielectric portion 131 can be an insulating material, such as silicon oxide.

[0131] For example, the material of the third dielectric portion 132 can be an insulating material, such as silicon oxide.

[0132] For example, the first gate structure 123 includes a first gate layer and a first gate dielectric layer stacked together. The first gate layer is made of a conductive material, and the first gate dielectric layer is made of an insulating material. In the plane containing the first direction Z and the second direction X, the cross-sectional shapes of the first gate layer and the first gate dielectric layer are the same or substantially the same.

[0133] For example, the steps of forming the first gate structure 123, the second dielectric portion 131, and the third dielectric portion 132 described above can be performed before the A100 step described above.

[0134] In some embodiments, such as Figure 8 and Figure 13 As shown, during the process of forming the first gate structure 123, the second dielectric portion 131 and the third dielectric portion 132, a plurality of back gates 18 and a plurality of redundant portions 181 are formed simultaneously.

[0135] Specifically, a chemical vapor deposition process can be used to form a third dielectric layer, and an etching process can be used to etch the third dielectric layer to form multiple third dielectric portions 132. For example, refer to... Figure 13 The cross-sectional shape of the multiple third medium sections 132 can be consistent with... Figure 8 The cross-sectional shapes of the multiple semiconductor pillars 11 are the same or similar. Then, a first gate dielectric layer can be formed on the two opposite sidewalls of two adjacent semiconductor pillars 11 using a chemical vapor deposition process. Then, a first gate layer and a redundancy portion are simultaneously formed using a sputtering process, wherein the first gate dielectric layer and the first gate layer constitute a first gate structure 123. Next, a stop layer 182 is formed on the back gate using a chemical vapor deposition process, and a back gate 18 is formed using a sputtering process. Then, a second dielectric portion 131 can be formed using a chemical vapor deposition process.

[0136] The back gate 18 is located between two adjacent semiconductor pillars 11 and between two adjacent first gate structures 123. The redundancy portion 181 is located on the side of the back gate 18 near the first end 110 and between two adjacent first gate structures 123.

[0137] For example, a stop layer 182 is also provided between the back gate 18 and the redundancy portion 181. For example, the material of the stop layer 182 can be nickel nitride or the like.

[0138] For example, the material of the back gate 18 is the same as the material of the gate layer 121.

[0139] like Figure 7As shown, in the above A100, the formation of the first gap 14, the first dielectric portion 13 and the gate structure 12 includes: A110 to A140.

[0140] A110, combined Figure 8 and Figure 14 Remove the portion of the third dielectric portion 132 corresponding to the first end 110 to expose the surface of the first gate structure 123.

[0141] For example, a mask and etching process are used to remove the portion of the third dielectric portion 132 corresponding to the first end 110. For example, the thickness of the third dielectric portion 132 removed by etching along the first direction Z can be 60 nm.

[0142] For example, the thickness of the mask can be around 20 nm, and the mask can be a hard mask, the material of which can include titanium nitride, etc.

[0143] A120, such as Figure 9 and Figure 15 As shown, the portion of the first gate structure 123 that is in contact with the first end 110 connected to the two adjacent semiconductor pillars 11 is removed, exposing the surface of the second dielectric portion 131 near the first end 110.

[0144] For example, the thickness of the first gate structure 123 is about 20 nm.

[0145] For example, using an etching process and the same mask described above, a portion of the first gate structure 123 is removed. After the steps of A110 described above, the mask is thinned to a thickness of approximately 10 nm.

[0146] like Figure 9 As shown, during the process of removing a portion of the first gate structure 123 in the above-mentioned A120, a portion of the redundant portion 181 is simultaneously removed, so that the end face of the redundant portion 181 near the first end is flush or approximately flush with the end face of the first gate structure 123 near the first end.

[0147] A130, such as Figure 10 and Figure 16 As shown, a portion of the second medium portion 131 near the first end 110 is removed to form the first medium portion 13.

[0148] For example, an etching process can be used to remove a portion of the second dielectric portion 131 near the first end 110 to form the first dielectric portion 13.

[0149] For example, along the first direction Z, the size of the removed second dielectric portion 131 can be approximately 35 nm.

[0150] For example, the first gate structure 123 includes a first gate layer and a first gate dielectric layer. During the process of removing a portion of the second dielectric portion 131 near the first end 110, a portion of the first gate dielectric layer near the first end is simultaneously removed to form a gate dielectric layer 122. The end face of the gate dielectric layer 122 near the first end is in the same plane or approximately in the same plane as the end face of the first dielectric portion 13 near the first end.

[0151] like Figure 16 As shown, during the process of removing a portion of the second medium portion 131 near the first end 110 in the above A130, a portion of the third medium portion 132 is removed again, such that the plane of the end face of the third medium portion 132 near the first end is in the same plane or approximately in the same plane as the plane of the end face of the first medium portion 13 near the first end.

[0152] A140, such as Figure 11 and Figure 17 As shown, the portion of the first gate structure 123 that protrudes from the first dielectric portion 13 is removed, forming two gate structures 12 and a first gap 14.

[0153] For example, an etching process can be used to remove the portion of the first gate structure 123 that protrudes from the first dielectric portion 13. For instance, the portion of the first gate layer in the first gate structure 123 that protrudes from the first dielectric portion 13 can be removed to form a gate layer 121.

[0154] like Figure 11 and Figure 17 As shown, in A140, during the process of removing the portion of the first gate structure 123 that protrudes from the first dielectric portion 13, the redundant portion 181 is removed simultaneously. This simplifies the fabrication process of the semiconductor structure 10.

[0155] It should be understood that, among them, Figures 8 to 17 These are structural diagrams corresponding to each step in the fabrication method of the semiconductor device 100 according to some embodiments. These structural diagrams are schematic diagrams.

[0156] In some examples, combined Figure 5 and Figure 17 During the formation of the first gap 14, the first dielectric portion 13, and the two gate structures 12, the first gap 17 is formed simultaneously. The first gap 17 is located between two adjacent rows of semiconductor pillars 11 and is located on the side of the first dielectric portion 13 near the first end 110. The first gap 17 is connected to the first gap 14.

[0157] This simplifies the fabrication process of semiconductor structure 10.

[0158] In some embodiments, such as Figure 12 As shown, the method for fabricating the semiconductor structure 10 further includes:

[0159] A first insulating portion 16 is formed. The first insulating portion 16 is located on the side of the gate structure 12 near the first end 110. Along the row direction X, the first insulating portion 16 is also located between two adjacent semiconductor pillars 11, and is disposed along the first ends 110 where the two adjacent semiconductor pillars 11 connect. The first insulating portion 16 and the first dielectric portion 13 form a first gap 14. Figure 5 As shown, two first insulating portions 16 on the same side of two adjacent rows and located in the same column of semiconductor pillars 11 are separated by a first gap 17.

[0160] In some embodiments, such as Figure 12 As shown, the second insulating part 19 is formed simultaneously during the formation of the first insulating part 16.

[0161] The second insulating portion 19 is located on the side of the back grid 18 near the first end 110. The two second insulating portions 19 on the same side of the two adjacent rows and the same column of the back grid 18 are separated by a first gap 17.

[0162] For example, a gap may exist within the second insulating part 19.

[0163] For example, a chemical vapor deposition process can be used to simultaneously form the first insulating portion 16 and the second insulating portion 19.

[0164] In addition, the inventors tested the oxygen content and leakage current in the semiconductor structure. The materials used for the first dielectric layer and the gate dielectric layer in the semiconductor structure are both silicon oxide. Figure 18 This is a graph showing the oxygen element detection results of the semiconductor structure formed in one of the above implementation methods. Figure 18 In the middle, the first dielectric portion 13' protrudes from the gate dielectric layer 122', and the leakage current of the semiconductor structure is detected, and the leakage current is relatively large. Figure 19 This is a graph showing the detection results of a semiconductor structure prepared using the methods described in the embodiments of this disclosure. Figure 19 In this structure, the first dielectric portion 13 is approximately flush with the gate dielectric layer 122, and the distance between the end face of the first dielectric portion 13 near the first end and the end face of the gate dielectric layer 122 near the first end is small. Leakage current detection of this semiconductor structure shows a small leakage current. Therefore, the semiconductor structure 10 provided by the embodiments of this disclosure can effectively reduce leakage current, alleviate leakage phenomena in transistors within the semiconductor structure, and improve the storage performance of the semiconductor structure.

[0165] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A semiconductor pillar array, wherein each of the semiconductor pillars extends along a first direction; The first ends of the plurality of semiconductor pillars located in the same row are connected to each other; Multiple gate structures are arranged along the row direction, with each gate structure located between two adjacent semiconductor pillars; the first direction intersects the row direction. A plurality of first dielectric portions are located along the row direction, and the first dielectric portions are located between two adjacent gate structures between two adjacent semiconductor pillars; Multiple first gaps are located between the first ends of two adjacent semiconductor pillars and the first dielectric portion; along the first direction, the distance between the end face of the first dielectric portion near the first end and the end face of the gate structure near the first end is smaller than the distance between the end face of the first dielectric portion near the first end and the first end.

2. The semiconductor structure according to claim 1, characterized in that, Along the first direction, the distance between the end face of the first dielectric portion near the first end and the end face of the gate structure near the first end ranges from 0 nm to 20 nm.

3. The semiconductor structure according to claim 1, characterized in that, The gate structure includes: a gate layer and a gate dielectric layer; along the row direction, the gate dielectric layer is located between the gate layer and the semiconductor pillar; Along the first direction, the distance between the end face of the first dielectric portion near the first end and the end face of the gate layer near the first end is less than the distance between the end face of the first dielectric portion near the first end and the first end.

4. The semiconductor structure according to claim 3, characterized in that, Along the first direction, the distance between the end face of the first dielectric portion near the first end and the end face of the gate layer near the first end ranges from 0 nm to 20 nm.

5. The semiconductor structure according to claim 3, characterized in that, The plane containing the end face of the gate layer near the first end is flush with the plane containing the end face of the gate dielectric layer near the first end.

6. The semiconductor structure according to claim 1, characterized in that, Also includes: Multiple first gaps; The first gap is located between two adjacent rows of semiconductor pillars and is located on the side of the first dielectric portion near the first end; The first gap is connected to the first void.

7. The semiconductor structure according to claim 1, characterized in that, Also includes: Multiple first insulating portions; the first insulating portions are located on the side of the gate structure near the first end; Along the row direction, the first insulating portion is also located between two adjacent semiconductor pillars and is disposed along the first end where the two adjacent semiconductor pillars are connected; The first gap is located between the first insulating portion and the first dielectric portion.

8. The semiconductor structure according to claim 7, characterized in that, Along the first direction, the distance between the end face of the first dielectric portion near the first insulating portion and the end face of the gate structure near the first insulating portion is less than the distance between the end face of the first dielectric portion near the first insulating portion and the end face of the first insulating portion away from the gate structure.

9. The semiconductor structure according to claim 1, characterized in that, Also includes: Back grid and second insulation section; The back gate is located between two adjacent semiconductor pillars, and the back gate and the gate structure are arranged alternately in the row direction. The semiconductor pillar is disposed between adjacent gate structures and the back gate. The second insulating portion is located on the side of the back grid near the first end.

10. The semiconductor structure according to any one of claims 1 to 9, characterized in that, Also includes: The bit line located at the first end of a row of semiconductor pillars on the side furthest from the gate structure; The bit line extends along the row direction.

11. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor pillar array is formed, wherein each semiconductor pillar extends along a first direction; The first ends of the plurality of semiconductor pillars located in the same row are connected to each other; Multiple gate structures are formed along the row direction, with each gate structure located between two adjacent semiconductor pillars; the first direction intersects the row direction. A plurality of first dielectric portions are formed along the row direction, wherein the first dielectric portions are located between two adjacent gate structures between two adjacent semiconductor pillars; Multiple first gaps are formed, and the first gaps are located between the first ends of two adjacent semiconductor pillars and the first dielectric portion; Along the first direction, the distance between the end face of the first dielectric portion near the first end and the end face of the gate structure near the first end is less than the distance between the end face of the first dielectric portion near the first end and the first end.

12. The preparation method according to claim 11, characterized in that, The process of forming multiple gate structures, forming multiple first dielectric portions, and forming multiple first gaps includes: A first gate structure is formed, and along the row direction, the first gate structure is located between two adjacent semiconductor pillars and on one side of the first end where the two adjacent semiconductor pillars are connected; A second dielectric portion is formed, wherein one second dielectric portion is located between the two adjacent semiconductor pillars and on the side of the first gate structure opposite to the semiconductor pillars; A third dielectric portion is formed, which is located between two adjacent rows of semiconductor pillars and on the side of the first gate structure away from the second dielectric portion.

13. The preparation method according to claim 12, characterized in that, The preparation method further includes: Remove the portion of the third dielectric portion corresponding to the first end to expose the surface of the first gate structure; Remove the portion of the first gate structure that is in contact with the first end connected to the two adjacent semiconductor pillars, exposing the surface of the second dielectric portion near the first end; The second medium portion near the first end is removed to form the first medium portion; Remove the portion of the first gate structure that protrudes from the first dielectric portion to form two gate structures and the first gap.

14. The preparation method according to claim 13, characterized in that, During the process of forming the first gap, the first dielectric portion, and the two gate structures, the first gap is formed simultaneously; the first gap is located between two adjacent rows of semiconductor pillars and is located on the side of the first dielectric portion near the first end; the first gap is connected to the first gap.

15. The preparation method according to claim 14, characterized in that, The preparation method further includes: A first insulating portion is formed; the first insulating portion is located on the side of the gate structure near the first end; along the row direction, the first insulating portion is also located between two adjacent semiconductor pillars and is disposed along the first end connected to the two adjacent semiconductor pillars; the first insulating portion and the first dielectric portion form the first gap; the two first insulating portions on the same side of two semiconductor pillars in two adjacent rows and located in the same column are separated by the first gap.

16. The preparation method according to claim 12, characterized in that, During the process of forming the first gate structure, the second dielectric portion and the third dielectric portion, multiple back gates and multiple redundant portions are formed simultaneously. The back gate is located between two adjacent semiconductor pillars and between two adjacent first gate structures; the redundant portion is located on the side of the back gate closer to the first end and between two adjacent first gate structures. During the process of removing the portion of the first gate structure that protrudes from the first dielectric portion, the redundant portion is removed simultaneously.

17. The preparation method according to claim 16, characterized in that, During the process of forming the first insulating part, the second insulating part is formed simultaneously; The second insulating portion is located on the side of the back grid near the first end; the two second insulating portions on the same side of two back grids in two adjacent rows and in the same column are separated by the first gap.

18. A semiconductor device, characterized in that, include: The semiconductor structure as described in any one of claims 1 to 10; And peripheral devices; The peripheral devices are connected to the semiconductor structure.

19. A storage system, characterized in that, include: The semiconductor device as described in claim 18; A controller is coupled to the semiconductor device to control the semiconductor device.

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