Memory and method of forming the same, electronic device

Abstract

This disclosure provides a memory and a method for forming the same, as well as an electronic device. The method for forming the memory includes: providing a substrate; forming a plurality of stacked structures arranged along a first direction and a second direction on the surface of the substrate; the stacked structures include a first semiconductor layer and a second semiconductor layer spaced apart along a third direction, the substrate, the first semiconductor layer, and the second semiconductor layer comprising the same semiconductor material; laterally etching both sides of the first semiconductor layer and the second semiconductor layer along the second direction to form a first active layer and a second active layer extending along the first direction, respectively; the first active layer and an adjacent second active layer constitute an active group; and forming a gate structure extending along the second direction between the first active layer and the second active layer in the active group.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a memory and a method of forming the same, and an electronic device. Background Technology

[0002] As memory integration density increases, transistors in memory cells can adopt a horizontal dual-gate single-channel structure, where the gate is located on the upper and lower sides of the horizontal channel. However, this structure not only makes the word lines (i.e., gates) between upper and lower memory cells close together, which easily leads to coupling effects, but also makes the fabrication process of word lines more complex and increases the difficulty of connecting word lines and word line steps. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a memory and a method for forming the same, as well as an electronic device.

[0004] In a first aspect, embodiments of this disclosure provide a method for forming a memory, the method comprising: providing a substrate; forming a plurality of stacked structures arranged along a first direction and a second direction on the surface of the substrate; the stacked structures including a first semiconductor layer and a second semiconductor layer spaced apart along a third direction, the substrate, the first semiconductor layer and the second semiconductor layer comprising the same semiconductor material; laterally etching both sides of the first semiconductor layer and the second semiconductor layer along the second direction to respectively form a first active layer and a second active layer extending along the first direction; the first active layer and an adjacent second active layer constituting an active group; forming a gate structure extending along the second direction between the first active layer and the second active layer in the active group; wherein the first direction intersects the second direction and is parallel to the plane where the memory is located, and the third direction is perpendicular to the plane where the memory is located.

[0005] In some embodiments, the stacked structure further includes a first sacrificial layer and a second sacrificial layer, wherein the first sacrificial layer, the first semiconductor layer, the second sacrificial layer, and the second semiconductor layer are alternately stacked along the third direction; forming a plurality of stacked structures arranged along a first direction and a second direction includes: forming an initial stacked structure; the projection of the initial stacked structure on the substrate is a grid shape, including a first initial sacrificial layer, a first initial semiconductor layer, a second initial sacrificial layer, and a second initial semiconductor layer alternately stacked along the third direction; the thickness of the first initial sacrificial layer is greater than the thickness of the second initial sacrificial layer; etching the intersections in the initial stacked structure along both sides of the first direction to form a first etching groove and a second etching groove, respectively, and the remaining initial stacked structure constitutes a plurality of stacked structures; wherein the projection of the stacked structure on the substrate is a cross shape, and two adjacent stacked structures along the first direction share the first etching groove or the second etching groove.

[0006] In some embodiments, the method further includes: forming an insulating structure at the bottom of both the first etched groove and the second etched groove; the top surface of the insulating structure does not exceed the bottom surface of the bottommost first semiconductor layer.

[0007] In some embodiments, forming a first active layer and a second active layer extending along the first direction includes: removing the first sacrificial layer and the second sacrificial layer to form a first lateral groove and a second lateral groove, respectively; the dimension of the first lateral groove along the third direction is larger than the dimension of the second lateral groove along the third direction; forming a first isolation structure and a second intermediate isolation structure in the first lateral groove and the second lateral groove, respectively; laterally etching both sides of the first semiconductor layer and the second semiconductor layer along the second direction to form the first active layer and the second active layer; the first active layer and the second active layer on both sides of the second intermediate isolation structure along the third direction constitute an active group.

[0008] In some embodiments, the method further includes: forming a first filling structure between the sidewalls of the plurality of stacked structures along the first direction before removing the first sacrificial layer and the second sacrificial layer; and simultaneously thinning the first semiconductor layer and the second semiconductor layer through the first lateral groove and the second lateral groove after forming the first lateral groove and the second lateral groove.

[0009] In some embodiments, forming a first isolation structure and a second intermediate isolation structure in the first transverse groove and the second transverse groove respectively includes: forming a second initial isolation structure at least on the exposed surfaces of the first transverse groove and the second transverse groove; the thickness of the second initial isolation structure is less than half of the third-direction dimension of the first transverse groove and greater than half of the third-direction dimension of the second transverse groove; removing the second initial isolation structure located in the first transverse groove, wherein the second initial isolation structure located in the second transverse groove constitutes the second intermediate isolation structure; and forming the first isolation structure in the first transverse groove.

[0010] In some embodiments, laterally etching both sides of the first semiconductor layer and the second semiconductor layer along the second direction to form the first active layer and the second active layer includes: removing the first filling structure to form a third etching groove; the third etching groove exposing both sides of the first semiconductor layer and the second semiconductor layer along the second direction; and laterally etching the first semiconductor layer and the second semiconductor layer through the third etching groove to form the first active layer and the second active layer.

[0011] In some embodiments, after forming the first active layer and the second active layer, the method further includes: forming a third isolation structure in the gap between the first isolation structure and the second intermediate isolation structure along the third direction; and filling the third etched groove with a second filling structure.

[0012] In some embodiments, the second intermediate isolation structure includes a first sub-part extending along the second direction and second sub-parts located on both sides of the first sub-part along the second direction; forming a gate structure extending along the second direction includes: laterally etching the second intermediate isolation structure along the first direction through the first etched groove until the first sub-part is removed, forming a third lateral groove, the remaining second sub-part constituting the second isolation structure; forming a gate dielectric layer on the exposed upper and lower surfaces of the third lateral groove; forming a gate metal layer between the gate dielectric layer on the middle surface of the first active layer and the second active layer; wherein the gate dielectric layer and the gate metal layer constitute the gate structure, and a plurality of gate metal layers arranged along the second direction are interconnected to form word lines.

[0013] In some embodiments, after forming the gate structure, the method further includes forming a fourth isolation structure in the gap between the gate dielectric layer along the third direction.

[0014] In some embodiments, after forming the gate structure, the method further includes forming a bit line structure in the first etched groove.

[0015] In some embodiments, the method further includes: laterally etching a portion of the second isolation structure, a portion of the first active layer, and a portion of the second active layer through the second etching groove to form a fourth lateral groove; forming a first electrode on the surface exposed by the fourth lateral groove; and sequentially forming a dielectric layer and a second electrode on the surface exposed by the first electrode; wherein the first electrode, the dielectric layer, and the second electrode constitute a capacitor structure, and a plurality of second electrodes arranged along the second direction and the third direction are interconnected.

[0016] In some embodiments, after forming the first electrode, the method further includes: removing a portion of the first isolation structure through the second etched groove to expose a portion of the surface of the first electrode along the second direction and the third direction.

[0017] In a second aspect, embodiments of this disclosure provide a memory, the memory comprising: a substrate; a plurality of active groups located on the surface of the substrate, arranged in an array along a first direction and a second direction, and stacked along a third direction; the active groups comprising a first active layer and a second active layer spaced apart along the third direction and extending along the first direction; a gate structure located between the first active layer and the second active layer in the active groups and extending along the second direction; wherein the substrate, the first active layer, and the second active layer comprise the same semiconductor material; the first direction intersects the second direction and is parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.

[0018] In some embodiments, in the third direction, the spacing between the first active layer and the second active layer in the active group is smaller than the spacing between adjacent active groups.

[0019] Thirdly, embodiments of this disclosure provide an electronic device, including: a processor; and a memory as described in any of the above embodiments, wherein the memory is coupled to the processor.

[0020] This disclosure provides a memory and a method for forming the same, as well as an electronic device. The method for forming the memory includes: providing a substrate; forming a plurality of stacked structures arranged along a first direction and a second direction on the surface of the substrate; the stacked structures include a first semiconductor layer and a second semiconductor layer spaced apart along a third direction, the substrate, the first semiconductor layer, and the second semiconductor layer comprising the same semiconductor material; laterally etching both sides of the first semiconductor layer and the second semiconductor layer along the second direction to form a first active layer and a second active layer extending along the first direction, respectively; the first active layer and an adjacent second active layer constitute an active group; and forming a gate structure extending along the second direction between the first active layer and the second active layer in the active group.

[0021] Here, since the substrate, the first semiconductor layer, and the second semiconductor layer all use the same semiconductor material, that is, the substrate, the first active layer, and the second active layer are made of the same material, on the one hand, this makes the process compatibility between the substrate, the first active layer, and the second active layer high, which not only reduces production costs but also improves the production yield of the memory. On the other hand, the same material has the same physical parameters such as the coefficient of thermal expansion, which not only allows for a more uniform stress distribution when the temperature changes, reducing the generation of local stress, but also allows for uniform heat dissipation, avoiding the problem of local overheating.

[0022] In addition, the active group (i.e., the first active layer and the second active layer) and the gate structure can form a single-gate dual-channel transistor. Since the gate structure is located between the first active layer and the second active layer in the active group, it not only makes the word lines (i.e., the gate structures) in adjacent transistors farther apart in the third direction, reducing the coupling effect between word lines, but also allows two channels in a transistor to be controlled by one word line at the same time, reducing the number of word lines and simplifying the difficulty of word line fabrication and connection. Attached Figure Description

[0023] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0024] Figure 1 This is a flowchart illustrating a memory formation method provided in an embodiment of the present disclosure.

[0025] Figures 2 to 40 This is a schematic diagram of the structure during the formation process of the memory provided in the embodiments of this disclosure;

[0026] Figure 41 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0027] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0028] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0029] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0030] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0032] Currently, in three-dimensional dynamic random access memory (3D DRAM) including silicon channel word line staircases, the transistors in the memory cells can adopt a horizontal dual-gate single-channel structure, where the gate is located on the upper and lower sides of the horizontal channel; however, this structure has the following main disadvantages:

[0033] 1) The word lines (i.e. gates) between upper and lower memory cells are close together, resulting in a large coupling effect between word lines; in addition, in order to reduce the size of the memory, word lines are usually made thinner, which makes the resistance of word lines larger, resulting in a larger RC delay of the memory cell, affecting the read and write speed of the memory.

[0034] 2) The gap between storage cells in the vertical direction is increased, which leads to a decrease in storage density.

[0035] 3) A memory cell includes word lines located on the upper and lower sides of the channel, which makes the word line formation process and integration method more complex, thereby increasing the difficulty of connecting word lines and word line steps.

[0036] Based on this, the present disclosure provides a memory and a method for forming the same; the memory and the method for forming the same in the present disclosure will be described in detail below with reference to the accompanying drawings.

[0037] Before introducing the embodiments of this disclosure, let's define three directions that may be used in the following embodiments to describe the three-dimensional structure. The three directions may include a first (X-axis) direction, a second (Y-axis) direction, and a third (Z-axis) direction. The Z-axis direction can be a direction perpendicular to the plane where the substrate is located; the X-axis and Y-axis directions are two perpendicular directions on the plane where the substrate is located, wherein the X-axis direction can be the direction in which the first active layer extends.

[0038] This disclosure provides a method for forming a memory. Figure 1 This is a schematic flowchart of a memory formation method provided in an embodiment of the present disclosure, as shown below. Figure 1 As shown, the method for forming the memory includes the following steps:

[0039] Step S110: Provide a substrate.

[0040] In this embodiment, the substrate may be a silicon substrate. In other embodiments, the substrate may also be a germanium substrate, a silicon germanide substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.

[0041] In step S120, multiple stacked structures are formed on the surface of the substrate, arranged along the X-axis and Y-axis directions. The stacked structures include a first semiconductor layer and a second semiconductor layer arranged at intervals along the Z-axis direction. The substrate, the first semiconductor layer, and the second semiconductor layer are made of the same semiconductor material.

[0042] In this embodiment of the disclosure, each stack structure is used to form multiple storage cells stacked along the Z-axis, and the number of stack structures can be set according to actual needs; for example, the number of stack structures can be 2, 4 or 8.

[0043] In this embodiment of the present disclosure, each first semiconductor layer and a corresponding second semiconductor layer are used to form one memory cell. The number of first semiconductor layers and second semiconductor layers can be set according to the actual number of memory cells to be stacked. For example, the number of first semiconductor layers and second semiconductor layers can both be 4, so that 4 memory cells stacked along the Z-axis can be formed. Or, the number of first semiconductor layers and second semiconductor layers can both be 5, so that 5 memory cells stacked along the Z-axis can be formed.

[0044] Furthermore, the substrate, the first semiconductor layer, and the second semiconductor layer all comprise the same semiconductor material. For example, the substrate, the first semiconductor layer, and the second semiconductor layer can all be monocrystalline silicon. This ensures high process compatibility during memory formation, reducing production costs and improving memory production yield. On the other hand, the same material has consistent physical parameters such as the coefficient of thermal expansion, which not only ensures a more uniform stress distribution during temperature changes, reducing the generation of local stress, but also allows for uniform heat dissipation, avoiding local overheating.

[0045] In other embodiments, the materials of the substrate and the semiconductor layers (i.e., the first semiconductor layer and the second semiconductor layer) can also be different; for example, the substrate can be made of germanium, and the first and second semiconductor layers can be made of silicon. This allows for the selection of suitable materials according to actual needs, improving the flexibility of the process during memory fabrication.

[0046] In step S130, the sides of the first semiconductor layer and the second semiconductor layer are etched laterally along the Y-axis to form the first active layer and the second active layer extending along the X-axis, respectively; the first active layer and the adjacent second active layer constitute an active group.

[0047] In this embodiment of the present disclosure, both the first active layer and the second active layer include a channel structure and a source and a drain located on both sides of the channel structure along the X-axis direction.

[0048] In step S140, a gate structure extending along the Y-axis is formed between the first active layer and the second active layer in the active group.

[0049] In this embodiment of the disclosure, the gate structure includes a gate dielectric layer and a gate metal layer; wherein, the gate dielectric layer is located on the opposite surfaces of the first active layer and the second active layer in the same active group; the gate metal layer is located between adjacent gate dielectric layers in the Z-axis direction, and multiple gate metal layers arranged along the Y-axis direction are interconnected to form a word line.

[0050] In this embodiment of the disclosure, the active group (i.e., the first active layer and the second active layer) and the gate structure can constitute a single-gate dual-channel transistor. Since the gate structure is located between the first active layer and the second active layer in the active group, it not only makes the word lines (i.e., gate structures) in adjacent transistors farther apart in the Z-axis direction, reducing the coupling effect between word lines, but also allows two channels in a transistor to be controlled simultaneously by a word line, reducing the number of word lines and simplifying the difficulty of word line fabrication and connection.

[0051] Next, the memory formation process will be explained in detail. Figures 2 to 40 This is a schematic diagram of the structure during the formation process of the memory provided in an embodiment of the present disclosure; wherein, Figures 2 to 40 It includes a three-dimensional view, a sectional view along a-a', and a sectional view along b-b'.

[0052] In some embodiments, step S110 provides, as Figure 2 The substrate 110 shown.

[0053] In this embodiment, the substrate 110 may be a silicon substrate. In other embodiments, the substrate 110 may also be a germanium substrate, a silicon germanide substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, etc.

[0054] In some embodiments, in step S120, a structure is formed on the surface of the substrate 110 as shown in the figure. Figure 8 The diagram shows multiple stacked structures 120 arranged along the X-axis and Y-axis directions; each stacked structure 120 includes a first semiconductor layer 121 and a second semiconductor layer 122 spaced apart along the Z-axis direction, and the substrate 110, the first semiconductor layer 121 and the second semiconductor layer 122 are made of the same semiconductor material.

[0055] In some embodiments, the stacked structure 120 further includes a first sacrificial layer 123 and a second sacrificial layer 124, wherein the first sacrificial layer 123, the first semiconductor layer 121, the second sacrificial layer 124 and the second semiconductor layer 122 are stacked alternately along the Z-axis direction; step S120 specifically includes steps S121 and S122.

[0056] Step S121, forming as follows Figure 5 The initial stacked structure 120a shown is projected onto the substrate 110 in a grid shape, including a first initial sacrificial layer 123a, a first initial semiconductor layer 121a, a second initial sacrificial layer 124a, and a second initial semiconductor layer 122a stacked alternately along the Z-axis direction; the thickness of the first initial sacrificial layer 123a is greater than the thickness of the second initial sacrificial layer 124a.

[0057] In implementation, firstly, a first sacrificial material layer 123a', a first semiconductor material layer 121a', a second sacrificial material layer 124a', and a second semiconductor material layer 122a' are sequentially stacked on the surface of the substrate 110 to form a structure as shown in the figure. Figure 3 The stacked material layer 120a' is shown. The number of layers—the first sacrificial material layer 123a', the first semiconductor material layer 121a', the second sacrificial material layer 124a', and the second semiconductor material layer 122a'—can be set according to the required capacitance density (or storage density). More layers result in a higher integration density and greater capacitance density in the formed memory 100; for example, Figure 3 The diagram shows that each material layer cycle has 5 layers, thus forming a memory 100 comprising 5 layers of storage cells.

[0058] Please continue to refer to this. Figure 3 A sacrificial layer (e.g., a first sacrificial material layer 123a') can be covered on the surface of the topmost second semiconductor material layer 122a'; in this way, the surface of the topmost second semiconductor material layer 122a' can be protected from damage or contamination during the formation of the memory 100.

[0059] In this embodiment, a first semiconductor material layer 121a' and a second semiconductor material layer 122a' are used to form a first active layer and a second active layer (i.e., a dual-channel structure in a transistor). A first sacrificial material layer 123a' is used to occupy the position for the subsequent formation of a first isolation structure, thereby protecting the surface of the area covered by the first sacrificial material layer 123a' from damage or contamination during memory formation. A second sacrificial material layer 124a' is used to occupy the position for the subsequent formation of a gate structure, thereby protecting the surface of the area covered by the second sacrificial material layer 124a' from damage or contamination during memory formation.

[0060] Furthermore, the dimension d1 of the first sacrificial material layer 123a' in the Z-axis direction is larger than the dimension d2 of the second sacrificial material layer 124a' in the Z-axis direction. This allows for a greater thickness of the subsequently formed first isolation structure, resulting in a greater distance between adjacent memory cells and reduced leakage current. Simultaneously, it allows for a smaller thickness of the subsequently formed gate structure, thus making the thickness of the first and second active layers in the same active group (see reference) more consistent. Figure 8 The small spacing between the components ensures the high integration density of the memory.

[0061] In this embodiment of the present disclosure, the materials of the first sacrificial material layer 123a' and the second sacrificial material layer 124a' can be silicon germanide (SiGe); the first semiconductor material layer 121a' and the second semiconductor material layer 122a' can be single-crystal silicon layers. Here, there is a certain etching selectivity between the semiconductor material layer and the sacrificial material layer, so that the semiconductor material layer or the sacrificial material layer can be selectively etched away during the etching process.

[0062] In this embodiment of the present disclosure, the first sacrificial material layer 123a', the first semiconductor material layer 121a', the second sacrificial material layer 124a', and the second semiconductor material layer 122a' can be formed sequentially and alternately through an epitaxial process. In this way, the lattice constants between the semiconductor material layer and the sacrificial material layer can be basically matched, thereby reducing defects (dislocations, cracks, internal stresses, etc.) in the first semiconductor material layer 121a' and the second semiconductor material layer 122a', and further reducing defects in the subsequently formed first active layer and second active layer, thus improving the performance of the memory.

[0063] It should be noted that in the embodiments of this disclosure, the substrate 110, the first semiconductor material layer 121a', and the second semiconductor material layer 122a' are made of the same material, for example, they can all be single-crystal silicon; in this way, the process compatibility during the formation of the memory can be guaranteed to be high, which not only reduces the production cost but also improves the production yield of the memory; on the other hand, the same material has the same physical parameters such as the coefficient of thermal expansion, so it can not only have a more uniform stress distribution when the temperature changes, reducing the generation of local stress, but also make the heat diffuse evenly, avoiding the problem of local overheating.

[0064] The growth processes described in this disclosure include, but are not limited to: vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), ion beam epitaxy, solid phase epitaxy, and combinations thereof.

[0065] Next, in such Figure 3 The surface of the stacked material layer 120a' shown is formed as follows: Figure 4 The first initial hard mask layer 130a is shown. The material of the first initial hard mask layer 130a can be any suitable material such as silicon oxide. In other embodiments, the first initial hard mask layer 130a may not be formed.

[0066] Finally, Figure 4A patterned first mask layer (not shown) is formed on the surface of the first initial hard mask layer 130a; the first initial hard mask layer 130a and the stacked material layer 120a' are etched sequentially through the first mask layer to form a patterned first mask layer (not shown). Figure 5 The first hard mask layer 130 and the initial stacked structure 120a are shown. The projections of the first hard mask layer 130 and the initial stacked structure 120a onto the substrate 110 are both grid-shaped. The initial stacked structure 120a includes a first initial sacrificial layer 123a, a first initial semiconductor layer 121a, a second initial sacrificial layer 124a, and a second initial semiconductor layer 122a, which are alternately stacked along the Z-axis direction. Afterwards, the first mask layer is removed.

[0067] It should be noted that the number of intersections in the grid (i.e., the projection of the initial stacked structure 120a) can be set according to the number of storage cells required for each layer; specifically, the number of intersection areas in each grid (e.g., Figure 6 (As shown by the dashed line area), a storage unit can be formed subsequently. For example, Figure 6 As shown in the left figure, when the number of intersections in the grid is 4, each subsequent layer can form 4 storage cells arranged in an array along the X-axis and Y-axis directions; for example, Figure 6 As shown in the right figure, when the number of intersections in the grid is 9, each subsequent layer can form 9 memory cells arranged in an array along the X-axis and Y-axis directions. In this embodiment, the example of each layer forming 4 memory cells is used for illustration.

[0068] The etching processes described in this disclosure include, but are not limited to, dry etching, wet etching, and combinations thereof.

[0069] In this embodiment of the disclosure, after forming the initial stacked structure 120a and before removing the first sacrificial layer 123 and the second sacrificial layer 124, the method for forming the memory 100 further includes: forming, between the sidewalls of the plurality of stacked structures 120 along the X-axis direction, as shown in the figure. Figure 7 The first filling structure 140 is shown.

[0070] In implementation, a first sub-filling structure 141 can be formed on the surface of the substrate 110 and on the exposed sidewalls of the stacked structure 120 and the first hard mask layer 130; a second sub-filling structure 142 is filled into the gaps between the first sub-filling structures 141; the first sub-filling structures 141 and the second sub-filling structures 142 together constitute the first filling structure 140. Here, the material of the first sub-filling structure 141 can be any suitable material such as silicon nitride; the material of the second sub-filling structure 142 can be any suitable material such as silicon oxide.

[0071] In this embodiment of the disclosure, the first filling structure 140 can provide support for the first initial semiconductor layer 121a and the second initial semiconductor layer 122a after the first sacrificial layer 123 and the second sacrificial layer 124 are removed.

[0072] Step S122: Etch the intersection points in the initial stacked structure 120a on both sides along the X-axis direction to form shapes as shown below. Figure 8 The first etched groove 151 and the second etched groove 152 shown, the remaining initial stacked structure 120a constitutes as follows. Figure 8 The multiple stacked structures 120 shown.

[0073] In implementation, firstly, in situations such as Figure 7 The top surface of the structure shown (i.e., the initial stacked structure 120a and the first filling structure 140) is formed as... Figure 8 The second hard mask layer 131 is shown. The material of the second hard mask layer 131 can be any suitable material such as silicon oxide. In other embodiments, the second hard mask layer 131 may not be formed.

[0074] It should be noted that, in order to show the structure at the bottom of the second hard mask layer 131, the second hard mask layer 131 shown in the 3D view is a perspective structure.

[0075] Next, a patterned second mask layer (not shown) is formed on the surface of the second hard mask layer 131. The openings of the second mask layer are located on both sides of the intersection in the initial stacked structure 120a along the X-axis. The second hard mask layer 131, the first hard mask layer 130, and the initial stacked structure 120a are sequentially etched through the second mask layer to form a patterned second mask layer 131, the first hard mask layer 130, and the initial stacked structure 120a. Figure 8 The first etched groove 151, the second etched groove 152, and the stacked structure 120 are shown; wherein the first etched groove 151 and the second etched groove 152 are located on both sides of the intersection point in the stacked structure 120 along the X-axis direction.

[0076] Among them, such as Figure 9 As shown, Figure 8 The projection of the stacked structure 120 onto the substrate 110 is shown; by Figure 9 It can be seen that in the initial stacking structure 120a (i.e. Figure 6 When the number of intersections of the grid (as shown in the left figure) is 4, four stacked structures 120 can be formed in an array along the X-axis and Y-axis directions. The projection of each stacked structure 120 on the substrate 110 is a cross shape (as shown in the dashed area).

[0077] Furthermore, two adjacent stacked structures 120 along the X-axis direction share either the first etched groove 151 or the second etched groove 152. In this embodiment, the example of two adjacent stacked structures 120 along the X-axis direction sharing the second etched groove 152 will be used for illustration.

[0078] In this embodiment of the disclosure, due to process limitations, the bottom of the etched grooves (i.e., the first etched groove 151 and the second etched groove 152) is etched down to the substrate 110. To prevent the subsequently formed structure from connecting with the substrate 110, after forming the first etched groove 151 and the second etched groove 152, the method for forming the memory 100 further includes: forming, at the bottom of both the first etched groove 151 and the second etched groove 152, the following... Figure 10 The insulating structure 160 shown; the top surface of the insulating structure 160 does not exceed the bottom surface of the bottommost first semiconductor layer 121.

[0079] This allows the bit line structure subsequently formed in the first etched groove 151 and the capacitor structure subsequently formed in the second etched groove 152 to be isolated from the substrate 110; thereby avoiding leakage current, resulting in better electrical isolation of the memory and improving the reliability of the memory.

[0080] In other embodiments, the insulating structure 160 may also be formed before the bit line structure and the capacitor structure. This disclosure does not limit the formation order of the insulating structure 160.

[0081] In some embodiments, in step S130, the two sides of the first semiconductor layer 121 and the second semiconductor layer 122 are etched laterally along the Y-axis direction to form, respectively, the following... Figure 19 The first active layer 171 and the second active layer 172 extend along the X-axis direction as shown; the first active layer 171 and the adjacent second active layer 172 constitute an active group 170.

[0082] In some embodiments, step S130 includes steps S131 to S133.

[0083] Step S131, remove such Figure 10 The first sacrificial layer 123 and the second sacrificial layer 124 shown are respectively formed as follows Figure 11 The first transverse groove 153 and the second transverse groove 154 are shown; the dimension d1 of the first transverse groove 153 along the Z-axis is greater than the dimension d2 of the second transverse groove 154 along the Z-axis.

[0084] In some embodiments, the method of forming the memory further includes: after forming the first lateral groove 153 and the second lateral groove 154, simultaneously thinning the first semiconductor layer 121 and the second semiconductor layer 122 through the first lateral groove 153 and the second lateral groove 154.

[0085] In this embodiment of the disclosure, the methods for thinning the first semiconductor layer 121 and the second semiconductor layer 122 include the following two:

[0086] Method 1: Etch the first semiconductor layer 121 and the second semiconductor layer 122 directly (e.g., wet etching) until the required thickness is formed, then stop etching.

[0087] Method 2: In-situ oxidation of the first semiconductor layer 121 and the second semiconductor layer 122, oxidizing a portion of the first semiconductor layer 121 and a portion of the second semiconductor layer 122 into a silicon oxide layer, and removing the silicon oxide layer by wet etching or dry etching techniques.

[0088] In this embodiment of the disclosure, by thinning the first semiconductor layer 121 and the second semiconductor layer 122, the gap between the first semiconductor layer 121 and the second semiconductor layer 122 is increased. This has two advantages: firstly, it increases the gap between the first active layer and the second active layer in the same active group, increasing the space available for forming the gate structure and thus reducing the process complexity of the gate structure; secondly, it increases the spacing between adjacent active groups along the Z-axis, thereby increasing the thickness of the formed first isolation structure and reducing leakage current between adjacent active groups.

[0089] Step S132, forming as shown in the first transverse groove 153 and the second transverse groove 154 respectively. Figure 14 The first isolation structure 182 and the second intermediate isolation structure 181b are shown.

[0090] In some embodiments, step S132 specifically includes steps S1321 to S1323.

[0091] Step S1321, at least on the exposed surfaces of the first transverse groove 153 and the second transverse groove 154, a shape is formed as shown in the figure. Figure 12 The second initial isolation structure 181a shown has a thickness less than half the dimension d1 of the first transverse groove 153 along the Z-axis and greater than half the dimension d2 of the second transverse groove 154 along the Z-axis.

[0092] In this embodiment of the disclosure, the material of the second initial isolation structure 181a can be any kind of insulating material, such as silicon oxide or silicon oxynitride.

[0093] In this embodiment, since the thickness of the second initial isolation structure 181a is less than half of the dimension d1 of the first transverse groove 153 along the Z-axis, there is a gap A between the second initial isolation structures 181a in the first transverse groove 153. This makes it easier to remove the second initial isolation structure 181a in the first transverse groove 153 through the gap A in subsequent processes.

[0094] Please continue to refer to this. Figure 12The projection of gap A onto substrate 100 is similar to the projection of stacked structure 120 onto substrate (see reference). Figure 9 (The shape of 120); Specifically, the gap A includes a plurality of first sub-gap extending along the X-axis direction and passing through the first etched groove 151 and the second etched groove 152, and a second sub-gap extending along the Y-axis direction and passing through the intersection.

[0095] Furthermore, since the thickness of the second initial isolation structure 181a is greater than half of the dimension d2 of the second transverse groove 154 along the Z-axis, the second initial isolation structure 181a fills the second transverse groove 154. In this way, the etching solution can be less likely to etch the second initial isolation structure 181a in the second transverse groove 154.

[0096] In this embodiment of the disclosure, please continue to refer to Figure 12 Due to the deposition process, the second initial isolation structure 181a is also deposited on the surfaces exposed by the first etched groove 151 and the second etched groove 152.

[0097] Step S1322: Remove the second initial isolation structure 181a located in the first transverse groove 153. The second initial isolation structure 181a located in the second transverse groove 154 is configured as follows: Figure 13 The second intermediate isolation structure 181b is shown.

[0098] In this embodiment of the disclosure, please refer to Figure 12 Since there is a gap A between the second initial isolation structures 181a in the first transverse groove 153, the etching solution can pass through the gap A to etch the second initial isolation structures 181a in the first transverse groove 153, thereby removing the second initial isolation structures 181a in the first transverse groove 153.

[0099] It should be noted that during etching, although the etching solution will etch the second initial isolation structure 181a (i.e., the second intermediate isolation structure 181b) in the second transverse groove 154, the second initial isolation structure 181a fills the second transverse groove 154, thus exposing a small area. Therefore, the etching solution only causes minor damage to the second initial isolation structure 181a (i.e., the second intermediate isolation structure 181b) in the second transverse groove 154, and does not affect its actual function.

[0100] Step S1323, in the first transverse groove 153, form as shown Figure 14 The first isolation structure 182 is shown.

[0101] During implementation, in cases such as Figure 13The exposed surfaces of the structure shown (i.e., in the first transverse groove 153, the first etched groove 151, and the second etched groove 152) form a first initial isolation structure (not shown). Removing the first initial isolation structures located in the first etched groove 151 and the second etched groove 152 leaves the remaining first initial isolation structure located in the first transverse groove 153 as shown. Figure 14 The first isolation structure 182 is shown.

[0102] In this embodiment of the present disclosure, after forming the first isolation structure 182, the method for forming the memory further includes: forming, in the first etched groove 151 and the second etched groove 152, as shown in the figure. Figure 15 The third sacrificial layer 125 is shown. The third sacrificial layer 125 includes a first sub-sacrificial layer 125a and a second sub-sacrificial layer 125b. The materials of the first sub-sacrificial layer 125a and the second sub-sacrificial layer 125b can be one or any combination of silicon nitride, silicon oxynitride, amorphous carbon, or silicon carbonitride.

[0103] Step S133: Laterally etch both sides of the first semiconductor layer 121 and the second semiconductor layer 122 along the Y-axis direction to form as shown in the figure. Figure 19 The first active layer 171 and the second active layer 172 shown; the first active layer 171 and the second active layer 172 on both sides of the second intermediate isolation structure 181b along the Z-axis direction constitute an active group 170.

[0104] In some embodiments, step S133 specifically includes steps S1331 and S1332.

[0105] Step S1331, remove the first filling structure 140 to form as shown Figure 18 The third etched groove 155 is shown; the third etched groove 155 exposes the first semiconductor layer 121 and the second semiconductor layer 122 on both sides along the Y-axis.

[0106] Please refer to the following when implementing: Figure 16 A patterned third mask layer (not shown) is formed on the surface of the second hard mask layer 131, exposing the second hard mask layer 131 on top of the first filling structure 140 (i.e., the first sub-filling structure 141 and the second sub-filling structure 142). The second hard mask layer 131 is etched through the third mask layer to expose the first filling structure 140. Afterward, the third mask layer is removed.

[0107] It should be noted that, due to the different materials of the first sub-filling structure 141 and the second sub-filling structure 142, i.e., the different etching selectivity ratios of the first sub-filling structure 141 and the second sub-filling structure 142, the first sub-filling structure 141 and the second sub-filling structure 142 are in different directions along the Z-axis after etching the second hard mask layer 131.

[0108] Next, please refer to Figure 17 and Figure 18 The second sub-fill structure 142 and the first sub-fill structure 141 are removed in sequence to form a third etch groove 155; the third etch groove 155 exposes the first semiconductor layer 121 and the second semiconductor layer 122 on both sides along the Y-axis.

[0109] In step S1332, the first semiconductor layer 121 and the second semiconductor layer 122 are laterally etched through the third etching groove 155 to form a layer as shown in the figure. Figure 19 The first active layer 171 and the second active layer 172 are shown.

[0110] It should be noted that, in order to illustrate the structure of the first active layer 171 and the second active layer 172, Figure 19 The first isolation structure 182, the first hard mask layer 130, the second hard mask layer 131, and the second sub-sacrificial layer 125b are not shown in the left figure (i.e., the 3D view). The positions of the first isolation structure 182, the first hard mask layer 130, the second hard mask layer 131, and the second sub-sacrificial layer 125b can be found by referring to... Figure 19 Refer to the right-hand diagram (i.e., the sectional view along a-a').

[0111] In some embodiments, after forming the first active layer 171 and the second active layer 172, the method of forming the memory further includes: forming, in the gap between the first isolation structure 182 and the second intermediate isolation structure 181b along the Z-axis direction, a... Figure 20 and Figure 21 The third isolation structure 183 is shown; in the third etched groove 155, it is filled with, as shown in the figure Figure 22 The second filling structure 190 is shown.

[0112] In practice, a surface exposed by the third etched groove 155, and the gap between the first active layer 171 and the second active layer 172, can be formed as shown in the figure. Figure 20 and Figure 21 The third isolation structure 183 shown is filled with the gap between the first active layer 171 and the second active layer 172.

[0113] Next, a third sub-filling structure 191 is formed on the exposed surface of the third isolation structure 183 (i.e., the third etched groove 155); a fourth sub-filling structure 192 is filled in the gap between the third sub-filling structures 191 (i.e., in the third etched groove 155); the third sub-filling structure 191 and the fourth sub-filling structure 192 together constitute the second filling structure 190.

[0114] Here, the materials of the third isolation structure 183 and the fourth sub-filling structure 192 can be any insulating material, such as silicon oxide or silicon oxynitride. The material of the third sub-filling structure 191 can be any suitable material such as silicon nitride.

[0115] In some embodiments, step S140 involves forming a layer between the first active layer 171 and the second active layer 172 in the active group 170, as shown in the figure. Figure 29 The gate structure 200 shown extends along the Y-axis.

[0116] In some embodiments, step S140 includes steps S141 to S143.

[0117] Step S141: Through the first etching groove 151, the second intermediate isolation structure 181b is etched laterally along the X-axis direction until the first sub-part 1811 is removed, forming as shown. Figure 25 and Figure 26 The third transverse groove 156 shown, and the remaining second sub-part 1812 constitute the second isolation structure 181.

[0118] Please refer to the following when implementing: Figure 23 The third sacrificial layer 125 (i.e., the first sub-sacrificial layer 125a and the second sub-sacrificial layer 125b) in the first etched groove 151 is removed, exposing the sidewall of the second intermediate isolation structure 181b along the X-axis.

[0119] It should be noted that, please refer to Figure 24 , is the projection of the second intermediate isolation structure 181b onto the substrate; wherein the second intermediate isolation structure 181b includes a first sub-part 1811 extending along the Y-axis direction, and a second sub-part 1812 located on both sides of the first sub-part 1811 along the Y-axis direction.

[0120] Finally, the second intermediate isolation structure 181b is etched laterally along the X-axis direction through the first etched groove 151 until the first sub-part 1811 is removed, forming as shown. Figure 25 and Figure 26 The third transverse groove 156 shown, and the remaining second sub-part 1812 constitute the second isolation structure 181.

[0121] Step S142, on the exposed upper and lower surfaces of the third transverse groove 156, form as shown in the figure. Figure 27 The gate dielectric layer 201 is shown.

[0122] In practice, an initial gate dielectric layer (not shown) is formed on the exposed surfaces of the first etched groove 151 and the third lateral groove 156. The initial gate dielectric layer located in the first etched groove 151 is removed, and the remaining initial gate dielectric layer located on the exposed surface of the third lateral groove 156 forms as shown. Figure 27The gate dielectric layer 201 is shown.

[0123] Please continue to refer to this. Figure 27 The gate dielectric layer 201 is located on the opposite surfaces of the first active layer 171 and the second active layer 172 in the same active group 170.

[0124] Step S143, between the gate dielectric layer 201 on the middle surface of the first active layer 171 and the second active layer 172, a structure is formed as shown in the figure. Figure 29 The gate metal layer 202 shown; wherein, the gate dielectric layer 201 and the gate metal layer 202 constitute the gate structure 200, and multiple gate metal layers 202 arranged along the Y-axis direction are interconnected to form word lines.

[0125] During implementation, the surfaces exposed by the first etched groove 151 and the third transverse groove 156 (i.e., the first active layer 171 and the second active layer 172) are formed as follows: Figure 28 The initial gate metal layer 202a is shown; next, the initial gate metal layer 202a located in the first etched groove 151 and part of the third transverse groove 156 is removed, and the remaining initial gate metal layer 202a forms as shown. Figure 29 The gate metal layer 202 is shown.

[0126] Please refer to Figure 30 This is the projection of the remaining third lateral groove 156, gate metal layer 202, and second isolation structure 181 onto the substrate 110; by Figure 20 As can be seen, multiple gate metal layers 202 arranged along the Y-axis are interconnected, thus forming word lines.

[0127] In this embodiment of the disclosure, the material of the gate dielectric layer 201 can be silicon oxide or other suitable materials; the material of the gate metal layer 202 can be any material with good conductivity, such as any one of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu).

[0128] In this embodiment, since the gate structure 200 is located on the opposite surface between the first active layer 171 and the second active layer 172, the gate structure 200 can be a single gate structure. This reduces the volume and complexity of the gate structure 200 and enables a denser layout, thereby reducing the size of the memory.

[0129] Furthermore, the active group 170 (i.e., the first active layer 171 and the second active layer 172) and the gate structure 200 can constitute a single-gate dual-channel transistor. Since the gate structure 200 is located between the first active layer 171 and the second active layer 172 in the active group 170, it not only makes the word lines (i.e., the gate metal layer 202) in adjacent transistors farther apart in the Z-axis direction, reducing the coupling effect between word lines, but also allows two channels in a transistor to be controlled simultaneously by one word line, reducing the number of word lines and simplifying the difficulty of word line fabrication and connection.

[0130] In some embodiments, after forming the gate structure 200, the method for forming the memory 100 further includes: forming, in the gaps between the gate dielectric layers 201 along the Z-axis direction, as shown in the figure. Figure 31 The fourth isolation structure 184 is shown.

[0131] Here, the material of the fourth isolation structure 184 can be any kind of insulating material, such as silicon oxide or silicon oxynitride.

[0132] In some embodiments, after forming the gate structure 200, the method for forming the memory 100 further includes: forming, in the first etched groove 151, a... Figure 31 The bitline structure 220 is shown.

[0133] In this embodiment of the disclosure, the material of the bit line structure 220 can be any material with good conductivity, such as any one of titanium, titanium nitride, tungsten nitride, tungsten, cobalt, platinum, palladium, ruthenium, and copper.

[0134] In this embodiment of the disclosure, after forming the bit line structure 220, in order to avoid damage to the bit line structure 220 by subsequent processes, the method for forming the memory further includes: forming as shown in the figure. Figure 31 The fifth isolation structure 185 on the top surface of the cover bit line structure 220 shown.

[0135] In some embodiments, the method of forming the memory 100 further includes steps S11 to S13.

[0136] Step S11: Through the second etching groove 152, a portion of the second isolation structure 181, a portion of the first active layer 171, and a portion of the second active layer 172 are laterally etched to form a structure as shown in the figure. Figure 33 The fourth transverse groove 157 is shown.

[0137] Please refer to the following when implementing: Figure 32The third sacrificial layer 125 (i.e., the first sub-sacrificial layer 125a and the second sub-sacrificial layer 125b) in the second etched groove 152 is removed. Next, a portion of the second isolation structure 181, a portion of the first active layer 171, and a portion of the second active layer 172 are laterally etched through the second etched groove 152 to form... Figure 33 The fourth transverse groove 157 is shown.

[0138] Step S12, on the exposed surface of the fourth transverse groove 157, form as shown Figure 36 The first electrode 211 is shown.

[0139] During implementation, surfaces exposed by the second etched groove 152 and the fourth transverse groove 157 can be formed as follows: Figure 34 The first initial electrode 211a is shown. Next, the first initial electrode 211a on the surface of the fourth transverse groove 157 is filled with, as shown in the figure. Figure 35 The fourth sacrificial layer 126 is shown. Finally, the first initial electrode 211a in the second etched groove 152 is removed, and the first initial electrode 211a covered by the fourth sacrificial layer 126 forms as shown. Figure 36 The first electrode 211 is shown. Then, the fourth sacrificial layer 126 is removed; here, the material of the fourth sacrificial layer 126 can be one or any combination of silicon nitride, silicon oxynitride, amorphous carbon or silicon carbonitride.

[0140] In some embodiments, please refer to Figure 37 After forming the first electrode 211, the method for forming the memory 100 further includes: removing a portion of the first isolation structure 182 through the second etching groove 152, exposing a portion of the surface of the first electrode 211 along the Y-axis and Z-axis directions.

[0141] This increases the area between the first electrode 211 and the subsequently formed second electrode, thereby increasing the capacitance of the capacitor structure. In other embodiments, it is also possible to directly... Figure 36 A dielectric layer and a second electrode are formed on the surface of the structure shown.

[0142] Step S13, on the exposed surface of the first electrode 211, sequentially form as shown in the figure. Figure 38 The dielectric layer 212 and the second electrode 213 are shown; wherein, the first electrode 211, the dielectric layer 212 and the second electrode 213 constitute a capacitor structure 210, and a plurality of second electrodes 213 arranged along the Y-axis and Z-axis directions are interconnected.

[0143] During implementation, on the exposed surfaces of the first electrode 211 (i.e., the second etched groove 152 and the fourth transverse groove 157), the following are sequentially formed: Figure 38 The dielectric layer 212 and the second electrode 213 are shown.

[0144] In this embodiment of the disclosure, the materials of the first electrode 211 and the second electrode 213 may include metal nitrides or metal silicides, such as titanium nitride. The dielectric material may include a high-k dielectric material, such as one or any combination of lanthanum oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium silicate, or zirconium oxide.

[0145] Finally, please refer to Figure 39 After forming the capacitor structure 200, the method for forming the memory 100 further includes: forming a conductive structure 230 that fills the second etched groove 152; next, removing the fifth isolation structure 185, the first hard mask layer 130, and the second hard mask layer 131 from the top surface of the bit line structure 220 using a CMP process. In this embodiment, the material of the conductive structure 230 may be tungsten.

[0146] In this embodiment, the formed capacitor structure 210 extends along the X-axis direction, meaning that the capacitor structure 210 is arranged horizontally. This horizontal arrangement reduces the possibility of tipping or breaking, thereby improving the stability of the capacitor structure 210. Furthermore, the multiple second electrodes 213 arranged along the Y-axis and Z-axis directions are interconnected (i.e., electrically connected through the conductive structure 230), which further improves the integration density of the memory and enables miniaturization.

[0147] in addition, Figure 40 Another type of memory is shown, and Figure 39 The differences between the memory types shown are: Figure 40 The capacitor in the middle is a single-sided capacitor, which is composed of... Figure 36 The structure shown is formed; Figure 39 The capacitor in the middle is a double-sided capacitor, made of Figure 37 The structure shown is formed.

[0148] In summary, the single-gate dual-channel memory formed by the embodiments of this disclosure can effectively increase the distance of the word lines (i.e., the gate metal layer) in the Z-axis direction, thereby increasing the size of the word lines in the Z-axis direction. This, in turn, increases the memory cell read / write speed while increasing the memory density, and reduces the process integration complexity of word line formation. Furthermore, compared to the word lines (i.e., dual-gate single-channel structure) in the prior art, this disclosure can reduce the number of word line connections, thereby reducing the difficulty of connecting word lines to word line steps.

[0149] In addition, please refer to Figure 39 and Figure 40This disclosure also provides a memory 100, comprising: a substrate 110; a plurality of active groups 170 located on the surface of the substrate 110, arranged in an array along the X-axis and Y-axis directions and stacked along the Z-axis direction; the active groups 170 include a first active layer 171 and a second active layer 172 spaced apart along the Z-axis direction and extending along the X-axis direction; a gate structure 200 located between the first active layer 171 and the second active layer 172 in the active groups 170 and extending along the Y-axis direction; wherein the substrate 110, the first active layer 171 and the second active layer 172 comprise the same semiconductor material; the X-axis direction intersects the Y-axis direction and is parallel to the plane where the substrate 110 is located, and the Z-axis direction is perpendicular to the plane where the substrate 110 is located.

[0150] In this embodiment, the substrate 110, the first active layer 171, and the second active layer 172 are made of the same semiconductor material, for example, both of which can be single-crystal silicon. This ensures high process compatibility during memory formation, reducing production costs and improving memory production yield. On the other hand, the same material has consistent physical parameters such as the coefficient of thermal expansion, which not only ensures a more uniform stress distribution during temperature changes, reducing the generation of local stress, but also allows for uniform heat dissipation, avoiding local overheating.

[0151] In some embodiments, please refer to Figure 39 and Figure 40 In the Z-axis direction, the spacing d2 between the first active layer 171 and the second active layer 172 in the active group 170 is smaller than the spacing d1 between adjacent active groups 170. This allows the distance between adjacent memory cells to be greater in the Z-axis direction, reducing leakage current; at the same time, it makes the thickness of the formed gate structure 200 smaller, ensuring the integration density of the memory.

[0152] In this embodiment of the disclosure, please continue to refer to Figure 39 and Figure 40 The gate structure 200 includes a gate dielectric layer 201 and a gate metal layer 202. The gate dielectric layer 201 is located on the opposite surfaces of the first active layer 171 and the second active layer 172 in the same active group 170. The gate metal layer 202 is located between the gate dielectric layers 201 on the middle surface of the active layers (i.e., the first active layer 171 and the second active layer 172). The multiple gate metal layers 202 arranged along the Y-axis direction are interconnected to form word lines.

[0153] In this embodiment of the disclosure, the active group (i.e., the first active layer and the second active layer) and the gate structure can constitute a transistor with a single-gate dual-channel structure. Since the gate structure is located between the first active layer and the second active layer in the active group, the word lines (i.e., the gate structures) in adjacent transistors are far apart in the Z-axis direction, which reduces the coupling effect between word lines.

[0154] In this embodiment of the disclosure, please continue to refer to Figure 39 and Figure 40 The memory 100 also includes a second isolation structure 181 located between the opposing surfaces of the first active layer 171 and the second active layer 172 in the same active group 170 and adjacent to the gate structure 200.

[0155] In this embodiment of the disclosure, please continue to refer to Figure 39 and Figure 40 The memory 100 also includes a fourth isolation structure 184, located between the gate dielectric layers 201 and adjacent to the gate metal layer 202.

[0156] In this embodiment of the disclosure, please continue to refer to Figure 39 and Figure 40 The memory 100 also includes a capacitor structure 210, which is connected to one end of the first active layer 171 and the second active layer 172 along the X-axis. The capacitor structure 210 includes a first electrode 211, a dielectric layer 212, and a second electrode 213. The first electrode 211 is a cylindrical shape with its opening facing the X-axis (shown as a cross-sectional view in the figure), and the dielectric layer 212 covers the inner surface of the first electrode 211 (e.g., ...). Figure 40 As shown), or the surface covering the inner side and part of the outer side of the first electrode 211 (as shown). Figure 39 As shown, multiple second electrodes 213 arranged along the Y-axis and Z-axis directions are interconnected.

[0157] In this embodiment, the capacitor structure 210 extends along the X-axis, meaning that the capacitor structure 210 formed in this embodiment is arranged horizontally. The horizontal arrangement of the capacitor structure 210 reduces the possibility of tipping over or breaking, thereby improving the stability of the capacitor structure 210. Furthermore, the multiple second electrodes 213 arranged along the Y-axis and Z-axis are interconnected (i.e., electrically connected through the conductive structure 230), which further improves the integration density of the memory and enables miniaturization.

[0158] In this embodiment of the disclosure, please continue to refer to Figure 39 and Figure 40 The memory 100 also includes a bit line structure 220 that extends along the Z-axis and is connected to the other end of the first active layer 171 and the second active layer 172 along the X-axis.

[0159] In this embodiment of the disclosure, please continue to refer to Figure 39 and Figure 40 The memory 100 also includes an insulating structure 160 located at the bottom of the capacitor structure 210 and the bit line structure 220.

[0160] In this embodiment of the disclosure, please continue to refer to Figure 39 and Figure 40 The memory 100 also includes a second padding structure 190 (location can be referenced). Figure 22 The sub-filling structure 191, which fills the space between two adjacent columns of storage cells, includes a third sub-filling structure 191 located on the side wall of the storage cell and a fourth sub-filling structure 192 that fills the gap between the third sub-filling structures 191.

[0161] The memory provided in this embodiment is similar to the memory formed in the above embodiments. For technical features not disclosed in detail in this embodiment, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0162] This disclosure also provides an electronic device. Figure 41 This is a schematic diagram of the structure of an electronic device 300 provided in an embodiment of the present disclosure, as shown below. Figure 41 As shown, the electronic device 300 includes: a processor 310; and a memory 100 in any of the above embodiments; wherein the memory is coupled to the processor.

[0163] In some embodiments, the electronic device includes, but is not limited to, mobile phones, tablets, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, in-vehicle devices, servers, workstations, etc.

[0164] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0165] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0166] The above are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a memory, characterized in that, include: Provide substrate; On the surface of the substrate, a plurality of stacked structures are formed along a first direction and a second direction; the stacked structures include a first semiconductor layer and a second semiconductor layer spaced apart along a third direction, and the substrate, the first semiconductor layer and the second semiconductor layer comprise the same semiconductor material; The first semiconductor layer and the second semiconductor layer are laterally etched along the second direction to form a first active layer and a second active layer extending along the first direction, respectively; the first active layer and the adjacent second active layer constitute an active group; A gate structure extending along the second direction is formed between the first active layer and the second active layer in the active group; Wherein, the first direction intersects the second direction and is parallel to the plane where the memory is located, and the third direction is perpendicular to the plane where the memory is located.

2. The forming method according to claim 1, characterized in that, The stacked structure further includes a first sacrificial layer and a second sacrificial layer, wherein the first sacrificial layer, the first semiconductor layer, the second sacrificial layer, and the second semiconductor layer are stacked alternately along the third direction; Forming multiple stacked structures arranged along a first direction and a second direction, including: An initial stacked structure is formed; the projection of the initial stacked structure on the substrate is a grid shape, including a first initial sacrificial layer, a first initial semiconductor layer, a second initial sacrificial layer, and a second initial semiconductor layer stacked alternately along the third direction; the thickness of the first initial sacrificial layer is greater than the thickness of the second initial sacrificial layer; The intersections in the initial stacked structure are etched along both sides of the first direction to form a first etched groove and a second etched groove, respectively, and the remaining initial stacked structure constitutes multiple stacked structures; Wherein, the projection of the stacked structure onto the substrate is cross-shaped, and two adjacent stacked structures along the first direction share the first etching groove or the second etching groove.

3. The forming method according to claim 2, characterized in that, The method further includes: An insulating structure is formed at the bottom of both the first and second etched grooves; the top surface of the insulating structure does not exceed the bottom surface of the bottommost first semiconductor layer.

4. The forming method according to claim 2, characterized in that, Forming a first active layer and a second active layer extending along the first direction includes: The first sacrificial layer and the second sacrificial layer are removed to form a first transverse groove and a second transverse groove, respectively; the dimension of the first transverse groove along the third direction is larger than the dimension of the second transverse groove along the third direction. A first isolation structure and a second intermediate isolation structure are formed in the first transverse groove and the second transverse groove, respectively; The first and second semiconductor layers are laterally etched along the second direction to form the first active layer and the second active layer; the first active layer and the second active layer on both sides of the second intermediate isolation structure along the third direction constitute an active group.

5. The forming method according to claim 4, characterized in that, The method further includes: Before removing the first sacrificial layer and the second sacrificial layer, a first filling structure is formed between the sidewalls of the plurality of stacked structures along the first direction; After forming the first lateral groove and the second lateral groove, the first semiconductor layer and the second semiconductor layer are simultaneously thinned through the first lateral groove and the second lateral groove.

6. The forming method according to claim 4, characterized in that, A first isolation structure and a second intermediate isolation structure are formed in the first transverse groove and the second transverse groove, respectively, including: A second initial isolation structure is formed on at least the exposed surfaces of the first and second transverse grooves; the thickness of the second initial isolation structure is less than half the third-direction dimension of the first transverse groove and greater than half the third-direction dimension of the second transverse groove. Remove the second initial isolation structure located in the first transverse groove, and the second initial isolation structure located in the second transverse groove constitutes the second intermediate isolation structure; The first isolation structure is formed in the first transverse groove.

7. The forming method according to claim 5, characterized in that, Laterally etching both sides of the first semiconductor layer and the second semiconductor layer along the second direction to form the first active layer and the second active layer, including: The first filling structure is removed to form a third etched groove; the third etched groove exposes both sides of the first semiconductor layer and the second semiconductor layer along the second direction; The first semiconductor layer and the second semiconductor layer are laterally etched through the third etching groove to form the first active layer and the second active layer.

8. The forming method according to claim 7, characterized in that, After forming the first active layer and the second active layer, the method further includes: A third isolation structure is formed in the gap between the first isolation structure and the second intermediate isolation structure along the third direction; The third etched groove is filled with a second filling structure.

9. The forming method according to claim 4, characterized in that, The second intermediate isolation structure includes a first sub-part extending along the second direction, and a second sub-part located on both sides of the first sub-part along the second direction; Forming a gate structure extending along the second direction includes: The second intermediate isolation structure is etched laterally along the first direction through the first etched groove until the first sub-part is removed, forming a third lateral groove, and the remaining second sub-part constitutes the second isolation structure. A gate dielectric layer is formed on the exposed upper and lower surfaces of the third transverse groove; A gate metal layer is formed between the gate dielectric layer on the middle surface of the first active layer and the second active layer; The gate dielectric layer and the gate metal layer constitute the gate structure, and the plurality of gate metal layers arranged along the second direction are interconnected to form word lines.

10. The forming method according to claim 9, characterized in that, After forming the gate structure, the method further includes: A fourth isolation structure is formed in the gap between the gate dielectric layer and the third direction.

11. The forming method according to claim 9 or 10, characterized in that, After forming the gate structure, the method further includes: Bit line structures are formed in the first etched groove.

12. The forming method according to claim 9, characterized in that, The method further includes: The second etched groove is used to etch a portion of the second isolation structure, a portion of the first active layer, and a portion of the second active layer laterally to form a fourth lateral groove. A first electrode is formed on the surface exposed by the fourth transverse groove; A dielectric layer and a second electrode are sequentially formed on the exposed surface of the first electrode; The first electrode, the dielectric layer, and the second electrode constitute a capacitor structure, and a plurality of the second electrodes arranged along the second direction and the third direction are interconnected.

13. The forming method according to claim 12, characterized in that, After forming the first electrode, the method further includes: The second etched groove removes a portion of the first isolation structure, exposing a portion of the surface of the first electrode along the second direction and the third direction.

14. A memory, characterized in that, include: Substrate; Multiple active groups located on the surface of the substrate, arranged in an array along a first direction and a second direction, and stacked along a third direction; The active group includes a first active layer and a second active layer that are spaced apart along the third direction and extend along the first direction; A gate structure located between the first active layer and the second active layer in the active group and extending along the second direction; Wherein, the substrate, the first active layer and the second active layer comprise the same semiconductor material; The first direction intersects the second direction and is parallel to the plane where the substrate is located, while the third direction is perpendicular to the plane where the substrate is located.

15. The forming method according to claim 14, characterized in that, In the third direction, the spacing between the first active layer and the second active layer in the active group is smaller than the spacing between adjacent active groups.

16. An electronic device, characterized in that, include: processor; as well as, A memory, wherein the memory is coupled to the processor, the memory comprising the memory according to claims 14 and 15.

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