Semiconductor device and method of manufacturing the same

Abstract

This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor body, a dielectric material layer, and a contact portion penetrating the dielectric material layer. Along a first direction, the semiconductor body is located on one side of the dielectric material layer. The dielectric material layer contains a dopant element. Along the first direction, the dielectric material layer has a first position and a second position, with the first position located between the second position and the semiconductor body. The doping concentration of the dopant element at the first position is less than the doping concentration at the second position. Along a second direction, the width of the contact portion at the end furthest from the semiconductor body is less than the width of the contact portion at the end closest to the semiconductor body. The first and second directions intersect. The semiconductor device provided by this disclosure reduces the risk of leakage between adjacent contacts and improves reliability.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In semiconductor devices, the contacts connect capacitors and transistors. When making the contacts, etching is required. During the etching process, the aperture formed at the top is relatively large, which leads to a greater risk of leakage between adjacent contacts. Summary of the Invention

[0003] The purpose of this disclosure is to provide a semiconductor device and a method for manufacturing the same, so as to reduce the risk of leakage between two adjacent contacts and improve the reliability of the semiconductor device.

[0004] To achieve the above objectives, this disclosure provides a semiconductor device, including a semiconductor body, a dielectric material layer, and a contact portion penetrating the dielectric material layer. Along a first direction, the semiconductor body is located on one side of the dielectric material layer. The dielectric material layer contains a dopant element. Along the first direction, the dielectric material layer has a first position and a second position, the first position being located between the second position and the semiconductor body. The doping concentration of the dopant element at the first position is less than the doping concentration of the dopant element at the second position. Along a second direction, the width of the contact portion at the end furthest from the semiconductor body is less than the width of the contact portion at the end closest to the semiconductor body. The first direction intersects the second direction.

[0005] In one embodiment of this disclosure, the contact portion is frustum-shaped, and the sidewall of the contact portion is the circumferential sidewall of the frustum.

[0006] In one embodiment of this disclosure, the dielectric material layer is made of silicon nitride, and the doping element in the dielectric material layer is carbon.

[0007] In one embodiment of this disclosure, along the first direction, the carbon doping concentration gradually increases from the side of the dielectric material layer closer to the semiconductor body towards the direction away from the semiconductor body.

[0008] In one embodiment of this disclosure, along the second direction, there are multiple contact portions, and the distance between the ends of two adjacent contact portions that are away from the semiconductor body is greater than the distance between the ends of the two contact portions that are close to the semiconductor body.

[0009] In one embodiment of this disclosure, the semiconductor device further includes a capacitor and a conductive layer; along the second direction, there are multiple semiconductor bodies; along the first direction, each of the multiple semiconductor bodies has a first end and a second end opposite to each other, the first end being connected to the capacitor through the contact portion, and the second end being connected to the conductive layer.

[0010] In one embodiment of this disclosure, the semiconductor device further includes a first gate structure and a second gate structure, wherein the first gate structure and the second gate structure are respectively disposed on both sides of the semiconductor body along the second direction.

[0011] Based on the above objectives, this disclosure also provides a method for manufacturing a semiconductor device, comprising: providing a substrate having a first side and a second side disposed opposite to each other along a first direction; forming a semiconductor body, the semiconductor body including a first end and a second end opposite to each other along the first direction; forming a dielectric material layer on the first side of the substrate, wherein the dielectric material layer contains a dopant element, the dielectric material layer having a first position and a second position along the first direction, the first position being located between the second position and the semiconductor body, the doping concentration of the dopant element at the first position being less than the doping concentration of the dopant element at the second position; forming a via penetrating the dielectric material layer to expose the first end of the semiconductor body; wherein, along the second direction, the size of the via on the surface of the dielectric material layer away from the semiconductor body is smaller than the size of the via on the surface of the dielectric material layer near the semiconductor body, the second direction intersecting the first direction; and forming a contact portion within the via.

[0012] In one embodiment of this disclosure, forming a dielectric material layer on a first side of the substrate includes: using a deposition process to introduce a gas source into a reaction chamber, the gas source including a carbon source gas, a nitrogen source gas, and a silicon source gas, wherein the supply amount of the carbon source gas at a first moment is less than the supply amount of the carbon source gas at a second moment; wherein the second moment is later than the first moment.

[0013] In one embodiment of this disclosure, forming a dielectric material layer on a first side of the substrate includes: employing a deposition process to introduce a gas source into a reaction chamber, the gas source including a carbon source gas, a nitrogen source gas, and a silicon source gas; and gradually increasing the supply of carbon source gas as the deposition time increases, so that the carbon doping concentration in the dielectric material layer gradually increases from the side of the dielectric material layer closer to the semiconductor substrate to the direction away from the semiconductor substrate.

[0014] In one embodiment of this disclosure, forming a dielectric material layer on a first side of the substrate includes: depositing a silicon nitride layer on the first side of the substrate; and performing ion implantation on at least a first location and a second location of the silicon nitride layer to form the dielectric material layer, wherein the first location is located between the second location and the semiconductor body, and the implanted ions and their concentration are configured such that the etching rate of the first location of the dielectric material layer is greater than the etching rate of the second location.

[0015] In one embodiment of this disclosure, the implanted ions include carbon ions, and the concentration of carbon ions at the first position is less than the concentration of carbon ions at the second position.

[0016] In one embodiment of this disclosure, forming a dielectric material layer on a first side of the substrate includes: depositing a silicon nitride layer on the first side of the substrate; and performing ion implantation on the silicon nitride layer to form the dielectric material layer, wherein the implanted ions and their concentration are configured such that the etching rate of the dielectric material layer gradually decreases from the side of the dielectric material layer closer to the semiconductor body towards the direction away from the semiconductor body.

[0017] In one embodiment of this disclosure, the implanted ions include carbon ions, and the concentration of the carbon ions gradually increases from the side of the dielectric material layer closer to the semiconductor body toward the direction away from the semiconductor body.

[0018] The main beneficial effects of this disclosure are:

[0019] The semiconductor device disclosed herein includes a dielectric material layer containing doped elements. Along a first direction, the dielectric material layer has a first position and a second position. The first position is located between the second position and the semiconductor body. Since the doping concentration of the doped element at the first position is less than that at the second position, the etching rates at the first and second positions can be different when etching the dielectric material layer. Simultaneously, along the second direction, the width of the end of the contact portion away from the semiconductor body is less than the width of the end of the contact portion close to the semiconductor body. This effectively increases the distance between the ends of two adjacent contacts that are away from the semiconductor body, reducing the risk of leakage between two adjacent contacts and improving the reliability of the semiconductor device.

[0020] The semiconductor device manufacturing method disclosed herein involves adding doping elements such that the doping concentration of the doping element at a first location is less than that at a second location. During the etching of the dielectric material layer to form a through-hole, the etching rates at the first and second locations are different. Simultaneously, along the second direction, the size of the formed through-hole on the surface of the dielectric material layer away from the semiconductor body is smaller than the size of the through-hole on the surface of the dielectric material layer close to the semiconductor body. After forming a contact portion within the through-hole, it is ensured that along the second direction, the width of the contact portion away from the semiconductor body is smaller than the width of the contact portion close to the semiconductor body. This effectively increases the distance between the ends of two adjacent contacts away from the semiconductor body, reducing the risk of leakage between adjacent contacts and improving the reliability of the semiconductor device. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;

[0023] Figure 2 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure (capacitors not shown);

[0024] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0025] Figures 4 to 15 This is a partial structural schematic diagram of a semiconductor structure formed after performing certain steps in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0026] The technical solutions of this disclosure will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0027] Generally, terms can be understood, at least in part, based on their use in context. For example, the term "one or more," depending at least in part on the context, can be used to describe any feature, structure, or characteristic in the singular or in the plural form to describe a combination of features, structures, or characteristics. Similarly, terms such as "a" or "described" in this document can also be understood, at least in part on the context, to convey either a singular or plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, again, depending at least in part on the context.

[0028] It should be readily understood that, in the description of this disclosure, it is necessary to clarify that the meanings of “on,” “above,” and “above” should be interpreted in the broadest sense, such that “on” not only means “directly on” something, but also includes the meaning of being “on” something with an intermediate feature or layer between them. Furthermore, “above” or “above” not only means “on” or “above” something, but can also include it being “on” or “above” something without an intermediate feature or layer between them (i.e., directly on something).

[0029] Furthermore, for ease of description, this document uses spatially relative terms such as "below," "below," "lower layer," "above," "upper layer," etc., to describe the relationship between one element or feature and another element or feature as shown in the figure. Spatially related terms are intended to include different orientations of the device in use or process steps (in addition to the orientation shown in the figure). The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted accordingly.

[0030] In the description of this disclosure, the term "substrate" refers to a material on which subsequent material layers are added. A substrate includes a front side and a back side. The front side of the substrate is typically where a semiconductor device is formed; unless otherwise stated, the semiconductor device is formed on the front side of the substrate, and the back side is opposite to the front side. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0031] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend integrally over the structure of a bottom or upper layer, or may have a range smaller than that of the bottom or upper layer. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers therein, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnects, and / or vertical interconnect pathways are formed) and one or more dielectric layers.

[0032] In this disclosure, the terms “horizontal / horizontally / laterally” mean nominally parallel to the lateral surface of the substrate, and the terms “vertical” or “perpendicularly” mean nominally perpendicular to the lateral surface of the substrate.

[0033] See Figure 1 and Figure 2 As shown, this embodiment provides a semiconductor device including a semiconductor body 10, a dielectric material layer 20, and a contact portion 30 penetrating the dielectric material layer 20. Along a first direction, the semiconductor body 10 is located on one side of the dielectric material layer 20. The dielectric material layer 20 contains doped elements. Along the first direction, the dielectric material layer has a first position and a second position. The first position is located between the second position and the semiconductor body. The doping concentration of the doped element at the first position is less than the doping concentration of the doped element at the second position. Along a second direction, the width of the contact portion 30 at the end away from the semiconductor body 10 is less than the width of the contact portion 30 at the end close to the semiconductor body 10. The first direction and the second direction intersect.

[0034] by Figure 1 For example, in this embodiment, the first direction is represented by arrow direction D1, and the second direction is represented by arrow direction D2. For instance, the first direction is perpendicular to the second direction.

[0035] The semiconductor device provided in this embodiment has a dielectric material layer 20 containing doped elements. Along a first direction, the dielectric material layer has a first position and a second position. The first position is located between the second position and the semiconductor body. Since the doping concentration of the doped element at the first position is less than that at the second position, the etching rates at the first and second positions can be different when etching the dielectric material layer. At the same time, along the second direction, the width of the end of the contact portion 30 away from the semiconductor body 10 is less than the width of the end of the contact portion 30 close to the semiconductor body 10. This is equivalent to increasing the distance between the ends of two adjacent contacts away from the semiconductor body 10, reducing the risk of leakage between two adjacent contacts, and improving the reliability of the semiconductor device.

[0036] It should be understood that, along the first direction, the contact portion 30 has a first end and a second end, the first end being located on the side of the dielectric material layer 20 closer to the semiconductor body 10, and the first end of the contact portion 30 being connected to the semiconductor body 10, and the second end being located on the side of the dielectric material layer 20 away from the semiconductor body 10.

[0037] See Figure 2 As shown, the width of the end of the contact portion 30 away from the semiconductor body 10 refers to the maximum width W1 of the second end of the contact portion 30 along the second direction; the width of the end of the contact portion 30 close to the semiconductor body 10 refers to the maximum width W2 of the first end of the contact portion 30 along the second direction.

[0038] In some embodiments, the first position and the second position may refer to the layers where the first end and the second end of the contact portion are located, respectively. That is, the first position refers to the surface of the dielectric material layer 20 close to the semiconductor body 10, and the second position refers to the surface of the dielectric material layer 20 away from the semiconductor body 10.

[0039] In other embodiments, the first position and the second position may also be any two positions distributed along the first direction between the two surfaces of the dielectric material layer.

[0040] For example, the contact portion 30 is frustum-shaped, and the sidewall 31 of the contact portion 30 is the circumferential sidewall of the frustum.

[0041] The cross-sectional shape of the contact portion 30 is circular. It should be understood that the circular shape of the cross-sectional shape of the contact portion 30 means that it is approximately circular within the allowable machining error range.

[0042] The cross-section of the contact portion 30 is perpendicular to the first direction. Along the first direction, the diameter of the cross-section of the contact portion 30 varies at different locations. For example, the diameter of the cross-section of the contact portion 30 at a first location is larger than the diameter of the cross-section of the contact portion 30 at a second location.

[0043] In this embodiment, the maximum width W1 of the second end of the contact portion 30 along the second direction is the diameter of the second end of the contact portion 30; the maximum width W2 of the first end of the contact portion 30 along the second direction is the diameter of the first end of the contact portion 30.

[0044] In one embodiment, see Figure 1 As shown, along the first direction, the contact portion 30 includes a first structural layer 3010, a second structural layer 3020, a third structural layer 3030, and a fourth structural layer 3040. The first structural layer 3010 contacts the semiconductor body 10, and the material of the first structural layer 3010 can be polycrystalline silicon. The second structural layer 3020 contacts the first structural layer 3010, and the material of the second structural layer 3020 can be cobalt silicon. The third structural layer 3030 can serve as an adhesive layer. For example, a portion of the adhesive layer can be located between the second structural layer 3020 and the fourth structural layer 3040, and another portion of the adhesive layer can be located on the circumferential sidewall of the fourth structural layer 3040. The material of the third structural layer 3030 can be titanium nitride, and the material of the fourth structural layer 3040 can be a conductive material, such as tungsten.

[0045] See Figure 1 As shown, the semiconductor device also includes a capacitor 40 and a conductive layer 50; along the second direction, there are multiple semiconductor bodies 10; along the first direction, each of the multiple semiconductor bodies 10 has a first end and a second end, the first end is connected to the capacitor 40 through a contact portion 30, and the second end is connected to the conductive layer 50.

[0046] For example, the first end of the semiconductor body 10 can serve as the source and be connected to the capacitor 40. Specifically, the first end of the semiconductor body 10 is connected to the first end of the contact portion 30, and the second end of the contact portion 30 is connected to the capacitor 40. The second end of the semiconductor body 10 can serve as the drain and be connected to the conductive layer 50 (e.g., bit line).

[0047] In one embodiment, see Figure 2 As shown, along the second direction, there are multiple contact portions 30, and the distance L1 between the ends of two adjacent contact portions 30 that are away from the semiconductor body 10 is greater than the distance L2 between the ends of the two contact portions 30 that are close to the semiconductor body 10.

[0048] It should be noted that, Figure 2 Only the four middle contact parts are shown; the contact parts on both sides are not shown.

[0049] By adjusting the doping concentration of dopants at different locations, the etching rate can be changed so that L1 is greater than L2. This increases the distance between the ends of two adjacent contacts that are far from the semiconductor body 10, reduces the risk of leakage between adjacent contacts, and improves the reliability of the semiconductor device.

[0050] The distance L1 between the ends of two adjacent contact portions 30 that are furthest from the semiconductor body is the distance between the second ends of two adjacent contact portions 30. Since the cross-sectional shape of the contact portion 30 is circular, the distance L1 refers to the minimum distance between the second ends of two adjacent contact portions 30 along the second direction. Correspondingly, the distance L2 between the ends of two adjacent contact portions 30 that are furthest from the semiconductor body 10 refers to the minimum distance between the first ends of two adjacent contact portions 30 along the second direction.

[0051] When the centers of the cross-sections of two adjacent contact portions 30 are arranged along the second direction, the aforementioned distance L1 can also refer to the radial distance between the second ends of the two adjacent contact portions 30. Correspondingly, the distance L2 between the ends of two adjacent contact portions 30 that are away from the semiconductor body 10 can also refer to the radial distance between the first ends of the two adjacent contact portions 30.

[0052] For example, the semiconductor device provided in this embodiment may be Dynamic Random Access Memory (DRAM). DRAM may include multiple memory cells, and each memory cell includes a vertical transistor and a capacitor. For example, each memory cell may include one vertical transistor and one capacitor.

[0053] In one embodiment, see Figure 1 As shown, the semiconductor device also includes a first gate structure 60 and a second gate structure 70, which are respectively disposed on both sides of the semiconductor body 10 along the second direction.

[0054] For example, the semiconductor body 10 may include a channel structure of a vertical transistor and source and drain regions located at both ends of the channel structure. The first gate structure 60 may serve as the positive gate of the vertical transistor, and the second gate structure 70 may serve as the back gate of the vertical transistor. The second gate structures of two adjacent vertical transistors are connected together, and in the manufacturing process, the second gate structures of two adjacent vertical transistors can be fabricated simultaneously.

[0055] In one embodiment, the dielectric material layer 20 is made of silicon nitride, and the doping element in the dielectric material layer 20 includes carbon, so that the etching rate of the dielectric material layer at the first location is greater than the etching rate of the dielectric material layer at the second location.

[0056] Doping silicon nitride with carbon can form silicon carbon nitride. Compared with silicon nitride, silicon carbon nitride is more resistant to hydrofluoric acid corrosion. The etching rate of silicon carbon nitride is lower than that of silicon nitride. The higher the carbon doping concentration in silicon carbon nitride, the slower the etching rate.

[0057] For example, the first position can be located on the surface of the dielectric material layer close to the semiconductor body, and the second position can be located on the surface of the dielectric material layer away from the semiconductor body. Since the doping concentration of carbon element at the first position is less than that of doping element at the second position, the etching rate of the dielectric material layer at the first position is greater than that at the second position. That is, during the etching of the dielectric material layer to form a through-hole, less dielectric material layer is etched away at the second position, while more dielectric material layer is etched away at the first position. This is equivalent to increasing the distance between two adjacent through-holes at the first position. After the contact portion is formed, the distance between the ends of the contact portion away from the semiconductor body 10 is also increased accordingly, thereby reducing the risk of leakage between two adjacent contact portions and improving the reliability of the semiconductor device. At the same time, it can also ensure good contact between the contact portion and the semiconductor body.

[0058] In one embodiment, along the first direction, the carbon doping concentration gradually increases from the side of the dielectric material layer 20 near the semiconductor body 10 towards the direction away from the semiconductor body 10. This allows the etching rate of the dielectric material layer to gradually decrease from the side near the semiconductor body 10 towards the direction away from the semiconductor body 10, enabling a smooth transition of the hole wall formed after etching. For example, the hole wall can be a circumferential sidewall of a frustum. The contact portion formed within the via is frustum-shaped, and the sidewall 31 of the contact portion 30 is a circumferential sidewall of a frustum.

[0059] See Figure 3 As shown, this embodiment also provides a method for manufacturing a semiconductor device, which may include the following steps:

[0060] Step S302, a substrate 100 is provided, the substrate 100 having a first side and a second side disposed opposite to each other along a first direction;

[0061] Step S304: Forming a semiconductor body 10, wherein along a first direction, the semiconductor body 10 includes opposing first ends and second ends;

[0062] Step S306: A dielectric material layer 20 is formed on the first side of the substrate 100, wherein the dielectric material layer 20 contains doped elements, and along the first direction, the dielectric material layer 20 has a first position and a second position, the first position is located between the second position and the semiconductor body, and the doping concentration of the doped element at the first position is less than the doping concentration of the doped element at the second position.

[0063] Step S308: Form a via 301 through the dielectric material layer 20 to expose the first end of the semiconductor body 10; wherein, along the second direction, the size of the via 301 on the surface of the dielectric material layer 20 away from the semiconductor body 10 is smaller than the size of the via 301 on the surface of the dielectric material layer 20 close to the semiconductor body 10, and the second direction intersects the first direction.

[0064] Step S310: A contact portion 30 is formed in the through hole 301.

[0065] The semiconductor device manufacturing method provided in this embodiment adds a doping element such that the doping concentration of the doping element at the first position is less than that at the second position. During the etching of the dielectric material layer to form a via 301 penetrating the dielectric material layer 20, the etching rates at the first and second positions are different. At the same time, along the second direction, the size of the via 301 on the surface of the dielectric material layer 20 away from the semiconductor body 10 is smaller than the size of the via 301 on the surface of the dielectric material layer 20 close to the semiconductor body 10. After forming the contact portion 30 in the via 301, it can be ensured that along the second direction, the width of the end of the contact portion 30 away from the semiconductor body 10 is smaller than the width of the end of the contact portion 30 close to the semiconductor body 10. This is equivalent to increasing the distance between the ends of two adjacent contacts away from the semiconductor body 10, reducing the risk of leakage between two adjacent contacts, and improving the reliability of the semiconductor device.

[0066] It should be understood that, Figure 3 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 3 The steps shown can be adjusted in order according to actual needs. Figures 4 to 15 This is a partial structural schematic diagram of a semiconductor structure formed after performing certain steps in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. The following is in conjunction with... Figure 3 , Figures 4 to 15 The method for manufacturing a semiconductor device provided in the embodiments of this disclosure will be described in detail.

[0067] In step S302, the provided substrate 100 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0068] It should be understood that substrate 100 can be retained, removed, or thinned.

[0069] In step S304, forming a semiconductor body 10 includes forming a channel structure and a source and a drain located at both ends of the channel structure. For example, the first end of the semiconductor body 10 can serve as the source, and the second end can serve as the drain.

[0070] In some embodiments, the material of the semiconductor body can be the same as that of the substrate, so there is no obvious interface between the semiconductor body and the substrate.

[0071] See Figure 4 As shown, some exemplary processes following the formation of the semiconductor body 10 further include: forming a second gate structure 70 and a conductive material layer 600, the second gate structure 70 and the conductive material layer 600 being located on opposite sides of the semiconductor body 10. The conductive material layer 600 is joined together at its end near the second side of the substrate and will be broken in a subsequent process to form two first gate structures 60.

[0072] It should be noted that the process steps for forming the first gate structure and the second gate structure are understandable to those skilled in the art and are well-known and easy to implement for them; therefore, they will not be described in detail in this embodiment.

[0073] In step S306, the formation of the dielectric material layer 20 on the first side of the substrate 100 can be achieved by at least two methods: in-situ doping and ion implantation, which will be described in detail below.

[0074] In one embodiment, forming a dielectric material layer 20 on a first side of a substrate includes: using a deposition process to introduce a gas source into a reaction chamber, the gas source including a carbon source gas, a nitrogen source gas, and a silicon source gas, wherein the supply amount of the carbon source gas at a first moment is less than the supply amount of the carbon source gas at a second moment; wherein the second moment is later than the first moment.

[0075] Specifically, during the deposition process, doping elements, such as carbon, are introduced to achieve in-situ carbon doping, and the resulting dielectric material layer is made of silicon, carbon, and nitrogen.

[0076] For example, at the start of deposition, carbon source gas, nitrogen source gas, and silicon source gas are simultaneously introduced into the reaction chamber. The supply of carbon source gas at the first moment is less than the supply of carbon source gas at the second moment. The position of the silicon-carbon-nitrogen film layer formed at the first moment in the dielectric material layer 20 is the first position of the dielectric material layer 20. The position of the silicon-carbon-nitrogen film layer formed at the second moment in the dielectric material layer 20 is the second position of the dielectric material layer 20. Therefore, when the dielectric material layer 20 is subsequently etched, the etching rate at the first position is greater than the etching rate at the second position.

[0077] For example, the deposition process can be one or a combination of chemical vapor deposition (CVD) and atomic layer deposition (ALD).

[0078] In some embodiments, the first moment can be the initial moment of in-situ doping, for example, the moment when the carbon source gas first participates in the material growth; the second moment can be the final moment of in-situ doping, for example, the moment when the carbon source gas supply stops or the moment when the film growth stops.

[0079] It should be understood that the time when the carbon source gas supply stops can coincide with or precede the time when the membrane stops growing.

[0080] Accordingly, the first position is the position where the dielectric material layer 20 contacts the semiconductor body 10, and the second position is the position where the dielectric material layer 20 is furthest from the semiconductor body 10.

[0081] In other embodiments, the first time and the second time can also be any two different times other than the initial time and the final time during the deposition process.

[0082] In one embodiment, see Figure 5 As shown, forming a dielectric material layer 20 on the first side of the substrate 100 includes: using a deposition process to introduce a gas source into the reaction chamber, the gas source including carbon source gas, nitrogen source gas and silicon source gas, and gradually increasing the supply of carbon source gas as the deposition time increases, so that the doping concentration of carbon element in the dielectric material layer 20 gradually increases from the side of the dielectric material layer 20 close to the semiconductor body 10 to the direction away from the semiconductor body 10.

[0083] For example, the supply of carbon source gas can be gradually increased. This can be done by adding a specific amount of carbon source gas at set intervals, or by increasing the supply of carbon source gas according to a set ratio as the deposition time increases. This ensures that the carbon doping concentration in the dielectric material layer 20 gradually increases from the side of the dielectric material layer 20 closest to the semiconductor substrate 10 towards the direction away from the semiconductor substrate 10. This guarantees that the etching rate of the dielectric material layer 20 gradually decreases from the side of the dielectric material layer 20 closest to the semiconductor substrate 10 towards the direction away from the semiconductor substrate 10. In this way, a smoothly transitioned hole wall can be formed during the subsequent formation of the via 301. For example, the hole wall can be the circumferential sidewall of a frustum.

[0084] It should be noted that there are no restrictions on the setting time or the setting ratio.

[0085] In one embodiment, see Figure 6AAs shown, a dielectric material layer is formed on the first side of the substrate, including: depositing a silicon nitride layer 200 on the first side of the substrate; see also Figure 6B As shown, an ion implantation process is used to implant ions into at least a first position and a second position of a silicon nitride layer to form a dielectric material layer 20', wherein the first position is located between the second position and the semiconductor body, and the implanted ions and their concentration are configured such that the etching rate of the first position of the dielectric material layer 20 is greater than the etching rate of the second position.

[0086] For example, the first location can be located on the surface of the silicon nitride layer 200 close to the semiconductor body 10, and the second location can be located on the surface of the silicon nitride layer 200 away from the semiconductor body 10. During the etching and cleaning steps of the dielectric material layer 20' to form the via, less dielectric material layer is etched away at the second location, while more dielectric material layer is etched away at the first location. This is equivalent to increasing the distance between two adjacent vias at the first location. After the contact portion 30 is subsequently formed, the distance between the ends of the contact portion 30 away from the semiconductor body 10 is also increased accordingly, thereby reducing the risk of leakage between two adjacent contacts and improving the reliability of the semiconductor device; at the same time, it can also ensure good contact between the contact portion and the semiconductor body.

[0087] For example, the implanted ions include carbon ions, and the concentration of carbon ions at the first site is less than the concentration of carbon ions at the second site. This ensures that the etching rate at the first site of the dielectric material layer 20' is greater than the etching rate at the second site.

[0088] It should be understood that during ion implantation, the dopant element is initially implanted into the material layer, such as the silicon nitride layer 200, in ionic form. For example, the dopant element in the dielectric material layer 20' is carbon. The carbon element is initially implanted into the silicon nitride layer 200 in the form of carbon ions.

[0089] In one embodiment, forming a dielectric material layer on a first side of a substrate includes: depositing a silicon nitride layer 200 on the first side of the substrate; and performing ion implantation on the silicon nitride layer to form a dielectric material layer 20', wherein the implanted ions and their concentration are configured such that the etching rate of the dielectric material layer 20' gradually decreases from the side of the dielectric material layer 20' close to the semiconductor body 10 toward the direction away from the semiconductor body 10.

[0090] For example, during ion implantation, by adjusting process parameters, such as changing the energy of the implanted ions and controlling the implantation dose and number of implantations, ion distribution can be achieved at different depths of the silicon nitride layer, and a concentration gradient along the first direction can be formed through subsequent heat treatment or other methods.

[0091] For example, the implanted ions include carbon ions, and the concentration of carbon ions gradually increases from the side of the dielectric material layer 20 near the semiconductor body 10 towards the direction away from the semiconductor body 10. In this way, a smooth transition surface can be formed during the subsequent formation of the via 301. For example, the hole wall can be the circumferential sidewall of a frustum.

[0092] It should be noted that the energy of the carbon ions, as well as the dosage and number of implantations, are not limited here.

[0093] It should also be noted that when the second position is located below the surface of the dielectric material layer away from the semiconductor substrate, the dopant element can also be phosphorus or arsenic. For example, phosphorus or arsenic ions can be implanted into the silicon nitride layer using an ion implantation process.

[0094] In step S308, see Figure 7 and Figure 8 As shown, an etching process can be used to form a through-hole 301 that penetrates the dielectric material layer 20 to expose the first end of the semiconductor body 10, so that the first end of the semiconductor body 10 can be connected to the capacitor.

[0095] See Figure 7 As shown, a dry etching process can be used, for example, for... Figure 5 In the semiconductor structure shown, the dielectric material layer 20 is etched to form a via 301A with a large top dimension and a small bottom dimension. A post-etching cleaning step can then be performed to remove residues or contaminants generated during the etching process, improving process reliability and device performance. Hydrofluoric acid is typically used during cleaning. Since the dielectric material layer is silicon-carbon-nitrogen (SiCNI), the higher the carbon doping concentration in SiCNI, the stronger its resistance to hydrofluoric acid corrosion, and the slower the etching rate. Therefore, during cleaning, the etching rate of the dielectric material layer further away from the semiconductor substrate is slower, ensuring that the aperture of via 301A on the side of the dielectric material layer away from the semiconductor substrate hardly expands further. Simultaneously, the aperture of via 301A gradually expands radially towards the semiconductor substrate to form via 301. Figure 8 As shown.

[0096] For example, the cross-sectional shape of the formed through hole 301 can be circular. It should be understood that the circular shape of the cross-sectional shape of the through hole 301 means approximately circular within the allowable machining error range.

[0097] The cross-section of the through hole 301 is perpendicular to the first direction. Along the first direction, the diameter of the cross-section of the through hole 301 varies at different locations. For example, the diameter of the cross-section of the through hole 301 at the first location is larger than the diameter of the cross-section of the through hole 301 at the second location.

[0098] Since the dielectric material layer 20 has a certain thickness, the via 301 has a certain depth. For example, when the etching rate of the dielectric material layer 20 gradually decreases from the side of the dielectric material layer 20 close to the semiconductor body 10 to the direction away from the semiconductor body 10, the via 301 can be understood as a hollow frustum-shaped channel.

[0099] For example, the dimension W3 of the via 301 on the surface of the dielectric layer 20 away from the semiconductor body 10 refers to the diameter of the via 301 on the surface of the dielectric layer 20 away from the semiconductor body 10, and the dimension W4 of the via 301 on the surface of the dielectric layer 20 near the semiconductor body 10 refers to the diameter of the via 301 on the surface of the dielectric layer 20 near the semiconductor body 10; see also Figure 8 As shown, W3 is less than W4.

[0100] In some embodiments, the dielectric material layer 20 is made of silicon, carbon, and nitrogen. When the second position is the surface of the dielectric material layer away from the semiconductor body, the carbon content at the second position is the largest, and it will hardly be corroded by hydrofluoric acid during subsequent cleaning. Therefore, in the initial stage of forming the via, the size W3 of the via 301 on the surface of the dielectric material layer 20 away from the semiconductor body 10 can be made larger, which is beneficial for subsequent further etching to form a via with a good morphology.

[0101] In step S310, a contact portion 30 is formed in the through hole 301.

[0102] See Figure 2 and 8 As shown, the maximum width W1 of the second end of the contact portion 30 along the second direction is substantially equal to the size W3 of the through hole 301 on the surface of the dielectric material layer 20 away from the semiconductor body 10; the maximum width W2 of the first end of the contact portion 30 along the second direction is substantially equal to the diameter W4 of the through hole 301 on the surface of the dielectric material layer 20 close to the semiconductor body 10.

[0103] For example, see Figure 9 As shown, a first material layer 311 is deposited into the via 301. The first material layer 311 can be polysilicon. Then, a portion of the first material layer 311 is etched back, and the retained first material layer can serve as the first structural layer 3010. The resulting structure is as follows. Figure 10 As shown; see also Figure 11 As shown, a second material layer 312 is deposited above the retained first structural layer 3010. This second material layer can serve as a second structural layer 3020, and the second material layer 312 can be cobalt silicon. (See also...) Figure 12As shown, a third material is deposited on the surface of the second material layer and the walls of the through-hole 301 to form a third structural layer 3030. The third material can be titanium nitride. Then, a fourth material is deposited into the remaining space of the through-hole to form a fourth structural layer 3040. The fourth material can be tungsten. See also Figure 13 As shown, a capacitor 40 is formed on the side of the contact portion 30 away from the semiconductor body.

[0104] In some exemplary processes following the formation of the contact portion 30 within the via 301, the process further includes: removing a portion of the substrate and a portion of the conductive material layer 600 from the first surface, thereby breaking the conductive material layer 600 and forming two first gate structures 60 with the remaining conductive material layer 600. The first gate structures 60 can serve as word lines of vertical transistors, and the resulting structure is as follows: Figure 14 As shown.

[0105] See Figure 15 As shown, some exemplary processes following the formation of the first gate structure 60 also include: forming a conductive layer 50, which may serve as a bit line of a vertical transistor.

[0106] It should be noted that the semiconductor device provided in this embodiment can be manufactured using the semiconductor device manufacturing method provided in this embodiment.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor device, characterized in that, The device includes a semiconductor body, a dielectric material layer, and a contact portion penetrating the dielectric material layer. Along a first direction, the semiconductor body is located on one side of the dielectric material layer. The dielectric material layer contains a dopant element. Along the first direction, the dielectric material layer has a first position and a second position. The first position is located between the second position and the semiconductor body. The doping concentration of the dopant element at the first position is less than the doping concentration of the dopant element at the second position. Along the second direction, the width of the end of the contact portion away from the semiconductor body is smaller than the width of the end of the contact portion close to the semiconductor body, wherein the first direction intersects the second direction.

2. The semiconductor device according to claim 1, characterized in that, The contact portion is shaped like a frustum, and the sidewall of the contact portion is the circumferential sidewall of the frustum.

3. The semiconductor device according to claim 1, characterized in that, The dielectric material layer is made of silicon nitride, and the doping element in the dielectric material layer includes carbon.

4. The semiconductor device according to claim 3, characterized in that, Along the first direction, the carbon doping concentration gradually increases from the side of the dielectric material layer closer to the semiconductor body towards the direction away from the semiconductor body.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, Along the second direction, there are multiple contact portions, and the distance between the ends of two adjacent contact portions that are away from the semiconductor body is greater than the distance between the ends of the two contact portions that are close to the semiconductor body.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that, It also includes a capacitor and a conductive layer; along the second direction, there are multiple semiconductor bodies; along the first direction, each of the multiple semiconductor bodies has a first end and a second end, the first end being connected to the capacitor through the contact portion, and the second end being connected to the conductive layer.

7. The semiconductor device according to any one of claims 1 to 4, characterized in that, It also includes a first gate structure and a second gate structure, which are respectively disposed on both sides of the semiconductor body along the second direction.

8. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the substrate having a first side and a second side disposed opposite to each other along a first direction; A semiconductor body is formed, and along the first direction, the semiconductor body includes opposing first and second ends; A dielectric material layer is formed on a first side of the substrate, wherein the dielectric material layer contains a dopant element, and along the first direction, the dielectric material layer has a first position and a second position, the first position being located between the second position and the semiconductor body, and the doping concentration of the dopant element at the first position being less than the doping concentration of the dopant element at the second position. A via is formed through the dielectric material layer to expose a first end of the semiconductor body; wherein, along a second direction, the size of the via on the surface of the dielectric material layer away from the semiconductor body is smaller than the size of the via on the surface of the dielectric material layer near the semiconductor body, and the second direction intersects the first direction; A contact portion is formed within the through hole.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, A dielectric material layer is formed on a first side of the substrate, comprising: A deposition process is employed, in which a gas source is introduced into the reaction chamber. The gas source includes a carbon source gas, a nitrogen source gas, and a silicon source gas. The supply amount of the carbon source gas at a first moment is less than the supply amount of the carbon source gas at a second moment; wherein, the second moment is later than the first moment.

10. The method for manufacturing a semiconductor device according to claim 8, characterized in that, A dielectric material layer is formed on a first side of the substrate, comprising: A deposition process is employed, in which a gas source is introduced into the reaction chamber. The gas source includes carbon source gas, nitrogen source gas, and silicon source gas. As the deposition time increases, the supply of carbon source gas is gradually increased so that the carbon doping concentration in the dielectric material layer gradually increases from the side of the dielectric material layer closer to the semiconductor substrate to the side farther away from the semiconductor substrate.

11. The method for manufacturing a semiconductor device according to claim 8, characterized in that, A dielectric material layer is formed on a first side of the substrate, comprising: A silicon nitride layer is deposited on the first side of the substrate; An ion implantation process is used to implant ions into at least a first position and a second position of the silicon nitride layer to form the dielectric material layer, wherein the first position is located between the second position and the semiconductor body, and the implanted ions and their concentration are configured such that the etching rate of the first position of the dielectric material layer is greater than the etching rate of the second position.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, The injected ions include carbon ions, and the concentration of carbon ions at the first position is less than the concentration of carbon ions at the second position.

13. The method for manufacturing a semiconductor device according to claim 8, characterized in that, A dielectric material layer is formed on a first side of the substrate, comprising: A silicon nitride layer is deposited on the first side of the substrate; The silicon nitride layer is ion implanted using an ion implantation process to form the dielectric material layer, wherein the implanted ions and their concentration are configured such that the etching rate of the dielectric material layer gradually decreases from the side of the dielectric material layer closer to the semiconductor substrate toward the direction away from the semiconductor substrate.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The implanted ions include carbon ions, and the concentration of the carbon ions gradually increases from the side of the dielectric material layer closer to the semiconductor body towards the direction away from the semiconductor body.

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