Three-dimensional memory and methods of making the same, memory systems

Abstract

This application provides a three-dimensional memory and its fabrication method, as well as a memory system. The three-dimensional memory includes: a first semiconductor structure, which includes peripheral circuitry; a second semiconductor structure, located on one side of the first semiconductor structure along a first direction, which includes a first memory array and is coupled to the first semiconductor structure; and a third semiconductor structure, located along the first direction on the side of the first semiconductor structure away from the second semiconductor structure, which includes a second memory array and is coupled to the first semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and fabrication, and in particular to a three-dimensional memory and its fabrication method, and a memory system. Background Technology

[0002] In related technologies, planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells approaches its upper limit. 3D memory architecture can solve the density limitation problem in planar memory cells. 3D memory architecture includes a memory array and peripheral circuitry for controlling signals traveling to and from the memory array.

[0003] However, how to further improve storage density remains a problem worth paying attention to. Summary of the Invention

[0004] This application provides a three-dimensional memory and its fabrication method and memory system that can at least partially solve the above-mentioned problems in related technologies or other problems in the art.

[0005] In a first aspect, a three-dimensional memory is provided, the three-dimensional memory comprising: a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure, wherein the first semiconductor structure includes peripheral circuitry; the second semiconductor structure is located on one side of the first semiconductor structure along a first direction, the second semiconductor structure includes a first memory array, and the second semiconductor structure is coupled to the first semiconductor structure; along the first direction, the third semiconductor structure is located on the side of the first semiconductor structure away from the second semiconductor structure, the third semiconductor structure includes a second memory array, and the third semiconductor structure is coupled to the first semiconductor structure.

[0006] In one embodiment of this application, the first semiconductor structure and the second semiconductor structure are coupled through a first bonding layer; the first semiconductor structure and the third semiconductor structure are coupled through a second bonding layer.

[0007] In one embodiment of this application, the first bonding layer includes a first sub-bonding layer and a second sub-bonding layer; the first sub-bonding layer includes a first bonding contact, the second sub-bonding layer includes a second bonding contact, and the first bonding contact is in contact with the second bonding contact.

[0008] In one embodiment of this application, the second bonding layer includes a third sub-bonding layer and a fourth sub-bonding layer; the third sub-bonding layer includes a third bonding contact, the fourth sub-bonding layer includes a fourth bonding contact, and the third bonding contact is in contact with the fourth bonding contact.

[0009] In one embodiment of this application, the first semiconductor structure includes a first sub-bonding layer and a third sub-bonding layer, the first sub-bonding layer and the third sub-bonding layer being located on opposite sides of the peripheral circuit along the first direction.

[0010] In one embodiment of this application, the first semiconductor structure further includes a substrate, and the peripheral circuit includes a first peripheral circuit and a second peripheral circuit, the first peripheral circuit and the second peripheral circuit being located on opposite sides of the substrate along the first direction.

[0011] In one embodiment of this application, both the first memory array and the second memory array include memory cells arranged in an array, and the memory cells include a vertical transistor extending along the first direction and a memory portion coupled to the vertical transistor.

[0012] In one embodiment of this application, the second semiconductor structure further includes a pad-out interconnect layer; along the first direction, the memory portion in the first memory array is located between the pad-out interconnect layer and the vertical transistor in the first memory array.

[0013] In one embodiment of this application, the three-dimensional memory further includes a first bonding layer, through which the first semiconductor structure and the second semiconductor structure are coupled; along the first direction, the vertical transistor in the first memory array is located between the first bonding layer and the memory portion in the first memory array.

[0014] In one embodiment of this application, the three-dimensional memory further includes a second bonding layer, through which the first semiconductor structure and the third semiconductor structure are coupled; along the first direction, the vertical transistor in the second memory array is located between the second bonding layer and the memory portion in the second memory array.

[0015] In one embodiment of this application, the vertical transistor includes: a semiconductor body extending along the first direction, a gate structure located on at least one side of the semiconductor body, and a first active terminal and a second active terminal respectively disposed at two ends of the semiconductor body along the first direction.

[0016] In one embodiment of this application, the second semiconductor structure and the third semiconductor structure further include multiple word lines and multiple bit lines, respectively; the gate structure is coupled to the word lines, one of the first active terminal and the second active terminal is coupled to the bit lines, and the other of the first active terminal and the second active terminal is coupled to the memory cell.

[0017] In a second aspect, a memory system is provided, the memory system including a three-dimensional memory and a controller provided in the first direction of this application, the controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0018] Thirdly, a method for fabricating a three-dimensional memory is provided, the method comprising: forming a first semiconductor structure including peripheral circuitry; providing a second semiconductor structure including a first memory array and a third semiconductor structure including the second memory array; coupling the second semiconductor structure to the first semiconductor structure; and coupling the third semiconductor structure to the first semiconductor structure, wherein the second semiconductor structure and the third semiconductor structure are located on opposite sides of the first semiconductor structure along a first direction.

[0019] In one embodiment of this application, forming the first semiconductor structure includes: forming a first peripheral circuit on one side of a substrate; and forming a second peripheral circuit on the other side of the substrate.

[0020] In one embodiment of this application, a carrier wafer is provided and supported on the other side of the substrate before the first peripheral circuit is formed on one side of the substrate.

[0021] In one embodiment of this application, before forming the second peripheral circuit on the other side of the substrate, the carrier wafer is supported on the side of the substrate where the first peripheral circuit is formed; after forming the first peripheral circuit and the second peripheral circuit, the step of coupling the second semiconductor structure to the first semiconductor structure is performed.

[0022] In one embodiment of this application, the step of coupling the second semiconductor structure with the first semiconductor structure is performed before forming the second peripheral circuit on the other side of the substrate.

[0023] In one embodiment of this application, after a first peripheral circuit is formed on one side of the substrate, a first sub-bonding layer including a first bonding contact is formed.

[0024] In one embodiment of this application, after a second peripheral circuit is formed on the other side of the substrate, a third sub-bonding layer including a second bonding contact is formed.

[0025] According to at least one embodiment of the present application, the three-dimensional memory and its fabrication method, as well as the memory system, include a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure. The second and third semiconductor structures are located on opposite sides of the first semiconductor structure along a first direction. The second semiconductor structure is coupled to the first semiconductor structure so that a first memory array in the second semiconductor structure is coupled to a peripheral circuit in the first semiconductor structure. The third semiconductor structure is coupled to the first semiconductor structure so that a second memory array in the third semiconductor structure is coupled to a peripheral circuit in the first semiconductor structure. Compared with related technologies that couple a semiconductor structure including a memory array to a semiconductor structure including peripheral circuits to form a stacked structure, the three-dimensional memory in the embodiments of the present application can accommodate more memory cells within the same planar dimensions, thereby further improving the storage density of the three-dimensional memory. Attached Figure Description

[0026] Figure 1 A schematic cross-sectional view of a three-dimensional memory provided in an embodiment of this application;

[0027] Figure 2 A schematic diagram of a memory including an array of peripheral circuits and storage cells provided in an embodiment of this application;

[0028] Figure 3 A cross-sectional view of a three-dimensional memory provided in an embodiment of this application;

[0029] Figure 4 A schematic diagram of a memory including an array of peripheral circuits and storage cells, provided for another embodiment of this application;

[0030] Figure 5 A cross-sectional view of a three-dimensional memory provided in another embodiment of this application;

[0031] Figure 6 A block diagram of an exemplary system with a three-dimensional memory provided in an embodiment of this application;

[0032] Figure 7 A flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of this application;

[0033] Figure 8 A flowchart illustrating step S1 of a method for fabricating a three-dimensional memory according to an embodiment of this application;

[0034] Figure 9 A cross-sectional view of a first semiconductor structure provided in an embodiment of this application;

[0035] Figure 10 A cross-sectional view of a second semiconductor structure provided in an embodiment of this application;

[0036] Figure 11 A cross-sectional view of a third semiconductor structure provided in an embodiment of this application.

[0037] Figure label:

[0038] 1. Memory system;

[0039] 10. Three-dimensional memory; 20. Controller; 30. Host;

[0040] 110. First semiconductor structure; 111. Peripheral circuit; 1111. First peripheral circuit; 1112. Second peripheral circuit; 112. First sub-bonding layer; 113. First bonding contact; 114. Third sub-bonding layer; 115. Third bonding contact; 116. First interconnect layer; 117. Third interconnect layer; 118. Substrate; 119. Transistor;

[0041] 120. Second semiconductor structure; 121. First memory array; 122. Second sub-bonding layer; 123. Second bonding contact; 124. Pad-out interconnect layer; 125. Second interconnect layer; 126. Contact;

[0042] 130. Third semiconductor structure; 131. Second memory array; 132. Fourth sub-bonding layer; 133. Fourth bonding contact; 134. Fourth interconnect layer;

[0043] 140. Memory cell; 141. Vertical transistor; 142. Semiconductor body; 143. Gate structure; 144. First active terminal; 145. Second active terminal; 146. Gate dielectric layer; 148. Memory section;

[0044] 150. First bonding layer;

[0045] 160. Second bonding layer;

[0046] 170. Character line;

[0047] 180, bit line. Detailed Implementation

[0048] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this application. It will be apparent to those skilled in the art that the content of this application can also be used for various other applications.

[0049] It should be noted that the use of terms such as "an embodiment," "embodiment," "example embodiment," and "some embodiments" in the specification indicates that the described embodiments may include specific features, structures, or characteristics, but each embodiment does not necessarily include those specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0050] Generally, terms can be understood, at least in part, based on their use in context. For example, the term "one or more," as used herein, can be used, at least in part, depending on the context, to describe any feature, structure, or property in the singular or to describe a combination of features, structures, or properties in the plural. Similarly, terms such as "a," "an," or "described" can also be understood to convey, at least in part, singular or plural usage depending on the context.

[0051] It is understood that the meanings of “above,” “on top,” and “above” in this application should be interpreted in the broadest way possible, such that “above” means not only directly on something, but also includes the meaning of being on something with intermediate features or layers in between, and that “on top” or “above” means not only “above” or “above” something, but also includes the meaning of being “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0052] Furthermore, for ease of description, this document may use spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or feature and another element or feature as shown in the figure. Spatially related terms are intended to include different orientations of the device in use or operation (other than those shown in the figure). The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0053] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0054] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or upper layer of a structure, or may have a range smaller than that of the underlying or upper layer. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers therein, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0055] This application provides a three-dimensional memory 10 through some embodiments. Figure 1 A schematic cross-sectional view of a three-dimensional memory provided in an embodiment of this application; Figure 2 A schematic diagram of a memory including an array of peripheral circuits and storage cells provided in an embodiment of this application; Figure 3 A cross-sectional view of a three-dimensional memory provided in an embodiment of this application.

[0056] like Figures 1 to 3 As shown, the three-dimensional memory 10 includes a first semiconductor structure 110, a second semiconductor structure 120, and a third semiconductor structure 130. The first semiconductor structure 110 includes peripheral circuitry 111. The second semiconductor structure 120 is located on one side of the first semiconductor structure 110 along a first direction and includes a first memory array 121. The second semiconductor structure 120 is coupled to the first semiconductor structure 110. Along the first direction, the third semiconductor structure 130 is located on the side of the first semiconductor structure 110 away from the second semiconductor structure 120. The third semiconductor structure 130 includes a second memory array 131 and is coupled to the first semiconductor structure 110. The first direction is parallel to the Z-direction in the figure.

[0057] Specifically, peripheral circuitry 111 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the first memory array 121 and the second memory array 131. For example, peripheral circuitry 111 may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0058] The first semiconductor structure 110 is formed based on a first wafer, the second semiconductor structure 120 is formed based on a second wafer, and the third semiconductor structure 130 is formed based on a third wafer. That is, the peripheral circuit 111, the first memory array 121, and the second memory array 131 are formed on three different wafers. After fabricating the first semiconductor structure 110 including the peripheral circuit 111, the second semiconductor structure 120 including the first memory array 121, and the third semiconductor structure 130 including the second memory array 131 based on the three different wafers, the first semiconductor structure 110, the second semiconductor structure 120, and the third semiconductor structure 130 are coupled together to form a stacked structure.

[0059] According to an embodiment of this application, the three-dimensional memory 10 includes a first semiconductor structure 110, a second semiconductor structure 120, and a third semiconductor structure 130. The second semiconductor structure 120 and the third semiconductor structure 130 are located on opposite sides of the first semiconductor structure 110 along a first direction. The second semiconductor structure 120 is coupled to the first semiconductor structure 110 so that the first memory array 121 in the second semiconductor structure 120 is coupled to the peripheral circuit 111 in the first semiconductor structure 110. The third semiconductor structure 130 is coupled to the first semiconductor structure 110 so that the second memory array 131 in the third semiconductor structure 130 is coupled to the peripheral circuit 111 in the first semiconductor structure 110. Compared with the related art scheme of coupling a semiconductor structure including a memory array with a semiconductor structure including peripheral circuit 111 to form a stacked structure, the three-dimensional memory 10 in this embodiment can accommodate more memory cells 140 within the same planar size, thereby further improving the storage density of the three-dimensional memory 10.

[0060] like Figure 1 , Figure 3As shown, in some embodiments, the first semiconductor structure 110 and the second semiconductor structure 120 are coupled through a first bonding layer 150, and the first semiconductor structure 110 and the third semiconductor structure 130 are coupled through a second bonding layer 160. Since the first semiconductor structure 110, the second semiconductor structure 120, and the third semiconductor structure 130 are fabricated based on three different wafers, the first semiconductor structure 110 and the second semiconductor structure 120 can be connected together by bonding (e.g., hybrid bonding) after the first semiconductor structure 110, the second semiconductor structure 120, and the third semiconductor structure 130 are respectively fabricated, and the first semiconductor structure 110 and the third semiconductor structure 130 can be connected together by bonding. After bonding is completed, data between the first memory array 121 in the second semiconductor structure 120 and the peripheral circuit 111 in the first semiconductor structure 110 can be executed through interconnection via the first bonding layer 150. Similarly, data between the second memory array 131 in the third semiconductor structure 130 and the peripheral circuit 111 in the first semiconductor structure 110 can be executed through interconnection via the second bonding layer 160.

[0061] Hybrid bonding (also known as metal / dielectric hybrid bonding) is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer) that can simultaneously achieve the effects of metal-to-metal (e.g., copper-to-copper) bonding and dielectric-to-dielectric (e.g., silicon oxide-to-silicon oxide) bonding.

[0062] like Figure 3 As shown, in some embodiments, the first bonding layer 150 includes a first sub-bonding layer 112 and a second sub-bonding layer 122. The first sub-bonding layer 112 includes a first bonding contact 113, and the second sub-bonding layer 122 includes a second bonding contact 123. The first bonding contact 113 contacts the second bonding contact 123. The first sub-bonding layer 112 is formed on a first semiconductor structure 110, and the second sub-bonding layer 122 is formed on a second semiconductor structure 120. When the first semiconductor structure 110 and the second semiconductor structure 120 are bonded, each first bonding contact 113 in the first sub-bonding layer 112 contacts each second bonding contact 123 in the second sub-bonding layer 122, thereby establishing an electrical connection.

[0063] like Figure 3As shown, in some embodiments, the second bonding layer 160 includes a third sub-bonding layer 114 and a fourth sub-bonding layer 132. The third sub-bonding layer 114 includes a third bonding contact 115, and the fourth sub-bonding layer 132 includes a fourth bonding contact 133. The third bonding contact 115 and the fourth bonding contact 133 are in contact. The third sub-bonding layer 114 is formed on the first semiconductor structure 110, and the fourth sub-bonding layer 132 is formed on the third semiconductor structure 130. When the first semiconductor structure 110 and the third semiconductor structure 130 are bonded, each third bonding contact 115 in the third sub-bonding layer 114 makes corresponding contact with each fourth bonding contact 133 in the fourth sub-bonding layer 132, thereby establishing an electrical connection.

[0064] It is understood that each bonding contact may include a conductive material, such as copper. The remaining areas of each sub-bonding layer, excluding the bonding contacts, may be formed of a dielectric material (such as silicon oxide). The bonding contacts and surrounding dielectric in each sub-bonding layer may be used for hybrid bonding.

[0065] like Figure 3 As shown, in one embodiment, the first semiconductor structure 110 includes a first sub-bonding layer 112 and a third sub-bonding layer 114, which are located on opposite sides of the peripheral circuit 111 along a first direction. This arrangement facilitates the bonding of the first semiconductor structure 110 to the second semiconductor structure 120 and the third semiconductor structure 130 via the first sub-bonding layer 112 and the third sub-bonding layer 114, respectively.

[0066] like Figure 3 As shown, in some embodiments, the first semiconductor structure 110 further includes a substrate 118, and the peripheral circuit 111 includes a first peripheral circuit 1111 and a second peripheral circuit 1112, which are located on opposite sides of the substrate 118 along a first direction.

[0067] The substrate 118 may include silicon (e.g., single-crystal silicon, c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. The substrate 118 can provide a fabrication basis for the formation of the first peripheral circuit 1111 and the second peripheral circuit 1112, wherein both the first peripheral circuit 1111 and the second peripheral circuit 1112 may include multiple transistors (e.g., planar transistors or 3D transistors), and a portion of the structure of the transistors may be formed on or in the substrate 118.

[0068] The first peripheral circuit 1111 and the second peripheral circuit 1112 are located on opposite sides of the substrate 118 along the first direction. That is, the first peripheral circuit 1111 and the second peripheral circuit 1112 can be formed from a single wafer through a two-sided processing method. Specifically, the first peripheral circuit 1111 can be formed by processing on the first side of the wafer, and the second peripheral circuit 1112 can be formed by processing on the second side of the wafer. The first peripheral circuit 1111 is located on the side of the substrate 118 closest to the second semiconductor structure 120, and the first memory array 121 in the second semiconductor structure 120 is coupled to the first peripheral circuit 1111. This shortens the coupling path between the first memory array 121 and the first peripheral circuit 1111, thereby reducing the number of interconnect structures between them. Similarly, the second peripheral circuit 1112 is located on the side of the substrate 118 close to the third semiconductor structure 130, and the second memory array 131 in the third semiconductor structure 130 is coupled to the second peripheral circuit 1112. This helps to shorten the coupling path between the second memory array 131 and the second peripheral circuit 1112, thereby helping to reduce the number of interconnect structures between the second memory array 131 and the second peripheral circuit 1112.

[0069] like Figure 3 As shown, in some embodiments, the first semiconductor structure 110 further includes a first interconnect layer 116. Along a first direction, the first interconnect layer 116 is located between the first peripheral circuit 1111 and the first sub-bonding layer 112. The first interconnect layer 116 is used to transmit electrical signals to and from the first peripheral circuit 1111. The second semiconductor structure 120 further includes a second interconnect layer 125. Along a first direction, the second interconnect layer 125 is located between the first memory array 121 and the second sub-bonding layer 122. The second interconnect layer 125 is used to transmit electrical signals to and from the first memory array 121.

[0070] The first interconnect layer 116 and the second interconnect layer 125 may each include multiple interconnects (also referred to as "contacts"), including lateral interconnects and vertical interconnect access (VIA) contacts. The first interconnect layer 116 and the second interconnect layer 125 may also each include one or more interlayer dielectric layers, in which interconnects and via contacts can be formed. The first memory array 121 is coupled to the first peripheral circuit 1111 in sequence through the interconnects in the second interconnect layer 125, the second bonding contact 123 in the second sub-bonding layer 122, the first bonding contact 113 in the first sub-bonding layer 112, and the interconnects in the first interconnect layer 116.

[0071] like Figure 3As shown, in some embodiments, the first semiconductor structure 110 further includes a third interconnect layer 117. Along the first direction, the third interconnect layer 117 is located between the second peripheral circuit 1112 and the third sub-bonding layer 114. The third interconnect layer 117 is used to transmit electrical signals to and from the second peripheral circuit 1112. The third semiconductor structure 130 further includes a fourth interconnect layer 134. Along the first direction, the fourth interconnect layer 134 is located between the second memory array 131 and the fourth sub-bonding layer 132. The fourth interconnect layer 134 is used to transmit electrical signals to and from the second memory array 131.

[0072] Both the third interconnect layer 117 and the fourth interconnect layer 134 may include multiple interconnects (also referred to as "contacts"), including lateral interconnects and vertical interconnect access (VIA) contacts. Both the third interconnect layer 117 and the fourth interconnect layer 134 may also include one or more interlayer dielectric layers, where interconnects and via contacts can be formed. The second memory array 131 is coupled to the second peripheral circuit 1112 sequentially through the interconnects in the fourth interconnect layer 134, the fourth bonding contact 133 in the fourth sub-bonding layer 132, the third bonding contact 115 in the third sub-bonding layer 114, and the interconnects in the third interconnect layer 117.

[0073] Figure 4 A schematic diagram of a memory including an array of peripheral circuits and storage cells, provided for another embodiment of this application. (See diagram below.) Figure 3 , Figure 4 As shown, in some embodiments, both the first storage array 121 and the second storage array 131 include arrayed storage cells 140, and the storage cell 140 includes a vertical transistor 141 extending along a first direction and a storage section 148 coupled to the vertical transistor 141.

[0074] Vertical transistors 141 replace conventional planar transistors as switching and selection devices in the memory array. Compared to planar transistors, the two active terminals (drain and source) of vertical transistor 141 overlap in a plane perpendicular to the stacking direction of the three-dimensional memory 10, which can reduce the planar size of the transistor and simplify the complexity of interconnect wiring. In one embodiment, the first memory array 121 and the second memory array 131 can be DRAM cell arrays. A DRAM cell can be a 1T1C cell consisting of a vertical transistor 141 and a capacitor. It should be understood that DRAM cells can have any suitable configuration, such as 2T1C cells, 3T1C cells, etc.

[0075] In other embodiments, the first storage array 121 and the second storage array 131 are not limited to DRAM cell arrays, but can be any other suitable type of storage cell array 140 that can use transistors as switching and selection devices, such as PCM cell arrays, static random-access memory (SRAM) cell arrays, FRAM cell arrays, resistive memory cell arrays, magnetic memory cell arrays, etc.

[0076] like Figure 3 , Figure 4 As shown, in some embodiments, the vertical transistor 141 includes a semiconductor body 142 extending along a first direction, a gate structure 143 located on at least one side of the semiconductor body 142, and a first active terminal 144 and a second active terminal 145 respectively disposed at two ends of the semiconductor body 142 along the first direction.

[0077] The semiconductor body 142 may have a cuboid or cylindrical shape, and the gate structure 143 may be located on only one side of the semiconductor body 142 or on multiple sides of the semiconductor body 142 such that the semiconductor body 142 is at least partially surrounded by the gate structure 143. The gate structure 143 may include any suitable conductive material, such as polysilicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN)), or silicides. It is understood that the vertical transistor 141 may also include a gate dielectric layer 146 located between the gate structure 143 and the semiconductor body 142. The gate dielectric layer 146 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric.

[0078] The first active terminal 144 and the second active terminal 145 can be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). The memory unit 148 can be coupled to the first active terminal 144 or the second active terminal 145 of the vertical transistor 141, and the vertical transistor 141 controls the selection and / or state switching of the corresponding memory unit 148 coupled to the vertical transistor 141.

[0079] Figure 5 A cross-sectional view of a three-dimensional memory provided in another embodiment of this application. (See attached image.) Figure 5As shown, in some embodiments, the second semiconductor structure 120 further includes a pad-out interconnect layer 124. The pad-out interconnect layer 124 may include one or more interconnects in an interlayer dielectric layer, such as contact pads. For the purpose of pad outlining, the interconnects in the pad-out interconnect layer 124 can transmit electrical signals between the three-dimensional memory 10 and external circuitry. In some embodiments, along a first direction, the pad-out interconnect layer 124 is located on the side of the first memory array 121 opposite to the first semiconductor structure 110. This allows the connection process between the pad-out interconnect layer 124 and external circuitry to be less hindered or interfered with by the first semiconductor structure 110 and the third semiconductor structure 130, thereby improving connection efficiency.

[0080] In some embodiments, the storage portion 148 in the first storage array 121 is located between the pad-lead interconnect layer 124 and the vertical transistor 141 in the first storage array 121. With this configuration, during the formation of the second semiconductor structure 120, the vertical transistor 141 in the first storage array 121, the storage portion 18 in the first storage array 121, and finally the pad-lead interconnect layer 124 can be formed sequentially. This process optimizes the manufacturing process and thus improves the fabrication efficiency of the second semiconductor structure 120.

[0081] like Figure 5 As shown, in some embodiments, the second semiconductor structure 120 further includes one or more contacts 126 extending through portions of the pad-out interconnect layer 124 to couple the pad-out interconnect layer 124 to the first memory array 121 and the second interconnect layer 125. This allows the first peripheral circuitry 1111 and the second peripheral circuitry 1112 to be coupled to external circuitry via the first interconnect layer 116, the first sub-bonding layer 112, the second sub-bonding layer 122, the second interconnect layer 125, and the pad-out interconnect layer 124.

[0082] like Figure 3 or Figure 5As shown, in one embodiment, the three-dimensional memory 10 further includes a first bonding layer 150, through which the first semiconductor structure 110 and the second semiconductor structure 120 are coupled. Along the first direction, a vertical transistor 141 in the first memory array 121 is located between the first bonding layer 150 and the memory section 148 in the first memory array 121. It is understood that compared to the connection structure between the memory section 148 and the first peripheral circuit 1111 in the first memory array 121, the interconnection structure between the vertical transistor 141 and the first peripheral circuit 1111 in the first memory array 121 is more complex. Therefore, placing the vertical transistor 141 closer to the first semiconductor structure 110 can avoid the aforementioned interconnection structure from needing to cross many structures along the first direction while remaining structurally complex, thus increasing the risk of interference between structures.

[0083] like Figure 3 or Figure 5 As shown, the three-dimensional memory 10 also includes a second bonding layer 160, through which the first semiconductor structure 110 and the third semiconductor structure 130 are coupled. Along the first direction, the vertical transistor 141 in the second memory array 131 is located between the second bonding layer 160 and the memory section 148 in the second memory array 131. It is understood that compared to the connection structure between the memory section 148 and the second peripheral circuit 1112 in the second memory array 131, the interconnection structure between the vertical transistor 141 and the second peripheral circuit 1112 in the second memory array 131 is more complex. Therefore, placing the vertical transistor 141 closer to the first semiconductor structure 110 avoids the aforementioned interconnection structure from having to cross many structures along the first direction while remaining structurally complex, thus increasing the risk of interference between structures. On the other hand, the above arrangement also allows the second semiconductor structure 120 and the third semiconductor structure 130 to be arranged face-to-face on opposite sides of the first semiconductor structure 110 and bonded to the first semiconductor structure 110 respectively. This helps to reduce the complexity of the layout of the three-dimensional memory 10, thereby reducing the design difficulty.

[0084] like Figure 3 , Figure 4 As shown, in one embodiment, the second semiconductor structure 120 and the third semiconductor structure 130 further include multiple word lines 170 and multiple bit lines 180, respectively. The gate structure 143 is coupled to the word line 170, one of the first active terminal 144 and the second active terminal 145 is coupled to the bit line 180, and the other of the first active terminal 144 and the second active terminal 145 is coupled to the memory cell 140.

[0085] The word lines 170 can extend along the row direction of the array, and multiple word lines 170 can be arranged at intervals along the column direction of the array. The word lines 170 are coupled to the gate structures 143 of each vertical transistor 141 located in the same row. The word lines 170 are used to control the switching of the vertical transistors 141 located in the row.

[0086] Bit lines 180 can extend along the column direction of the array, and multiple bit lines 180 can be arranged at intervals along the row direction of the array. Bit lines 180 are coupled to one of the active terminals of vertical transistors 141 located in the same column. Bit lines 180 are used to send data to and / or receive data from memory units 148 located in the column.

[0087] In some embodiments, the gate structure 143 and the word line 170 can be continuous conductive structures, that is, the gate structure 143 and the word line 170 are integral structures and are formed by the same process. In other words, the gate structure 143 can be regarded as part of the word line 170, or the word line 170 can be regarded as an extension of the gate structure 143 to be coupled to the peripheral circuit 111.

[0088] Figure 6 This is a block diagram of an exemplary system with a three-dimensional memory provided in an embodiment of this application. Figure 6 As shown, another embodiment of this application provides a memory system 1, which includes a three-dimensional memory 10 and a controller 20. The controller 20 is coupled to the three-dimensional memory 10 and configured to control the three-dimensional memory 10. The three-dimensional memory 10 is the same as that described in any of the embodiments above, and will not be repeated here.

[0089] In some embodiments, the memory system 1 further includes a host 30, which is coupled to the controller 20 and configured to send data to or receive data from the three-dimensional memory 10.

[0090] The controller 20 can control the three-dimensional memory 10 via channel CH, and the three-dimensional memory 10 can perform operations based on the control of the controller 20 in response to requests from the host 30. The three-dimensional memory 10 can receive commands CMD and addresses ADDR from the controller 20 via channel CH and access the region selected from the memory cell array in response to the address. In other words, the three-dimensional memory 10 can perform internal operations corresponding to commands on the region selected by the address. In some embodiments, the three-dimensional storage system can be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc. The memory system 1 provided in this application has the same beneficial effects as the three-dimensional memory 10 provided in this application, and will not be described in detail here.

[0091] Another aspect of this application provides a method for fabricating a three-dimensional memory 10. Figure 7 This is a schematic flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of this application, as shown below. Figure 7 As shown, the manufacturing method includes the following steps:

[0092] S1, forming a first semiconductor structure 110 including peripheral circuitry 111;

[0093] S2, a second semiconductor structure 120 including a first memory array 121 and a third semiconductor structure 130 including a second memory array 131 are provided;

[0094] S3, to couple the second semiconductor structure 120 to the first semiconductor structure 110;

[0095] S4, the third semiconductor structure 130 is coupled to the first semiconductor structure 110, wherein the second semiconductor structure 120 and the third semiconductor structure 130 are located on opposite sides of the first semiconductor structure 110 along the first direction.

[0096] The specific processes for each step in the above manufacturing method will be explained in detail below.

[0097] Figure 8 This is a flowchart illustrating step S1 of a method for fabricating a three-dimensional memory according to an embodiment of this application. Figure 8 As shown, step S1, forming a first semiconductor structure 110 including peripheral circuitry 111, may include:

[0098] S11, a first peripheral circuit 1111 is formed on one side of the substrate 118;

[0099] S12, a second peripheral circuit 1112 is formed on the other side of the substrate 118.

[0100] Please refer to the first semiconductor structure 110 after formation. Figure 9 Specifically, in one embodiment of this application, the material used to fabricate the substrate 118 may be silicon (e.g., single-crystal silicon, c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. Alternatively, the substrate 118 may be single-crystal silicon.

[0101] After forming the substrate 118, a plurality of transistors 119 can be formed on one side of the substrate 118. The transistors 119 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing, and any other suitable process. In some embodiments, doped regions are formed in the substrate 118 by ion implantation and / or thermal diffusion, and the doped regions serve, for example, as the source and drain of the transistors 119. In some embodiments, isolation regions (e.g., STI) are also formed in the substrate 118 by wet / dry etching and thin film deposition. The transistors 119 can form a first peripheral circuit 1111 on the substrate 118.

[0102] After forming the first peripheral circuit 1111 on one side of the substrate 118, the second peripheral circuit 1112 can be formed on the other side of the substrate 118 using the same process, which will not be described in detail here.

[0103] In some embodiments, a carrier wafer may be provided before the first peripheral circuit 1111 is formed on one side of the substrate 118, and the carrier wafer may be supported on the other side of the substrate 118. During the formation of the first peripheral circuit 1111 on one side of the substrate 118, the carrier wafer may provide support to the substrate 118 to disperse the stress on the substrate 118 during the processing, thereby preventing damage or breakage of the substrate 118.

[0104] In some embodiments, after forming a first peripheral circuit 1111 on one side of the substrate 118, a first sub-bonding layer 112 including a first bonding contact 113 is formed. This facilitates bonding the first sub-bonding layer 112 to the second semiconductor structure 120 in a subsequent step S3.

[0105] Specifically, the first sub-bonding layer 112 may include a plurality of first bonding contacts 113 surrounded by a dielectric. A dielectric layer (e.g., an ILD layer) may be deposited over the first peripheral circuit 1111 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Then, contact holes through the dielectric layer are first patterned using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer) to form the first bonding contacts 113 that penetrate the dielectric layer and are directly or indirectly coupled to the first peripheral circuit 1111. The contact holes may be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer prior to depositing the conductor.

[0106] In some embodiments, after forming a second peripheral circuit 1112 on the other side of the substrate 118, a third sub-bonding layer 114 including a second bonding contact 123 is formed. This facilitates bonding the third sub-bonding layer 114 to the third semiconductor structure 130 in a subsequent step S4.

[0107] Specifically, the third sub-bonding layer 114 may include a plurality of third bonding contacts 115 surrounded by a dielectric. A dielectric layer (e.g., an ILD layer) may be deposited over the second peripheral circuit 1112 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Then, contact holes through the dielectric layer are first patterned using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer) to form the third bonding contacts 115 that penetrate the dielectric layer and are directly or indirectly coupled to the second peripheral circuit 1112. The contact holes may be filled with a conductor (e.g., copper). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer prior to depositing the conductor.

[0108] Step S2 provides a second semiconductor structure 120 including a first memory array 121 and a third semiconductor structure 130 including a second memory array 131, which may include:

[0109] The process involves using a second semiconductor structure 120, which includes a first memory array 121, and a third semiconductor structure 130, which includes a second memory array 131, that has already been fabricated. It should be noted that the semiconductor structure including the memory array can be fabricated using mature methods in the prior art. In other words, the second semiconductor structure 120 and the third semiconductor structure 130 can be fabricated using any method in the prior art, which will not be elaborated upon here. In the fabrication method described in this application, the second semiconductor structure 120 and the third semiconductor structure 130 can be directly used.

[0110] The second semiconductor structure 120 provided in step S2 is provided in [reference]. Figure 10 Please refer to the third semiconductor structure 130 provided in step S2. Figure 11 .

[0111] Step S3, which couples the second semiconductor structure 120 to the first semiconductor structure 110, may include:

[0112] By coupling the second semiconductor structure 120 to one side of the first semiconductor structure 110, the first peripheral circuit 1111 is closer to the second semiconductor structure 120 than the second peripheral circuit 1112. This allows the first memory array 121 in the second semiconductor structure 120 to be coupled to the first peripheral circuit 1111, and simplifies the arrangement of the interconnect layer between the two, thereby avoiding an overly complex interconnect layer structure.

[0113] In one embodiment, before forming the second peripheral circuit 1112 on the other side of the substrate 118, a carrier wafer is supported on the side of the substrate 118 where the first peripheral circuit 1111 is formed; and after forming the first peripheral circuit 1111 and the second peripheral circuit 1112, a step of coupling the second semiconductor structure 120 with the first semiconductor structure 110 is performed.

[0114] In other words, after forming the first peripheral circuit 1111 on one side of the substrate 118, the substrate 118 is flipped over, and a carrier wafer is supported on the side of the substrate 118 where the first peripheral circuit 1111 is formed. Then, a second peripheral circuit 1112 is formed on the other side of the substrate 118. In this way, during the formation of the second peripheral circuit 1112, the carrier wafer can provide support for the substrate 118 to disperse the stress on the substrate 118 during processing, thereby preventing damage or breakage of the substrate 118. After the fabrication of the first peripheral circuit 1111 and the second peripheral circuit 1112 is completed, the second semiconductor structure 120 is coupled to the first semiconductor structure 110.

[0115] In another different embodiment, the step of coupling the second semiconductor structure 120 with the first semiconductor structure 110 is performed before the second peripheral circuit 1112 is formed on the other side of the substrate 118.

[0116] In other words, after forming the first peripheral circuit 1111 on one side of the substrate 118, the second semiconductor structure 120 can be coupled to the first semiconductor structure 110. Then, the second peripheral circuit 1112 is formed on the other side of the substrate 118. Thus, during the formation of the second peripheral circuit 1112, the second semiconductor structure 120 can provide support for the substrate 118 to disperse the stress on the substrate 118 during processing, thereby preventing damage or breakage of the substrate 118. Since the second semiconductor structure 120 replaces the function of the carrier wafer, the number of times the carrier wafer is used can be reduced, which helps to simplify the manufacturing process and improve manufacturing efficiency.

[0117] Step S4, which couples the third semiconductor structure 130 to the first semiconductor structure 110, may include:

[0118] The third semiconductor structure 130 is coupled to the other side of the first semiconductor structure 110, such that the second semiconductor structure 120 and the third semiconductor structure 130 are respectively disposed on opposite sides of the first semiconductor structure 110 along the first direction. After coupling, the second peripheral circuit 1112 is closer to the third semiconductor structure 130 than the first peripheral circuit 1111. This allows the second memory array 131 in the third semiconductor structure 130 to be coupled to the second peripheral circuit 1112, and simplifies the arrangement of the interconnect layer between the two, thereby avoiding an overly complex interconnect layer structure.

[0119] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A three-dimensional memory, characterized in that, include: A first semiconductor structure, the first semiconductor structure including peripheral circuitry; A second semiconductor structure is located on one side of the first semiconductor structure along a first direction. The second semiconductor structure includes a first memory array and is coupled to the first semiconductor structure. A third semiconductor structure, along the first direction, is located on the side of the first semiconductor structure away from the second semiconductor structure, the third semiconductor structure includes a second memory array, and the third semiconductor structure is coupled to the first semiconductor structure.

2. The three-dimensional memory according to claim 1, characterized in that, The first semiconductor structure and the second semiconductor structure are coupled through a first bonding layer; The first semiconductor structure and the third semiconductor structure are coupled through a second bonding layer.

3. The three-dimensional memory according to claim 2, characterized in that, The first bonding layer includes a first sub-bonding layer and a second sub-bonding layer; The first sub-bonding layer includes a first bonding contact, and the second sub-bonding layer includes a second bonding contact, wherein the first bonding contact is in contact with the second bonding contact.

4. The three-dimensional memory according to claim 3, characterized in that, The second bonding layer includes a third sub-bonding layer and a fourth sub-bonding layer; The third sub-bonding layer includes a third bonding contact, and the fourth sub-bonding layer includes a fourth bonding contact. The third bonding contact is in contact with the fourth bonding contact.

5. The three-dimensional memory according to claim 4, characterized in that, The first semiconductor structure includes a first sub-bonding layer and a third sub-bonding layer, which are located on opposite sides of the peripheral circuit along the first direction.

6. The three-dimensional memory according to any one of claims 1 to 5, characterized in that, The first semiconductor structure further includes a substrate, and the peripheral circuit includes a first peripheral circuit and a second peripheral circuit, which are located on opposite sides of the substrate along the first direction.

7. The three-dimensional memory according to any one of claims 1 to 5, characterized in that, Both the first memory array and the second memory array include memory cells arranged in an array, and each memory cell includes a vertical transistor extending along the first direction and a memory section coupled to the vertical transistor.

8. The three-dimensional memory according to claim 7, characterized in that, The second semiconductor structure also includes a pad-out interconnect layer; Along the first direction, the storage portion in the first storage array is located between the pad-out interconnect layer and the vertical transistor in the first storage array.

9. The three-dimensional memory according to claim 7, characterized in that, It also includes a first bonding layer, through which the first semiconductor structure and the second semiconductor structure are coupled; Along the first direction, the vertical transistor in the first memory array is located between the first bonding layer and the memory section in the first memory array.

10. The three-dimensional memory according to claim 9, characterized in that, It also includes a second bonding layer, through which the first semiconductor structure and the third semiconductor structure are coupled; Along the first direction, the vertical transistor in the second memory array is located between the second bonding layer and the memory section in the second memory array.

11. The three-dimensional memory according to claim 7, characterized in that, The vertical transistor includes: A semiconductor body extending along the first direction; A gate structure located on at least one side of the semiconductor body; A first active terminal and a second active terminal are respectively disposed at two ends of the semiconductor body along the first direction.

12. The three-dimensional memory according to claim 11, characterized in that, The second semiconductor structure and the third semiconductor structure further include multiple word lines and multiple bit lines, respectively; The gate structure is coupled to the word line, one of the first active terminal and the second active terminal is coupled to the bit line, and the other of the first active terminal and the second active terminal is coupled to the memory cell.

13. A memory system, characterized in that, include: At least one three-dimensional memory according to any one of claims 1 to 12; as well as A controller coupled to the three-dimensional memory, the controller being configured to control the three-dimensional memory.

14. A method for fabricating a three-dimensional memory, characterized in that, include: Forming a first semiconductor structure including peripheral circuitry; A second semiconductor structure including a first memory array and a third semiconductor structure including the second memory array are provided; Couple the second semiconductor structure to the first semiconductor structure; The third semiconductor structure is coupled to the first semiconductor structure, wherein the second semiconductor structure and the third semiconductor structure are located on opposite sides of the first semiconductor structure along a first direction.

15. The method for manufacturing a three-dimensional memory according to claim 14, characterized in that, Forming the first semiconductor structure includes: A first peripheral circuit is formed on one side of the substrate; A second peripheral circuit is formed on the other side of the substrate.

16. The method for manufacturing a three-dimensional memory according to claim 15, characterized in that, Before forming the first peripheral circuit on one side of the substrate, a carrier wafer is provided and the carrier wafer is supported on the other side of the substrate.

17. The method for fabricating a three-dimensional memory according to claim 16, wherein the carrier wafer is supported on the side of the substrate where the first peripheral circuit is formed before forming the second peripheral circuit on the other side of the substrate; After forming the first peripheral circuit and the second peripheral circuit, the step of coupling the second semiconductor structure to the first semiconductor structure is performed.

18. The method for fabricating a three-dimensional memory according to claim 16, wherein before forming a second peripheral circuit on the other side of the substrate, the step of coupling the second semiconductor structure with the first semiconductor structure is performed.

19. The method for manufacturing a three-dimensional memory according to claim 15, characterized in that, After forming a first peripheral circuit on one side of the substrate, a first sub-bonding layer including a first bonding contact is formed.

20. The method for fabricating a three-dimensional memory according to claim 15, wherein after forming a second peripheral circuit on the other side of the substrate, a third sub-bonding layer including a second bonding contact is formed.

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