Semiconductor device and method of manufacturing the same

Abstract

This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor body, an insulating layer, and a contact portion penetrating the insulating layer. Along a first direction, the semiconductor body is located on one side of the insulating layer. The insulating layer includes a first insulating layer and a second insulating layer, with the first insulating layer located between the second insulating layer and the semiconductor body. Along the first direction, the contact portion has a first end and a second end, with the first end of the contact portion contacting the semiconductor body. Along a second direction, the width of the second end of the contact portion is less than or equal to the width of the first end of the contact portion. The first and second directions intersect. The semiconductor device provided by this disclosure can increase the contact area between the first end of the contact portion and the semiconductor body, while simultaneously reducing the risk of leakage current and improving the reliability of the semiconductor device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In semiconductor devices, the contacts connect capacitors and transistors. When making the contacts, the insulating layer above the transistor needs to be etched first. In order to ensure that the contact area between the contact and the transistor is as large as possible, a large aperture needs to be formed at the bottom of the insulating layer. However, during the etching process, the aperture formed at the top of the insulating layer will be even larger, resulting in a greater risk of leakage between two adjacent contacts. Summary of the Invention

[0003] The purpose of this disclosure is to provide a semiconductor device and a method for manufacturing the same, so as to reduce the risk of leakage between the contacts of two adjacent memory nodes and improve the reliability of the semiconductor device.

[0004] To achieve the above objectives, this disclosure provides a semiconductor device, including a semiconductor body, an insulating layer, and a contact portion penetrating the insulating layer; along a first direction, the semiconductor body is located on one side of the insulating layer; the insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer being located between the second insulating layer and the semiconductor body; along the first direction, the contact portion has a first end and a second end, the first end of the contact portion contacting the semiconductor body; along a second direction, the width of the second end of the contact portion is less than or equal to the width of the first end of the contact portion, wherein the first direction intersects the second direction.

[0005] In one embodiment of this disclosure, a stepped surface is provided between the two ends of the sidewall of the contact portion along the first direction.

[0006] In one embodiment of this disclosure, along the first direction, the contact portion includes a first sidewall and a second sidewall, the extension directions of the first sidewall and the second sidewall both intersecting the stepped surface; along the first direction, the stepped surface is located between the first sidewall and the second sidewall.

[0007] In one embodiment of this disclosure, the contact portion includes a first sub-portion and a second sub-portion, the end of the first sub-portion connected to the semiconductor body is the first end of the contact portion, and the size of the end of the first sub-portion connected to the second sub-portion is larger than the size of the end of the second sub-portion connected to the first sub-portion.

[0008] In one embodiment of this disclosure, the material of the first sub-part includes polycrystalline silicon, and the material of the second sub-part includes a conductive material.

[0009] In one embodiment of this disclosure, the material of the first insulating layer includes silicon nitride, and the material of the second insulating layer includes silicon carbon nitride or silicon boron nitride.

[0010] In one embodiment of this disclosure, the material of the first insulating layer comprises silicon nitride doped with phosphorus or arsenic, and the material of the second insulating layer comprises silicon nitride.

[0011] In one embodiment of this disclosure, along the second direction, there are multiple contact portions, and the distance between the second ends of two adjacent contact portions is greater than or equal to the distance between the first ends of the two contact portions.

[0012] In one embodiment of this disclosure, the semiconductor device further includes a capacitor and a conductive layer; along the second direction, there are multiple semiconductor bodies; along the first direction, each of the multiple semiconductor bodies has a first end and a second end opposite to each other, the first end of the semiconductor body is connected to the capacitor through the contact portion, and the second end of the semiconductor body is connected to the conductive layer.

[0013] In one embodiment of this disclosure, the semiconductor device further includes a first gate structure and a second gate structure, wherein the first gate structure and the second gate structure are respectively disposed on both sides of the semiconductor body along the second direction.

[0014] To achieve the above objectives, this disclosure also provides a method for manufacturing a semiconductor device, comprising: providing a substrate having a first side and a second side disposed opposite to each other along a first direction; forming a semiconductor body, wherein, along the first direction, the semiconductor body includes a first end and a second end opposite to each other; forming an insulating layer on the first side of the substrate, wherein the insulating layer includes a first insulating layer and a second insulating layer, the second insulating layer being located on the side of the first insulating layer away from the substrate; forming a through-hole through the insulating layer to expose the first end of the semiconductor body; wherein, along a second direction, the size of the through-hole on the surface of the insulating layer away from the semiconductor body is less than or equal to the size of the through-hole on the surface of the insulating layer near the semiconductor body, the second direction intersecting the first direction; and forming a contact portion within the through-hole.

[0015] In one embodiment of this disclosure, forming an insulating layer on a first side of the substrate includes: depositing a first insulating material on the first side of the substrate to form the first insulating layer; and depositing a second insulating material on a side of the first insulating layer away from the substrate to form the second insulating layer; wherein the first insulating material comprises silicon nitride, and the second insulating material comprises silicon carbon nitride or silicon boron nitride.

[0016] In one embodiment of this disclosure, forming an insulating layer on a first side of the substrate includes: depositing a silicon nitride layer on the first side of the substrate; performing ion implantation on a target location of the silicon nitride layer using an ion implantation process to form a second insulating layer, wherein the first insulating layer is an unimplanted silicon nitride layer; wherein the implanted ions are configured such that the etching rate of the second insulating layer is less than the etching rate of the first insulating layer.

[0017] In one embodiment of this disclosure, the implanted ions include carbon ions or boron ions.

[0018] In one embodiment of this disclosure, forming an insulating layer on a first side of the substrate includes: depositing a silicon nitride layer on the first side of the substrate; performing ion implantation on a target location of the silicon nitride layer using an ion implantation process to form a first insulating layer', wherein the second insulating layer' is a silicon nitride layer without ion implantation; wherein the implanted ions are configured such that the etching rate of the first insulating layer is greater than the etching rate of the second insulating layer.

[0019] In one embodiment of this disclosure, the implanted ions include phosphorus ions or arsenic ions.

[0020] The main beneficial effects of this disclosure are:

[0021] The semiconductor device provided in this disclosure has a width of the second end of the contact portion that is less than or equal to the width of the first end of the contact portion. This allows the width of the first end of the contact portion to be increased without significantly increasing the width of the second end of the contact portion. This increases the contact area between the first end of the contact portion and the semiconductor body, while reducing the risk of leakage and improving the reliability of the semiconductor device.

[0022] The semiconductor device manufacturing method disclosed herein includes an insulating layer comprising a first insulating layer and a second insulating layer. During the etching process, the etching rates of the first insulating layer and the second insulating layer can be controlled respectively to ensure that the width of the second end of the contact portion is less than or equal to the width of the first end of the contact portion. This allows for an increase in the width of the first end of the contact portion without significantly increasing the width of the second end of the contact portion, thereby increasing the contact area between the first end of the contact portion and the semiconductor body. Simultaneously, it reduces the risk of leakage current and improves the reliability of the semiconductor device. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;

[0025] Figure 2 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure (capacitors not shown);

[0026] Figure 3 for Figure 2 A magnified view of a section at point A in the middle;

[0027] Figure 4 Another schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure;

[0028] Figure 5 Another schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure (capacitor not shown);

[0029] Figure 6 This is a schematic diagram of a third structure of a semiconductor device provided in an embodiment of this disclosure;

[0030] Figure 7 A schematic diagram of a third structure of a semiconductor device provided in an embodiment of this disclosure (capacitor not shown);

[0031] Figure 8 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0032] Figures 9 to 23 This is a partial structural schematic diagram of a semiconductor structure formed after performing certain steps in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0033] The technical solutions of this disclosure will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0034] Generally, terms can be understood, at least in part, based on their use in context. For example, the term "one or more," depending at least in part on the context, can be used to describe any feature, structure, or characteristic in the singular or in the plural form to describe a combination of features, structures, or characteristics. Similarly, terms such as "a" or "described" in this document can also be understood, at least in part on the context, to convey either a singular or plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, again, depending at least in part on the context.

[0035] It should be readily understood that, in the description of this disclosure, it is necessary to clarify that the meanings of “on,” “above,” and “above” should be interpreted in the broadest sense, such that “on” not only means “directly on” something, but also includes the meaning of being “on” something with an intermediate feature or layer between them. Furthermore, “above” or “above” not only means “on” or “above” something, but can also include it being “on” or “above” something without an intermediate feature or layer between them (i.e., directly on something).

[0036] Furthermore, for ease of description, this document uses spatially relative terms such as "below," "below," "lower layer," "above," "upper layer," etc., to describe the relationship between one element or feature and another element or feature as shown in the figure. Spatially related terms are intended to include different orientations of the device in use or process steps (in addition to the orientation shown in the figure). The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted accordingly.

[0037] In the description of this disclosure, the term "substrate" refers to a material on which subsequent material layers are added. A substrate includes a front side and a back side. The front side of the substrate is typically where a semiconductor device is formed; unless otherwise stated, the semiconductor device is formed on the front side of the substrate, and the back side is opposite to the front side. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0038] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend integrally over the structure of a bottom or upper layer, or may have a range smaller than that of the bottom or upper layer. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers therein, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnects, and / or vertical interconnect pathways are formed) and one or more dielectric layers.

[0039] In this disclosure, the terms “horizontal / horizontally / laterally” mean nominally parallel to the lateral surface of the substrate, and the terms “vertical” or “perpendicularly” mean nominally perpendicular to the lateral surface of the substrate.

[0040] See Figures 1 to 7 As shown, this embodiment provides a semiconductor device, including a semiconductor body 10, an insulating layer 20, and a contact portion 30 penetrating the insulating layer 20; along a first direction, the semiconductor body 10 is located on one side of the insulating layer 20; the insulating layer 20 includes a first insulating layer 21 and a second insulating layer 22, the first insulating layer 21 being located between the second insulating layer 22 and the semiconductor body 10; along the first direction, the contact portion 30 has a first end and a second end, the first end of the contact portion 30 contacting the semiconductor body 10, and along a second direction, the width of the second end of the contact portion 30 being less than or equal to the width of the first end of the contact portion 30, wherein the first direction intersects the second direction.

[0041] by Figure 1 For example, in this embodiment, the first direction is represented by arrow direction D1, and the second direction is represented by arrow direction D2. For instance, the first direction is perpendicular to the second direction.

[0042] The semiconductor device provided in this embodiment has a width of the second end of the contact portion 30 that is less than or equal to the width of the first end of the contact portion 30. This allows the width of the first end of the contact portion 30 to be increased without significantly increasing the width of the second end of the contact portion 30. This increases the contact area between the first end of the contact portion 30 and the semiconductor body 10, while reducing the risk of leakage and improving the reliability of the semiconductor device.

[0043] It should be understood that the width of the first end of the contact portion 30 refers to the maximum width W1 of the first end of the contact portion 30 along the second direction; the width of the second end of the contact portion 30 refers to the maximum width W2 of the second end of the contact portion 30 along the second direction. Not significantly increasing the width of the second end of the contact portion 30 means that the width of the second end of the contact portion 30 does not exceed the width of the first end of the contact portion 30.

[0044] In some embodiments, see Figure 2 As shown, W2 is less than W1.

[0045] In other embodiments, see Figure 5 As shown, W2 equals W1.

[0046] In one embodiment, the cross-sectional shape of the contact portion 30 is circular. It should be understood that the circular shape of the cross-sectional shape of the contact portion 30 means that it is approximately circular within the allowable machining error range.

[0047] The cross-section of the contact portion 30 is perpendicular to the first direction. Along the first direction, the diameter of the cross-section of the contact portion 30 is different at different locations.

[0048] In this embodiment, the maximum width W1 of the first end of the contact portion 30 along the second direction refers to the diameter of the first end of the contact portion 30, and the maximum width W2 of the second end of the contact portion 30 along the second direction refers to the diameter of the second end of the contact portion 30.

[0049] In one embodiment, see Figure 1 As shown, along the first direction, the contact portion 30 includes a first structural layer 3010, a second structural layer 3020, a third structural layer 3030, and a fourth structural layer 3040. The first structural layer 3010 contacts the semiconductor body 10, and the material of the first structural layer 3010 can be polycrystalline silicon. The second structural layer 3020 contacts the first structural layer 3010, and the material of the second structural layer 3020 can be cobalt silicon. The third structural layer 3030 can serve as an adhesive layer. For example, a portion of the adhesive layer can be located between the second structural layer 3020 and the fourth structural layer 3040, and another portion of the adhesive layer can be located on the circumferential sidewall of the fourth structural layer 3040. The material of the third structural layer 3030 can be titanium nitride, and the material of the fourth structural layer 3040 can be a conductive material, such as tungsten.

[0050] In one embodiment, see Figure 3 As shown, the contact portion 30 includes a first sub-portion 30a and a second sub-portion 30b. The end of the first sub-portion 30a that is connected to the semiconductor body 10 is the first end of the contact portion 30. The size W3 of the end of the first sub-portion 30a that is connected to the second sub-portion 30b is greater than the size W4 of the end of the second sub-portion 30b that is connected to the first sub-portion 30a.

[0051] For example, the first sub-part 30a is frustum-shaped and has a smaller diameter end and a larger diameter end along the first direction. The end of the first sub-part 30a that connects to the semiconductor body 10 is the smaller diameter end of the first sub-part 30a. The end of the first sub-part 30a that connects to the second sub-part 30b is the larger diameter end of the first sub-part 30a. The second sub-part 30b is also frustum-shaped and has a smaller diameter end and a larger diameter end along the first direction. The end of the second sub-part 30b that connects to the first sub-part 30a is the larger diameter end of the second sub-part 30b, and the end of the second sub-part 30b that is away from the first sub-part is the smaller diameter end of the second sub-part. The smaller diameter end of the second sub-part 30b is the second end of the contact portion 30.

[0052] For example, the dimension W3 of the end where the first sub-part 30a connects to the second sub-part 30b refers to the diameter of the end with the larger diameter of the first sub-part 30a, and the dimension W4 of the end where the second sub-part 30b connects to the first sub-part 30a refers to the diameter of the end with the larger diameter of the second sub-part 30b.

[0053] In one embodiment, the material of the first sub-part 30a may include polycrystalline silicon, and the material of the second sub-part 30b may include a conductive material, such as tungsten.

[0054] In some embodiments, the first structural layer 3010 forms at least a portion of the first sub-part 30a, and the fourth structural layer 3040 forms at least a portion of the second sub-part 30b.

[0055] In some embodiments, the first structural layer 3010 forms a first sub-part 30a, and the second structural layer 3020, the third structural layer 3030 and the fourth structural layer 3040 together form a second sub-part 30b.

[0056] In some embodiments, see Figure 3 As shown, the first structural layer 3010 and the second structural layer 3020 together form the first sub-part 30a, and the third structural layer 3030 and the fourth structural layer 3040 together form the second sub-part 30b.

[0057] In some embodiments, a portion of the first structural layer 3010 and a portion of the second structural layer 3020 together form a first sub-part 30a, and another portion of the second structural layer 3020, the third structural layer 3030 and the fourth structural layer 3040 together form a second sub-part 30b.

[0058] In some embodiments, a portion of the first structural layer 3010, the second structural layer 3020, and the third structural layer 3030 together form a first sub-part 30a, and another portion of the third structural layer 3030 and the fourth structural layer 3040 together form a second sub-part 30b.

[0059] In one embodiment, see Figure 3 As shown, along the first direction, there is a stepped surface 313 between the two ends of the sidewall 31 of the contact portion 30.

[0060] Because the materials of the first insulating layer 21 and the second insulating layer 22 are different, the etching rates of the first insulating layer 21 and the second insulating layer 22 are different during the etching process. The diameter of the through hole formed in the first insulating layer 21 is different from the diameter of the through hole in the second insulating layer 22. As a result, the hole wall of the through hole has a stepped surface 313 between the two ends along the first direction. The hole wall can serve as the side wall 31 of the contact portion 30. Therefore, the side wall 31 of the contact portion 30 has a stepped surface 313 between the two ends.

[0061] In some embodiments, see Figure 3 As shown, along the first direction, the contact portion 30 includes a first sidewall 311 and a second sidewall 312, and the extension directions of the first sidewall 311 and the second sidewall 312 both intersect the step surface 313; along the first direction, the step surface 313 is located between the first sidewall 311 and the second sidewall 312.

[0062] For example, the first sidewall 311 is the circumferential sidewall of the first sub-part 30a, and the second sidewall 312 is the circumferential sidewall of the second sub-part 30b.

[0063] Since the first sub-part 30a is shaped like a frustum, and a frustum has a generatrix, the generatrix of the frustum can be understood as the generatrix of the first sub-part. The extension direction of the first sidewall 311 refers to the extension direction of the generatrix of the first sub-part 30a. Similarly, the extension direction of the second sidewall 312 refers to the extension direction of the generatrix of the second sub-part 30b.

[0064] In some embodiments, the stepped surface 313 may be parallel to the contact surface between the first insulating layer 21 and the second insulating layer 22. For example, see... Figure 3 As shown, the stepped surface 313 can coincide with the contact surface between the first insulating layer and the second insulating layer.

[0065] In some embodiments, see Figure 3 As shown, the surface of the second structural layer 3020 that is away from the first structural layer 3010 can be coplanar with the step surface.

[0066] In some embodiments, the surface of the second structural layer 3020 away from the first structural layer 3010 may also be located on either side of the step surface along the first direction.

[0067] Of course, in other embodiments, the surface of the first structural layer 3010 near the second structural layer 3020 may also be flush with the step surface.

[0068] See Figure 1 and Figure 4 As shown, the first insulating layer 21 is made of silicon nitride, and the second insulating layer 22 is made of silicon carbon nitride. Compared with silicon nitride, silicon carbon nitride has stronger resistance to hydrofluoric acid corrosion, and the etching rate of silicon carbon nitride is lower than that of silicon nitride. Therefore, the etching rate of the second insulating layer 22 is lower than that of the first insulating layer 21. During the etching of the insulating layer 20 to form through-holes, less of the second insulating layer 22 is etched away, while more of the first insulating layer 21 is etched away. This is equivalent to increasing the distance between the surfaces of two adjacent through-holes on the second insulating layer 22 away from the surface of the first insulating layer 21. After the contact portion 30 is subsequently formed, the distance between the second ends of two adjacent contact portions 30 also increases accordingly, thereby reducing the risk of leakage between adjacent contact portions and improving the reliability of the semiconductor device. At the same time, it also ensures good contact between the contact portion and the semiconductor body.

[0069] It should be noted that the material of the second insulating layer 22 may also include silicon boron nitride.

[0070] See Figure 6 and Figure 7 As shown, the first insulating layer 21' is made of silicon nitride doped with phosphorus or arsenic, and the second insulating layer 22' is made of silicon nitride. Compared to silicon nitride, silicon nitride doped with phosphorus or arsenic has a faster etching rate; therefore, the etching rate of the second insulating layer 22 is less than that of the first insulating layer 21.

[0071] During the etching of the insulating layer 20 to form through-holes, less of the second insulating layer 22 is etched away, while more of the first insulating layer 21 is etched away. This is equivalent to increasing the distance between the surfaces of two adjacent through-holes on the second insulating layer 22 away from the surface of the first insulating layer 21. After the contact portion 30 is subsequently formed, the distance between the second ends of two adjacent contact portions 30 also increases accordingly, thereby reducing the risk of leakage between two adjacent contact portions and improving the reliability of the semiconductor device. At the same time, it can also ensure good contact between the contact portion and the semiconductor body.

[0072] In one embodiment, the number of contact portions 30 along the second direction is plurality, see [reference] Figure 2As shown, the distance L2 between the second ends of two adjacent contact portions 30 is greater than the distance L1 between the first ends of the two contact portions 30. See also Figure 5 As shown, the distance L2 between the second ends of two adjacent contact portions 30 is equal to the distance L1 between the first ends of the two contact portions 30.

[0073] It should be noted that, Figure 2 Only the four middle contact parts are shown; the contact parts on both sides are not shown.

[0074] Since the insulating layer 20 includes a first insulating layer 21 and a second insulating layer 22, the etching rates of the first insulating layer 21 and the second insulating layer 22 can be controlled respectively during the etching process, so that L2 is greater than or equal to L1. This increases the distance between the second ends of two adjacent contacts, reduces the risk of leakage between two adjacent contacts, and improves the reliability of the semiconductor device.

[0075] Since the cross-sectional shape of the contact portion 30 is circular, the aforementioned distance L1 refers to the minimum distance along the second direction between the first ends of two adjacent contact portions 30. Correspondingly, the aforementioned distance L2 refers to the minimum distance along the second direction between the second ends of two adjacent contact portions 30.

[0076] When the centers of the cross-sections of two adjacent contact portions 30 are arranged along the second direction, the aforementioned distance L1 can also refer to the radial distance between the second ends of the two adjacent contact portions 30. For example, L1 is equal to the difference between the distance between the centers of the second ends of the two adjacent contact portions 30 and the radius of the two contact portions 30.

[0077] Correspondingly, the distance L2 between the ends of two adjacent contact portions 30 that are away from the semiconductor body 10 can also refer to the radial distance between the first ends of two adjacent contact portions 30.

[0078] In one embodiment, the semiconductor device further includes a capacitor 40 and a conductive layer 50; along the second direction, there are multiple semiconductor bodies 10; along the first direction, each of the multiple semiconductor bodies 10 has a first end and a second end, the first end of the semiconductor body 10 is connected to the capacitor 40 through a contact portion 30, and the second end of the semiconductor body 10 is connected to the conductive layer 50.

[0079] For example, the number of semiconductor bodies 10 and the number of contacts 30 can be in one-to-one correspondence. The first end of the semiconductor body 10 can serve as the source and be connected to the capacitor 40. Specifically, the first end of the semiconductor body 10 is connected to the first end of the contact 30, and the second end of the contact 30 is connected to the capacitor 40. The second end of the semiconductor body 10 can serve as the drain and be connected to the conductive layer 50 (e.g., bit line).

[0080] For example, the semiconductor device provided in this embodiment may be Dynamic Random Access Memory (DRAM). DRAM may include multiple memory cells, and each memory cell includes a vertical transistor and a capacitor. For example, each memory cell may include one vertical transistor and one capacitor.

[0081] In one embodiment, see Figure 1 As shown, the semiconductor device also includes a first gate structure 60 and a second gate structure 70, which are respectively disposed on both sides of the semiconductor body 10 along the second direction.

[0082] For example, the semiconductor body 10 may include a channel structure of a vertical transistor and source and drain regions located at both ends of the channel structure. The first gate structure 60 may serve as the positive gate of the vertical transistor, and the second gate structure 70 may serve as the back gate of the vertical transistor. The second gate structures of two adjacent vertical transistors are connected together, and in the manufacturing process, the second gate structures of two adjacent vertical transistors can be fabricated simultaneously.

[0083] See Figure 8 As shown, this embodiment also provides a method for manufacturing a semiconductor device, which may include the following steps:

[0084] Step S802, a substrate 100 is provided, the substrate 100 having a first side and a second side disposed opposite to each other along a first direction;

[0085] Step S804: Forming a semiconductor body 10, wherein along a first direction, the semiconductor body 10 includes opposing first ends and second ends;

[0086] Step S806: An insulating layer 20 is formed on a first side of the substrate 100, wherein the insulating layer includes a first insulating layer 21 and a second insulating layer 22, and the second insulating layer 22 is located on the side of the first insulating layer 21 away from the substrate 100.

[0087] Step S808: A through-hole 301 is formed through the insulating layer 20 to expose the first end of the semiconductor body 10; wherein, along the second direction, the size of the through-hole 301 on the surface of the insulating layer 20 away from the semiconductor body 10 is less than or equal to the size of the through-hole 301 on the surface of the insulating layer 20 close to the semiconductor body 10, and the second direction intersects the first direction.

[0088] In step S810, a contact portion 30 is formed within the through hole 301.

[0089] The semiconductor device provided in this embodiment, since the insulating layer 20 includes a first insulating layer 21 and a second insulating layer 22, can control the etching rates of the first insulating layer 21 and the second insulating layer 22 respectively during the etching process, ensuring that the width of the second end of the contact portion 30 is less than or equal to the width of the first end of the contact portion 30. In this way, the width of the first end of the contact portion 30 can be increased without significantly increasing the width of the second end of the contact portion 30, thereby increasing the contact area between the first end of the contact portion 30 and the semiconductor body 10. At the same time, the risk of leakage current is reduced and the reliability of the semiconductor device is improved.

[0090] It should be understood that, Figure 8 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 3 The steps shown can be adjusted in order according to actual needs. Figures 9 to 23 This is a partial structural schematic diagram of a semiconductor structure formed after performing certain steps in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. The following is in conjunction with... Figure 8 , Figures 9 to 23 The manufacturing method of the semiconductor device provided in the embodiments of this disclosure will be described in detail.

[0091] In step S802, the provided substrate 100 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0092] It should be understood that substrate 100 can be retained, removed, or thinned.

[0093] In step S804, forming a semiconductor body 10 includes forming a channel structure and a source and a drain located at both ends of the channel structure. For example, the first end of the semiconductor body 10 can serve as the source, and the second end can serve as the drain.

[0094] In some embodiments, the material of the semiconductor body can be the same as that of the substrate, so there is no obvious interface between the semiconductor body and the substrate.

[0095] See Figure 9 As shown, some exemplary processes following the formation of the semiconductor body 10 further include: forming a second gate structure 70 and a conductive material layer 600, the second gate structure 70 and the conductive material layer 600 being located on opposite sides of the semiconductor body 10. The conductive material layer 600 is joined together at its end near the second side of the substrate and will be broken in a subsequent process to form two first gate structures 60.

[0096] It should be noted that the process steps for forming the first gate structure and the second gate structure are understandable to those skilled in the art and are well-known and easy to implement for them; therefore, they will not be described in detail in this embodiment.

[0097] In step S806, there are multiple ways to form an insulating layer 20 on the first side of the substrate 100. Three implementation methods will be mainly introduced below.

[0098] In some implementations, see Figure 10 and Figure 11 As shown, forming an insulating layer 20 on a first side of a substrate 100 includes: depositing a first insulating material on the first side of the substrate to form a first insulating layer 21; and depositing a second insulating material on the side of the first insulating layer 21 away from the substrate to form a second insulating layer 22; wherein the first insulating material includes silicon nitride, and the second insulating material includes silicon carbon nitride or silicon boron nitride.

[0099] For example, the first insulating material and the second insulating material can be deposited using, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), or any other suitable film deposition technique.

[0100] Compared to silicon nitride, silicon carbon nitride or silicon boron nitride has stronger resistance to hydrofluoric acid corrosion. The etching rate of silicon carbon nitride is lower than that of silicon nitride; therefore, the etching rate of the second insulating layer 22 is lower than that of the first insulating layer 21. During the etching and cleaning of the insulating layer 20 to form through-holes, less of the second insulating layer 22 is etched away, while more of the first insulating layer 21 is etched away. This effectively increases the distance between adjacent through-holes on the surface of the second insulating layer 22 away from the surface of the first insulating layer 21. After the contact portion 30 is subsequently formed, the distance between the second ends of the contact portion 30 also increases accordingly, thereby reducing the risk of leakage between adjacent contact portions and improving the reliability of the semiconductor device. Simultaneously, it also ensures good contact between the contact portion and the semiconductor body.

[0101] In other embodiments, forming an insulating layer 20 on a first side of the substrate 100 includes depositing a silicon nitride layer 200 on the first side of the substrate, such as... Figure 12 As shown; see also Figure 13A As shown, ion implantation is performed on the target site of the silicon nitride layer 200 to form a second insulating layer 22, and the first insulating layer 21 is a silicon nitride layer without implanted ions; wherein, the implanted ions are configured such that the etching rate of the second insulating layer is less than the etching rate of the first insulating layer.

[0102] It should be understood that during ion implantation, the dopant element is initially implanted into the material layer, such as the silicon nitride layer 200, in ionic form. For example, during ion implantation, by adjusting process parameters, such as changing the energy of the implanted ions and controlling the implantation dose and number of implantations, ion distribution can be achieved at different depths in the silicon nitride layer, thereby enabling ion implantation at target locations in the silicon nitride layer to form the second insulating layer 22.

[0103] For example, the implanted ions include carbon ions or boron ions. The material of the second insulating layer 22 includes silicon carbon nitride or boron carbon nitride.

[0104] It should be noted that the energy of carbon or boron ions, as well as the dosage and number of implantations, are not limited here.

[0105] In other embodiments, forming an insulating layer 20 on a first side of the substrate 100 includes: depositing a silicon nitride layer 200 on the first side of the substrate, such as... Figure 12 As shown; see also Figure 13B As shown, ion implantation is performed on the target site of the silicon nitride layer 200 to form a first insulating layer 21' and a second insulating layer 22' which is a silicon nitride layer without implanted ions; wherein the implanted ions are configured such that the etching rate of the first insulating layer 21' is greater than the etching rate of the second insulating layer 22'.

[0106] For example, the injected ions include phosphorus ions or arsenic ions.

[0107] Compared to silicon nitride, silicon nitride doped with phosphorus or arsenic has a faster etching rate. Therefore, the etching rate of the second insulating layer 22' is less than that of the first insulating layer 21'.

[0108] In step S808, see Figure 14 and Figure 15 As shown, an etching process can be used to form a through-hole 301 that penetrates the insulating layer 20 to expose the first end of the semiconductor body 10, so that the first end of the semiconductor body 10 can be connected to the capacitor.

[0109] See Figure 14 As shown, a dry etching process can be used, for example, for... Figure 11In the semiconductor structure shown, the insulating layer 20 is etched to form a via 301A with a large top dimension and a small bottom dimension. A post-etching cleaning step can then be performed to remove residues or contaminants generated during the etching process, improving process reliability and device performance. Hydrofluoric acid is typically used during the cleaning process. For example, since the material of the second insulating layer is silicon-carbon-nitrogen, it has stronger resistance to hydrofluoric acid corrosion and a slower etching rate compared to the first insulating layer 21. Therefore, during the cleaning process, more of the first insulating layer 21 is etched away, while less of the second insulating layer 22 is etched away, resulting in a portion of the surface of the second insulating layer 22 facing the first insulating layer 21 being exposed; this exposed portion is the step surface. For example, the exposed second insulating layer can be annular in shape. The formed via 301, as shown... Figure 15 As shown.

[0110] For example, the cross-sectional shape of the formed through hole 301 can be circular. It should be understood that the circular shape of the cross-sectional shape of the through hole 301 means approximately circular within the allowable machining error range.

[0111] The cross-section of the through hole 301 is perpendicular to the first direction. Along the first direction, the diameter of the cross-section of the through hole 301 is different at different positions.

[0112] Because the insulating layer 20 has a certain thickness, the through hole 301 has a certain depth. For example, see... Figure 15 As shown, the through hole 301 can be understood as a combination of two hollow frustum-shaped channels. Specifically, the hollow frustum-shaped channel formed in the first insulating layer is connected to the hollow frustum-shaped channel formed in the second insulating layer.

[0113] For example, the dimension W5 of the via 301 on the surface of the second insulating layer 22 away from the semiconductor body 10 refers to the diameter of the via 301 on the surface of the second insulating layer 22 away from the semiconductor body 10, and the dimension W6 of the via 301 on the surface of the first insulating layer 21 near the semiconductor body 10 refers to the diameter of the via 301 on the surface of the first insulating layer 21 near the semiconductor body 10; see also Figure 15 As shown, W5 is less than W6.

[0114] Since the material of the second insulating layer includes silicon carbon nitrogen or silicon boron nitrogen, it will hardly be corroded by hydrofluoric acid during the subsequent cleaning process. Therefore, in the initial stage of forming the via, the size W3 of the via 301 on the surface of the second insulating layer 22 away from the semiconductor body 10 can be made larger, which is beneficial for subsequent further etching to form a via with a good morphology.

[0115] In step S310, a contact portion 30 is formed within the through hole 301. The maximum width W2 of the second end of the formed contact portion 30 along the second direction is substantially equal to the dimension W5 of the through hole 301 on the surface of the second insulating layer 22 away from the semiconductor body 10; the maximum width W1 of the first end of the contact portion 30 along the second direction is substantially equal to the dimension W6 of the through hole 301 on the surface of the first insulating layer 21 near the semiconductor body 10.

[0116] For example, see Figure 16 As shown, a first material layer 3110 is deposited into the via 301. The first material layer 3110 can be polysilicon. Then, a portion of the first material layer 3110 is etched back, and the retained first material layer can serve as the first structural layer 3010. The resulting structure is as follows. Figure 17 As shown; see also Figure 18 As shown, a second material layer is deposited above the first structural layer 3010. This second material layer can serve as the second structural layer 3020, and it can be cobalt-silicon. (See also...) Figure 19 As shown, a third material is deposited on the surface of the second material layer and the walls of the via 301 to form a third structural layer 3030. The third material can be titanium nitride. Then, a fourth material is deposited into the remaining space of the via to form a fourth structural layer 3040. The fourth material can be tungsten. (See also...) Figure 20 As shown, a capacitor 40 is formed on the side of the contact portion 30 away from the semiconductor body.

[0117] In some exemplary processes following the formation of the contact portion 30 within the via 301, the process further includes: removing a portion of the substrate and a portion of the conductive material layer 600 from the first surface, thereby breaking the conductive material layer 600 and forming two first gate structures 60 from the remaining conductive material layer 600. The first gate structures 60 can serve as word lines of vertical transistors. Then, a conductive layer 50 is formed, which can serve as bit lines of vertical transistors. The resulting structure is as follows: Figure 21 As shown.

[0118] In some embodiments, the exemplary process following the formation of the through-hole 301 further includes: using, for example, a wet etching process to further etch the hole wall of the through-hole 301, thereby forming a hollow cylindrical channel, i.e., through-hole 301B, as shown below. Figure 22 As shown. At this point, W5 equals W6.

[0119] See Figure 23 As shown, a contact portion 30 is formed within the through hole 301B. The formed contact portion can be a cylindrical structure.

[0120] It should be noted that the steps of forming the contact portion 30 in the through hole 301B and the subsequent steps of forming the first gate structure 60 and the conductive layer 50 are basically the same as those described above, and will not be repeated here.

[0121] It should be noted that the semiconductor device provided in this embodiment can be manufactured using the semiconductor device manufacturing method provided in this embodiment.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor device, characterized in that, The device includes a semiconductor body, an insulating layer, and a contact portion penetrating the insulating layer; along a first direction, the semiconductor body is located on one side of the insulating layer; the insulating layer includes a first insulating layer and a second insulating layer, with the first insulating layer located between the second insulating layer and the semiconductor body. Along the first direction, the contact portion has a first end and a second end, the first end of the contact portion being in contact with the semiconductor body; along the second direction, the width of the second end of the contact portion is less than or equal to the width of the first end of the contact portion, wherein the first direction intersects the second direction.

2. The semiconductor device according to claim 1, characterized in that, Along the first direction, there is a stepped surface between the two ends of the sidewall of the contact portion.

3. The semiconductor device according to claim 2, characterized in that, Along the first direction, the contact portion includes a first sidewall and a second sidewall, the extension directions of the first sidewall and the second sidewall both intersect the stepped surface; along the first direction, the stepped surface is located between the first sidewall and the second sidewall.

4. The semiconductor device according to claim 1, characterized in that, The contact portion includes a first sub-portion and a second sub-portion. The end of the first sub-portion that is connected to the semiconductor body is the first end of the contact portion. The size of the end of the first sub-portion that is connected to the second sub-portion is larger than the size of the end of the second sub-portion that is connected to the first sub-portion.

5. The semiconductor device according to claim 4, characterized in that, The material of the first sub-part includes polycrystalline silicon, and the material of the second sub-part includes a conductive material.

6. The semiconductor device according to claim 1, characterized in that, The material of the first insulating layer includes silicon nitride, and the material of the second insulating layer includes silicon carbon nitride or silicon boron nitride.

7. The semiconductor device according to claim 1, characterized in that, The material of the first insulating layer includes silicon nitride doped with phosphorus or arsenic, and the material of the second insulating layer includes silicon nitride.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, Along the second direction, there are multiple contact portions, and the distance between the second ends of two adjacent contact portions is greater than or equal to the distance between the first ends of the two contact portions.

9. The semiconductor device according to any one of claims 1 to 7, characterized in that, It also includes a capacitor and a conductive layer; along the second direction, there are multiple semiconductor bodies; along the first direction, each of the multiple semiconductor bodies has a first end and a second end, the first end of the semiconductor body is connected to the capacitor through the contact portion, and the second end of the semiconductor body is connected to the conductive layer.

10. The semiconductor device according to any one of claims 1 to 7, characterized in that, It also includes a first gate structure and a second gate structure, which are respectively disposed on both sides of the semiconductor body along the second direction.

11. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the substrate having a first side and a second side disposed opposite to each other along a first direction; A semiconductor body is formed, and along the first direction, the semiconductor body includes opposing first and second ends; An insulating layer is formed on a first side of the substrate, wherein the insulating layer includes a first insulating layer and a second insulating layer, the second insulating layer being located on the side of the first insulating layer away from the substrate; A through-hole is formed through the insulating layer to expose a first end of the semiconductor body; wherein, along a second direction, the size of the through-hole on the surface of the insulating layer away from the semiconductor body is less than or equal to the size of the through-hole on the surface of the insulating layer near the semiconductor body, and the second direction intersects the first direction; A contact portion is formed within the through hole.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, An insulating layer is formed on a first side of the substrate, comprising: A first insulating material is deposited on a first side of the substrate to form a first insulating layer; a second insulating material is deposited on the side of the first insulating layer away from the substrate to form a second insulating layer; wherein the first insulating material comprises silicon nitride and the second insulating material comprises silicon carbon nitride or silicon boron nitride.

13. The method for manufacturing a semiconductor device according to claim 11, characterized in that, An insulating layer is formed on a first side of the substrate, comprising: A silicon nitride layer is deposited on the first side of the substrate; Ion implantation is performed on the target site of the silicon nitride layer to form the second insulating layer, wherein the first insulating layer is an unimplanted silicon nitride layer; wherein the implanted ions are configured such that the etching rate of the second insulating layer is less than the etching rate of the first insulating layer.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The injected ions include carbon ions or boron ions.

15. The method for manufacturing a semiconductor device according to claim 11, characterized in that, An insulating layer is formed on a first side of the substrate, comprising: A silicon nitride layer is deposited on the first side of the substrate; Ion implantation is performed on the target sites of the silicon nitride layer to form the first insulating layer, and the second insulating layer is a silicon nitride layer without implanted ions; wherein the implanted ions are configured such that the etching rate of the first insulating layer is greater than the etching rate of the second insulating layer.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The injected ions include phosphorus ions or arsenic ions.

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