Semiconductor device with storage node contact

Abstract

A semiconductor device includes: a bit line located on a substrate and extending in a first direction parallel to an upper surface of the substrate; a semiconductor pattern located on the bit line and extending in a direction perpendicular to the upper surface of the substrate; a gate electrode located on a side surface of the semiconductor pattern and extending in a second direction intersecting the first direction; a memory node contact located on the upper surface of the semiconductor pattern; an upper insulating layer covering the side surface of the memory node contact; and a cover pattern located between the upper insulating layer and the gate electrode. The upper insulating layer is located on the upper surface of the cover pattern. Both the upper surface of the semiconductor pattern and the upper surface of the cover pattern have a concave profile.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductors, and more specifically, to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices are essential in the electronics industry due to their characteristics such as miniaturization, versatility, and / or low manufacturing cost. Semiconductor devices can include: semiconductor memory devices for storing logic data, semiconductor logic devices for processing logic data, and hybrid semiconductor devices that include both memory elements and logic elements.

[0003] As electronic devices become faster and consume less power, there is a growing demand for semiconductor devices that operate at high speeds and / or low voltages. To meet these requirements, semiconductor devices with higher integration levels are needed. Summary of the Invention

[0004] A semiconductor device according to some embodiments of the present disclosure may include: a bit line located on a substrate and extending in a first direction parallel to an upper surface of the substrate; a semiconductor pattern located on the bit line and extending in a direction perpendicular to the upper surface of the substrate; a gate electrode located on a side surface of the semiconductor pattern and extending in a second direction intersecting the first direction; a memory node contact located on the upper surface of the semiconductor pattern; an upper insulating layer covering the side surface of the memory node contact; and a cover pattern located between the upper insulating layer and the gate electrode, wherein the upper insulating layer is located on the upper surface of the cover pattern, and both the upper surface of the semiconductor pattern and the upper surface of the cover pattern have concave profiles.

[0005] A semiconductor device according to some embodiments of the present disclosure may include: a bit line located on a substrate and extending in a first direction parallel to an upper surface of the substrate; a semiconductor pattern located on the bit line and extending in a direction perpendicular to the upper surface of the substrate; a gate electrode located on a side surface of the semiconductor pattern and extending in a second direction intersecting the first direction; a memory node contact located on the upper surface of the semiconductor pattern; an upper insulating layer covering the side surface of the memory node contact; and a cover pattern located between the upper insulating layer and the gate electrode, wherein the upper insulating layer is located on the upper surface of the cover pattern, the memory node contact includes a first region and a second region located between the first region and the semiconductor pattern, the upper surface of the cover pattern has a concave profile, and the lower surface of the second region of the memory node contact has a convex profile.

[0006] A semiconductor device according to some embodiments of the present disclosure may include: a bit line located on a substrate and extending in a first direction parallel to an upper surface of the substrate; a semiconductor pattern located on the bit line and extending in a direction perpendicular to the upper surface of the substrate; a gate electrode located on a side surface of the semiconductor pattern and extending in a second direction intersecting the first direction; a back gate electrode spaced apart from the gate electrode in the first direction and extending in the second direction, the semiconductor pattern being located between the back gate electrode and the gate electrode; a memory node contact located on the upper surface of the semiconductor pattern; a landing pad located on the memory node contact; a data storage pattern located on the landing pad; an upper insulating layer covering a side surface of the memory node contact; and a cover pattern located between the upper insulating layer and the gate electrode, wherein the upper insulating layer is located on the upper surface of the cover pattern, and both the upper surface of the semiconductor pattern and the upper surface of the cover pattern have concave profiles. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

[0008] Figure 2 and Figure 3 This is a schematic perspective view of a semiconductor device according to some embodiments of the present disclosure.

[0009] Figure 4 This is a top view showing a semiconductor device according to some embodiments of the present disclosure.

[0010] Figure 5 It corresponds to Figure 4 A cross-sectional view of line A-A'.

[0011] Figure 6 and Figure 7 It corresponds to Figure 5 An enlarged view of P1 in the image.

[0012] Figure 8 It corresponds to Figure 4 A cross-sectional view of line A-A'.

[0013] Figure 9 It corresponds to Figure 8 A magnified view of P2 in the image.

[0014] Figure 10 This is a top view showing a semiconductor device according to some embodiments of the present disclosure.

[0015] Figures 11 to 17 This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0016] Figure 18 This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0017] Embodiments of this disclosure provide semiconductor devices with improved productivity and methods for manufacturing the same.

[0018] Exemplary embodiments of this disclosure will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments.

[0019] Figure 1 This is a block diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

[0020] refer to Figure 1 The semiconductor device may include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and control logic 5.

[0021] The memory cell array 1 may include multiple memory cells MC arranged in two or three dimensions. Each memory cell MC may be disposed between and connected to intersecting word lines WL and bit lines BL. Each memory cell MC may include a select element TR and a data storage element DS. The select element TR and the data storage element DS may be electrically connected to each other. The select element TR may be connected to both word line WL and bit line BL. In other words, the select element TR may be disposed at the point where word line WL and bit line BL intersect.

[0022] The select element TR may include a field-effect transistor. The data storage element DS may include a capacitor, a magnetic tunnel junction pattern, or a variable resistor. For example, the gate of the transistor serving as the select element TR may be connected to the word line WL, and the source / drain terminals of the transistor may be connected to the bit line BL and the data storage element DS, respectively.

[0023] Row decoder 2 can decode externally input addresses and select a word line WL of memory cell array 1. The address decoded in row decoder 2 can be provided to the row driver, and the row driver can provide predetermined voltages to the selected word line WL and the unselected word line WL respectively in response to the control of the control circuit.

[0024] The readout amplifier 3 can sense, amplify, and output the voltage difference between the selected bit line BL and the reference bit line based on the address decoded by the slave decoder 4.

[0025] Column decoder 4 provides a data transfer path between the sense amplifier 3 and external components (e.g., a memory controller). Column decoder 4 can decode externally input addresses to select a bit line BL. Control logic 5 generates control signals for controlling the writing of data to or reading data from the memory cell array 1.

[0026] Figure 2 and Figure 3 This is a schematic perspective view of a semiconductor device according to some embodiments of the present disclosure.

[0027] refer to Figure 2 and Figure 3 The semiconductor device may include a peripheral circuit structure PS and a cell array structure CS connected to the peripheral circuit structure PS on the substrate 100. The substrate 100 may have a plate shape extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 are parallel to the upper surface of the substrate 100 and may intersect each other. A third direction D3 may be perpendicular to the upper surface of the substrate 100 and may intersect the first direction D1 and the second direction D2.

[0028] The peripheral circuit structure PS may include a core and peripheral circuitry formed on the substrate 100. The core and peripheral circuitry may include a reference... Figure 1 The description includes row decoder 2, column decoder 4, readout amplifier 3, and control logic 5.

[0029] The cell array structure CS can include Figure 1 The storage cell array 1 includes two-dimensional or three-dimensional arrangements. Figure 1 The storage unit MC. As an example. Figure 1Each memory cell MC may include a vertical channel transistor (TR) as its selected element. A vertical channel transistor may include a channel whose longitudinal direction is D3.

[0030] refer to Figure 2 The peripheral circuit structure PS can be disposed on the substrate 100. The cell array structure CS can be disposed on the peripheral circuit structure PS. The peripheral circuit structure PS can be connected to the cell array structure CS through additional contacts.

[0031] refer to Figure 3 The semiconductor device can have a chip-to-chip (C2C) structure. A peripheral circuit structure PS can be disposed on a substrate 100. A first metal pad LMP can be disposed on the upper part of the peripheral circuit structure PS. The first metal pad LMP can be electrically connected to the core and the peripheral circuit. The first metal pad LMP in the peripheral circuit structure PS can be bonded to a second metal pad UMP of the cell array structure CS, which will be described later. Therefore, the peripheral circuit structure PS and the cell array structure CS can be bonded.

[0032] The cell array structure CS can be disposed on the carrier substrate 200. The second metal pad UMP can be disposed at the lower part of the cell array structure CS. The second metal pad UMP can be electrically connected to... Figure 1 Storage cell array 1.

[0033] Figure 4 This is a top view of a semiconductor device according to some embodiments of the present disclosure. Figure 5 It corresponds to Figure 4 A cross-sectional view of line A-A'. Figure 6 and Figure 7 It corresponds to Figure 5 An enlarged view of P1 in the image.

[0034] Figure 4 and Figure 5 These are the references shown. Figure 2 and Figure 3 Top view and cross-sectional view of the elements in the described cell array structure CS.

[0035] Semiconductor devices may include a lower insulating layer (LIL). The lower insulating layer (LIL) may include an insulating material. As an example, the lower insulating layer (LIL) may be disposed on a reference... Figure 2 The lower part of the described cell array structure CS. In this case, the lower insulating layer LIL can be connected with the reference. Figure 2 The described peripheral circuit structure shows adjacent and contacting PS. (Reference) Figure 2 The described peripheral circuit structure PS can be referenced. Figure 2 The substrate 100 described is located between the substrate 100 and the lower insulating layer LIL. The lower insulating layer LIL may include connections to a reference. Figure 2The description includes the core and interconnections of the peripheral circuit structure PS.

[0036] As another example, the cell array structure CS of semiconductor devices (e.g., see...) Figure 2 The lower insulating layer (LIL) is flipped so that it can be set at the reference. Figure 3 The upper part of the described cell array structure CS. In this case, the lower insulating layer LIL can be connected to the reference. Figure 3 The described carrier substrates 200 are adjacent to and in contact with each other. The accompanying drawings show a cell array structure CS of a semiconductor device in a non-inverted state (see, for example, [reference needed]). Figure 2 The disclosure includes top and cross-sectional views of the sample, but is not limited thereto.

[0037] Bit lines BL can be disposed in a lower insulating layer LIL. Bit lines BL in the lower insulating layer LIL can extend in a first direction D1. Bit lines BL can include a conductive material. As an example, bit lines BL can include at least one of the following: doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), metallic materials (e.g., titanium (Ti), molybdenum (Mo), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), ruthenium (Ru), iridium (Ir), cobalt (Co), etc.), metal silicide materials (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), or metal nitride materials (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). Bit lines BL can be a single layer or a composite layer. Multiple bit lines BL can be disposed. Bit lines BL can be spaced apart from each other in a second direction D2. As used herein, "extend" includes "being stretched" or "being oriented in a certain direction." For example, "extend in the first direction D1" includes "stretch in the first direction D1" or "orient along the first direction D1".

[0038] Bit line contacts DC can be disposed in the lower insulating layer LIL. Bit line contacts DC can be disposed on the bit line BL. Bit line contacts DC can be located between the lower surface E2 of the semiconductor pattern SP (described later) and the bit line BL. Therefore, the bit line BL can be connected to the semiconductor pattern SP via bit line contacts DC. Bit line contacts DC can include a conductive material. In an embodiment, bit line contacts DC can include doped silicon. Multiple bit line contacts DC can be disposed. Multiple bit line contacts DC located on the bit line BL can be spaced apart from each other in a first direction D1.

[0039] Semiconductor patterns SP can be disposed on bit lines BL. In one embodiment, semiconductor patterns SP can be disposed on the upper surface of the bit line contact DC. The semiconductor patterns SP located on the bit line BL can extend in a third direction D3. Multiple semiconductor patterns SP can be disposed. Semiconductor patterns SP located on a bit line BL can be spaced apart from each other in a first direction D1. Semiconductor patterns SP can be spaced apart from each other in a second direction D2.

[0040] The semiconductor pattern SP may include a semiconductor material. In one embodiment, the semiconductor pattern SP may include at least one of silicon (e.g., single-crystal silicon), germanium, or silicon-germanium. In another embodiment, the semiconductor pattern SP may include an oxide semiconductor. In this case, the oxide semiconductor may include, but is not limited to, at least one of the following: indium gallium zinc oxide (InGaZnO), indium gallium silicon oxide (InGaSiO), indium tin zinc oxide (InSnZnO), indium zinc oxide (InZnO), zinc oxide (ZnO), zinc tin oxide (ZnSnO), zinc oxynitride (ZnON), zirconium zinc tin oxide (ZrZnSnO), stannous oxide (SnO), hafnium indium zinc oxide (HfInZnO), gallium zinc tin oxide (GaZnSnO), aluminum zinc tin oxide (AlZnSnO), ytterbium gallium zinc oxide (YbGaZnO), or indium gallium oxide (InGaO). In another embodiment, the semiconductor pattern SP may include indium gallium zinc oxide (IGZO). In yet another embodiment, the semiconductor pattern SP may include a two-dimensional semiconductor material. In this case, the two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0041] Word lines WL can be disposed on the side surface of a semiconductor pattern SP. Word lines WL can be located between adjacent semiconductor patterns SP in the first direction D1. Word lines WL can extend in the second direction D2. Multiple word lines WL can be disposed. Word lines WL can be spaced apart from each other in the first direction D1. In an embodiment, pairs of adjacent word lines WL in the first direction D1 can be located between adjacent semiconductor patterns SP in the first direction D1. In an embodiment, pairs of adjacent word lines WL in the first direction D1 can be spaced apart from each other, and a cut pattern CT is located between the pairs of word lines.

[0042] The word line WL may include a gate electrode GE extending in a second direction D2 and a third direction D3, and a gate insulating pattern GI located between the semiconductor pattern SP and the gate electrode GE. The gate electrode GE may include a conductive material. As an example, the gate electrode GE may include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). In an embodiment, the gate insulating pattern GI may include at least one of silicon oxide or a high-k dielectric material. Herein, a high-k dielectric material is defined as a material with a dielectric constant higher than that of silicon oxide.

[0043] A first gate cover pattern GC1 may be disposed on the upper surface of the gate electrode GE. The first gate cover pattern GC1 may be located between the gate electrode GE and the upper insulating layer UIL, which will be described later. A portion of the side surface of the first gate cover pattern GC1 may be covered by a gate insulating pattern GI. The first gate cover pattern GC1 may include an insulating material. In an embodiment, the first gate cover pattern GC1 may include silicon oxide.

[0044] The first gate overlay pattern GC1 may be located between adjacent gate electrodes GE in the first direction D1, and may space the gate electrodes apart. The first gate overlay pattern GC1 may extend in the third direction D3.

[0045] The second gate overlay pattern GC2 may be located between the gate electrode GE and the lower insulating layer LIL. The second gate overlay pattern GC2 may include an insulating material. In one embodiment, the second gate overlay pattern GC2 may include silicon oxide.

[0046] A back gate structure (BGS) can be disposed on the side surface of a semiconductor pattern (SP). The back gate structure (BGS) can be located between adjacent semiconductor patterns (SP) in the first direction (D1). The back gate structure (BGS) and word line (WL) can be spaced apart from each other in the first direction (D1), and the semiconductor pattern (SP) is located between the back gate structure (BGS) and the word line (WL). The back gate structure (BGS) can extend along the second direction (D2) between adjacent semiconductor patterns (SP) in the first direction (D1). Multiple back gate structures (BGS) can be disposed. The back gate structures (BGS) can be spaced apart from each other in the first direction (D1).

[0047] When a back-gate structure (BGS) is configured, the threshold voltage of the transistor, including the semiconductor pattern SP, can be adjusted by applying a voltage to the BGS. Adjusting the threshold voltage via the BGS is easier than adjusting it by injecting impurities into the semiconductor pattern SP. Adjusting the threshold voltage via the BGS prevents accidental transistor turn-on.

[0048] The back-gate structure BGS may include a back-gate electrode BGE and a back-gate insulating pattern BGI covering the side surface of the back-gate electrode BGE. The back-gate electrode BGE may be spaced apart from the gate electrode GE in a first direction D1, and a semiconductor pattern SP is located between the back-gate electrode and the gate electrode. As an example, the back-gate electrode BGE may include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). In an embodiment, the back-gate insulating pattern BGI may include at least one of silicon oxide or a high-k dielectric material.

[0049] The first back gate cover pattern BGC1 can be disposed on the upper surface of the back gate electrode BGE. The first back gate cover pattern BGC1 can be located between the back gate electrode BGE and the upper insulating layer UIL, which will be described later.

[0050] The second back gate cover pattern BGC2 may be located between the back gate electrode BGE and the lower insulating layer LIL. Each of the first back gate cover pattern BGC1 and the second back gate cover pattern BGC2 may include an insulating material. In an embodiment, each of the first back gate cover pattern BGC1 and the second back gate cover pattern BGC2 may include silicon oxide.

[0051] The memory node contact BC can be disposed on the semiconductor pattern SP. The memory node contact BC can be disposed on the upper surface E1 of the semiconductor pattern SP. The memory node contact BC can include a conductive material. In one embodiment, the memory node contact BC can include doped silicon. Multiple memory node contacts BC can be disposed. The memory node contacts BC can be spaced apart from each other in a first direction D1 and a second direction D2.

[0052] Because the memory node contact BC is formed through an engraving process described later, the shape of the memory node contact BC can follow the shape of the semiconductor pattern SP when viewed from a top view. As shown in the figure, the semiconductor pattern SP can have a rectangular shape when viewed from a top view, but is not limited to this.

[0053] Landing pads LP can be disposed on the memory node contact BC. Landing pads LP can be connected to the semiconductor pattern SP via the memory node contact BC. Landing pads LP can include conductive materials. As an example, landing pads LP can include at least one of doped semiconductor materials (e.g., doped silicon, doped germanium, etc.) or metallic materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). Multiple landing pads LP can be disposed. Landing pads LP can be spaced apart from each other in a first direction D1 and a second direction D2.

[0054] The storage node contact BC and landing pad LP can together form the connection structure CNS.

[0055] The blocking pattern may be located between the storage node contact BC and the landing pad LP. As an example, the blocking pattern may include at least one of a metal silicide (e.g., a silicide of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) or a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0056] The upper insulating layer UIL can be applied to the side surface of each of the storage node contacts BC and landing pads LP. The upper insulating layer UIL can cover the side surface of each of the storage node contacts BC and landing pads LP. The upper insulating layer UIL can surround the side surface of each of the storage node contacts BC and landing pads LP. The upper insulating layer UIL can space multiple storage node contacts BC apart from each other. The upper insulating layer UIL can separate multiple landing pads LP from each other.

[0057] The upper insulating layer UIL may include an insulating material. In one embodiment, the upper insulating layer UIL may include an insulating material different from each of the first gate cover pattern GC1 and the first back gate cover pattern BGC1. In another embodiment, the upper insulating layer UIL may include an insulating material with a dielectric constant higher than that of each of the first gate cover pattern GC1 and the first back gate cover pattern BGC1. In yet another embodiment, the upper insulating layer UIL may include SiN.

[0058] The data storage pattern DSP can be set on the landing pad LP. The data storage pattern DSP can be connected to the semiconductor pattern SP via the landing pad LP and the memory node contact BC. Multiple data storage pattern DSPs can be set. The data storage pattern DSPs can be arranged spaced apart from each other in a first direction D1 and a second direction D2. The data storage pattern DSPs can correspond to a reference. Figures 1 to 3 The data storage element DS is described.

[0059] In embodiments, the data storage pattern DSP can be a capacitor including a lower electrode, a dielectric layer, and an upper electrode. In this case, the semiconductor device according to the present disclosure can be a dynamic random access memory (DRAM). The data storage pattern DSP can include a magnetic tunnel junction pattern. In this case, the semiconductor device according to the present disclosure can be a magnetic random access memory (MRAM). The data storage pattern DSP can also include a phase change material or a variable resistance material. In this case, the semiconductor device according to the present disclosure can be a phase change random access memory (PRAM) or a resistive random access memory (ReRAM). However, this is merely illustrative and the present disclosure is not limited thereto, and the data storage pattern DSP can include various structures and / or materials capable of storing data.

[0060] refer to Figure 6 Various features of the configuration described below can be formed through the engraving process of the storage node contacting the BC. These features will be described in detail below.

[0061] The upper surface E1 of the semiconductor pattern SP can have a concave profile. The upper surface E1 of the semiconductor pattern SP can have a concave profile recessed into the semiconductor pattern SP.

[0062] The memory node contact BC may include a first region R1 and a second region R2 located between the first region R1 and the semiconductor pattern SP. The first region R1 and the second region R2 may be distinguished at a first height LV1. The first height LV1 may be defined as the height of the upper surface of the semiconductor pattern SP. The first region R1 of the memory node contact BC is defined above the first height LV1, while the second region R2 of the memory node contact BC is defined below the first height LV1.

[0063] The second region R2 of the memory node contact BC can be inserted into and thus embedded within the semiconductor pattern SP. Since the upper surface E1 of the semiconductor pattern SP has a concave profile, the lower surface B2b of the second region R2 can have a convex profile. The lowest surface of the second region R2 can be located at a vertical height below the first height LV1. In an embodiment, the lower surface B2b of the second region R2 can be located at a vertical height lower than the upper surface Gia of the gate insulating pattern GI and the upper surface BGIa of the back gate insulating pattern BGI.

[0064] A portion of the semiconductor pattern SP may be located between the second region R2 of the memory node contact BC and the gate insulating pattern GI, and between the second region R2 and the back gate insulating pattern BGI. In an embodiment, each of the gate insulating pattern GI and the back gate insulating pattern BGI may be in contact with the lower surface B1b of the first region R1 of the memory node contact BC.

[0065] At the first height LV1, relative to the first direction D1, the first region R1 of the storage node contact BC can have a first width W1, and the second region R2 of the storage node contact BC can have a second width W2. Relative to the first direction D1, the semiconductor pattern SP can have a third width W3. The first width W1 can be greater than the second width W2 and the third width W3. In one example, the second width W2 can be substantially equal to the third width W3.

[0066] The upper insulating layer UIL can be disposed on the upper surface GCa of the first gate cover pattern GC1 and the upper surface of the first back gate cover pattern BGC1. Each of the upper surface GCa of the first gate cover pattern GC1 and the upper surface of the first back gate cover pattern BGC1 can have a concave profile. The lower surface Ub of the upper insulating layer UIL can have a convex profile. The upper surface Ua of the upper insulating layer UIL can be coplanar with the upper surface La of the landing pad LP.

[0067] refer to Figure 7 ,and Figure 6 The shape of the first region R1 of the storage node contact BC is different. The upper surface B1a of the first region R1 of the storage node contact BC can have a concave profile. The upper surface B1a of the first region R1 can be recessed into the second region R2. The lower surface Lb of the landing pad LP can have a convex profile.

[0068] In the following text, reference will be made to Figure 8 and Figure 9 This section describes semiconductor devices according to some embodiments of the present disclosure. For the sake of simplicity, descriptions overlapping with the above will be omitted, and the differences from the above will be primarily described.

[0069] Figure 8 It corresponds to Figure 4 A cross-sectional view of line A-A'. Figure 9 It corresponds to Figure 8 A magnified view of P2 in the image.

[0070] refer to Figure 4 , Figure 8 and Figure 9 Each of the upper surface Gia of the gate insulating pattern GI and the upper surface BGIa of the back gate insulating pattern BGI can be located at a vertical height lower than the first height LV1. The lower surface B1b of the first region R1 of the memory node contact BC can be located at a vertical height lower than the first height LV1. A portion of the first region R1 of the memory node contact BC can cover the upper side surface Ss of the semiconductor pattern SP. Therefore, the contact area between the memory node contact BC and the semiconductor pattern SP can be increased. Therefore, the electrical characteristics of the semiconductor device can be improved.

[0071] The upper part of the semiconductor pattern SP may be located between a portion of the first region R1 of the memory node contact BC and the second region R2 of the memory node contact BC.

[0072] Figure 10 This is a top view of a semiconductor device according to some embodiments of the present disclosure.

[0073] refer to Figure 10 Because the memory node contact BC is formed through an engraving process described later, the shape of the memory node contact BC can follow the shape of the semiconductor pattern SP when viewed from a top view. As shown in the figure, the semiconductor pattern SP can have a semi-elliptical shape when viewed from a top view. The memory node contact BC can also have a semi-elliptical shape.

[0074] Because the landing pad LP is formed through the engraving process described below, its shape can follow the shape of the storage node contact BC when viewed from a top view. As shown in the figure, the landing pad LP can have a semi-elliptical shape when viewed from a top view.

[0075] In the following text, reference will be made to Figures 11 to 18 Methods for manufacturing semiconductor devices according to some embodiments of this disclosure are described. For the sake of simplicity, descriptions overlapping with the above will be omitted, and the differences from the above will be primarily described.

[0076] Figures 11 to 17 This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 11 , Figure 14 and Figure 16 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Figure 12 , Figure 13 , Figure 15 and Figure 17 They correspond to Figure 11 , Figure 14 and Figure 16 A cross-sectional view of line A-A'.

[0077] refer to Figure 11 and Figure 12 A first substrate 110 can be fabricated. A dummy insulating layer 120 and a second substrate can be sequentially formed on the first substrate 110. In one example, the first substrate 110 and the second substrate may include semiconductor materials. The dummy insulating layer 120 may include insulating materials.

[0078] Then, a first patterning process can be performed on each of the dummy insulating layer 120 and the second substrate, and thus a first trench can be formed. A first patterning process can be performed on the second substrate, and thus a second trench can be formed. A back gate structure BGS and a first back gate cover pattern BGC1 can be formed in the first trench. A word line WL and a first gate cover pattern GC1 can be formed in the second trench.

[0079] Through a first patterning process and a second patterning process, the second substrate can be divided into semiconductor patterns SP extending in a second direction D2 and a third direction D3 respectively and spaced apart from each other in a first direction D1. A third patterning process can be performed on the semiconductor patterns SP such that the semiconductor patterns SP can be divided into multiple semiconductor patterns SP spaced apart from each other in the second direction D2.

[0080] Subsequently, a removal process can be performed on the top of each semiconductor pattern SP. A first recess RS1 can be formed on the top surface E1 of each semiconductor pattern SP. The first recess RS1 can be perpendicularly overlapped with the semiconductor pattern SP. The first recess RS1 can expose each of the side surfaces of the gate insulating pattern GI and the back gate insulating pattern BGI. The top surface E1 of each semiconductor pattern SP can be exposed through the first recess RS1 and can have a concave profile.

[0081] refer to Figure 11 and Figure 13 The second recess RS2 can be formed by removing a portion of each of the gate insulating pattern GI and the back gate insulating pattern BGI exposed by the first recess RS1. Therefore, the width W5 of the second recess RS2 can be greater than the width W4 of the first recess RS1 relative to the first direction D1. In other words, the width of the recess can be widened by a removal process on the inner wall of the first recess RS1. In an embodiment, the width W4 of the first recess RS1 can be compared with a reference... Figure 6 The third width W3 described is basically the same.

[0082] refer to Figure 14 and Figure 15 A memory node contact BC can be formed in the second recess RS2. In one embodiment, forming the memory node contact BC may include forming the memory node contact BC by an engraving process. In another embodiment, forming the memory node contact BC may include: forming a memory node contact layer that fills the interior of the second recess RS2 and covers the upper surface of each of the first gate cover pattern GC1 and the first back gate cover pattern BGC1, and removing the upper portion of the memory node contact layer to form the memory node contact BC.

[0083] According to this disclosure, the memory node contact BC can be formed by an engraving process. A first recess RS1 can be formed by removing the upper part of the semiconductor pattern SP, and then a second recess RS2 can be formed by removing the inner wall of the first recess RS1. Since the second recess RS2 overlaps with the semiconductor pattern SP, the memory node contact BC filling the second recess RS2 can self-align with the semiconductor pattern SP. Therefore, misalignment between the memory node contact BC and the semiconductor pattern SP can be prevented. Therefore, manufacturing process defects in semiconductor devices can be reduced. Therefore, the productivity of the method for manufacturing semiconductor devices can be improved.

[0084] Furthermore, when forming the memory node contact BC via an embossing process, a mask pattern may be required to form the memory node contact layer covering the upper surface of the first substrate 110, and to divide the memory node contact layer into memory node contacts BC spaced apart from each other in a first direction D1 and a second direction D2. When forming the memory node contact BC via a etching process, the memory node contact BC can be formed without a mask pattern. Therefore, the productivity of the method for manufacturing semiconductor devices can be improved by either not using a mask pattern or using a mask pattern in a formation process with an alternative configuration.

[0085] Furthermore, due to the step of forming the second recess RS2, the width of the recess located on the semiconductor pattern SP can be widened. Therefore, the width of the memory node contact BC can be wider than when the second recess RS2 is not formed (i.e., when only the first recess RS1 is formed). Therefore, the memory node contact BC and the landing pad formed subsequently ( Figure 5 The contact area between the LPs in the semiconductor device can be increased. Therefore, the electrical characteristics of the semiconductor device can be improved.

[0086] refer to Figure 16 and Figure 17 An upper insulating layer UIL can be formed between the memory node contacts BC using an engraving process. In one embodiment, forming the upper insulating layer UIL may include: removing a portion of each of the first gate cover pattern GC1, a portion of the first back gate cover pattern BGC1, and a portion of the back gate insulating pattern BGI between the memory node contacts BC to form a third recess RS3, and filling the third recess RS3 with the upper insulating layer UIL. The third recess RS3 may expose the side surfaces of the memory node contacts BC. The third recess RS3 may expose the upper surfaces of each of the first gate cover pattern GC1 and the first back gate cover pattern BGC1. When the upper insulating layer UIL is formed by the engraving process, the upper surface GCa of the first gate cover pattern GC1 (e.g., see...) Figure 6Both the upper surface of the first back gate overlay pattern BGC1 and the lower surface of the upper insulating layer UIL can have a concave profile. Therefore, the lower surface Ub of the upper insulating layer UIL (e.g., see...) Figure 6 It can have a convex profile.

[0087] refer to Figure 4 and Figure 5 In reference Figure 16 and Figure 17 Following the described upper insulating layer UIL formation process, landing pads LP can be formed on the memory node contacts BC by an engraving process. In an embodiment, forming the landing pads LP may include: removing the upper portion of each memory node contact BC, filling the area where the upper portion of each memory node contact BC has been removed, forming a landing pad layer covering the upper surface of the upper insulating layer UIL, and removing the upper portion of the landing pad layer to separate it into landing pads LP. In an embodiment, by removing the upper portion of each memory node contact BC, the upper surface B1a of each memory node contact BC (e.g., see...) Figure 7 It can have a concave profile, as shown in the reference. Figure 7 As described above. In an implementation, the lower surface Lb of each landing pad LP (e.g., see...) Figure 7 It can have a convex profile.

[0088] In this implementation, a barrier pattern can be formed on the upper surface of the storage node contact BC after the process of removing the upper part of each storage node contact BC and before the process of forming the landing pad layer. At this time, a cleaning process can be performed on the upper surface of each storage node contact BC before the process of forming the barrier pattern. Therefore, oxides that are unnecessarily formed on the upper surface of each storage node contact BC can be removed.

[0089] According to the concept of this disclosure, an upper insulating layer UIL comprising a nitride-based insulating material can replace an insulating pattern comprising an oxide-based insulating material between the storage node contacts BC. Therefore, during the cleaning step, cleaning fluid can be prevented from penetrating beneath the upper insulating layer UIL. This prevents process defects caused by the cleaning fluid and improves the productivity of the semiconductor device manufacturing process.

[0090] According to this disclosure, the landing pad LP can be formed by an engraving process. The height of the landing pad LP can vary depending on the degree to which the storage node contact BC is removed. Therefore, adjusting the height of the landing pad LP is easier than forming the landing pad LP by an embossing process.

[0091] As an example, a barrier pattern can be formed on the storage node contact BC prior to the formation process of the landing pad LP.

[0092] Then, a data storage pattern DSP can be formed on the connection structure CNS.

[0093] Subsequently, the first substrate 110 (see, for example, see...) Figure 17 The top and bottom of the first substrate 110 can be inverted. Therefore, the first substrate 110 (see, for example, see...) Figure 17 The lower surface of the substrate 110 can be exposed. The first substrate 110 can be removed (e.g., see...). Figure 17 ) and dummy insulation layer 120 (for example, see Figure 17 At this time, the gate electrode GE (for example, see...) Figure 17 A portion of the gate electrode GE is removed, such that (see, for example, see...) Figure 17 The semiconductor pattern SP can be divided into pairs of gate electrodes GE spaced apart from each other in the first direction D1. In this embodiment, a portion of the semiconductor pattern SP can be removed. When referring to... Figure 12 The upper surface E1 of the described semiconductor pattern SP is defined as the first surface and Figure 12 When the lower surface E2 of the semiconductor pattern SP shown is defined as the second surface, the second surface of the semiconductor pattern SP can be exposed by a removal process. The first surface of the semiconductor pattern SP can be opposite to the second surface of the semiconductor pattern SP.

[0094] The second gate cover pattern GC2 can be formed as part of the alternative gate electrode GE, and the second back gate cover pattern BGC2 can be formed as part of the alternative back gate electrode BGE.

[0095] Bit line contacts DC and bit lines BL can be sequentially formed on the second surface of the semiconductor pattern SP. A lower insulating layer LIL can be formed to cover the bit line contacts DC and bit lines BL. The lower insulating layer LIL can be formed at different times, either before or after the formation of the bit line contacts DC and bit lines BL.

[0096] Figure 18 This is a diagram illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. More specifically, Figure 18 It corresponds to Figure 11 A cross-sectional view of line A-A'.

[0097] refer to Figure 11 and Figure 18 In reference Figure 13 Following the process described for the second recess RS2, with Figure 13Unlike the previous method, the lower surface of the second recess RS2 can be formed at a vertical height lower than the uppermost surface of the semiconductor pattern SP. Therefore, a portion of the upper surface Ss of the semiconductor pattern SP can be exposed by the second recess RS2. The second recess RS2 can be formed such that the upper surface Gia of the gate insulating pattern GI is at a vertical height lower than the uppermost surface of the semiconductor pattern SP. Through the second recess RS2, the upper surface BGIa of a portion of the back gate insulating pattern BGI can be formed at a vertical height lower than the uppermost surface of the semiconductor pattern SP.

[0098] Then, the reference can be manufactured using the methods described above for manufacturing semiconductor devices. Figure 4 , Figure 8 and Figure 9 The semiconductor device described.

[0099] According to this disclosure, memory node contacts can be formed by an engraving process that fills the area above a removed portion of a semiconductor pattern. Therefore, the memory node contacts can self-align with the semiconductor pattern. This prevents misalignment between the memory node contacts and the semiconductor pattern. Consequently, manufacturing process defects in semiconductor devices can be reduced. Therefore, the productivity of methods for manufacturing semiconductor devices can be improved.

[0100] Furthermore, forming memory node contacts via an engraving process eliminates the need for the mask pattern required when forming memory node contacts via an embossing process, or allows the use of a mask pattern in an alternative formation process. Therefore, the productivity of methods for manufacturing semiconductor devices can be improved.

[0101] According to the concept of this disclosure, an upper insulating layer comprising a nitride-based insulating material can replace the insulating pattern comprising an oxide-based insulating material between memory node contacts. Therefore, during the cleaning process of the upper surface of the memory node contacts forming the blocking pattern, cleaning fluid can be prevented from penetrating below the upper insulating layer. Thus, process defects caused by cleaning fluid can be prevented, and the productivity of semiconductor device manufacturing methods can be improved.

[0102] According to this disclosure, landing pads can be formed by an engraving process that fills the upper, removed area of ​​the storage node contact. The height of the landing pad can vary depending on the degree to which the storage node contact is removed. Therefore, adjusting the height of the landing pad can be easier than forming the landing pad through an embossing process.

[0103] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope that may be claimed, but rather as descriptions of features characteristic of particular embodiments of a particular invention. Certain features described in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from a combination may be removed from that combination, and the combination may refer to a sub-combination or a variation of a sub-combination.

[0104] While embodiments have been described above, those skilled in the art will understand that various modifications and variations can be made without departing from the spirit and scope of this disclosure as defined in the appended claims. Therefore, the exemplary embodiments of this disclosure should be considered illustrative rather than restrictive in all respects, and the spirit and scope of this disclosure are indicated by the appended claims.

[0105] In addition to the above-described implementation methods, the following implementation methods are also innovative.

[0106] Embodiment 1 is a method for manufacturing a semiconductor device. The method includes: forming a semiconductor pattern on a first substrate, the semiconductor pattern extending in a direction perpendicular to the first substrate; sequentially forming a gate insulating pattern and a gate electrode on a side surface of the semiconductor pattern; forming a cover pattern on the gate electrode; removing an upper portion of the semiconductor pattern to form a first recess exposing the side surface of the gate insulating pattern; removing a portion of the gate insulating pattern exposed by the first recess to form a second recess; forming a memory node contact in the second recess; removing a portion of the cover pattern to form a third recess exposing the side surface of the memory node contact; and forming an upper insulating layer in the third recess.

[0107] Implementation 2 is a method based on Implementation 1, wherein the method further includes: removing the upper part of the storage node contact; and forming a landing pad in the area where the upper part of the storage node contact is removed.

[0108] Implementation 3 is based on the method of Implementation 1, wherein, after the process of removing the upper part of the storage node contact, the upper surface of the storage node contact may have a concave profile.

[0109] Implementation method 4 is based on the method of implementation method 1, wherein the width of the second recess may be greater than the width of the first recess relative to the first direction.

[0110] Implementation 5 is based on the method of Implementation 1, wherein, after the process of forming the first recess, the upper surface of the semiconductor pattern may have a concave profile.

[0111] Implementation 6 is based on the method of Implementation 1, wherein, after the process of forming the third recess, the upper surface of the cover pattern may have a concave profile.

[0112] Implementation 7 is a method based on Implementation 1, wherein the upper insulating layer may include an insulating material different from the covering pattern.

[0113] Implementation 8 is based on the method of Implementation 1, wherein a portion of the side surface of the semiconductor pattern can be exposed by a second recess.

[0114] Embodiment 9 is a method based on Embodiment 1, wherein the first surface of the semiconductor pattern can be exposed by a first recess, and the method of manufacturing a semiconductor device may further include: flipping a first substrate and then removing the first substrate to expose a second surface of the semiconductor pattern, the second surface of the semiconductor pattern being opposite to the first surface of the semiconductor pattern; and forming bit lines on the second surface of the semiconductor pattern.

[0115] Implementation 10 is a method based on Implementation 1, wherein the method may further include: forming a back gate electrode spaced apart from the gate electrode, and a semiconductor pattern being disposed between the back gate electrode and the gate electrode.

Claims

1. A semiconductor device, the semiconductor device comprising: Bit lines are located on the substrate and extend in a first direction parallel to the upper surface of the substrate; A semiconductor pattern located on the bit line and extending in a direction perpendicular to the upper surface of the substrate; A gate electrode, the gate electrode being located on a side surface of the semiconductor pattern and extending in a second direction intersecting the first direction; A memory node contact is located on the upper surface of the semiconductor pattern; An upper insulating layer that covers the side surface of the storage node contact; as well as A cover pattern is provided, which is located between the upper insulating layer and the gate electrode. The upper insulating layer is located on the upper surface of the covering pattern, and The upper surface of the semiconductor pattern and the upper surface of the cover pattern both have concave contours.

2. The semiconductor device according to claim 1, wherein, The memory node contact includes a first region and a second region located between the first region and the semiconductor pattern, and The lower surface of the second region in contact with the storage node has a convex profile.

3. The semiconductor device of claim 2, further comprising a gate insulating pattern located between the semiconductor pattern and the gate electrode, and in, The lower surface of the second region in contact with the storage node is positioned below the upper surface of the gate insulating pattern.

4. The semiconductor device according to claim 2, wherein, The upper surface of the first region that the storage node contacts has a concave profile.

5. The semiconductor device according to claim 2, wherein, A portion of the first region contacted by the storage node covers the upper side surface of the semiconductor pattern.

6. The semiconductor device according to claim 2, wherein, The lower surface of the first region in contact with the storage node is positioned below the uppermost surface of the semiconductor pattern.

7. The semiconductor device according to claim 1, wherein, The memory node contact includes a first region and a second region located between the first region and the semiconductor pattern. The second region contacted by the storage node is inserted into the semiconductor pattern.

8. The semiconductor device according to claim 1, wherein, The memory node contact includes a first region and a second region located between the first region and the semiconductor pattern. Wherein, the first area contacted by the storage node is defined above the first height, and the second area contacted by the storage node is defined below the first height, and Wherein, relative to the first direction, the width of the first region contacted by the storage node, defined by reference to the first height, is greater than the width of the second region contacted by the storage node, defined by reference to the first height.

9. The semiconductor device according to claim 8, wherein, Relative to the first direction, the width of the second region, defined by the reference first height, in contact with the storage node is equal to the width of the semiconductor pattern.

10. The semiconductor device according to claim 1, wherein, The upper insulating layer and the covering pattern comprise different insulating materials.

11. The semiconductor device according to claim 1, wherein, The lower surface of the upper insulating layer has a convex profile.

12. The semiconductor device according to claim 1, wherein, Each of the semiconductor pattern and the memory node contact has a semi-elliptical shape.

13. The semiconductor device according to claim 1, wherein, The semiconductor pattern is a first semiconductor pattern, and The semiconductor device further includes: A second semiconductor pattern and a third semiconductor pattern, the second semiconductor pattern and the third semiconductor pattern being spaced apart from each other in the first direction, and the first semiconductor pattern being located between the second semiconductor pattern and the third semiconductor pattern; and A back gate electrode, wherein the back gate electrode is located between the first semiconductor pattern and the second semiconductor pattern, and The gate electrode includes a pair of gate electrodes located between the first semiconductor pattern and the third semiconductor pattern and spaced apart from each other along the first direction.

14. A semiconductor device, the semiconductor device comprising: Bit lines are located on the substrate and extend in a first direction parallel to the upper surface of the substrate; A semiconductor pattern located on the bit line and extending in a direction perpendicular to the upper surface of the substrate; A gate electrode, the gate electrode being located on a side surface of the semiconductor pattern and extending in a second direction intersecting the first direction; A memory node contact is located on the upper surface of the semiconductor pattern; An upper insulating layer that covers the side surface of the storage node contact; as well as A cover pattern is provided, which is located between the upper insulating layer and the gate electrode. The upper insulating layer is located on the upper surface of the covering pattern. The memory node contact includes a first region and a second region located between the first region and the semiconductor pattern. The upper surface of the overlay pattern has a concave profile, and the lower surface of the second region in contact with the storage node has a convex profile.

15. The semiconductor device according to claim 14, wherein, The second region that the storage node contacts is embedded within the semiconductor pattern.

16. The semiconductor device according to claim 14, wherein, The first area contacted by the storage node is defined above a first height, and the second area contacted by the storage node is defined below the first height. Wherein, relative to the first direction, the width of the second region of the storage node contact defined by reference to the first height is smaller than the width of the first region of the storage node contact defined by reference to the first height, and equal to the width of the semiconductor pattern.

17. The semiconductor device of claim 14, further comprising a gate insulating pattern located between the semiconductor pattern and the gate electrode, and in, A portion of the semiconductor pattern is located between the second region of the memory node contact and the gate insulating pattern.

18. The semiconductor device according to claim 14, wherein, The lowest surface of the second region in contact with the storage node is positioned below the highest surface of the semiconductor pattern.

19. The semiconductor device according to claim 14, wherein, The upper insulating layer and the covering pattern comprise different insulating materials, and The lower surface of the upper insulating layer has a convex profile.

20. A semiconductor device, the semiconductor device comprising: Bit lines are located on the substrate and extend in a first direction parallel to the upper surface of the substrate; A semiconductor pattern located on the bit line and extending in a direction perpendicular to the upper surface of the substrate; A gate electrode, the gate electrode being located on a side surface of the semiconductor pattern and extending in a second direction intersecting the first direction; A back gate electrode, which is spaced apart from the gate electrode in a first direction and extends in a second direction, wherein the semiconductor pattern is located between the back gate electrode and the gate electrode; A memory node contact is located on the upper surface of the semiconductor pattern; A landing pad, which is located on the storage node contact; A data storage pattern, the data storage pattern being located on the landing pad; An upper insulating layer that covers the side surface of the storage node contact; as well as A cover pattern is provided, which is located between the upper insulating layer and the gate electrode. The upper insulating layer is located on the upper surface of the covering pattern, and The upper surface of the semiconductor pattern and the upper surface of the cover pattern both have concave contours.

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