Semiconductor device including word line structure

Abstract

This disclosure relates to a semiconductor device including a word line structure. A semiconductor device includes: a bit line configured to extend in a first direction; a word line structure configured to extend in a second direction; an active region having one side contacting the bit line and configured to extend in a third direction; and a back gate configured to extend parallel to the word line structure. The word line structure includes: a lower word line extending parallel to the back gate; an upper word line spaced apart from the lower word line in a third direction; and a vertical connection extending in a third direction and contacting both the lower and upper word lines.

Description

[0001] Cross-references to related applications

[0002] This patent document claims priority and benefit to Korean Patent Application No. 10-2025-0047327, filed with the Korean Intellectual Property Office on April 11, 2025, the entire contents of which are incorporated herein by reference as part of the disclosure of this application. Technical Field

[0003] The technologies and embodiments disclosed in this patent document generally relate to semiconductor devices, and more specifically, to semiconductor devices including word line structures. Background Technology

[0004] With miniaturization and higher integration of semiconductor devices becoming major priorities, memory cells included in semiconductor devices can be formed with three-dimensional (3D) patterns. Miniaturized memory cells with three-dimensional (3D) patterns can be equipped with configurations that improve the operating characteristics of the memory cells. Summary of the Invention

[0005] Various embodiments of this disclosure relate to memory devices including word line structures.

[0006] According to one embodiment of this disclosure, a semiconductor device may include: a bit line extending in a first direction; a first word line structure extending in a second direction; an active region having one end in contact with the bit line and extending upward in a third direction; and a back gate extending parallel to the first word line structure. The first word line structure may include: a first lower word line extending parallel to the back gate; a first upper word line spaced apart from the first lower word line in a third direction; and a vertical connection extending upward in a third direction to connect the first lower word line and the first upper word line.

[0007] In some embodiments, the semiconductor device may further include a memory element that is in contact with the other end of the active region.

[0008] In some embodiments, the first upper word line may include a material with a resistance less than that of the first lower word line.

[0009] In some embodiments, the vertical connection portion may include a material with a resistance less than that of the first lower letter line.

[0010] In some embodiments, the second character line structure adjacent to the first character line structure in the first direction may include a second upper character line. The horizontal height of the first upper character line in the third direction may be different from the horizontal height of the second upper character line in the third direction.

[0011] In some embodiments, the second character line structure adjacent to the first character line structure may include a second bottom character line. The horizontal height of the first bottom character line in the third direction is the same as the horizontal height of the second bottom character line in the third direction.

[0012] In some embodiments, the back gate may be configured to be parallel to the side surfaces of a plurality of active regions that are repeatedly arranged along a second direction.

[0013] In some embodiments, the first upper word line can receive an activation voltage from the word line driver.

[0014] In some embodiments, a second word line structure adjacent to the first word line structure in a first direction may include a second upper word line. The first upper word line may be connected to a first word line driver, and the second upper word line may be connected to a second word line driver.

[0015] In some embodiments, the first word line driver and the second word line driver may respectively provide activation voltages to the first upper word line and the second upper word line connected to the first word line driver and the second word line driver respectively.

[0016] In some embodiments, the width of the first upper character line in the first direction may be greater than the width of the first lower character line in the first direction.

[0017] In some embodiments, the thickness of the first upper character line in the third direction may be greater than the thickness of the first lower character line in the third direction.

[0018] According to another embodiment of this disclosure, a semiconductor device may include: a plurality of lower word lines arranged repeatedly in a first direction and extending in a second direction; a plurality of upper word lines configured to overlap the plurality of lower word lines in a vertical direction and extend in the second direction; a plurality of vertical interconnects configured to connect the plurality of lower word lines and the plurality of upper word lines; a plurality of active regions arranged repeatedly parallel to the side surfaces of the plurality of lower word lines and extending upward in a third direction; and a plurality of bit lines contacting the plurality of active regions, wherein some of the plurality of active regions are arranged repeatedly in the first direction and collectively contact one of the plurality of bit lines.

[0019] In some embodiments, the semiconductor device may further include a plurality of memory elements that are respectively connected to a plurality of active regions.

[0020] In some embodiments, the upper character lines that are adjacent to each other in a first direction among a plurality of upper character lines can be set at different horizontal heights in a third direction.

[0021] In some embodiments, multiple bottom lines can be set at the same horizontal height in a third-party upward direction.

[0022] It should be understood that the foregoing general description and the following detailed description of this disclosure are illustrative and exemplary, intended to provide further explanation of this disclosure, and the scope of this disclosure is not limited to the examples or embodiments described in this specification. Attached Figure Description

[0023] The above and other features and advantages of this disclosure will become readily apparent when considered in conjunction with the accompanying drawings and with reference to the following detailed description.

[0024] Figure 1 This is a circuit diagram illustrating the equivalent circuitry of a memory cell array according to an embodiment of the present disclosure.

[0025] Figure 2 This is a perspective view showing a portion of a memory cell array according to an embodiment of the present disclosure.

[0026] Figure 3 This illustrates the following according to embodiments of the present disclosure: Figure 2 A cross-sectional view of an example memory cell array taken by the line (A-A').

[0027] Figure 4 This illustrates the acquisition of information from a third party according to embodiments of this disclosure. Figure 2 A diagram showing the layout structure of the storage cell array.

[0028] Figure 5 This is a diagram illustrating voltage fluctuations in a word line structure according to an embodiment of the present disclosure. Detailed Implementation

[0029] This disclosure provides embodiments and examples of semiconductor devices including word line structures that can be configured to fundamentally solve one or more technical or engineering problems and mitigate limitations or disadvantages encountered in semiconductor devices. Recognizing the above problems, embodiments of this disclosure provide semiconductor devices capable of reducing the boost effect caused by voltages applied to adjacent word lines. A word line structure according to embodiments of this disclosure may include a lower word line, an upper word line, and a vertical connection, and can quickly provide an activation voltage received through the upper word line to the lower word line.

[0030] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Throughout the drawings, the same reference numerals will be used as much as possible to refer to the same or similar parts. While the present disclosure is open to various modifications and alternatives, specific embodiments are illustrated by way of example in the drawings. However, the present disclosure should not be construed as limiting itself to the embodiments described herein.

[0031] In the following description, various embodiments will be illustrated with reference to the accompanying drawings. However, it should be understood that this disclosure is not limited to the specific embodiments, but includes various modifications, equivalents, and / or substitutions of the embodiments. Embodiments of this disclosure can provide a variety of effects that can be directly or indirectly recognized through this disclosure.

[0032] In the following description, detailed descriptions of the relevant known configurations or features contained herein will be omitted to avoid obscuring the subject matter.

[0033] The terminology used herein is for describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” “comprises,” and / or “containing,” when used in this specification, specify the presence of the said constituent elements, steps, operations, and / or components, but do not exclude the presence or addition of one or more other constituent elements, steps, operations, and / or components thereof. The term “and / or” can include a combination of multiple items or any one of multiple items.

[0034] In the following, a semiconductor device and a method of manufacturing the same according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 This is a circuit diagram illustrating the equivalent circuitry of a memory cell array according to an embodiment of the present disclosure.

[0036] Reference Figure 1 The memory cell array may include multiple bit lines BL1, BL2, BL3 and BL4 that all extend along a first direction (i.e., the X-axis direction), and multiple word line structures WL1, WL2, WL3 and WL4 that all extend along a second direction (i.e., the Y-axis direction).

[0037] A memory cell array can include multiple memory cells (MCs), and each memory cell (MC) can be located in an area where word lines and bit lines intersect each other.

[0038] Each memory cell (MC) may include a transistor and a memory element. Word lines may be connected to the gates of the transistors included in the memory cell (MC). Furthermore, one end of the transistor included in the memory cell may be in contact with a bit line, and the other end of the transistor may be in contact with a memory element. The memory element may be, for example, a capacitive element, such as a capacitor.

[0039] Figure 2 This is a perspective view showing a portion of a memory cell array according to an embodiment of the present disclosure.

[0040] Figure 3 This illustrates the following according to embodiments of the present disclosure: Figure 2A cross-sectional view of an example memory cell array taken by the line (A-A').

[0041] Figure 4 This illustrates the results obtained in a third direction (i.e., the Z-axis direction) according to an embodiment of this disclosure. Figure 2 A diagram showing the layout structure of the storage cell array.

[0042] Reference Figure 2 The following will refer to Figures 2 to 4 Description has Figure 1 Part 10 of the memory cell array shown in the equivalent circuit diagram.

[0043] The memory cell array can be formed on a substrate (not shown). The substrate may include a semiconductor substrate, such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, etc.

[0044] Bit lines 100 can be disposed in a substrate (not shown). Bit lines 100 can extend in a first direction (i.e., the X-axis direction) and can be repeated in a second direction (i.e., the Y-direction).

[0045] Each bit line 100 may include a conductive material. The conductive material may be, for example, a doped semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound.

[0046] Word line structures 200a and 200b can be arranged repeatedly in a first direction (i.e., the X-axis direction) and can be spaced apart from bit line 100 in a third direction (i.e., the Z-axis direction). Word line structures 200a and 200b can be electrically isolated from bit line 100 by insulating material.

[0047] The word line structure 200a may include a lower word line 210a extending in a second direction (i.e., the Y-axis direction), while the word line structure 200b may include a lower word line 210b extending in the second direction.

[0048] The character line structure 200a may include an upper character line 230a that overlaps with the lower character line 210a in a third direction (i.e., the Z-axis direction) and extends in a second direction. A plurality of vertical connecting portions 221a and 222a extend between the upper character line 230a and the lower character line 210a to interconnect the upper character line 230a and the lower character line 210a. The character line structure 200b may include an upper character line 230b that overlaps with the lower character line 210b in a third direction and extends in a second direction. A plurality of vertical connecting portions 221b and 222b extend between the upper character line 230b and the lower character line 210b to interconnect the upper character line 230b and the lower character line 210b.

[0049] The lower word line 210a, vertical connecting portions 221a and 222a, and upper word line 230a may include conductive materials. The conductive material may be, for example, any of a doped semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound. The lower word line 210b, vertical connecting portions 221b and 222b, and upper word line 230b may include conductive materials. The conductive material may be, for example, any of a doped semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound.

[0050] The vertical connecting portions 221a and 222a and the upper digit line 230a may include the same material, and may include a material with a lower resistance than the lower digit line 210a. The vertical connecting portions 221b and 222b and the upper digit line 230b may include the same material, and may include a material with a lower resistance than the lower digit line 210b.

[0051] For example, the vertical connecting portions 221a, 222a, 221b and 222b and the upper word lines 230a and 230b may include a metallic material such as copper (Cu), while the lower word lines 210a and 210b may include a doped semiconductor material.

[0052] The upper letter lines 230a and 230b can have higher conductivity than the lower letter lines 210a and 210b. Furthermore, when viewed along the second direction, the cross-sectional area of ​​the upper letter line 230a can be larger than that of the lower letter line 210a, and the cross-sectional area of ​​the upper letter line 230b can be larger than that of the lower letter line 210b.

[0053] Furthermore, the width of the upper character line 230a in the first direction (i.e., the X-axis direction) can be greater than that of the lower character line 210a. The width of the upper character line 230b in the first direction (i.e., the X-axis direction) can be greater than that of the lower character line 210b. The thickness of the upper character line 230a in the third direction (i.e., the Z-axis direction) can be greater than that of the lower character line 210a. The thickness of the upper character line 230b in the third direction (i.e., the Z-axis direction) can be greater than that of the lower character line 210b.

[0054] For example, vertical connection portions 221a, 222a, 221b, and 222b can each be formed as through-silicon vias (TSVs). Vertical connection portions 221a and 222a can be arranged at opposite ends of the lower word line 210a in the second direction (i.e., the Y-axis direction). Vertical connection portions 221b and 222b can be arranged at opposite ends of the lower word line 210b in the second direction (i.e., the Y-axis direction).

[0055] The upper word lines 230a and 230b can be regions that receive activation voltage from the word line driver. The activation voltage supplied to the upper word lines 230a and 230b can be provided to the lower word lines 210a and 210b through the vertical connection portions 221a, 222a, 221b, and 222b. For example, the activation voltage supplied to the upper word line 230a can be provided to the lower word line 210a through the vertical connection portions 221a and 222a, and the activation voltage supplied to the upper word line 230b can be provided to the lower word line 210b through the vertical connection portions 221b and 222b.

[0056] When an activation voltage is applied to the lower word line 210a, a channel region can be formed in the active region 300 adjacent to the lower word line 210a. When an activation voltage is applied to the lower word line 210b, a channel region can be formed in the active region 300 adjacent to the lower word line 210b.

[0057] In adjacent word line structures 200a and 200b, one word line structure can be referred to as the first word line structure 200a, and the other word line structure can be referred to as the second word line structure 200b.

[0058] The first character line structure 200a may include a first lower character line 210a, first vertical connecting portions 221a and 222a, and a first upper character line 230a.

[0059] The second character line structure 200b may include a second lower character line 210b, second vertical connecting portions 221b and 222b, and a second upper character line 230b.

[0060] The horizontal height of the first upper character line 230a in the third direction (i.e., the Z-axis direction) can be different from the horizontal height of the second upper character line 230b in the same direction. Therefore, adjacent upper character lines 230a and 230b can be spaced apart from each other in the third direction (i.e., the Z-axis direction).

[0061] Furthermore, the first upper word line 230a and the adjacent second upper word line 230b can be connected to different word line drivers. Each of the upper word lines 230a and 230b can be used as a region to receive voltage from the word line driver.

[0062] Since the upper word lines 230a and 230b are spaced apart from each other, the voltage applied to one upper word line (e.g., 230a) can reduce or minimize the voltage fluctuations generated in the other upper word line (e.g., 230b) adjacent to that upper word line.

[0063] The voltage applied to the first upper character line 230a can be supplied to the first lower character line 210a through the first vertical connecting portions 221a and 222a. Since the first vertical connecting portions 221a and 222a are provided at both ends of the first lower character line 210a, the voltage applied to the first upper character line 230a can be quickly transmitted to the first lower character line 210a.

[0064] Similarly, the voltage applied to the second upper word line 230b can be provided to the second lower word line 210b through the second vertical connection portions 221b and 222b.

[0065] like Figure 2 As shown, each word line structure (e.g., 200a) is exemplary shown to include two vertical connections (e.g., 221a and 222a), but the scope or spirit of this disclosure is not limited thereto. In other embodiments, each word line structure may also include additional vertical connections to facilitate voltage transmission from the upper word line 230a to the lower word line 210a. When vertical connections are added, the number of voltage transmission paths within the word line structure can be increased.

[0066] Reference Figure 2 and Figure 3 One side of the active region 300 may contact the bit line 100. The active region 300 may extend from the bit line 100 along a third direction (i.e., the Z-axis direction). The active region 300 may be a region in which a channel is formed. The active region 300 may include, for example, doped polysilicon, undoped polysilicon, amorphous silicon, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (In2O3), etc. The other end of the active region 300 in the third direction may contact the memory element 500.

[0067] When an activation voltage is applied to word line structures 200a and 200b adjacent to the active region 300, a channel can be formed in the active region 300.

[0068] Multiple active regions 300 can be arranged in an array shape in a first direction (i.e., the X-axis direction) and a second direction (i.e., the Y-axis direction). Active regions 300 that are repeatedly arranged in the first direction (i.e., the X-axis direction) can be connected together to a single bit line 100.

[0069] Multiple active regions 300 arranged repeatedly in the second direction (i.e., the Y-axis direction) can be arranged parallel to and adjacent to the side surfaces of the lower word lines 210a and 210b, respectively.

[0070] The back gate 400 included in the word line structures 200a and 200b can extend parallel to the lower word lines 210a and 210b, respectively. The back gate 400 can be arranged parallel to and adjacent to the side surface of the active regions 300 arranged along the second direction (i.e., the Y-axis direction).

[0071] Electrical interference between the active regions 300 that are adjacent to each other but separated by the back grid 400 placed between them can be minimized.

[0072] The back gate 400 may include a conductive material. The conductive material may be, for example, any of a doped semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound.

[0073] The storage element 500 may be, for example, a capacitive element, such as a capacitor. According to another embodiment, the storage element 500 may include a transistor structure.

[0074] The storage element 500 can be formed in a cylindrical shape, such as a cylindrical, square, or hexagonal prism.

[0075] Figure 3 The cross-section shows some of the connections and arrangements between the components included in the memory cell array.

[0076] Reference Figure 3 One end of the active region 300 can contact the bit line 100, and the lower word lines 210a and 210b can be respectively set on both sides of the active region 300.

[0077] Bit line 100 can be electrically isolated from back gate 400 and word line structures 200a and 200b. Although Figure 3 The insulating material is not shown in the figure, but it can be disposed between the bit line 100 and the word line structures 200a and 200b, and it can also be disposed between the bit line 100 and the back grid 400.

[0078] A back gate 400 may be disposed between adjacent active regions 300, and a storage element 500 may be connected to the other end of an active region 300. An insulating material may be disposed between the back gate 400 and the active region 300 to electrically isolate the active region 300 from the back gate 400.

[0079] The lower letter lines 210a and 210b can be connected to the vertical connecting parts 221a and 221b respectively, while the vertical connecting parts 221a and 221b can be connected to the upper letter lines 230a and 230b respectively.

[0080] Adjacent word lines 230a and 230b can be spaced apart from storage element 500 in a third direction (i.e., the Z-axis direction).

[0081] The storage element 500 can be electrically isolated from word line structures 200a and 200b.

[0082] Adjacent upper lines 230a and 230b can be set at different horizontal heights in the third direction (i.e., the Z-axis direction).

[0083] Figure 4 The diagram shows some layout patterns of word lines, back grids, and memory elements.

[0084] Reference Figure 4 Multiple bit lines 100a, 100b, 100c and 100d extending in the first direction (i.e. the X-axis direction) can be repeated in the second direction (i.e. the Y-axis direction).

[0085] The multiple word line structures 200a, 200b, 200c and 200d, which all extend in the second direction (i.e. the Y-axis direction), can be repeated in the first direction (i.e. the X-axis direction).

[0086] For ease of description and better understanding of this disclosure, these bit lines may be referred to as the first bit line 100a, the second bit line 100b, the third bit line 100c, and the fourth bit line 100d, respectively. Similarly, these word line structures may be referred to as the first word line structure 200a, the second word line structure 200b, the third word line structure 200c, and the fourth word line structure 200d, respectively.

[0087] A back gate 400a and multiple memory elements 500aa, 500ab, 500ac, 500ad, 500ba, 500bb, 500bc and 500bd can be set between a pair of adjacent word lines (e.g. 200a and 200b).

[0088] The back gate 400a can be arranged parallel to and adjacent to the side surfaces of a plurality of storage elements (e.g., 500aa, 500ab, 500ac and 500ad) that are repeatedly arranged in the second direction (i.e. the Y-axis direction).

[0089] The back gate 400a can be positioned between a pair of memory elements (e.g., 500aa and 500ba) connected to the same bit line (e.g., 100a).

[0090] According to one embodiment, the first word line structure 200a and the third word line structure 200c can be connected to a word line driver. Furthermore, the second word line structure 200b and the fourth word line structure 200d can be connected to another word line driver.

[0091] The word line driver connected to the first word line structure 200a and the third word line structure 200c can be called the first word line driver, while the word line driver connected to the second word line structure 200b and the fourth word line structure 200d can be called the second word line driver.

[0092] The first word line driver and the second word line driver can provide activation voltages to word lines respectively coupled to the first word line driver and the second word line driver. The activation voltages are provided to regions, such as the upper word line, included in each word line structure.

[0093] Figure 5 This is a diagram illustrating voltage fluctuations in a word line structure according to an embodiment of the present disclosure.

[0094] Reference Figure 4 The second letter structure WL2 (for example, Figure 4 200b) and the third word line structure WL3 (e.g. Figure 4 (200c) can be a word line structure arranged adjacent to each other.

[0095] Reference Figure 1 and Figure 5 Due to the activation voltage applied to the second word line structure WL2, voltage fluctuations may occur in the third word line structure WL3.

[0096] When an activation voltage is applied to the second word line structure WL2, voltage fluctuations may occur in the third word line structure WL3, which is adjacent to the second word line structure WL2.

[0097] When an activation voltage is applied to the second word line structure WL2, electrical interference may occur in the third word line structure WL3, which is adjacent to the second word line structure WL2. This electrical interference in the third word line structure WL3 may cause unexpected voltage fluctuations within the third word line structure WL3, which may lead to data loss in the memory cell.

[0098] In traditional word line structures, an upper word line may not be provided separately, and the activation voltage can be directly applied to the lower word line. Adjacent lower word lines can be arranged at the same horizontal height in the third direction (i.e., the Z-axis direction). Therefore, when the activation voltage is directly applied to the lower word line, significant voltage fluctuations may occur in adjacent word line structures (see...). Figure 5 (Bias voltage 2).

[0099] In contrast, word line structures (e.g., WL2 and WL3) according to embodiments of this disclosure can be configured such that the upper word lines included in each word line structure are spaced apart from each other in a third direction (i.e., the Z-axis direction). When the upper word lines to which activation voltages are directly applied are spaced apart from each other in a third direction, smaller voltage fluctuations occur in adjacent word line structures WL3 (see...). Figure 5 (Bias voltage 1).

[0100] As can be clearly seen from the above description, the semiconductor device according to the embodiments of this disclosure can reduce the boost effect caused by the voltage applied to adjacent word lines.

[0101] The word line structure according to the embodiments of this disclosure may include a lower word line, an upper word line, and a vertical connecting portion, and can quickly provide the activation voltage received in the upper word line to the lower word line.

[0102] The embodiments disclosed herein can provide a variety of effects that can be directly or indirectly understood through the aforementioned patent documents.

[0103] Those skilled in the art will understand that this disclosure can be implemented in other specific ways than those described herein. Furthermore, claims not expressly set forth in the appended claims may be combined as embodiments, or may be included as new claims through subsequent amendments after filing.

[0104] Although several exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments can be designed based on what is described and / or shown in this patent document.

Claims

1. A semiconductor device, comprising: Bit lines that extend in the first direction; The first character line structure extends in the second direction; An active region, one end of which contacts the bit line and extends upward in a third direction; as well as The back grille extends parallel to the first character line structure. The first character line structure includes: The first lower digit line extends parallel to the back grille; The first upper character line is spaced apart from the first lower character line in the direction of the third character line; and A vertical connecting portion that extends upward from the third party to connect the first lower character line to the first upper character line.

2. The semiconductor device according to claim 1, further comprising: A storage element that is in contact with the other end of the active region.

3. The semiconductor device according to claim 1, wherein, The first upper character line is made of a material with a resistance less than that of the first lower character line.

4. The semiconductor device according to claim 1, wherein, The vertical connecting portion comprises a material with a resistance less than that of the first lower letter line.

5. The semiconductor device according to claim 1, in, The second character line structure adjacent to the first character line structure in the first direction includes a second upper character line, and The first upper character line is at a different horizontal height from the second upper character line in the same direction.

6. The semiconductor device according to claim 1, in, The second character line structure adjacent to the first character line structure includes a second lower character line, and Wherein, the first lower character line is at the same horizontal height as the second lower character line in the same horizontal direction in the third direction.

7. The semiconductor device according to claim 1, wherein, The back gate is configured to be parallel to the side surfaces of a plurality of active regions that are repeatedly arranged along the second direction.

8. The semiconductor device according to claim 1, wherein, The first upper word line receives an activation voltage from the word line driver.

9. The semiconductor device according to claim 1, in, The second character line structure adjacent to the first character line structure in the first direction includes a second upper character line. Wherein, the first upper word line is connected to the first word line driver, and The second upper word line is connected to the second word line driver.

10. The semiconductor device according to claim 9, wherein, The first word line driver and the second word line driver respectively provide activation voltages to the first upper word line and the second upper word line, which are respectively connected to the first word line driver and the second word line driver.

11. The semiconductor device according to claim 1, wherein, The width of the first upper character line in the first direction is greater than the width of the first lower character line in the first direction.

12. The semiconductor device according to claim 1, wherein, The thickness of the first upper character line in the third direction is greater than the thickness of the first lower character line in the third direction.

13. A semiconductor device, comprising: Multiple lower-character lines are repeated in the first direction and extend in the second direction; Multiple upper character lines overlap with the multiple lower character lines in a third direction and extend in the second direction; Multiple vertical connecting parts connect the multiple lower character lines to the multiple upper character lines; Multiple active regions are repeatedly arranged parallel to the side surfaces of the multiple lower character lines and extend upward in the third region; as well as Multiple bit lines, which are in contact with the multiple active regions. Some of the multiple active regions are repeatedly arranged in the first direction and collectively contact one of the multiple bit lines.

14. The semiconductor device according to claim 13, further comprising: Multiple storage elements are connected to the multiple active regions, respectively.

15. The semiconductor device according to claim 13, wherein, Among the multiple upper character lines, the upper character lines that are adjacent to each other in the first direction are set at different horizontal heights in the third direction.

16. The semiconductor device according to claim 13, wherein, The multiple lower digit lines are set at the same horizontal height on the third side.

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