Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device disclosed herein includes: a substrate; word lines stacked on the substrate; a channel region disposed between the word lines; a first contact structure connected to one end of the channel region; a second contact structure connected to the other end of the channel region; a bit line in contact with the first contact structure; and an electrode structure in contact with the second contact structure, wherein the first contact structure includes multiple layers of two-dimensional semiconductor material stacked between the channel region and the bit lines, and the second contact structure includes multiple layers of two-dimensional semiconductor material stacked between the channel region and the electrode structure.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0046761, filed on April 10, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Some aspects of this disclosure provide semiconductor memory devices with improved performance and reliability. Background Technology

[0003] For traditional two-dimensional or planar semiconductor devices, the integration density depends primarily on the area occupied by a single memory cell, and is therefore greatly influenced by the level of fine patterning technology. However, the integration density of two-dimensional semiconductor devices, while improving, remains limited due to the extremely expensive equipment required for pattern miniaturization. Accordingly, three-dimensional semiconductor devices incorporating memory cells arranged in three dimensions have been proposed. Summary of the Invention

[0004] However, the aspects of this disclosure and the improvements provided are not limited to what is set forth herein. The above and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description of this disclosure given below.

[0005] According to some embodiments of the present disclosure, a semiconductor memory device includes: a substrate; word lines stacked on the substrate; a channel region disposed between the word lines; a first contact structure connected to one end of the channel region; a second contact structure connected to the other end of the channel region; a bit line in contact with the first contact structure; and an electrode structure in contact with the second contact structure, wherein the first contact structure includes multiple layers of two-dimensional semiconductor material stacked between the channel region and the bit lines, and the second contact structure includes multiple layers of two-dimensional semiconductor material stacked between the channel region and the electrode structure.

[0006] According to some embodiments of this disclosure, a semiconductor memory device includes: a substrate; word lines stacked on the substrate in a vertical direction; a channel region disposed between the word lines and including a single layer of two-dimensional semiconductor material; an insulating pattern disposed between the word lines in a vertical direction; a first contact structure connected to a first source / drain region of the channel region; a second contact structure connected to a second source / drain region of the channel region; a bit line extending in a vertical direction and connected to the first contact structure; and an electrode structure connected to the second contact structure, wherein the first contact structure is disposed between the channel region and the bit line and includes at least one layer of two-dimensional semiconductor material surrounding at least a portion of the first source / drain region; and the second contact structure is disposed between the channel region and the electrode structure and includes at least one layer of two-dimensional semiconductor material surrounding at least a portion of the second source / drain region.

[0007] According to some embodiments of this disclosure, a semiconductor memory device includes: a substrate; word lines extending on the substrate along a first horizontal direction parallel to the upper side of the substrate and spaced apart from each other along a second horizontal direction different from the first horizontal direction; a channel region disposed between the word lines along the second horizontal direction and including a single layer of two-dimensional semiconductor material; a first contact structure connected to a first region of the channel region; a second contact structure connected to a second region of the channel region; a bit line extending on the substrate along the second horizontal direction and connected to the first contact structure; and an electrode structure connected to the second contact structure, wherein the first contact structure is disposed between the first region and the bit line and includes a multilayer two-dimensional semiconductor material layer in contact with the first region; and the second contact structure is disposed between the second region and the electrode structure and includes a multilayer two-dimensional semiconductor material layer in contact with the second region.

[0008] Specific details of other embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0009] The above and other aspects and features of this disclosure will become clearer from the illustrative examples described in detail with reference to the accompanying drawings, in which:

[0010] Figure 1 This is a layout diagram showing an example of a semiconductor memory device;

[0011] Figure 2 This is a plan view showing an example of a semiconductor memory device;

[0012] Figure 3 It is along Figure 2 Example of a cross-sectional view taken by line A-A';

[0013] Figure 4 yes Figure 3 A magnified view of region P;

[0014] Figure 5 This is a diagram illustrating an example of a semiconductor memory device;

[0015] Figure 6 This is a plan view showing an example of a semiconductor memory device;

[0016] Figure 7 It is along Figure 6 Example of a cross-sectional view taken by line B-B';

[0017] Figure 8 This is a plan view showing an example of a semiconductor memory device;

[0018] Figure 9 It is along Figure 8Example of a cross-sectional view taken from line C-C';

[0019] Figures 10 to 16 This is a diagram illustrating an example of a method for manufacturing semiconductor memory devices;

[0020] Figures 17 to 21 This is a diagram illustrating an example of a method for manufacturing semiconductor memory devices;

[0021] Figures 22 to 27 This is a diagram illustrating an example of a method for manufacturing semiconductor memory devices. Detailed Implementation

[0022] Although terms such as first and second are used in this specification to describe various elements or components, it will be understood that these elements or components are not limited by these terms, which are used only as identifiers. These terms are only used to distinguish individual elements or components from other elements or components. Therefore, the first element or component mentioned below may also be referred to as the second element or component in the technical concept of this disclosure.

[0023] Figure 1 This is a layout diagram showing an example of a semiconductor memory device.

[0024] refer to Figure 1 The semiconductor memory device 1000 may include a cell array region (MCA) and a peripheral circuit region (PCA). In some embodiments, the MCA may be a region where memory cell transistors of a dynamic random access memory (DRAM) device are disposed, while the PCA may be a peripheral circuit region of the DRAM device. For example, the PCA may include peripheral circuit transistors for sending signals and / or power to the memory cell transistors included in the MCA. In some embodiments, the peripheral circuit transistors may be included in various circuits (e.g., circuitry of the PCA), such as command decoders, control logic, address buffers, row decoders, column decoders, sense amplifiers, and data input / output circuitry.

[0025] Figure 2 This is a plan view showing an example of a semiconductor memory device. Figure 3 It is along Figure 2 Example of a cross-sectional view taken by line A-A'. Figure 4 yes Figure 3 A magnified view of region P. For reference. Figure 2 schematically shown Figure 1 An example of a portion of the cell array region MCA.

[0026] refer to Figures 2 to 4The semiconductor memory device may include a first substrate 100, a stacked structure ST, a word line structure WLS, a bit line BL, an electrode structure CAP, a semiconductor film 20, a first contact structure CT1, a second contact structure CT2, and a spacer pattern SP.

[0027] The upper side of the first substrate 100 may be disposed in a plane formed by a first direction X1 and a second direction Y1. The upper side of the first substrate 100 may be perpendicular to a third direction Z1. In this specification, the first direction X1, the second direction Y1, and the third direction Z1 may intersect each other. The first direction X1, the second direction Y1, and the third direction Z1 may be substantially perpendicular to each other. In some embodiments, the first direction X1 may be referred to as a first horizontal direction, the second direction Y1 may be referred to as a second horizontal direction, and the third direction Z1 may be referred to as a vertical direction.

[0028] The first substrate 100 may be bulk silicon or silicon-on-insulator (SOI). The first substrate 100 may be a silicon substrate, or may include other materials, such as, but not limited to, silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In the following description, the first substrate 100 will be described as a substrate including silicon, but not limited thereto.

[0029] A stacked structure ST can be disposed on a first substrate 100. The stacked structure ST may include multiple word line structures WLS, multiple insulating patterns 60, and multiple semiconductor films 20. Multiple stacked structures ST can be stacked alternately and repeatedly on a third direction Z1.

[0030] The word line structure WLS may include word lines WL and a gate insulating film 50. For example, the gate insulating film 50 may be disposed between word lines WL and semiconductor films 20 that are adjacent to each other along the third direction Z1.

[0031] The word lines WL can be conductive patterns (e.g., metallic conductive lines) stacked on the first substrate 100 along a third direction Z1. Each word line WL can extend in a first direction X1. From a planar viewpoint, each word line WL can be spaced apart in a second direction Y1. From a vertical viewpoint, adjacent word lines WL can be spaced apart in a third direction Z1.

[0032] Word lines (WL) may include conductive materials. As an example, word lines (WL) may include, but are not limited to, at least one of the following: doped semiconductor materials (doped silicon, doped silicon germanium, doped germanium, etc.), conductive metal nitrides (titanium nitride, tantalum nitride, etc.), metals (tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0033] The gate insulating film 50 may include at least one of a high dielectric constant insulating film, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. As an example, the high dielectric constant material may include at least one of the following: for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0034] An insulating pattern 60 can be disposed between adjacent word lines WL along the third direction Z1. The insulating pattern 60 can electrically isolate the word lines WL. Multiple insulating patterns 60 and multiple word line structures WLS can be stacked alternately and repeatedly along the third direction Z1.

[0035] The insulating pattern 60 may include an insulating material. The insulating pattern 60 may include at least one of the following: a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, a carbon nitride film, and a carbon oxynitride film. For example, the insulating pattern 60 may include a silicon oxide film. Viewed from a planar perspective, for example along a vertical direction, the word line WL, the gate insulating film 50, the insulating pattern 60, and the channel region CH, as described below, may overlap each other.

[0036] Bit lines BL can be conductive patterns (e.g., metallic conductive lines) that extend vertically (i.e., in the third direction Z1) from the upper side of the first substrate 100. Bit lines BL can be arranged in the second direction Y1. Adjacent bit lines BL can be spaced apart in the second direction Y1.

[0037] The gate of the memory cell transistor can be connected to the word line WL, and the first source / drain region of the memory cell transistor can be connected to the bit line BL. The second source / drain region of the memory cell transistor can be connected to the electrode structure CAP. The second source / drain region of the memory cell transistor can be connected to the storage electrode of the capacitor.

[0038] The electrode structure CAP can be connected to the second source / drain region SD2. In some embodiments, the electrode structure CAP can be a capacitor. The electrode structure CAP can include a storage electrode SE, a plate electrode PE, and a capacitor dielectric film CIL. The electrode structure CAP can share the capacitor dielectric film CIL and the plate electrode PE. For example, multiple storage electrodes SE can be provided connected to each second source / drain region SD2, and a capacitor dielectric film CIL can cover the surface of each storage electrode SE. A plate electrode PE can cover the capacitor dielectric film CIL. Each electrode structure CAP can be defined by a storage electrode SE.

[0039] The plate electrode PE may include, but is not limited to, doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), metals (e.g., ruthenium, iridium, titanium, niobium, tungsten, cobalt, molybdenum, or tantalum), and conductive metal oxides (e.g., iridium oxide or niobium oxide). As an example, the plate electrode PE may include conductive metal nitrides, metals, and conductive metal oxides. The conductive metal nitrides, metals, and conductive metal oxides may be contained within a metal conductive film.

[0040] The capacitor dielectric film (CIL) may include, for example, high dielectric constant materials (e.g., hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof). In some embodiments, the capacitor dielectric film (CIL) may include a stacked film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked sequentially. In some embodiments, the capacitor dielectric film (CIL) may include hafnium (Hf).

[0041] Semiconductor films 20 can be stacked on a third direction Z1. For example, word lines WL can be disposed between adjacent semiconductor films 20 along the third direction Z1. Adjacent word lines WL on the third direction Z1 can be spaced apart from gate insulating films 50, with semiconductor films 20 interposed therebetween. Semiconductor films 20 can also be disposed between adjacent gate insulating films 50 on the third direction Z1.

[0042] The semiconductor films 20 may be spaced apart from each other in the first direction X1 and the third direction Z1. The semiconductor films 20 may extend in the second direction Y1. For example, the semiconductor films 20 may be arranged three-dimensionally on the first substrate 100.

[0043] The semiconductor film 20 may penetrate or extend within the word lines WL in the second direction Y2. Each word line WL may have a structure surrounding a channel region CH of the semiconductor film 20 (e.g., a full-around gate structure). A gate insulating film 50 may be disposed between the semiconductor film 20 and the word lines WL. The gate insulating film 50 may be in contact with the semiconductor film 20. The word lines WL may be disposed between the gate insulating film 50 and the insulating pattern 60. The gate insulating film 50 may be in contact with the word lines WL, but in some embodiments, it may not be in contact with the insulating pattern 60.

[0044] The semiconductor film 20 may include a first source / drain region SD1, a channel region CH, and a second source / drain region SD2.

[0045] The first source / drain region SD1 can be disposed on one side of the channel region CH. The second source / drain region SD2 can be disposed on the other side of the channel region CH. The first source / drain region SD1 and the second source / drain region SD2 can be symmetrical to each other, with the channel region CH located between them. Each of the first source / drain region SD1 and the second source / drain region SD2 can be, but is not limited to, a semiconductor material doped with impurities.

[0046] The first source / drain region SD1 can be connected to the bit line BL. The second source / drain region SD2 can be connected to the electrode structure CAP. For example, the second source / drain region SD2 can be connected to the storage electrode SE of the electrode structure CAP. In some embodiments, the second contact structure CT2 can be provided as the storage electrode SE, but the technical concept of this disclosure is not limited thereto. The second contact structure CT2 can contact the capacitor dielectric film CIL.

[0047] The first source / drain region SD1 may include: a first upper side US1, extending along the second direction Y1 toward the bit line BL; a first lower side BS1, opposite to the first upper side; and a first sidewall SW1, connecting the first upper side US1 and the first lower side BS1.

[0048] The second source / drain region SD2 may include: a second upper side US2 extending toward the plate electrode PE along the second direction Y1; a second lower side BS2 opposite to the second upper side US2; and a second sidewall SW2 connecting the second upper side US2 and the second lower side BS2.

[0049] The first contact structure CT1 can contact each of the first upper side US1, the first sidewall SW1, and the first lower side BS1. The first contact structure CT1 can surround each of the first upper side US1, the first sidewall SW1, and the first lower side BS1. The second contact structure CT2 can contact each of the second upper side US2, the second sidewall SW2, and the second lower side BS2. The second contact structure CT2 can surround each of the second upper side US2, the second sidewall SW2, and the second lower side BS2.

[0050] The first contact structure CT1 may include at least one two-dimensional semiconductor material layer stacked between the channel region CH and the bit line BL. The first contact structure CT1 may be in contact with one end of the channel region CH. In some embodiments, one end of the channel region CH may also be referred to as the first source / drain region SD1.

[0051] The second contact structure CT2 may include at least one layer of two-dimensional semiconductor material stacked between the channel region CH and the electrode structure CAP. The second contact structure CT2 may contact the other end of the channel region CH. In some embodiments, the other end of the channel region CH may also be referred to as the second source / drain region SD2.

[0052] The semiconductor film 20 may include a two-dimensional material having a two-dimensional crystal structure. This two-dimensional material may have a single-layer or multi-layered structure. Each layer constituting the two-dimensional material may have an atomic-level thickness. For example, the semiconductor film 20 may include graphene, TMD (transition metal dichalcogenide), black phosphorus, or hBN (hexagonal boron nitride).

[0053] Transition metal compounds (TMDs) can include, for example, a transition metal selected from Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, and Re, and a chalcogenide selected from S, Se, and Te. A TMD can be represented, for example, MX2, where M represents a transition metal and X represents a chalcogenide. For example, M can be Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, etc., and X can be S, Se, Te, etc. Therefore, for example, a TMD can include MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, ReSe2, etc. Alternatively, a TMD may not be represented as MX2. In this case, for example, a TMD can include CuS, which is a compound of the transition metal Cu and the chalcogenide S. On the other hand, a TMD can be a chalcogenide material including a non-transition metal. Non-transition metals can include, for example, Ga, In, Sn, Ge, Pb, etc. In this context, TMD can include compounds of elements such as Ga, In, Sn, Ge, and Pb with chalcogen elements such as S, Se, and Te. For example, TMD can include SnSe2, GaS, GaSe, GaTe, GeSe, In2Se3, InSnS2, etc.

[0054] The channel region CH may include a single layer of two-dimensional semiconductor material (two-dimensional semiconductor material monolayer). In this case, the two-dimensional semiconductor material layer included in the channel region CH may be made of a single material. However, the channel region CH may include, but is not limited to, two-dimensional semiconductor material layers composed of different materials.

[0055] The first contact structure CT1 may include at least one layer of two-dimensional semiconductor material. The first contact structure CT1 may include a multilayer structure composed of or formed of two-dimensional semiconductor material layers. The number of two-dimensional semiconductor material layers included in the first contact structure CT1 may be (but is not limited to) 2 or more, and 10 or fewer. For example, the first contact structure CT1 may include at least one of MoS2, MoSe2, WS2, and WSe2.

[0056] The second contact structure CT2 may include at least one layer of two-dimensional semiconductor material. The second contact structure CT2 may include a multilayer structure composed of two-dimensional semiconductor material layers. The number of two-dimensional material layers included in the second contact structure CT2 may be (but is not limited to) two or more, and ten or fewer. For example, the second contact structure CT2 may include at least one of MoS2, MoSe2, WS2, and WSe2.

[0057] For example, the two-dimensional semiconductor material layer of the first contact structure CT1 and the two-dimensional semiconductor material layer of the second contact structure CT2 may contain the same material as each other. As another example, the two-dimensional semiconductor material layer of the first contact structure CT1 and the two-dimensional semiconductor material layer of the second contact structure CT2 may contain different materials as each other.

[0058] For example, the first contact structure CT1 may include a two-dimensional semiconductor material layer composed of different materials. The second contact structure CT2 may include a two-dimensional semiconductor material layer composed of different materials.

[0059] As another example, the first contact structure CT1 may include a multilayer two-dimensional semiconductor material layer composed of the same material as each other. The second contact structure CT2 may include a multilayer two-dimensional semiconductor material layer composed of the same material as each other.

[0060] The spacer pattern SP can be disposed between the bit line BL and the word line WL, and between the electrode structure CAP and the word line WL. The spacer pattern SP can include a first spacer pattern 71 and a second spacer pattern 72. The gate insulating film 50, the word line WL, and the insulating pattern 60 can be disposed between the first spacer pattern 71 and the second spacer pattern 72.

[0061] The first spacer pattern 71 may extend in the first direction X1. The first spacer pattern 71 may be disposed between the bit line BL and the word line WL along the second direction Y1. The first spacer pattern 71 may electrically separate the bit line BL and the word line WL. The first spacer pattern 71 may contact a portion of the semiconductor film 20. The first spacer pattern 71 may directly contact the gate insulating film 50, the word line WL, and the insulating pattern 60. The first spacer pattern 71 may be disposed on one sidewall of the gate insulating film 50, one sidewall of each word line WL, and one sidewall of the insulating pattern 60. The first spacer pattern 71 may directly contact the first source / drain region SD1, but its arrangement is not limited thereto.

[0062] The second spacer pattern 72 can be disposed between the electrode structure CAP and the word line WL. The second spacer pattern 72 can extend in the first direction X1. The second spacer pattern 72 can be spaced apart from the first spacer pattern 71 in the second direction Y1. The second spacer pattern 72 can electrically separate the electrode structure CAP from the word line WL. The second spacer pattern 72 can contact a portion of the semiconductor film 20. The second spacer pattern 72 can directly contact the gate insulating film 50, the word line WL, and the insulating pattern 60. The second spacer pattern 72 can be disposed on the other sidewall of the gate insulating film 50, the other sidewall of each word line WL, and the other sidewall of the insulating pattern 60. The second spacer pattern 72 can directly contact the second source / drain region SD2, but its arrangement is not limited thereto.

[0063] The spacer pattern SP may include at least one of the following: silicon oxide film, silicon nitride film, silicon oxynitride film, carbon-containing silicon oxide film, carbon-containing silicon nitride film, and carbon-containing silicon oxynitride film. As an example, the spacer pattern SP may be formed from a silicon nitride film.

[0064] The semiconductor memory device may also include a lower protective pattern 120 and a vertical insulating pattern 130.

[0065] The lower protective pattern 120 may be disposed on the first substrate 100. The lower protective pattern 120 may be disposed between the first substrate 100 and the bit line BL. The lower protective pattern 120 may be disposed between the word lines WL closest to the first substrate 100. The lower protective pattern 120 may include at least one of the following: a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, a carbon nitride film, and a carbon oxynitride film. As an example, the lower protective pattern 120 may be formed of a silicon nitride film.

[0066] A vertical insulating pattern 130 may be disposed on the lower protective pattern 120. The vertical insulating pattern 130 may be disposed between bit lines BL. The vertical insulating pattern 130 may extend along a third direction Z1 on the lower protective pattern 120. The vertical insulating pattern 130 may cover the sidewalls of the bit lines BL. The vertical insulating pattern 130 may be made of at least one insulating material selected from silicon oxide and silicon nitride.

[0067] The semiconductor memory device may also include an upper insulating film formed on the stacked structure ST. For example, the upper insulating film may be disposed on the semiconductor film 20 located on top of the stacked structure ST, but is not limited thereto. Although the semiconductor memory device is shown as having eight semiconductor films 20 stacked on a third direction Z1, the number of films is not limited thereto. For example, the number of stacked semiconductor films 20 may be more than eight.

[0068] Figure 5 This illustrates another example of a semiconductor memory device (e.g., with...). Figure 4(The diagram corresponds to another example). For ease of explanation, brief descriptions or omissions will be used. Figures 1 to 4 The repeated parts of the description, and Figures 1 to 4 The description also applies to, or similarly applies to, other than, other applications. Figure 5 The corresponding elements, unless the context otherwise indicates or implies.

[0069] refer to Figure 5 The first contact structure CT1 of the semiconductor memory device may include: a first contact film CT1a in contact with the first source / drain region SD1, and a second contact film CT1b on the first contact film CT1a and in contact with the bit line BL. The second contact structure CT2 includes: a third contact film CT2a in contact with the second source / drain region SD2, and a fourth contact film CT2b on the third contact film CT2a and in contact with the electrode structure CAP.

[0070] Figure 6 This is a plan view showing an example of a semiconductor memory device. Figure 7 It is along Figure 6 Example of a cross-sectional view taken from line B-B'. For ease of explanation, brief descriptions or omissions will be used. Figures 1 to 5 The repeated parts of the description.

[0071] refer to Figure 6 and Figure 7 The semiconductor memory device may include a second substrate 200, a bit line BL, a word line WL, an active region ACT, a first contact structure 210, an insulating pillar 260, and a second contact structure 270.

[0072] The second substrate 200 may be a silicon substrate, or may include other materials, such as, but not limited to, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0073] The lower insulating layer 201 and the bit line BL can be sequentially stacked on the second substrate 200. The lower insulating layer 201 may include at least one of the following: a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, a carbon nitride film, and a carbon oxynitride film. As an example, the lower insulating layer 201 may include a silicon oxide film.

[0074] Bit lines BL can be disposed on the lower insulating layer 201. Bit lines BL can be conductive patterns (e.g., metallic conductive lines) extending along a second direction Y2 on the second substrate 200. From a planar view, each bit line BL can be spaced apart in a first direction X2.

[0075] The word lines WL can be conductive patterns (e.g., metallic conductive lines) stacked on the second substrate 200 along a third direction Z2. Each word line WL can extend in a first direction X2. From a planar view, each word line WL can be spaced apart in a second direction Y2. Adjacent word lines WL in the second direction Y2 can be positioned at the same location in the third direction Z2.

[0076] The active region ACT can be positioned between word lines WL along the second direction Y2. The active region ACT can be... Figure 7 Corresponding to the channel region 250. The channel region 250 is disposed between word lines WL along the second direction Y2 and may include a single layer of two-dimensional semiconductor material. In some embodiments, a gate insulating film may be disposed between the word lines WL and the channel region 250.

[0077] The first contact structure 210 may be connected to a first region of the channel region 250. The first contact structure 210 may contact the first region of the channel region 250. The bit line BL may be connected to the first contact structure 210. The bit line BL may contact the first contact structure 210. The first contact structure 210 is disposed between the first region and the bit line BL, and may include at least one two-dimensional semiconductor material layer in contact with the first region. The first contact structure 210 may include a multilayer structure of two-dimensional semiconductor material layers, each layer of which extends along a second direction Y2 on the bit line BL.

[0078] The first contact structure 210 may include a first contact film 211, a second contact film 212, and a third contact film 213 sequentially stacked on the bit line BL. Each of the first contact film 211, the second contact film 212, and the third contact film 213 may include the aforementioned two-dimensional semiconductor material layer. Although the number of contact film layers included in the first contact structure 210 is shown as three layers, its number is not limited to this. The number of contact film layers included in the first contact structure 210 may be at least one or more layers. Each of the first contact film 211, the second contact film 212, and the third contact film 213 included in the first contact structure 210 may include the same two-dimensional semiconductor material, or may include two-dimensional semiconductor materials that are different from each other.

[0079] The first molded insulating film 220 and the third molded insulating film 240 may be alternately stacked with the word line WL in the third direction Z2. The word line WL may be disposed between the first molded insulating film 220 and the third molded insulating film 240. The first molded insulating film 220 may be disposed between the first contact structure 210 and the word line WL in the third direction Z2. The third molded insulating film 240 may be disposed between the word line WL and the second contact structure 270 in the third direction Z2. For example, the first molded insulating film 220 may include a nitride-based material, and the third molded insulating film 240 may include a nitride-based material.

[0080] Insulating posts 260 may be disposed between word lines WL along the second direction Y2. Insulating posts 260 may be disposed between first molded insulating films 220 along the second direction Y2. Insulating posts 260 may be disposed between at least a portion of third molded insulating films 240 along the second direction Y2. Insulating posts 260 may include at least one of the following: silicon oxide film, silicon nitride film, silicon oxynitride film, carbon-containing silicon oxide film, silicon carbonitride film, and silicon carbonitride film. For example, insulating posts 260 may include silicon oxide film.

[0081] The channel region 250 may extend along the upper side and part of the sidewall of the third molded insulating film 240 and the sidewall of the insulating post 260 on the upper side of the first contact structure 210.

[0082] The second contact structure 270 can be connected to the second region of the channel region 250. The second contact structure 270 can contact the second region of the channel region 250. The electrode structure CAP can be connected to the second contact structure 270. The storage electrode SE of the electrode structure CAP can contact the second contact structure 270. The second contact structure 270 can be disposed between the second region and the electrode structure CAP, and can include at least one two-dimensional semiconductor material layer in contact with the second region. The second contact structure 270 can include a multilayer two-dimensional semiconductor material layer extending over the second region along the upper side and sidewalls of the third molded insulating film 240.

[0083] The second contact structure 270 may extend along the upper side and sidewalls of the third molded insulating film 240 on the surface of the second region of the channel region 250. The second contact structure 270 may include a fourth contact film 271 and a fifth contact film 272, which are stacked sequentially on the upper side and part of the sidewalls of the channel region 250 and on the upper side of the insulating pillar 260. Each of the fourth contact film 271 and the fifth contact film 272 may include the aforementioned two-dimensional semiconductor material layer. Although the number of contact film layers included in the second contact structure 270 is shown as two layers, its number is not limited to this. The number of contact film layers included in the second contact structure 270 may be at least one or more layers. Each of the fourth contact film 271 and the fifth contact film 272 included in the second contact structure 270 may include the same two-dimensional semiconductor material, or may include two-dimensional semiconductor materials different from each other. The second contact structure 270 may include a two-dimensional semiconductor material different from that of the first contact structure 210, or may include the same two-dimensional semiconductor material.

[0084] The storage electrode SE and plate electrode PE can include, but are not limited to, doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, niobium nitride, tungsten nitride, etc.), metals (e.g., ruthenium, iridium, titanium, niobium, tungsten, cobalt, molybdenum, tantalum, etc.), and conductive metal oxides (e.g., iridium oxide, niobium oxide, etc.). As an example, the plate electrode PE can include conductive metal nitrides, metals, and conductive metal oxides. The conductive metal nitrides, metals, and conductive metal oxides can be contained within a conductive metal film.

[0085] The capacitor dielectric film (CIL) may include, for example, high dielectric constant materials (e.g., hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof). In some embodiments, the capacitor dielectric film (CIL) may include a stacked film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked sequentially. In some embodiments, the capacitor dielectric film (CIL) may include hafnium (Hf).

[0086] Figure 8 This is a plan view showing an example of a semiconductor memory device. Figure 9 It is along Figure 8 Example of a cross-sectional view taken from line C-C'. For ease of explanation, brief descriptions or omissions will be used. Figures 1 to 7 The repeated parts of the description.

[0087] refer to Figure 8 and Figure 9 The semiconductor memory device may include a third substrate 300, bit lines BL, word lines WL, back gate BG, active region ACT, first contact structure 310, first molded insulating film 340 and second molded insulating film 350.

[0088] The third substrate 300 may be a silicon substrate, or may include other materials, such as, but not limited to, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0089] The lower insulating layer 301 and the bit line BL can be stacked sequentially on the third substrate 300. The lower insulating layer 301 may include at least one of the following: a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, a carbon nitride film, and a carbon oxynitride film. As an example, the lower insulating layer 301 may include a silicon oxide film.

[0090] Bit lines BL can be disposed on the lower insulating layer 301. Bit lines BL can be conductive patterns (e.g., metallic conductive lines) extending along the second direction Y3 on the third substrate 300. From a planar view, each bit line BL can be spaced apart in the first direction X3.

[0091] Word lines WL can be conductive patterns (e.g., metallic conductive lines) stacked on a third substrate 300 along a third direction Z3. Each word line WL can extend in a first direction X3. From a planar view, each word line WL can be spaced apart in a second direction Y3. Word lines WL adjacent to each other in the second direction Y3 can be positioned at the same location in the third direction Z3.

[0092] The back gate (BG) can be disposed between word lines (WL) along the second direction Y3. The back gate (BG) includes a conductive material and may include at least one of the following: a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a two-dimensional material, and a metal.

[0093] The active region ACT can be positioned between word lines WL along the second direction Y3. The active region ACT can be... Figure 9 Corresponding to the channel region 320. The channel region 320 is disposed between word lines WL along the second direction Y3 and may include a single layer of two-dimensional semiconductor material. The channel region 320 may protrude a first length T1 from the upper side of the second molded insulating film 350, which will be described below, along the third direction Z3.

[0094] The gate insulating film 330 can be disposed between the word line WL and the channel region 320. The gate insulating film 330 can be disposed on each sidewall of the channel region 320.

[0095] The first contact structure 310 may be connected to a first region of the channel region 320. The first contact structure 310 may contact the first region of the channel region 320. The bit line BL may be connected to the first contact structure 310. The bit line BL may contact the first contact structure 310. The first contact structure 310 is disposed between the first region and the bit line BL, and may include at least one two-dimensional semiconductor material layer in contact with the first region. The first contact structure 310 may include a multilayer structure of two-dimensional semiconductor material layers, each layer of which extends along a second direction Y3 on the bit line BL.

[0096] The first contact structure 310 may include a first contact film 311, a second contact film 312, and a third contact film 313 sequentially stacked on the bit line BL. Each of the first contact film 311, the second contact film 312, and the third contact film 313 may include the aforementioned two-dimensional semiconductor material layer. Although the number of contact film layers included in the first contact structure 310 is shown as three layers, its number is not limited to this. The number of contact film layers included in the first contact structure 310 may be at least one or more layers. Each of the first contact film 311, the second contact film 312, and the third contact film 313 included in the first contact structure 310 may include the same two-dimensional semiconductor material, or may include different two-dimensional semiconductor materials from each other.

[0097] The first molded insulating film 340 may be disposed on the first contact structure 310. For example, the first molded insulating film 340 may include a nitride-based material.

[0098] The second molded insulating film 350 may be disposed on the word line WL and the back gate BG. For example, the second molded insulating film 350 may comprise a nitride-based material. The second molded insulating film 350 may be in contact with the upper portion of the channel region 320.

[0099] The second contact structure 360 ​​can be connected to the second region of the channel region 320. The second contact structure 360 ​​can contact the second region of the channel region 320. The electrode structure CAP can be connected to the second contact structure 360. The storage electrode SE of the electrode structure CAP can contact the second contact structure 360. The second contact structure 360 ​​can be disposed between the second region and the electrode structure CAP, and can include at least one two-dimensional semiconductor material layer in contact with the second region. The second contact structure 360 ​​can include at least one two-dimensional semiconductor material layer extending along the upper side of the second molded insulating film 350 over the second region.

[0100] The second contact structure 360 ​​may cover the upper portion of the channel region 320 exposed on the second molded insulating film 350. The second contact structure 360 ​​may include a multilayer structure of two-dimensional semiconductor material layers extending along the surface of the channel region 320. Although the number of contact film layers included in the second contact structure 360 ​​is shown as one layer, its number is not limited thereto. The number of contact film layers included in the second contact structure 360 ​​may be at least one or more layers. When the contact films included in the second contact structure 360 ​​form a multilayer structure, each contact film may include the same two-dimensional semiconductor material, or may include different two-dimensional semiconductor materials from each other.

[0101] Figures 10 to 16 This illustrates the manufacture of semiconductor memory devices (e.g., such as...). Figures 1 to 5 The diagram illustrates an example of a method using the described device. For ease of explanation, brief descriptions or omissions will be used. Figures 1 to 5 The repeated parts of the description. For reference. Figures 10 to 16 yes Figure 3 The graph of region Q in the diagram.

[0102] First, refer to Figure 10 A first substrate 100 may be provided. A molded structure MS may be formed on the first substrate 100.

[0103] The molded structure MS may include alternately stacked sacrificial films 10 and semiconductor films 20. For example, sacrificial films 10 may be formed between adjacent semiconductor films 20 in the third direction Z1, and semiconductor films 20 may be formed between adjacent sacrificial films 10 in the third direction Z1. The thicknesses of the sacrificial films 10 and semiconductor films 20 are not limited to those shown in the figures.

[0104] The sacrificial film 10 can be formed of a material that is etch-selective to the semiconductor film 20. For example, the sacrificial film 10 can be formed of at least one of silicon germanium, silicon oxide, silicon nitride, and silicon oxynitride. The semiconductor film 20 can be formed of the two-dimensional material described above.

[0105] Subsequently, a first trench TR1 penetrating the molded structure MS can be formed. The first trench TR1 can expose the sidewalls of the sacrificial film 10 and the semiconductor film 20. Although not specifically shown, the formation of the first trench TR1 may include forming a mask pattern on the molded structure MS having an opening corresponding to the first trench TR1, and using the mask pattern as an etching mask to etch the molded structure MS. The first trench TR1 can expose the upper side of the first substrate 100, and the upper side of the first substrate 100 located below the first trench TR1 may be recessed during the etching process due to over-etching, thereby forming a recessed region.

[0106] refer to Figure 11 A portion of the sacrificial film 10 exposed by the first trench TR1 can be removed. A portion of the sacrificial film 10 can be removed horizontally, thereby forming a first groove R1 on the semiconductor film 20. The first groove R1 can expose a portion of the upper and lower sides of the semiconductor film 20 adjacent to each other in the third direction Z1, as well as the sidewalls of the remaining sacrificial film 10 after removal. The formation of the first groove R1 may include an etching process of the sacrificial film 10, which has etching selectivity for both the first substrate 100 and the semiconductor film 20.

[0107] refer to Figure 12 A first interlayer insulating film 30 can be formed inside the first groove R1. The first interlayer insulating film 30 can be formed on a portion of the upper side and a portion of the lower side of the semiconductor film 20 exposed by the first groove R1, and on the sidewalls of the sacrificial film 10. The first interlayer insulating film 30 can be formed between adjacent semiconductor films 20 along the third direction Z1. Each interlayer insulating film 30 can be formed at a height equal to the height of each sacrificial film 10 in the third direction Z1. The first interlayer insulating film 30 can include an insulating material. The first interlayer insulating film 30 can include at least one of the following: silicon oxide film, silicon nitride film, silicon oxynitride film, carbon-containing silicon oxide film, carbon nitride film, and carbon oxynitride film. As an example, the first interlayer insulating film 30 can include a silicon oxide film.

[0108] refer to Figure 13 The remaining sacrificial film 10 can be removed. Each sacrificial film 10 can be removed horizontally to form a second groove R2 on the semiconductor film 20. The second groove R2 can expose other portions of the upper and lower sides of the semiconductor films 20 adjacent to each other along the third direction Z1, as well as a sidewall of the first interlayer insulating film 30. The formation of the second groove R2 may include an etching process of the sacrificial film 10, which has etching selectivity for the first substrate 100, the semiconductor film 20, and the interlayer insulating film 30.

[0109] refer to Figure 14 A gate insulating film 50 can be formed in the second groove R2, word lines WL can be formed between the gate insulating films 50, and a word line structure WLS can be formed. The word line structure WLS can be formed between adjacent semiconductor films 20 along the third direction Z1. Subsequently, a horizontal etching process can be performed on the word line structure WLS. The space formed after the etching process can be filled with an insulating material. As a result, an insulating pattern 60 can be formed between adjacent word line structures WLS along the third direction Z1, and a second interlayer insulating film 70 can be formed on the sidewalls of the word line structure WLS. The insulating pattern 60 and the second interlayer insulating film 70 can include at least one of the following: silicon oxide film, silicon nitride film, silicon oxynitride film, carbon-containing silicon oxide film, silicon carbon nitride film, and silicon carbon oxynitride film. As an example, the insulating pattern 60 and the second interlayer insulating film 70 can include a silicon oxide film.

[0110] refer to Figure 15 The spacer pattern SP can be formed by removing a portion of the first interlayer insulating film 30 and the second interlayer insulating film 70. Each of the third groove R3 and the fourth groove R4 can be formed in the space formed by removing a portion of the first interlayer insulating film 30 and the second interlayer insulating film 70. Only a portion of the first interlayer insulating film 30 and the second interlayer insulating film 70 can be removed to form each of the first spacer pattern 71 and the second spacer pattern 72. The third groove R3 exposes a portion of the upper and lower sides of the semiconductor films 20 adjacent to each other along the third direction Z1, as well as the sidewalls of the first spacer pattern 71. The fourth groove R4 can expose the remaining portions of the upper and lower sides of the semiconductor films 20 adjacent to each other along the third direction Z1, as well as the sidewalls of the second spacer pattern 72. The spacer pattern SP can be formed on each of the upper and lower portions of the semiconductor film 20. The first spacer pattern 71 and the second spacer pattern 72 can be formed on the sidewalls of the word line structure WLS and the insulating pattern 60.

[0111] refer to Figure 16A two-dimensional semiconductor material layer 80 can be formed on one end of the semiconductor film 20, the other end of the semiconductor film 20, and the sidewalls of the spacer pattern SP. The two-dimensional semiconductor material layer 80 can be formed around each of the upper side, the sidewall of one end of the semiconductor film 20, and the lower side of one end of the semiconductor film 20. Similarly, the two-dimensional semiconductor material layer 80 can be formed around each of the upper side, the sidewall of the other end of the semiconductor film 20, and the lower side of the other end of the semiconductor film 20.

[0112] The two-dimensional semiconductor material layer 80 may include the aforementioned two-dimensional semiconductor material. The two-dimensional semiconductor material layer 80 may be formed by, for example, but not limited to, atomic layer deposition (ALD) processes. Multiple two-dimensional semiconductor material layers 80 may be included to form a multilayer structure.

[0113] Next, refer to Figure 3 At least a portion of the two-dimensional semiconductor material layer 80 on the spacer pattern SP can be removed. The two-dimensional semiconductor material layer 80 can be formed only around one end of the semiconductor film 20 and the other end of the semiconductor film 20.

[0114] Subsequently, a bit line BL can be formed at one end of the semiconductor film 20. The bit line BL can be in direct contact with the two-dimensional semiconductor material layer 80. The bit line BL can be in direct contact with the first spacer pattern 71. An electrode structure CAP can be formed at the other end of the semiconductor film 20. A capacitor dielectric film CIL can be conformally formed along the other end of the semiconductor film 20 and the second spacer pattern 72. The two-dimensional semiconductor material layer 80 can be in contact with the capacitor dielectric film CIL of the electrode structure CAP. For example, the two-dimensional semiconductor material layer 80 at the other end of the semiconductor film 20 can be used as the storage electrode SE of the electrode structure CAP, but this configuration is not limited to this.

[0115] Figures 17 to 21 This illustrates the fabrication of an example semiconductor memory device (e.g., reference). Figure 6 and Figure 7 A diagram illustrating a method for describing a semiconductor memory device. For ease of explanation, brief descriptions or omissions will be used in conjunction with the methods described above. Figures 6 to 7 The repeated parts of the description. For reference. Figures 17 to 21 It shows Figure 7 The diagram is a schematic diagram.

[0116] refer to Figure 17 A lower insulating layer 201 and a bit line BL can be sequentially formed on the second substrate 200.

[0117] The first contact structure 210 may be formed on the bit line BL. The first contact structure 210 may include a first contact film 211, a second contact film 212, and a third contact film 213 sequentially stacked on the bit line BL. Each of the first contact film 211, the second contact film 212, and the third contact film 213 may include the aforementioned two-dimensional semiconductor material layer. Although the number of contact film layers included in the first contact structure 210 is shown as three, its number is not limited to this. The number of contact film layers included in the first contact structure 210 may be at least one or more layers. Each of the first contact film 211, the second contact film 212, and the third contact film 213 included in the first contact structure 210 may include the same two-dimensional semiconductor material, or may include different two-dimensional semiconductor materials. In some embodiments, the first contact structure 210 may be referred to as the first contact structure.

[0118] A first molded insulating film 220, a second molded insulating film 230, and a third molded insulating film 240 may be formed on the first contact structure 210. For example, the first molded insulating film 220 may include a nitride-based material, the second molded insulating film 230 may include an oxide-based material, and the third molded insulating film 240 may include a nitride-based material.

[0119] refer to Figure 18 A portion of the first molded insulating film 220, the second molded insulating film 230, and the third molded insulating film 240 can be removed to form a first groove RC1 within the first molded insulating film 220, the second molded insulating film 230, and the third molded insulating film 240. The first groove RC1 can extend in the third direction Z2 within the first molded insulating film 220, the second molded insulating film 230, and the third molded insulating film 240 to expose the upper side of the first contact structure 210.

[0120] Subsequently, a channel region 250 can be formed inside the first groove RC1. The channel region 250 can be formed on the upper side of the third molded insulating film 240 and on the sidewalls and bottom side of the first groove RC1. The channel region 250 can contact the upper side of the first contact structure 210. The channel region 250 can include the two-dimensional semiconductor material described above. The channel region 250 can be formed by, for example, but not limited to, atomic layer deposition (ALD) processes.

[0121] refer to Figure 19An insulating post 260 can be formed on the channel region 250 to fill the interior of the first groove RC1. The insulating post 260 can extend within the first groove RC1 in a third direction Z2. The insulating post 260 can contact the channel region 250. The insulating post 260 can include at least one of the following: a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, a carbon nitride film, and a carbon oxynitride film. As an example, the insulating post 260 can include a silicon oxide film. A planarization process can be performed on the upper side of the insulating post 260 and the upper side of the channel region 250. Therefore, in some embodiments, the upper side of the insulating post 260 and the upper side of the channel region 250 can be located on the same plane.

[0122] refer to Figure 20 The second molded insulating film 230 is removed along a horizontal direction (e.g., the second direction Y2), and word lines WL are formed in the region where the second molded insulating film 230 has been removed. Word lines WL may be located between the first molded insulating film 220 and the third molded insulating film 240 along a third direction Z2. Insulating pillars 260 may be located between word lines WL along the second direction Y2. Gate insulating film may be located between word lines WL and channel region 250.

[0123] refer to Figure 21 A portion of the upper part of the insulating post 260 can be removed. Therefore, the upper side of the insulating post 260 can be located below the upper side of the channel region 250. A second contact structure 270 can be formed in the region where the upper portion of the insulating post 260 is removed. The second contact structure 270 can be formed on the upper side and part of the side surface of the channel region 250, as well as on the upper side of the insulating post 260.

[0124] The second contact structure 270 may include a fourth contact film 271 and a fifth contact film 272, which are stacked sequentially on the upper side and part of the side of the channel region 250 and on the upper side of the insulating pillar 260. Each of the fourth contact film 271 and the fifth contact film 272 may include the two-dimensional semiconductor material layer described above. Although the number of contact film layers included in the second contact structure 270 is shown as two layers, the number is not limited thereto. The number of contact film layers included in the second contact structure 270 may be at least one or more layers. Each of the fourth contact film 271 and the fifth contact film 272 included in the second contact structure 270 may include the same two-dimensional semiconductor material, or may include two-dimensional semiconductor materials that are different from each other. In some embodiments, the second contact structure 270 may be referred to as a second contact structure.

[0125] Subsequently, reference Figure 7 At least a portion of the second contact structure 270 located on the insulating post 260 can be removed. Therefore, the second contact structures 270 can be spaced apart from each other on the insulating post 260.

[0126] Subsequently, an electrode structure CAP can be formed on the second contact structure 270. The second contact structure 270 can contact the storage electrode SE of the electrode structure CAP.

[0127] Figures 22 to 27 This illustrates the manufacture of semiconductor memory devices (e.g., Figure 8 and Figure 9 The diagram illustrates an example of a method for using semiconductor memory devices. For ease of explanation, brief descriptions or omissions related to the use of... Figure 8 and Figure 9 The repeated parts of the description. For reference. Figures 22 to 27 It shows Figure 9 The diagram is a schematic diagram.

[0128] refer to Figure 22 A lower insulating layer 301 and a bit line BL can be sequentially formed on a third substrate 300. The third substrate 300 can be a silicon substrate, or it can include other materials, such as, but not limited to, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The bit line BL can be disposed on the lower insulating layer 301.

[0129] The lower insulating layer 301 may include at least one of the following: a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, a carbon-containing silicon nitride film, and a carbon-containing silicon oxynitride film. As an example, the lower insulating layer 301 may include a silicon oxide film.

[0130] The first contact structure 310 may be formed on the bit line BL. The first contact structure 310 may include a first contact film 311, a second contact film 312, and a third contact film 313 sequentially stacked on the bit line BL. Each of the first contact film 311, the second contact film 312, and the third contact film 313 may include the aforementioned two-dimensional semiconductor material layer. Although the number of contact film layers included in the first contact structure 310 is shown as three, its number is not limited to this. The number of contact film layers included in the first contact structure 310 may be at least one or more layers. Each of the first contact film 311, the second contact film 312, and the third contact film 313 included in the first contact structure 310 may include the same two-dimensional semiconductor material, or may include different two-dimensional semiconductor materials. In some embodiments, the first contact structure 310 may be referred to as a first contact structure.

[0131] Subsequently, a molded insulating film can be formed on the first contact structure 310. The molded insulating film may include, for example, at least one of the following: a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, a carbon nitride film, and a carbon oxynitride film. As an example, the molded insulating film may include a silicon oxide film.

[0132] Subsequently, an etching process can be performed on the molded insulating film to form a molded insulating pattern ILD. The molded insulating pattern ILD can contact a portion of the upper side of the first contact structure 310.

[0133] Subsequently, a channel region 320 can be formed on the upper side of the first contact structure 310 and on the sidewalls and upper side of the molded insulating pattern ILD. The channel region 320 can contact the upper side of the first contact structure 310. The channel region 320 can include the two-dimensional semiconductor material described above. The channel region 320 can be formed, for example, but not limited to, by an atomic layer deposition (ALD) process.

[0134] refer to Figure 23 The molded insulating pattern ILD and the channel region 320 on the molded insulating pattern ILD can be removed to form a first groove RS1 on the first contact structure 310. Channel regions 320 spaced apart in the second direction Y3 can be formed through the first groove RS1. The channel regions 320 on the first contact structure 310 can be removed to form a second groove RS2. Each of the first groove RS1 and the second groove RS2 can expose the upper side of the first contact structure 310.

[0135] refer to Figure 24 A gate insulating film 330 can be formed on each sidewall of the channel region 320. The gate insulating film 330 can be formed on the channel region 320 in a direction parallel to the third direction Z3.

[0136] Subsequently, a portion of the upper part of the channel region 320 can be removed to form a third recess RS3. The upper side of the channel region 320 can be recessed and exposed through the third recess RS3. On the third direction Z3, the length of the gate insulating film 330 can be greater than the length of the channel region 320.

[0137] refer to Figure 25 A first molded insulating film 340 may be formed on the first contact structure 310. For example, the first molded insulating film 340 may include a nitride-based material.

[0138] Subsequently, an etching process can be performed on the first molded insulating film 340 to form a fourth groove RS4 that exposes the sidewalls of the gate insulating film 330. The sidewalls of the gate insulating film 330 and the upper side of the first molded insulating film 340 can be exposed through the fourth groove RS4.

[0139] refer to Figure 26 Conductive material can be formed in the fourth groove RS4. The conductive material can be formed on the first molded insulating film 340. Accordingly, word lines WL and back gates BG between word lines WL can be formed. Back gates BG can be formed between channel regions 320.

[0140] Subsequently, the upper portion of the word line WL and the upper portion of the back gate BG can be partially removed to form a fifth groove RS5. The fifth groove RS5 exposes the upper side of the word line WL and the upper side of the back gate BG. The fifth groove RS5 also exposes the upper portion of the channel region 320 and the upper portion of the gate insulating film 330. In the third direction Z3, the height of the upper side of the word line WL and the upper side of the back gate BG can be lower than the height of the upper side of the channel region 320 and the upper side of the gate insulating film 330.

[0141] An etching process can be performed on the upper part of the gate insulating film 330. The upper side of the channel region 320 and the upper side of the gate insulating film 330 can be located on the same plane.

[0142] refer to Figure 27 The gate insulating film 330 on the word line WL and back gate BG can be removed. Therefore, the upper part of the channel region 320 can be exposed in the fifth groove RS5 region.

[0143] Subsequently, a second molded insulating film 350 can be formed on the word line WL and the back gate BG. The second molded insulating film 350 can be formed in the region of the fifth groove RS5. The second molded insulating film 350 can surround the upper region of the exposed channel region 320. For example, the second molded insulating film 350 can include a nitride-based material.

[0144] Subsequently, a portion of the upper part of the second molded insulating film 350 can be removed to form a sixth groove RS6. The sixth groove RS6 can expose a portion of the side and top of the channel region 320 and the top of the second molded insulating film 350. Therefore, the channel region 320 can protrude beyond the second molded insulating film 350 in the third direction Z3.

[0145] Next, refer to Figure 9 A second contact structure 360 ​​covering the upper portion of the channel region 320 can be formed on the second molded insulating film 350. Although the number of contact film layers included in the second contact structure 360 ​​is shown as one layer, its number is not limited thereto. The number of contact film layers included in the second contact structure 360 ​​can be at least one layer or more layers. When the contact film included in the second contact structure 360 ​​is a multilayer structure, each contact film can include the same two-dimensional semiconductor material, or can include two-dimensional semiconductor materials that are different from each other. In some embodiments, the second contact structure 360 ​​may be referred to as a second contact structure.

[0146] Subsequently, an electrode structure CAP can be formed on the second contact structure 360. The second contact structure 360 ​​can contact the storage electrode SE of the electrode structure CAP.

[0147] As described above, at least one or more two-dimensional semiconductor material layers can be formed in the first contact structure contacting the bit line BL and the second contact structure contacting the electrode structure CAP. Accordingly, the resistance characteristics of the contact structure can be improved. The two-dimensional semiconductor material layers can form a multilayer structure. The first contact structure and the second contact structure can include the same two-dimensional semiconductor material layer, or they can include two-dimensional semiconductor material layers that are different from each other. The two-dimensional semiconductor material layers can include, but are not limited to, at least one of MoS2, MoSe2, WS2, and WSe2.

[0148] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of possible claims. In a single embodiment, specific features described in the context of a standalone implementation of this disclosure may also be combined and implemented. Conversely, different features described in the context of a single implementation may also be implemented individually in multiple embodiments, or in appropriate sub-combinations. Furthermore, although features may be described above as functioning in certain combinations, in some cases one or more features may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

[0149] Although certain examples have been specifically shown and described, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor memory device, comprising: Substrate; Word lines, on the substrate; The channel area is located between the word lines; A first contact structure is connected to the first end of the channel region; A second contact structure is connected to the second end of the channel region; The bit line contacts the first contact structure; as well as The electrode structure is in contact with the second contact structure. The first contact structure includes a first two-dimensional semiconductor material layer forming a first multilayer structure, wherein the first two-dimensional semiconductor material layer is located between the channel region and the bit line. The second contact structure includes a second two-dimensional semiconductor material layer forming a second multilayer structure, wherein the second two-dimensional semiconductor material layer is located between the channel region and the electrode structure.

2. The semiconductor memory device according to claim 1, in, The first contact structure contacts the first end of the channel region, and The second contact structure contacts the second end of the channel region.

3. The semiconductor memory device according to claim 1, in, The first contact structure includes a first contact film that contacts the first end of the channel region, and a second contact film on the first contact film, the second contact film contacting the bit line, and... The second contact structure includes a third contact film that contacts the second end of the channel region, and a fourth contact film on the third contact film, wherein the fourth contact film contacts the electrode structure.

4. The semiconductor memory device according to claim 1, comprising: A first spacer pattern extends in a first horizontal direction parallel to the upper side of the substrate, wherein the first spacer pattern is located between the bit line and the word line in a second horizontal direction different from the first horizontal direction; A second spacer pattern extends in the first horizontal direction, wherein the second spacer pattern is spaced apart from the first spacer pattern in the second horizontal direction; and An insulating pattern is located between the letter lines in the vertical direction.

5. The semiconductor memory device according to claim 1, comprising: A gate insulating film is located between the word line and the channel region. The word line, the gate insulating film, and the channel region overlap each other in the vertical direction.

6. The semiconductor memory device according to claim 1, in, The channel region comprises a single layer of two-dimensional semiconductor material.

7. The semiconductor memory device according to claim 1, in, The first two-dimensional semiconductor material layer of the first contact structure and the second two-dimensional semiconductor material layer of the second contact structure comprise the same material as each other.

8. The semiconductor memory device according to claim 1, in, The first contact structure and the second contact structure are made of different materials.

9. The semiconductor memory device according to claim 1, in, The first two-dimensional semiconductor material layer of the first contact structure comprises materials that are different from each other, and The second two-dimensional semiconductor material layer of the second contact structure comprises materials that are different from each other.

10. The semiconductor memory device according to claim 1, in, The first contact structure includes at least one of MoS2, MoSe2, WS2, or WSe2, and The second contact structure includes at least one of MoS2, MoSe2, WS2, or WSe2.

11. A semiconductor memory device, comprising: Substrate; The letter lines are located on the substrate in the vertical direction; A channel region between the word lines, wherein the channel region comprises a single layer of two-dimensional semiconductor material; An insulating pattern is positioned between the letter lines in the vertical direction; The first contact structure is connected to the first source / drain region of the channel region; The second contact structure is connected to the second source / drain region of the channel region; Bit lines extend in the vertical direction, wherein the bit lines are connected to the first contact structure; and The electrode structure is connected to the second contact structure. The first contact structure is located between the channel region and the bit line. The first contact structure includes at least one first two-dimensional semiconductor material layer, and the at least one first two-dimensional semiconductor material layer contacts the first upper surface, first side surface, and first lower surface of the first source / drain region. The second contact structure is located between the channel region and the electrode structure. The second contact structure includes at least one second two-dimensional semiconductor material layer, and the at least one second two-dimensional semiconductor material layer is in contact with the second upper surface, the second side surface and the second lower surface of the second source / drain region.

12. The semiconductor memory device according to claim 11, wherein, The first side surface of the first source / drain region connects the first upper surface and the first lower surface of the first source / drain region, and The second side surface of the second source / drain region is connected to the second upper surface and the second lower surface of the second source / drain region.

13. The semiconductor memory device according to claim 11, wherein, The first contact structure includes a first contact film that contacts the first source / drain region and a second contact film that contacts the bit line. The second contact structure includes a third contact film that contacts the second source / drain region and a fourth contact film that contacts the electrode structure.

14. The semiconductor memory device of claim 11, comprising: A first spacer pattern is positioned between the bit line and the word line; as well as A second spacer pattern is positioned between the electrode structure and the word lines. Wherein, the first contact structure contacts the side surface of the first spacer pattern, and The second contact structure is in contact with the side surface of the second spacer pattern.

15. The semiconductor memory device according to claim 11, in, The electrode structure includes a plate electrode and a capacitor dielectric film between the plate electrode and the second contact structure; and The second contact structure is in contact with the capacitor dielectric film.

16. A semiconductor memory device, comprising: Substrate; Word lines extend on the substrate along a first horizontal direction parallel to the upper side of the substrate, wherein the word lines are spaced apart from each other along a second horizontal direction different from the first horizontal direction; A channel region is located between the word lines along the second horizontal direction, wherein the channel region comprises a single layer of two-dimensional semiconductor material; A first contact structure is connected to a first region of the channel region; A second contact structure is connected to a second region of the channel region; Bit lines, extending along the second horizontal direction on the substrate and connected to the first contact structure; and The electrode structure is connected to the second contact structure. Wherein, the first contact structure is located between the first region and the bit line, wherein the first contact structure includes a first two-dimensional semiconductor material layer forming a first multilayer structure, and wherein the first multilayer structure is in contact with the first region, and The second contact structure is located between the second region and the electrode structure, wherein the second contact structure includes a second two-dimensional semiconductor material layer forming a second multilayer structure, and wherein the second multilayer structure is in contact with the second region.

17. The semiconductor memory device of claim 16, comprising: A first insulating pattern is located between the word lines in the second horizontal direction; as well as The second insulating pattern is located on the letter line in the vertical direction.

18. The semiconductor memory device according to claim 17, in, Each of the first two-dimensional semiconductor material layers extends along the second horizontal direction on the bit line, and The second two-dimensional semiconductor material layers each extend along the upper side and sidewall of the second insulating pattern in the second region.

19. The semiconductor memory device of claim 16, comprising: A back gate, located between the word lines in the second horizontal direction, wherein the back gate comprises a conductive material.

20. The semiconductor memory device according to claim 19, in, Each of the first two-dimensional semiconductor material layers extends along the second horizontal direction on the bit line, and Each of the second two-dimensional semiconductor material layers extends along the surface of the second region.

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