Semiconductor memory device

Abstract

A semiconductor memory device includes: an active pattern comprising a first portion and a second portion connected along a vertical direction; a conductor located on a lower surface of the active pattern and connected to the active pattern, extending in a first horizontal direction intersecting the vertical direction; a first gate pattern located on a side of the first portion of the active pattern and extending in a second horizontal direction intersecting the vertical direction and the first horizontal direction; a second gate pattern located on a side of the second portion of the active pattern and spaced apart from the first gate pattern, extending in the second horizontal direction; and a data storage structure located on an upper surface of the active pattern and connected to the active pattern.

Description

Technical Field

[0001] This disclosure relates to a semiconductor memory device and a method for manufacturing the same. More specifically, this disclosure relates to a semiconductor memory device including a vertical channel transistor (VCT) and a method for manufacturing the same. Background Technology

[0002] There is a need for semiconductor devices with improved integration levels to meet consumers' demands for superior performance and low prices. In the case of semiconductor memory devices, high integration is particularly necessary because integration level is a significant factor determining product price.

[0003] In the case of two-dimensional or planar semiconductor memory devices, the integration density is primarily determined by the area occupied by a single memory cell, and is therefore greatly influenced by the level of fine pattern formation technology. However, the cost of miniaturizing patterns limits the improvement of the integration density of two-dimensional semiconductor memory devices. Summary of the Invention

[0004] Various aspects of this disclosure provide a semiconductor memory device including a vertical channel transistor having a channel extending in a vertical direction.

[0005] This disclosure also provides a semiconductor memory device with improved performance and integration.

[0006] This disclosure also provides a method for manufacturing semiconductor memory devices with improved performance and integration.

[0007] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art from the following detailed description of the disclosure.

[0008] According to one aspect of this disclosure, a semiconductor memory device is provided, comprising: an active pattern including a first portion and a second portion connected along a vertical direction; a conductor located on a lower surface of the active pattern and connected to the active pattern, extending in a first horizontal direction intersecting the vertical direction; a first gate pattern located on a side of the first portion of the active pattern and extending in a second horizontal direction intersecting the vertical direction and the first horizontal direction; a second gate pattern located on a side of the second portion of the active pattern and spaced apart from the first gate pattern, extending in the second horizontal direction; and a data storage structure located on an upper surface of the active pattern and connected to the active pattern.

[0009] According to another aspect of this disclosure, a semiconductor memory device is provided, comprising: an active pattern extending in a vertical direction; a conductor located on a lower surface of the active pattern, connected to the active pattern, and extending in a first horizontal direction intersecting the vertical direction; a gate structure located on a side of the active pattern and comprising a plurality of gate patterns disposed at different heights and spaced apart from each other in the vertical direction, each gate pattern extending in a second horizontal direction intersecting the vertical direction and the first horizontal direction; and a data storage structure located on an upper surface of the active pattern and connected to the active pattern.

[0010] According to another aspect of this disclosure, a semiconductor memory device is provided, comprising: an active pattern including a first portion and a second portion connected along a vertical direction, and including a first side and a second side opposite to each other in a first horizontal direction intersecting the vertical direction; a conductor located on a lower surface of the active pattern and connected to the active pattern, and extending in the first horizontal direction; a first gate pattern located on the first side of the first portion and extending in a second horizontal direction intersecting the vertical direction and the first horizontal direction; a second gate pattern located on a second side of the second portion and extending in the second horizontal direction; and a data storage structure located on an upper surface of the active pattern and connected to the active pattern.

[0011] Specific details of other implementation methods are included in the detailed embodiments and accompanying drawings. Attached Figure Description

[0012] The above and other aspects and features of this disclosure will become clearer by referring to the accompanying drawings and describing the embodiments of this disclosure in detail.

[0013] Figure 1 This is an example layout diagram used to illustrate a semiconductor memory device according to some implementation methods.

[0014] Figure 2 It is along Figure 1 The cross-sectional view taken from AA.

[0015] Figure 3 It is along Figure 1 A cross-sectional view of BB.

[0016] Figure 4a , Figure 4b , Figure 4c and Figure 4d It is used for explanation Figures 1 to 3 A diagram illustrating an example operation of a semiconductor memory device.

[0017] Figure 5 This is a cross-sectional view used to illustrate a semiconductor memory device according to some embodiments.

[0018] Figure 6 This is a cross-sectional view used to illustrate a semiconductor memory device according to some embodiments.

[0019] Figure 7a , Figure 7b and Figure 7c It is used for explanation Figure 6 A diagram illustrating an example operation of a semiconductor memory device.

[0020] Figure 8 This is a cross-sectional view used to illustrate a semiconductor memory device according to some embodiments.

[0021] Figure 9 This is a cross-sectional view used to illustrate a semiconductor memory device according to some embodiments.

[0022] Figure 10a and Figure 10b It is used for explanation Figure 9 A diagram illustrating an example operation of a semiconductor memory device.

[0023] Figure 11 This is a cross-sectional view used to illustrate a semiconductor memory device according to some embodiments.

[0024] Figure 12a and Figure 12b It is used for explanation Figure 11 A diagram illustrating an example operation of a semiconductor memory device.

[0025] Figure 13 This is an example layout diagram used to illustrate a semiconductor memory device according to some implementation methods.

[0026] Figure 14 and Figure 15 It is along Figure 13 Various cross-sectional views captured by CC.

[0027] Figure 16 It is a schematic layout diagram used to illustrate a semiconductor memory device according to some embodiments.

[0028] Figure 17 It is along Figure 16 The cross-sectional view of line DD.

[0029] Figure 18 It is along Figure 16 The cross-sectional view of line EE.

[0030] Figures 19 to 28 This is an intermediate stage diagram used to illustrate an example method for manufacturing a semiconductor memory device according to some embodiments. Detailed Implementation

[0031] In the following text, reference will be made to Figures 1 to 18 Describes a semiconductor memory device according to an example implementation.

[0032] Figure 1 This is an example layout diagram used to illustrate a semiconductor memory device according to some implementation methods. Figure 2 It is along Figure 1 The cross-sectional view taken from AA. Figure 3 It is along Figure 1 A cross-sectional view of BB. Figure 4a , Figure 4b , Figure 4c and Figure 4d It is used for explanation Figures 1 to 3 A diagram illustrating an example operation of a semiconductor memory device.

[0033] Reference Figures 1 to 3 According to some embodiments, a semiconductor memory device includes a plurality of active patterns 110, a gate dielectric film 130, a gate structure 150, a lower spacer 152, an intermediate spacer 154, an upper spacer 156, a contact pattern BC, a landing pad LP, a data storage structure 180, an upper insulating film 190, a conductor 210, a cover film 220, a pad film 240, a spacer film 245, a shielding conductive film 250, and a lower insulating film 260.

[0034] Multiple active patterns 110 can be arranged in two dimensions along a horizontal plane. For example, the active patterns 110 can be arranged in a matrix shape along a first horizontal direction X and a second horizontal direction Y that intersect each other.

[0035] Each active pattern 110 may extend in a vertical direction Z intersecting a horizontal plane. For example, each active pattern 110 may extend longitudinally in a vertical direction Z intersecting a first horizontal direction X and a second horizontal direction Y. The height of each active pattern 110 extending in the vertical direction Z may be greater than the width of each active pattern 110 (e.g., the width in the first horizontal direction X and / or the width in the second horizontal direction Y). The height of each active pattern 110 may be, but is not limited to, about two to about ten times the width of each active pattern 110. Each active pattern 110 may be provided as a channel region of a vertical channel transistor (VCT). A vertical channel transistor may refer to a structure having a channel length extending in the vertical direction Z. As used herein, "extend" includes "elongate" or "oriented along". For example, "extend along the vertical direction Z" includes "elongate along the vertical direction Z" or "oriented along the vertical direction Z".

[0036] Each active pattern 110 may include a semiconductor material. For example, each active pattern 110 may include an elemental semiconductor material, such as single-crystal silicon (single-crystal Si), polycrystalline silicon (polycrystalline Si), amorphous silicon (amorphous Si), silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, for example, each active pattern 110 may include a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO).

[0037] Each active pattern 110 may include one or more layers of semiconductor material. In some embodiments, each active pattern 110 may include a single-crystal semiconductor material. As an example, each active pattern 110 may include single-crystal silicon.

[0038] In some implementations, each active pattern 110 may include a first portion 111 and a second portion 112 connected along the vertical direction Z. For example, as Figure 2 and Figure 3 As shown, the first portion 111 may be the lower part of each active pattern 110, and the second portion 112 may be the upper part of each active pattern 110. The first portion 111 and the second portion 112 may be connected in the vertical direction Z to form an integral semiconductor pattern (e.g., an integral silicon pattern).

[0039] In some embodiments, the active patterns 110 arranged along the second horizontal direction Y can be separated from each other by the first interlayer insulating film 120. For example, as Figure 3 As shown, the active pattern 110 and the first interlayer insulating film 120 can be arranged alternately along the second horizontal direction Y.

[0040] The first interlayer insulating film 120 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof. As an example, the first interlayer insulating film 120 may include a silicon oxide film. The first interlayer insulating film 120 may be a single film made of one type of insulating material, or a multilayer film made of a combination of several types of insulating materials.

[0041] A gate dielectric film 130 may be situated between each active pattern 110 and the gate structure 150. For example, the gate dielectric film 130 may extend conformally along the contour of the side surface of each active pattern 110. In some embodiments, the gate dielectric film 130 may be formed on the side surface of each active pattern 110 intersecting a first horizontal direction X. In some embodiments, the gate dielectric film 130 may extend longitudinally in a second horizontal direction Y. In some embodiments, the gate dielectric film 130 may not be formed on the side surface of each active pattern 110 intersecting the second horizontal direction Y.

[0042] The gate dielectric film 130 may include, for example, but not limited to, at least one of silicon oxide, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or combinations thereof. The high-k material may include, but is not limited to, metal oxides or metal oxynitrides, such as at least one of hafnium dioxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), or combinations thereof.

[0043] Gate structures 150 may be disposed on the side surface of each active pattern 110. Gate structures 150 may be spaced apart from each active pattern 110 by gate dielectric film 130. Gate structures 150 may intersect each active pattern 110. For example, gate structures 150 may extend longitudinally in a second horizontal direction Y. Multiple gate structures 150 may be spaced apart from each other in a first horizontal direction X and extend side-by-side (or parallel) in the second horizontal direction Y. Each gate structure 150 may extend parallel to a row of active patterns 110 arranged along the second horizontal direction Y. Gate structures 150 may be configured as word lines of a semiconductor memory device according to some embodiments.

[0044] In some embodiments, the gate structure 150 may include a plurality of gate patterns 150A and 150B, which are disposed at different heights and spaced apart from each other in the vertical direction Z. Here, the expression "disposed at different heights" means that they are disposed at different heights in the vertical direction Z based on the lower surface of each active pattern 110. For example, the gate structure 150 may include a first gate pattern 150A and a second gate pattern 150B spaced apart from each other. Both the first gate pattern 150A and the second gate pattern 150B may extend longitudinally in the second horizontal direction Y. The first gate pattern 150A may intersect with a first portion 111 of each active pattern 110. The second gate pattern 150B may intersect with a second portion 112 of each active pattern 110.

[0045] In some embodiments, the first gate pattern 150A and the second gate pattern 150B may overlap in the vertical direction Z. For example, the first gate pattern 150A and the second gate pattern 150B may be arranged sequentially along the vertical direction Z. The first gate pattern 150A and the second gate pattern 150B may be spaced apart from each other in the vertical direction Z.

[0046] The gate structure 150 may include a conductive material, such as at least one of doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof. For example, the gate structure 150 may include, but is not limited to, doped polysilicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), niobium nitride (NbN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicon silicide (TaSi), tantalum silicon nitride (TaSiN), ruthenium titanium nitride (RuTiN), nickel silicide (NiSi), cobalt silicide (CoSi), and iridium oxide (IrO). x ), Ruthenium oxide (RuO) x (or at least one of their combinations)

[0047] Multiple gate patterns 150A and 150B can be configured to have voltages applied independently of each other. For example, a circuit (e.g., a processor) electrically connected to the multiple gate patterns 150A and 150B can be configured to apply different voltages to the first gate pattern 150A and the second gate pattern 150B. Thus, the first gate pattern 150A and the second gate pattern 150B can form channels independently of each other in each active pattern 110.

[0048] A lower spacer 152 may be formed on the lower surface of the gate structure 150. The lower spacer 152 may be located between the conductor 210 and the gate structure 150. The gate structure 150 may be spaced apart from the conductor 210 in the vertical direction Z by the lower spacer 152. The upper surface of the lower spacer 152 may be configured to be higher than the lower surface of each active pattern 110 in the vertical direction Z. That is, the lower surface of the gate structure 150 may be positioned higher than the lower surface of each active pattern 110 in the vertical direction Z. In some embodiments, the lower surface of the lower spacer 152 may be configured to be coplanar with the lower surface of each active pattern 110. In some embodiments, a portion of the gate dielectric film 130 may be located between each active pattern 110 and the lower spacer 152.

[0049] The lower spacer 152 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof. As an example, the lower spacer 152 may include a silicon nitride film. The lower spacer 152 may be a single film made of one type of insulating material, or a multilayer film made of a combination of several types of insulating materials.

[0050] Intermediate spacer 154 may be located between lower spacer 152 and upper spacer 156 in the vertical direction Z. Intermediate spacer 154 may cover the upper surface of the first gate pattern 150A. Second gate pattern 150B may be formed on the upper surface of intermediate spacer 154. In some embodiments, a portion of gate dielectric film 130 may be located between each active pattern 110 and intermediate spacer 154.

[0051] In some embodiments, the intermediate spacer 154 may be located between the first gate pattern 150A and the second gate pattern 150B in the vertical direction Z. The first gate pattern 150A and the second gate pattern 150B may be separated in the vertical direction Z by the intermediate spacer 154.

[0052] The intermediate spacer 154 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof. As an example, the intermediate spacer 154 may include a silicon oxide film. The intermediate spacer 154 may be a single film made of one type of insulating material, or it may be a multilayer film made of a combination of several types of insulating materials.

[0053] Upper spacer 156 may be formed on the upper surface of gate structure 150. Upper spacer 156 may be located between gate structure 150 and contact pattern BC and / or between gate structure 150 and etch stop film 162. Gate structure 150 may be spaced apart from contact pattern BC and / or etch stop film 162 in the vertical direction Z by upper spacer 156. In the vertical direction Z, the lower surface of upper spacer 156 may be positioned below the upper surface of each active pattern 110. That is, in the vertical direction Z, the upper surface of gate structure 150 may be positioned below the upper surface of each active pattern 110. In some embodiments, a portion of gate dielectric film 130 may be located between each active pattern 110 and upper spacer 156.

[0054] The upper spacer 156 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof. As an example, the upper spacer 156 may include a silicon nitride film. The upper spacer 156 may be a single film made of one type of insulating material, or it may be a multilayer film made of a combination of several types of insulating materials.

[0055] Contact patterns BC can be disposed on the upper surface of each active pattern 110. Contact patterns BC can be connected to each active pattern 110. For example, etch stop film 162 and second interlayer insulating film 164 can be sequentially stacked on the upper surface of the active pattern 110, the upper surface of the first interlayer insulating film 120, and the upper spacer 156. Contact patterns BC penetrate the etch stop film 162 and the second interlayer insulating film 164 and can contact the upper surface of each active pattern 110.

[0056] The contact pattern BC may include a conductive material, such as, but not limited to, at least one of the following: impurity-doped polycrystalline silicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal, or combinations thereof. As an example, the contact pattern BC may include a polycrystalline silicon film doped with n-type impurities (e.g., P, Sb, or As).

[0057] Landing pad LP can be disposed on the upper surface of contact pattern BC. Landing pad LP can be connected to contact pattern BC. For example, third interlayer insulating film 166 can be stacked on the upper surface of second interlayer insulating film 164. Landing pad LP can penetrate third interlayer insulating film 166 and contact the upper surface of contact pattern BC.

[0058] The landing pad LP may include a conductive material, such as, but not limited to, at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal, or combinations thereof. As an example, the landing pad LP may include a tungsten (W) film.

[0059] Data storage structure 180 can be disposed on the upper surface of landing pad LP and the upper surface of third interlayer insulating film 166. Data storage structure 180 can be connected to landing pad LP. Data storage structure 180 can be electrically connected to active pattern 110 through contact pattern BC and landing pad LP. Data storage structure 180 is controlled by wires 210 configured as bit lines and gate structure 150 configured as word lines, and can store data in unit memory cells corresponding to each active pattern 110.

[0060] In some implementations, the data storage structure 180 may be a capacitor. For example, the data storage structure 180 may include a lower electrode 182, a capacitor dielectric film 184, and an upper electrode 186 sequentially stacked on a landing pad LP. The data storage structure 180 may use the potential difference generated between the lower electrode 182 and the upper electrode 186 to store charge within the capacitor dielectric film 184.

[0061] Each of the lower electrode 182 and the upper electrode 186 may include a conductive material, such as, but not limited to, doped polysilicon, metal, metal nitride, etc. The capacitor dielectric film 184 may include, for example, but not limited to, silicon oxide or a high dielectric constant material.

[0062] The upper insulating film 190 may be stacked on the data storage structure 180. The upper insulating film 190 may cover at least a portion of the data storage structure 180. The upper insulating film 190 may include, for example, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof.

[0063] Conductors 210 may be disposed on the lower surface of each active pattern 110. Conductors 210 may intersect with gate structure 150. For example, conductors 210 may extend longitudinally in a first horizontal direction X. Multiple conductors 210 may be spaced apart from each other in a second horizontal direction Y and extend side-by-side (or parallel) in the first horizontal direction X. Each conductor 210 may be commonly connected to a row of active patterns 110 arranged along the first horizontal direction X. Conductors 210 may serve as bit lines for semiconductor memory devices according to some embodiments.

[0064] In some embodiments, the wire 210 may include a first conductive film 212, a second conductive film 214, and a third conductive film 216 sequentially stacked on the lower surface of each active pattern 110. Each of the first conductive film 212, the second conductive film 214, and the third conductive film 216 may include a conductive material, such as, but not limited to, at least one of impurity-doped polycrystalline silicon, TiN, TiSiN, tungsten, tungsten silicide, molybdenum, or combinations thereof. As an example, the first conductive film 212 may include a polycrystalline silicon film doped with n-type impurities (e.g., P, Sb, or As), the second conductive film 214 may include a TiSiN film or WSiN, and the third conductive film 216 may include a tungsten (W) film or molybdenum.

[0065] The cover film 220 may extend along the lower surface of the conductor 210. The cover film 220 may extend longitudinally in a first horizontal direction X. The cover film 220 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and combinations thereof. As an example, the cover film 220 may include a silicon nitride film.

[0066] The padding film 240 may be stacked below the conductor 210 and the cover film 220. For example, the padding film 240 may extend conformally along the contours of the side and lower surface of the cover film 220, the side of the conductor 210, the lower surface of the lower spacer 152, and the lower surface of the first interlayer insulating film 120.

[0067] The gasket film 240 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and combinations thereof. As an example, the gasket film 240 may include a silicon nitride film.

[0068] The spacer membrane 245 may be stacked below the liner membrane 240. For example, the spacer membrane 245 may extend conformally along the contours of the side and bottom surfaces of the liner membrane 240.

[0069] The spacer film 245 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and combinations thereof. As an example, the spacer film 245 may include a silicon oxide film.

[0070] The conductive shielding film 250 can be stacked below the spacer film 245. At least a portion of the conductive shielding film 250 can be situated between the conductors 210 arranged along the second horizontal direction Y. For example, as Figure 3 As shown, the shielding conductive film 250 can be formed to fill at least a portion of the area between one conductor 210 and another conductor 210. The shielding conductive film 250 can be separated from the conductor 210 by a pad film 240 and / or a spacer film 245.

[0071] The shielding conductive film 250 may include a conductive material, such as, but not limited to, at least one of doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof. The shielding conductive film 250 may be configured to have a predetermined bias voltage (e.g., ground voltage) applied to it. For example, a circuit (e.g., a processor) may be configured to apply a predetermined bias voltage (e.g., ground voltage) to the shielding conductive film 250. Therefore, the shielding conductive film 250 can reduce coupling noise between the conductors 210 in the second horizontal direction Y.

[0072] The lower insulating film 260 may be stacked below the shielding conductive film 250. The lower insulating film 260 may cover at least a portion of the shielding conductive film 250. The lower insulating film 260 may include, for example, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof.

[0073] refer to Figures 4a to 4d For each active pattern 110, the first gate pattern 150A may include a first gate electrode 1501 and a second gate electrode 1502, and the second gate pattern 150B may include a third gate electrode 1503 and a fourth gate electrode 1504.

[0074] Each active pattern 110 may include a first side surface S1 and a second side surface S2 opposite to each other in a first horizontal direction X. A first gate electrode 1501 may be disposed on the first side surface S1 of the first portion 111, and a second gate electrode 1502 may be disposed on the second side surface S2 of the first portion 111. A third gate electrode 1503 may be disposed on the first side surface S1 of the second portion 112, and a fourth gate electrode 1504 may be disposed on the second side surface S2 of the second portion 112. The first gate electrode 1501 to the fourth gate electrode 1504 may be configured to be voltage-applied independently of each other.

[0075] When the high-level voltage V is equal to or higher than the threshold voltage H When applied to at least a portion of the first gate pattern 150A and at least a portion of the second gate pattern 150B of each active pattern 110, the corresponding vertical channel transistor can be set to be in the on state.

[0076] As an example, such as Figure 4a As shown, the high-level voltage V H It can be applied to each of the first gate electrode 1501 and the fourth gate electrode 1504, and the low-level voltage V LIt can be applied to each of the second gate electrode 1502 and the third gate electrode 1503. In this case, the first portion 111 can form a channel with the first gate electrode 1501, and the second portion 112 can form a channel with the fourth gate electrode 1504. As a result, the vertical channel transistor can be turned on.

[0077] As another example, such as Figure 4b As shown, the high-level voltage V H It can be applied to each of the first gate electrode 1501 and the third gate electrode 1503, and the low-level voltage V L It can be applied to each of the second gate electrode 1502 and the fourth gate electrode 1504. In this case, the first portion 111 can form a channel with the first gate electrode 1501, and the second portion 112 can form a channel with the third gate electrode 1503. Therefore, the vertical channel transistor can be turned on.

[0078] When the low-level voltage V is equal to or lower than the threshold voltage L When applied to at least one of the first gate pattern 150A or the second gate pattern 150B of each active pattern 110, the corresponding vertical channel transistor VCT can be set to the off state.

[0079] As an example, such as Figure 4c As shown, the high-level voltage V H It can be applied to the first gate electrode 1501, and a low-level voltage V L It can be applied to each of the second gate electrode 1502 to the fourth gate electrode 1504. In this case, the first portion 111 can form a channel with the first gate electrode 1501, but the second portion 112 cannot form a channel. Therefore, the vertical channel transistor can be turned off.

[0080] As another example, such as Figure 4d As shown, the high-level voltage V H It can be applied to the fourth gate electrode 1504, and a low-level voltage V L It can be applied to each of the first gate electrode 1501 to the third gate electrode 1503. In this case, the second portion 112 can form a channel with the fourth gate electrode 1504, but the first portion 111 cannot form a channel. Therefore, the vertical channel transistor can be turned off.

[0081] In some embodiments, each active pattern 110 may be controlled by a pair of first gate patterns 150A and second gate patterns 150B arranged diagonally between a first horizontal direction X and a vertical direction Z. As an example, each active pattern 110 may be configured to be controlled by a first gate electrode 1501 and a fourth gate electrode 1504. As another example, each active pattern 110 may be configured to be controlled by a second gate electrode 1502 and a third gate electrode 1503.

[0082] As the integration density of semiconductor memory devices, including vertical-channel transistors (VCTs), continues to increase, coupling noise between adjacent word lines in the horizontal direction has become a problem. For example, two word lines that are horizontally opposite each other can be positioned between adjacent active patterns. However, as the integration density of semiconductor memory devices continues to increase in the horizontal direction, interference between channels controlled by the two word lines has increased.

[0083] Semiconductor memory devices according to some embodiments can reduce coupling noise between word lines in a first horizontal direction X by including multiple gate patterns 150A and 150B disposed at different heights in the vertical direction Z. Specifically, as described above, the first gate pattern 150A can be configured to control a first portion 111 of each active pattern 110, and the second gate pattern 150B can be configured to control a second portion 112 of each active pattern 110. In this case, a wide spacing can be provided between word lines in the first horizontal direction X. Furthermore, each active pattern 110 can be effectively controlled according to the voltage independently applied to each of the first gate pattern 150A and the second gate pattern 150B. Therefore, a semiconductor memory device with improved performance and integration can be provided.

[0084] Figure 5 This is a cross-sectional view used to illustrate a semiconductor memory device according to some embodiments. For ease of explanation, the above description will be brief or omitted. Figures 1 to 4d The repeated parts of the explanation.

[0085] refer to Figure 1 and Figure 5 In a semiconductor device according to some embodiments, a portion of the gate dielectric film 130 is located between the lower spacer 152 and the gate structure 150.

[0086] For example, the gate dielectric film 130 may extend conformally along the contours of the sides of each active pattern 110 and the upper surface of the lower spacer 152. The gate structure 150 may be stacked on the upper surface of the gate dielectric film 130.

[0087] Figure 6 This is a cross-sectional view used to illustrate a semiconductor memory device according to some embodiments. Figure 7a , Figure 7b and Figure 7c It is used for explanation Figure 6 A diagram illustrating an example operation of a semiconductor memory device. For ease of explanation, the above will be briefly described or omitted. Figures 1 to 5 The repeated parts of the explanation.

[0088] refer to Figure 1 and Figure 6 In a semiconductor device according to some embodiments, the second gate pattern 150B does not overlap with the first gate pattern 150A in the vertical direction Z.

[0089] For example, a pair of first gate patterns 150A and second gate patterns 150B can be arranged along a diagonal direction between a first horizontal direction X and a vertical direction Z. A pair of first gate patterns 150A and second gate patterns 150B can be arranged repeatedly along the first horizontal direction X.

[0090] In some embodiments, the first gate pattern 150A and the second gate pattern 150B may not overlap in the first horizontal direction X. For example, the upper surface of the first gate pattern 150A may be positioned lower than the lower surface of the second gate pattern 150B in the vertical direction Z. In this case, interference between the first gate pattern 150A and the second gate pattern 150B can be reduced.

[0091] Reference Figures 7a to 7c For each active pattern 110, a first gate pattern 150A may be disposed on a first side surface S1 of the first portion 111, but may not be disposed on a second side surface S2 of the first portion 111. Similarly, a second gate pattern 150B may be disposed on a second side surface S2 of the second portion 112, but may not be disposed on a first side surface S1 of the second portion 112. The first gate pattern 150A and the second gate pattern 150B may be configured to be energized independently of each other.

[0092] When the high-level voltage V is equal to or higher than the threshold voltage H When applied to both the first gate pattern 150A and the second gate pattern 150B of each active pattern 110, the corresponding vertical channel transistor can be set to be in the on state.

[0093] As an example, such as Figure 7a As shown, the high-level voltage V H It can be applied to each of the first gate pattern 150A and the second gate pattern 150B. In this case, the first portion 111 can form a channel with the first gate pattern 150A, and the second portion 112 can form a channel with the second gate pattern 150B. Therefore, the vertical channel transistor can be turned on.

[0094] For each active pattern 110, when the low-level voltage V is equal to or lower than the threshold voltage L When applied to at least one of the first gate pattern 150A and the second gate pattern 150B, the corresponding vertical channel transistor VCT can be set to the off state.

[0095] As an example, such as Figure 7b As shown, the high-level voltage V H It can be applied to the first gate pattern 150A, and a low-level voltage V L A second gate pattern 150B can be applied. In this case, the first portion 111 can form a channel from the first gate pattern 150A, but the second portion 112 cannot form a channel. Therefore, the vertical channel transistor can be turned off.

[0096] As another example, such as Figure 7c As shown, the low-level voltage V L It can be applied to the first gate pattern 150A, and a high-level voltage V H A second gate pattern 150B can be applied. In this case, the second portion 112 can form a channel from the second gate pattern 150B, but the first portion 111 cannot form a channel. Therefore, the vertical channel transistor can be turned off.

[0097] Figure 8 This is a cross-sectional view used to illustrate a semiconductor memory device according to some embodiments. For ease of explanation, the above description will be brief or omitted. Figures 1 to 7c The repeated parts of the explanation.

[0098] refer to Figure 1 and Figure 8 In a semiconductor device according to some embodiments, a portion of a first gate pattern 150A and a portion of a second gate pattern 150B overlap in a first horizontal direction X.

[0099] For example, the upper surface of the first gate pattern 150A can be positioned higher than the lower surface of the second gate pattern 150B in the vertical direction Z. In this case, the gate controllability of the gate structure 150 of each active pattern 110 can be improved.

[0100] Figure 9 This is a cross-sectional view used to illustrate a semiconductor memory device according to some embodiments. Figure 10a and Figure 10b It is used for explanation Figure 9 A diagram illustrating an example operation of a semiconductor memory device. For ease of explanation, the above will be briefly described or omitted. Figures 1 to 8 The repeated parts of the explanation.

[0101] refer to Figure 1 and Figure 9 In a semiconductor device according to some embodiments, each active pattern 110 includes a first portion 111, a second portion 112, and a third portion 113 connected along a vertical direction Z.

[0102] For example, the first portion 111 may be the lower part of each active pattern 110, the second portion 112 may be the central portion of each active pattern 110, and the third portion 113 may be the upper part of each active pattern 110. The first portion 111, the second portion 112, and the third portion 113 may be connected in the vertical direction Z to form an integral semiconductor pattern (e.g., an integral silicon pattern).

[0103] The gate structure 150 may include a plurality of gate patterns 150A to 150C, which are disposed at different heights and spaced apart from each other in the vertical direction Z. For example, the gate structure 150 may include a first gate pattern 150A, a second gate pattern 150B, and a third gate pattern 150C spaced apart from each other. Each of the first gate pattern 150A, the second gate pattern 150B, and the third gate pattern 150C may extend longitudinally in the second horizontal direction Y. The first gate pattern 150A may intersect with a first portion 111 of each active pattern 110. The second gate pattern 150B may intersect with a second portion 112 of each active pattern 110. The third gate pattern 150C may intersect with a third portion 113 of each active pattern 110.

[0104] In some embodiments, the first gate pattern 150A, the second gate pattern 150B, and the third gate pattern 150C may overlap in the vertical direction Z. For example, the first gate pattern 150A, the second gate pattern 150B, and the third gate pattern 150C may be arranged sequentially along the vertical direction Z. The first gate pattern 150A, the second gate pattern 150B, and the third gate pattern 150C may be spaced apart from each other in the vertical direction Z.

[0105] Multiple gate patterns 150A to 150C can be configured to have voltages applied independently of each other. For example, a circuit (e.g., a processor) electrically connected to the multiple gate patterns 150A to 150C can be configured to apply different voltages to the first gate pattern 150A, the second gate pattern 150B, and the third gate pattern 150C. Thus, the first gate pattern 150A, the second gate pattern 150B, and the third gate pattern 150C can form channels independently of each other within each active pattern 110.

[0106] In some embodiments, a first intermediate spacer 154A and a second intermediate spacer 154B may be formed between the lower spacer 152 and the upper spacer 156. The first intermediate spacer 154A may cover the upper surface of the first gate pattern 150A. The second gate pattern 150B may be formed on the upper surface of the first intermediate spacer 154A. The second intermediate spacer 154B may cover the upper surface of the second gate pattern 150B. A third gate pattern 150C may be formed on the upper surface of the second intermediate spacer 154B.

[0107] In some embodiments, the first intermediate spacer 154A may be located between the first gate pattern 150A and the second gate pattern 150B in the vertical direction Z. The first gate pattern 150A and the second gate pattern 150B may be separated in the vertical direction Z by the first intermediate spacer 154A.

[0108] In some embodiments, the second intermediate spacer 154B may be located between the second gate pattern 150B and the third gate pattern 150C in the vertical direction Z. The second gate pattern 150B and the third gate pattern 150C may be separated in the vertical direction Z by the second intermediate spacer 154B.

[0109] Each of the first intermediate spacer 154A and the second intermediate spacer 154B may include, for example, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof. As an example, each of the first intermediate spacer 154A and the second intermediate spacer 154B may include a silicon oxide film. Each of the first intermediate spacer 154A and the second intermediate spacer 154B may be a single film made of one type of insulating material, or may be a multilayer film made of a combination of several types of insulating materials.

[0110] refer to Figure 10a and Figure 10b For each active pattern 110, the first gate pattern 150A may include a first gate electrode 1501 and a second gate electrode 1502, the second gate pattern 150B may include a third gate electrode 1503 and a fourth gate electrode 1504, and the third gate pattern 150C may include a fifth gate electrode 1505 and a sixth gate electrode 1506.

[0111] A first gate electrode 1501 may be disposed on a first side surface S1 of a first portion 111, and a second gate electrode 1502 may be disposed on a second side surface S2 of the first portion 111. A third gate electrode 1503 may be disposed on a first side surface S1 of a second portion 112, and a fourth gate electrode 1504 may be disposed on a second side surface S2 of the second portion 112. A fifth gate electrode 1505 may be disposed on a first side surface S1 of a third portion 113, and a sixth gate electrode 1506 may be disposed on a second side surface S2 of the third portion 113. The first gate electrode 1501 to the sixth gate electrode 1506 may be configured to be subjected to voltages independently of each other.

[0112] When the high-level voltage V is equal to or higher than the threshold voltage H When applied to at least a portion of the first gate pattern 150A, at least a portion of the second gate pattern 150B, and at least a portion of the third gate pattern 150C of each active pattern 110, the corresponding vertical channel transistor can be set to be in the on state.

[0113] As an example, such as Figure 10a As shown, the high-level voltage V H It can be applied to each of the first gate electrode 1501, the fourth gate electrode 1504, and the fifth gate electrode 1505, and the low-level voltage V L It can be applied to each of the second gate electrode 1502, the third gate electrode 1503, and the sixth gate electrode 1506. In this case, the first portion 111 can form a channel with the first gate electrode 1501, the second portion 112 can form a channel with the fourth gate electrode 1504, and the third portion 113 can form a channel with the fifth gate electrode 1505. Therefore, the vertical channel transistor can be turned on.

[0114] When the low-level voltage V is equal to or lower than the threshold voltage L When at least one of the first gate pattern 150A, the second gate pattern 150B, and the third gate pattern 150C of each active pattern 110 is applied, the corresponding vertical channel transistor VCT can be set to the off state.

[0115] As an example, such as Figure 10b As shown, the high-level voltage V H It can be applied to each of the first gate electrode 1501 and the fifth gate electrode 1505, and the low-level voltage V LIt can be applied to each of the second gate electrode 1502, the third gate electrode 1503, the fourth gate electrode 1504, and the sixth gate electrode 1506. In this case, the first portion 111 can form a channel with the first gate electrode 1501, the third portion 113 can form a channel with the fifth gate electrode 1505, but the second portion 112 does not form a channel. Therefore, the vertical channel transistor can be turned off.

[0116] Figure 11 This is a cross-sectional view used to illustrate a semiconductor memory device according to some embodiments. Figure 12a and Figure 12b It is used for explanation Figure 11 A diagram illustrating an example operation of a semiconductor memory device. For ease of explanation, the above will be briefly described or omitted. Figures 1 to 10b The repeated parts of the explanation.

[0117] refer to Figure 1 and Figure 11 In a semiconductor device according to some embodiments, the second gate pattern 150B does not overlap with the first gate pattern 150A and the third gate pattern 150C in the vertical direction Z.

[0118] For example, the first gate pattern 150A and the third gate pattern 150C may overlap in the vertical direction Z. A pair of first gate patterns 150A and second gate patterns 150B may be arranged along a first diagonal direction between the first horizontal direction X and the vertical direction Z, and a pair of second gate patterns 150B and third gate patterns 150C may be arranged along a second diagonal direction between the first horizontal direction X and the vertical direction Z. A pair of first gate patterns 150A and second gate patterns 150B may be arranged repeatedly along the first horizontal direction X, and a pair of second gate patterns 150B and third gate patterns 150C may be arranged repeatedly along the first horizontal direction X.

[0119] refer to Figure 12a and Figure 12b For each active pattern 110, the first gate pattern 150A may be disposed on the first side S1 of the first portion 111, but may not be disposed on the second side S2 of the first portion 111. The second gate pattern 150B may be disposed on the second side S2 of the second portion 112, but may not be disposed on the first side S1 of the second portion 112. The third gate pattern 150C may be disposed on the first side S1 of the third portion 113, but may not be disposed on the second side S2 of the third portion 113. The first gate pattern 150A, the second gate pattern 150B, and the third gate pattern 150C may be configured to be energized independently of each other.

[0120] When the high-level voltage V is equal to or higher than the threshold voltageH When all the first gate patterns 150A, second gate patterns 150B and third gate patterns 150C of each active pattern 110 are applied, the corresponding vertical channel transistor VCT can be set to the on state.

[0121] As an example, such as Figure 12a As shown, the high-level voltage V H It can be applied to each of the first gate pattern 150A, the second gate pattern 150B, and the third gate pattern 150C. In this case, the first portion 111 can form a channel with the first gate pattern 150A, the second portion 112 can form a channel with the second gate pattern 150B, and the third portion 113 can form a channel with the third gate pattern 150C. Therefore, the vertical channel transistor can be turned on.

[0122] When the low-level voltage V is equal to or lower than the threshold voltage L When at least one of the first gate pattern 150A, the second gate pattern 150B, or the third gate pattern 150C is applied to each active pattern 110, the corresponding vertical channel transistor VCT can be set to the off state.

[0123] As an example, such as Figure 12b As shown, the high-level voltage V H It can be applied to each of the first gate pattern 150A and the third gate pattern 150C, and the low-level voltage V L A second gate pattern 150B can be applied. In this case, the first portion 111 can form a channel from the first gate pattern 150A, and the third portion 113 can form a channel from the third gate pattern 150C, but the second portion 112 cannot form a channel. Therefore, the vertical channel transistor can be turned off.

[0124] Figure 13 This is an example layout diagram used to illustrate a semiconductor memory device according to some implementation methods. Figure 14 and Figure 15 It is along Figure 13 Various cross-sectional views captured by CC. For ease of explanation, the above will be briefly described or omitted. Figures 1 to 12b The repeated parts of the explanation.

[0125] refer to Figures 13 to 15 The semiconductor device according to some embodiments also includes a back gate pattern 140.

[0126] A back gate pattern 140 may be disposed on the side of each active pattern 110. The back gate pattern 140 may be spaced apart from each active pattern 110 by a gate dielectric film 130. The back gate pattern 140 may intersect with each active pattern 110. For example, the back gate pattern 140 may extend longitudinally in a second horizontal direction Y. Multiple back gate patterns 140 may be spaced apart from each other in a first horizontal direction X and extend side-by-side (or parallel) in the second horizontal direction Y. Each back gate pattern 140 may extend parallel to a row of active patterns 110 arranged along the second horizontal direction Y.

[0127] Each active pattern 110 may be positioned between the gate structure 150 and the back gate pattern 140 in the first horizontal direction X. For example, as Figure 13 As shown, the gate structure 150 and the back gate pattern 140 can be arranged alternately along the first horizontal direction X. A row of active patterns 110 arranged along the second horizontal direction Y can be between a gate structure 150 and a back gate pattern 140.

[0128] The back gate pattern 140 can be configured to have a voltage applied to control the corresponding vertical channel transistor. The back gate pattern 140 can be configured to have a voltage applied independently of the gate structure 150.

[0129] As an example, refer to Figure 14 A high-level voltage equal to or higher than the threshold voltage (e.g., Figure 4a V H It can be applied to all the first gate pattern 150A, the second gate pattern 150B and the back gate pattern 140 to turn on the vertical channel transistor corresponding to each active pattern 110.

[0130] As another example, see Figure 14 In order to turn off the vertical-channel transistor corresponding to each active pattern 110, a low-level voltage equal to or lower than the threshold voltage (e.g., Figure 4a V L It can be applied to at least one of the first gate pattern 150A or the second gate pattern 150B and the back gate pattern 140.

[0131] As an example, refer to Figure 15 In order to turn on the vertical-channel transistor corresponding to each active pattern 110, a high-level voltage equal to or higher than the threshold voltage (e.g., Figure 4a V H It can be applied to all the first gate pattern 150A, the second gate pattern 150B, the third gate pattern 150C and the back gate pattern 140.

[0132] As another example, see Figure 15In order to turn off the vertical-channel transistor corresponding to each active pattern 110, a low-level voltage equal to or lower than the threshold voltage (e.g., Figure 10a V L It can be applied to at least one of the first gate pattern 150A, the second gate pattern 150B, or the third gate pattern 150C and the back gate pattern 140.

[0133] Figure 16 It is a schematic layout diagram used to illustrate a semiconductor memory device according to some embodiments. Figure 17 It is along Figure 16 The cross-sectional view of line DD. Figure 18 It is along Figure 16 The cross-sectional view of line EE. For ease of explanation, the above will be briefly described or omitted. Figures 1 to 15 The repeated parts of the explanation.

[0134] refer to Figures 16 to 18 In a semiconductor device according to some embodiments, a portion of the gate structure 150 overlaps with each active pattern 110 in a second horizontal direction Y.

[0135] For example, a portion of the first gate pattern 150A may be located between pairs of active patterns 110 arranged along the second horizontal direction Y. Alternatively, for example, a portion of the second gate pattern 150B may be located between pairs of active patterns 110 arranged along the second horizontal direction Y.

[0136] exist Figure 16 In the illustration, although the gate structure 150 is shown only as a portion (e.g., three sides) of the periphery of each active pattern 110, this is merely an example. In some embodiments, unlike the example shown, the gate structure 150 may be formed to completely surround the periphery of each active pattern 110 (e.g., four sides).

[0137] In the following text, reference will be made to Figures 1 to 28 A method for manufacturing a semiconductor memory device according to an example embodiment is described.

[0138] Figures 19 to 28 This is an intermediate stage diagram illustrating an example method for manufacturing a semiconductor memory device according to some embodiments. For ease of explanation, the above descriptions will be brief or omitted. Figures 1 to 18 The repeated parts of the explanation.

[0139] Reference Figure 19 An active film 110L is formed on a substrate 100.

[0140] The substrate 100 may be bulk silicon or silicon-on-insulator (SOI). The substrate 100 may be a silicon substrate, or may include other materials, such as silicon germanium, gallium arsenide, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, or gallium antimonide. Optionally, the substrate 100 may be a substrate with an epitaxial layer formed thereon, and may be a ceramic substrate, a quartz substrate, a glass substrate for displays, etc.

[0141] The active film 110L may include semiconductor materials. For example, the active film 110L may include elemental semiconductor materials such as single-crystal silicon (single-crystal Si), polycrystalline silicon (polycrystalline Si), amorphous silicon (amorphous Si), silicon-germanium (SiGe), silicon-germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, for example, the active film 110L may include metal oxide semiconductor materials such as indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO). The active film 110L may be formed by etching a portion of the substrate 100, or the active film 110L may be deposited or grown on the substrate 100.

[0142] Reference Figure 19 and Figure 20 The active film 110L is patterned to form multiple active patterns 110.

[0143] Multiple active patterns 110 can be arranged in two dimensions along a horizontal plane. For example, the active patterns 110 can be arranged in a matrix shape along a first horizontal direction X and a second horizontal direction Y that intersect each other. Each active pattern 110 can extend longitudinally in the vertical direction Z.

[0144] In some implementations, each active pattern 110 may include a first portion 111 and a second portion 112 connected along the vertical direction Z.

[0145] refer to Figure 21 A gate dielectric film 130 is formed on the active pattern 110.

[0146] For example, the gate dielectric film 130 may extend conformally along the contours of the substrate 100 and each active pattern 110.

[0147] Reference Figure 22 Lower spacer 152 and first gate pattern 150A are sequentially formed on gate dielectric film 130.

[0148] The lower spacer 152 and the first gate pattern 150A can be formed on the side surface of each active pattern 110. For example, an insulating film covering the gate dielectric film 130 can be formed, and a recess process can be performed on the insulating film. Therefore, the lower spacer 152 can be formed from the insulating film. Next, a conductive film covering the gate dielectric film 130 and the lower spacer 152 can be formed, and a recess process can be performed on the conductive film. Therefore, the first gate pattern 150A can be formed from the conductive film.

[0149] Reference Figure 23 Intermediate spacers 154 and second gate patterns 150B are sequentially formed on the gate dielectric film 130 and the first gate pattern 150A.

[0150] Intermediate spacer 154 and second gate pattern 150B can be formed on the side surface of each active pattern 110. For example, an insulating film covering the gate dielectric film 130 and the first gate pattern 150A can be formed, and a recessing process can be performed on the insulating film. Therefore, intermediate spacer 154 can be formed from the insulating film. Next, a conductive film covering the gate dielectric film 130 and intermediate spacer 154 can be formed, and a recessing process can be performed on the conductive film. Therefore, second gate pattern 150B can be formed from the conductive film.

[0151] refer to Figure 24 Upper spacer 156 is formed on the second gate pattern 150B.

[0152] Upper spacers 156 can be formed on the side surface of each active pattern 110. For example, an insulating film covering the gate dielectric film 130 and the second gate pattern 150B can be formed, and a recessing process can be performed on the insulating film. Therefore, upper spacers 156 can be formed from the insulating film.

[0153] After the upper spacer 156 is formed, the upper surface of each active pattern 110 can be exposed. For example, a planarization process (e.g., chemical mechanical polishing process) can be performed to expose the upper surface of each active pattern 110.

[0154] refer to Figure 25 This forms the contact pattern BC, the landing pad LP, and the data storage structure 180.

[0155] For example, etch stop film 162 and second interlayer insulating film 164 can be sequentially stacked on multiple active patterns 110, gate dielectric film 130 and upper spacer 156. Contact pattern BC penetrates etch stop film 162 and second interlayer insulating film 164 and can be connected to each active pattern 110.

[0156] Next, the third interlayer insulating film 166 can be stacked on the second interlayer insulating film 164. The landing pad LP penetrates the third interlayer insulating film 166 and can be connected to the contact pattern BC.

[0157] Next, a data storage structure 180 can be formed on the landing pad LP and the third interlayer insulating film 166. The data storage structure 180 may include a lower electrode 182, a capacitor dielectric film 184, and an upper electrode 186 sequentially stacked on the landing pad LP. After the data storage structure 180 is formed, an upper insulating film 190 covering at least a portion of the data storage structure 180 can be formed.

[0158] refer to Figure 25 and Figure 26 Remove the substrate 100.

[0159] For example, the carrier substrate 200 can be attached to Figure 25 As a result, after attaching the carrier substrate 200, it can be reversed. Figure 25 The result is as follows. Next, a thinning process can be performed on the substrate 100. The thinning process may include, but is not limited to, a back-side grinding process on the back side of the substrate 100. When the thinning process is performed, the upper surface of each active pattern 110 can be exposed.

[0160] refer to Figure 27 This forms the conductor 210 and the covering film 220.

[0161] For example, conductors 210 and cover films 220 may be sequentially stacked on a plurality of active patterns 110, gate dielectric films 130, and lower spacers 152. Each of conductors 210 and cover films 220 may extend longitudinally in a first horizontal direction X. Conductors 210 may be collectively connected to a row of active patterns 110 arranged along the first horizontal direction X.

[0162] In some embodiments, the wire 210 may include a first conductive film 212, a second conductive film 214 and a third conductive film 216 stacked in sequence.

[0163] refer to Figure 28 This forms a liner film 240, a spacer film 245, and a shielding conductive film 250.

[0164] The gasket film 240 can be stacked on the conductor 210 and the cover film 220. The spacer film 245 can be stacked on the gasket film 240. The shielding conductive film 250 can be stacked on the spacer film 245.

[0165] At least a portion of the shielding conductive film 250 may be located between the conductors 210 arranged along the second horizontal direction Y. For example, the shielding conductive film 250 may be formed to fill at least a portion of the area between one conductor 210 and another conductor 210. After the shielding conductive film 250 is formed, a lower insulating film 260 may be formed covering at least a portion of the shielding conductive film 250.

[0166] Next, refer to Figures 1 to 3 Remove the carrier substrate 200. Therefore, it is possible to manufacture the product used above. Figures 1 to 3 The semiconductor memory device described.

[0167] While this specification contains numerous specific details of implementation, these should not be construed as limiting the scope of any invention or the scope that can be claimed, but rather as descriptions of features specific to particular embodiments that may be tailored to particular inventions. Certain features described in the context of separate embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from a combination may be removed from that combination, and the combination may be for sub-combinations or variations thereof.

[0168] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the embodiments described above, but can be implemented in various different forms. Those skilled in the art will understand that the present disclosure can be practiced in other specific forms without altering the technical spirit or essential characteristics of the present disclosure. Therefore, it should be understood that the embodiments described above are not limiting, but illustrative in all respects.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: An active pattern, the active pattern comprising a first part and a second part, wherein the first part and the second part are connected along a vertical direction; A wire, the wire being located on the lower surface of the active pattern, wherein the wire is connected to the active pattern and extends in a first horizontal direction intersecting the vertical direction; A first gate pattern is located on the side of the first portion of the active pattern, wherein the first gate pattern extends in a second horizontal direction that intersects the vertical direction and the first horizontal direction. A second gate pattern, located on the side of the second portion of the active pattern, wherein the second gate pattern is spaced apart from the first gate pattern and extends in the second horizontal direction; and A data storage structure is located on the upper surface of the active pattern, wherein the data storage structure is connected to the active pattern.

2. The semiconductor memory device according to claim 1, further comprising: A gate dielectric film is located between the active pattern and the first gate pattern and between the active pattern and the second gate pattern, and extends along the side of the active pattern.

3. The semiconductor memory device according to claim 1, wherein, The first gate pattern and the second gate pattern overlap in the vertical direction.

4. The semiconductor memory device according to claim 1, wherein, The first gate pattern and the second gate pattern do not overlap in the vertical direction.

5. The semiconductor memory device according to claim 1, wherein, The active pattern includes a third portion connected to the second portion along the vertical direction, and The semiconductor memory device further includes a third gate pattern located on the side of the third portion of the active pattern, wherein the third gate pattern is spaced apart from the first gate pattern and the second gate pattern and extends in the second horizontal direction.

6. The semiconductor memory device according to claim 5, wherein, The first gate pattern, the second gate pattern, and the third gate pattern overlap in the vertical direction.

7. The semiconductor memory device according to claim 5, wherein, The first gate pattern and the third gate pattern overlap in the vertical direction, and The second gate pattern does not overlap with the first gate pattern and the third gate pattern in the vertical direction.

8. The semiconductor memory device according to claim 1, wherein, A portion of the first gate pattern or a portion of the second gate pattern overlaps with the active pattern in the second horizontal direction.

9. The semiconductor memory device according to claim 1, wherein, The data storage structure includes a lower electrode, a capacitor dielectric film, and an upper electrode sequentially stacked on the upper surface of the active pattern.

10. The semiconductor memory device according to claim 1, wherein, The first gate pattern and the second gate pattern are configured to be applied voltages independently of each other.

11. A semiconductor memory device, the semiconductor memory device comprising: An active pattern that extends in the vertical direction; A wire, the wire being located on the lower surface of the active pattern, wherein the wire is connected to the active pattern and extends in a first horizontal direction intersecting the vertical direction; A gate structure located on a side of the active pattern, wherein the gate structure comprises a plurality of gate patterns located at different heights and spaced apart from each other in the vertical direction, each of the plurality of gate patterns extending in a second horizontal direction intersecting the vertical direction and the first horizontal direction; and A data storage structure is located on the upper surface of the active pattern, wherein the data storage structure is connected to the active pattern.

12. The semiconductor memory device of claim 11, further comprising: A lower spacer, the lower spacer being located between the conductor and the gate structure.

13. The semiconductor memory device of claim 11, further comprising: An upper spacer is located between the gate structure and the data storage structure.

14. The semiconductor memory device according to claim 11, wherein, The data storage structure includes a lower electrode, a capacitor dielectric film, and an upper electrode sequentially stacked on the upper surface of the active pattern.

15. The semiconductor memory device according to claim 11, wherein, The plurality of gate patterns are configured to be applied voltages independently of each other.

16. A semiconductor memory device, the semiconductor memory device comprising: An active pattern comprising a first portion and a second portion, wherein the first portion and the second portion are connected along a vertical direction, wherein the active pattern comprises a first side and a second side opposite to each other in a first horizontal direction intersecting the vertical direction; A wire, the wire being located on the lower surface of the active pattern, wherein the wire is connected to the active pattern and extends in the first horizontal direction; A first gate pattern is located on the first side of the first portion, wherein the first gate pattern extends in a second horizontal direction that intersects the vertical direction and the first horizontal direction; A second gate pattern, the second gate pattern being located on the second side of the second portion, wherein the second gate pattern extends in the second horizontal direction; and A data storage structure is located on the upper surface of the active pattern, wherein the data storage structure is connected to the active pattern.

17. The semiconductor memory device according to claim 16, wherein, The first gate pattern and the second gate pattern do not overlap in the first horizontal direction.

18. The semiconductor memory device according to claim 16, wherein, A portion of the first gate pattern and a portion of the second gate pattern overlap in the first horizontal direction.

19. The semiconductor memory device according to claim 16, wherein, The data storage structure includes a lower electrode, a capacitor dielectric film, and an upper electrode sequentially stacked on the upper surface of the active pattern.

20. The semiconductor memory device according to claim 16, wherein, The first gate pattern and the second gate pattern are configured to be applied voltages independently of each other.

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