Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes: a substrate including a cell region and a peripheral region, the cell region including a cell active region; a plurality of bit line structures extending in a first horizontal direction; a memory contact connected to the cell active region; a first memory pad connected to the memory contact; a data storage pattern connected to the first memory pad; a peripheral gate structure disposed on the peripheral region; and a peripheral contact plug on both sides of the peripheral gate structure and connected to the substrate. The first memory pad includes a first silicide film on the memory contact and a first conductive film on the first silicide film. The peripheral contact plug includes a recess extending vertically into the substrate, a second silicide film on the bottom side of the recess, a second conductive film extending along the sidewall of the recess, and a third conductive film filling the interior of the recess. The width of the first conductive film is different from the width of the second conductive film in the second horizontal direction.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0048273, filed on April 14, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor memory devices. Background Technology

[0003] In response to the rapid development of the electronics industry and user demands, electronic devices are becoming smaller and lighter. Therefore, there is a need for highly integrated semiconductor components used in electronic devices, and the design rules for constructing these semiconductor components are decreasing. Summary of the Invention

[0004] This disclosure provides semiconductor memory devices with improved performance and reliability.

[0005] However, the aspects of this disclosure are not limited to those set forth herein. The above and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description of this disclosure given below.

[0006] A semiconductor memory device according to some embodiments of the present disclosure includes: a substrate including a cell region and a peripheral region defined around the cell region, the cell region including a cell active region defined by a cell element separation film; a plurality of bit line structures extending in a first horizontal direction on each of the cell element separation film and the cell active region; a storage contact connected to the cell active region between the plurality of bit line structures; a first storage pad connected to the storage contact; a data storage pattern connected to the first storage pad; a peripheral gate structure disposed on the substrate of the peripheral region; and a peripheral contact plug disposed on the peripheral region. The gate structure is located on both sides and connected to the substrate. The first storage pad includes a first silicide film and a first conductive film. The first silicide film is on the storage contact, and the first conductive film is on the first silicide film. The peripheral contact plug includes a recess, a second silicide film, a second conductive film, and a third conductive film. The recess extends vertically into the substrate. The second silicide film is on the bottom side of the recess. The second conductive film extends along the sidewall of the recess on the second silicide film. The third conductive film fills the interior of the recess on the second conductive film. In a second horizontal direction different from the first horizontal direction, the width of the first conductive film is different from the width of the second conductive film.

[0007] A semiconductor memory device according to some embodiments of the present disclosure includes: a substrate including a cell region and a peripheral region defined around the cell region, the cell region including a cell active region defined by a cell element separation film; a plurality of cell wires extending in a horizontal direction on each of the cell element separation film and the cell active region; a storage contact connected to the cell active region between the plurality of cell wires; a first storage pad connected to the storage contact; a data storage pattern connected to the first storage pad; a second storage pad between the first storage pad and the data storage pattern; a peripheral gate structure disposed on the substrate of the peripheral region; and a peripheral contact plug disposed on... On both sides of the peripheral gate structure and connected to the substrate; and peripheral wiring connected to the peripheral contact plug, on the peripheral gate structure, wherein the first storage pad includes a first silicide film and a first conductive film, the first silicide film on the storage contact, the first conductive film on the first silicide film, the peripheral contact plug including a recess, a second silicide film, a second conductive film and a third conductive film, the recess extending vertically into the substrate, the second silicide film on the bottom side of the recess, the second conductive film extending along the sidewall of the recess on the second silicide film, the third conductive film filling the interior of the recess on the second conductive film, and the thickness of the first conductive film in the vertical direction being greater than the thickness of the second storage pad.

[0008] A semiconductor memory device according to some embodiments of the present disclosure includes: a substrate including cell regions and a peripheral region defined around the cell regions, the cell regions including cell active regions defined by cell element separation films; a plurality of bit line structures extending in a horizontal direction on each of the cell element separation films and the cell active regions; memory contacts connected between the plurality of bit line structures to the cell active regions of the cell regions; a memory pad structure connected to the memory contacts; a data storage pattern connected to the memory pad structure; a peripheral gate structure disposed on the substrate of the peripheral regions; an interlayer insulating film disposed on the peripheral gate structure; peripheral contact plugs disposed on both sides of the peripheral gate structure, penetrating the interlayer insulating film and connected to the substrate; and peripheral wiring connected to the peripheral contact plugs on the peripheral gate structure, wherein the memory pad structure includes a first memory pad structure. A storage pad and a second storage pad, the first storage pad being on a storage contact, the second storage pad being between the first storage pad and a data storage pattern, the first storage pad including a first silicide film and a first conductive film, the first silicide film being on the storage contact, the first conductive film being on the first silicide film, a peripheral contact plug including a recess, a second silicide film, a second conductive film and a third conductive film, the recess extending vertically into the substrate, the second silicide film being on the bottom side of the recess, the second conductive film extending along the sidewall of the recess on the second silicide film, the third conductive film filling the interior of the recess on the second conductive film, the upper side of the bit line structure being located at the same vertical level as the upper side of the interlayer insulating film, the upper side of the second storage pad being located at the same vertical level as the upper side of the peripheral wiring, each of the first and second conductive films including titanium nitride, and each of the second storage pad and the third conductive film including tungsten.

[0009] A method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure includes: setting a substrate, the substrate including a cell region and a peripheral region defined around the cell region; forming a cell active region in the substrate of the cell region, the cell active region being defined by a cell element separation film; forming a plurality of bit line structures on the cell element separation film and the cell active region; forming a peripheral gate structure on the substrate of the peripheral region; forming a memory contact between the plurality of bit line structures, the memory contact being connected to the cell active region; forming a first silicide film and a first conductive film on the memory contact, the first conductive film being on the first silicide film; forming a cell protective film on the first conductive film of the cell region; and forming recesses on both sides of the peripheral gate structure. The recess extends into the substrate; a second silicide film and a pre-second conductive film are formed, the second silicide film being on the bottom side of the recess, and the pre-second conductive film extending along the sidewall of the recess on the second silicide film; a pre-third conductive film is formed on the pre-second conductive film, the pre-third conductive film filling the interior of the recess; the unit protective film of the unit region is removed; at least a portion of the pre-second conductive film and the pre-third conductive film of the peripheral region are removed to form the second conductive film and the third conductive film; a pre-fourth conductive film is formed on the first conductive film of the unit region; a pre-fifth conductive film is formed on the third conductive film of the peripheral region; the pre-fourth conductive film of the unit region is patterned to form the fourth conductive film; and the pre-fifth conductive film of the peripheral region is patterned to form the fifth conductive film.

[0010] Specific details of other embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0011] The above and other aspects and features of this disclosure will become clearer from the detailed description of illustrative embodiments with reference to the accompanying drawings.

[0012] Figure 1 This is a schematic layout diagram of a semiconductor memory device according to some embodiments.

[0013] Figure 2 Is as Figure 1 The layout of region R, which is part of the unit region.

[0014] Figure 3 Is only shown Figure 2 The layout of the character lines and active areas.

[0015] Figure 4 It is along Figure 2 The sectional view taken by line AA.

[0016] Figure 5 It is along Figure 1 The sectional view taken by line BB.

[0017] Figure 6 It is along Figure 2 The sectional view taken by the CC line.

[0018] Figure 7 This is a layout diagram used to explain a semiconductor memory device according to some embodiments.

[0019] Figure 8 This is a perspective view used to explain a semiconductor memory device according to some embodiments.

[0020] Figure 9 It is along Figure 7 The sectional view taken from lines DD and EE.

[0021] Figure 10 This is a layout diagram used to explain a semiconductor memory device according to some embodiments.

[0022] Figure 11 This is a perspective view used to explain a semiconductor memory device according to some embodiments.

[0023] Figure 12 These are diagrams used to explain semiconductor memory devices according to some embodiments.

[0024] Figures 13 to 20 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor memory device according to some embodiments. Detailed Implementation

[0025] While terms such as “first” and “second” are used to describe various elements or components in this specification, it is not to be construed that these elements or components are not limited by these terms. These terms are used only to distinguish individual elements or components from other elements or components. Therefore, it is not to be construed that, within the technical concept of this disclosure, a first element or component mentioned below may be a second element or component.

[0026] Figure 1 This is a schematic layout diagram of a semiconductor memory device according to some embodiments. Figure 2 Is as Figure 1 The layout of region R, which is part of the unit region. Figure 3 Is only shown Figure 2 The layout of the character lines and active areas. Figure 4 It is along Figure 2 The sectional view taken by line AA. Figure 5 It is along Figure 1 The sectional view taken by line BB. Figure 6 It is along Figure 2 The sectional view taken by the CC line.

[0027] For reference, Figure 5An exemplary cross-sectional view may be taken through the transistor formation region of the periphery. Although the cut line BB is indicated along... Figure 1 The first direction D1 is used for cutting, but the embodiment is not limited to this. Unlike the example shown, the cutting line BB can be indicated as cutting along the second direction D2.

[0028] In the illustrations relating to semiconductor memory devices according to some embodiments, although dynamic random access memory (DRAM) is shown as an example, the embodiments are not limited thereto.

[0029] Reference Figures 1 to 3 According to some embodiments, a semiconductor memory device may include a cell region 20, a cell region separation film 22, and a peripheral region 24.

[0030] The unit region separation membrane 22 may be formed along the periphery of the unit region 20. The unit region separation membrane 22 may separate the unit region 20 from the peripheral region 24. The peripheral region 24 may be defined around the unit region 20.

[0031] The cell region 20 may include multiple cell active regions ACT. The cell active regions ACT may be formed on a substrate ( Figure 4 The unit element separation membrane in 100) Figure 4 (105) is defined. As the design rules for semiconductor memory devices become more restrictive, as shown, the cell active region ACT can be arranged in the form of diagonal or slanted bars. For example, the cell active region ACT can extend on the third direction D3.

[0032] Multiple gate electrodes may be arranged across the cell active region ACT in the first direction D1. The multiple gate electrodes may extend parallel to each other. The multiple gate electrodes may be, for example, multiple word lines WL. The word lines WL may be arranged at equal intervals. The width of the word lines WL or the interval between word lines WL may be determined according to design rules.

[0033] Each cell active region ACT can be divided into three parts by two word lines WL extending in the first direction D1. The cell active region ACT may include a bit line connection region 103a and a memory connection region 103b. The bit line connection region 103a may be located in the central part of the cell active region ACT, and the memory connection region 103b may be located at the end of the cell active region ACT.

[0034] Multiple bit lines BL extending in a second direction D2 orthogonal to the word line WL can be set on the word line WL. The multiple bit lines BL can extend parallel to each other. The bit lines BL can be set at regular intervals. The width of the bit lines BL or the interval between the bit lines BL can be determined according to design rules.

[0035] Semiconductor memory devices according to some embodiments may include various contact arrangements formed on the cell active region ACT. Various contact arrangements may include, for example, direct contacts DC, buried contacts BC, landing pads (or mats, contact pads, or landing pads) LP, etc.

[0036] Here, the direct contact DC can mean the contact that electrically connects the cell's active region ACT to the bit line BL. The buried contact BC can mean the contact that connects the cell's active region ACT to the lower electrode of the capacitor. Figure 4 The contact element (191) is located in the cell. Due to the layout structure, the contact area between the buried contact element BC and the cell active region ACT may be small. Therefore, a conductive bonding pad LP can be introduced to increase the contact area between the buried contact element BC and the cell active region ACT, and to increase the contact area between the buried contact element BC and the lower electrode of the capacitor ( ). Figure 4 The contact area between 191 and 191.

[0037] The bonding pad LP can be positioned between the buried contact BC and the lower electrode of the capacitor. Figure 4 The bonding pad LP can be disposed between the cell active region ACT and the buried contact BC. In a semiconductor memory device according to some embodiments, the bonding pad LP can be disposed between the buried contact BC and the lower electrode 191 of the capacitor. By increasing the contact area through the introduction of the bonding pad LP, the contact resistance between the cell active region ACT and the lower electrode 191 of the capacitor can be reduced.

[0038] Direct contact DC can be connected to bit line connection area 103a. Buried contact BC can be connected to storage connection area 103b. Since the buried contact BC is located at both ends (or both ends) of the cell active region ACT, the bonding pad LP can be configured to be adjacent to both ends of the cell active region ACT to partially overlap with the buried contact BC. In other words, the buried contact BC can be formed between the cell active region ACT and the cell element separation film between the adjacent word line WL and the adjacent bit line BL. Figure 4 105) stacked.

[0039] The word line WL can be formed as a structure embedded within the substrate 100. The word line WL can be positioned across the active cell region ACT between the direct contact DC and the embedded contact BC. As shown, two word lines WL can be configured to intersect one active cell region ACT. Since the active cell region ACT extends along the third direction D3, the word line WL can have an angle of less than 90 degrees with the active cell region ACT.

[0040] The direct contact element DC and the buried contact element BC can be arranged symmetrically. Therefore, the direct contact element DC and the buried contact element BC can be arranged on a straight line along the first direction D1 and the second direction D2.

[0041] Meanwhile, unlike the direct contact DC and the buried contact BC, the bonding pad LP can be arranged in a zigzag pattern along the second direction D2 along which the bit line BL extends. Furthermore, the bonding pad LP can be configured to overlap the same side portion of each bit line BL along the first direction D1 along which the word line WL extends.

[0042] For example, each of the bonding pads LP of the first line may be stacked to the left of the corresponding bit line BL, and each of the bonding pads LP of the second line may be stacked to the right of the corresponding bit line BL.

[0043] Reference Figures 1 to 6 According to some embodiments, a semiconductor memory device may include a plurality of cell gate structures 110, a plurality of bit line structures 140ST, a plurality of memory contacts 120, a plurality of memory pad structures 160ST, a data storage pattern 190, a peripheral gate structure 240ST, a peripheral contact plug 260, and a peripheral wiring line 265.

[0044] The substrate 100 may include a cell region 20, a cell region separation film 22, and a peripheral region 24. The substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate 100 may include, but is not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0045] Multiple cell gate structures 110, multiple bit line structures 140ST, multiple memory contacts 120, multiple memory pads 160, and data storage patterns 190 may be disposed in the cell region 20. Peripheral gate structures 240ST, peripheral contact plugs 260, and peripheral wiring 265 may be disposed in the peripheral region 24.

[0046] A unit element separation membrane 105 may be formed in the unit region 20 of the substrate 100. The unit element separation membrane 105 may have a shallow trench isolation (STI) structure with excellent isolation properties. The unit element separation membrane 105 may define the active unit region ACT within the unit region 20. For example... Figure 2 and Figure 3As shown, the active cell region ACT defined by the cell element separation membrane 105 may have an elongated island shape including a short axis and a long axis. The active cell region ACT may have a slanted shape with an angle of less than 90 degrees relative to the word line WL formed in the cell element separation membrane 105. Furthermore, the active cell region ACT may have a slanted shape with an angle of less than 90 degrees relative to the bit line BL formed on the cell element separation membrane 105.

[0047] The unit region separation membrane 22 may also have an STI structure. The unit region 20 may be defined by the unit region separation membrane 22.

[0048] Each of the unit element separation membrane 105 and the unit region separation membrane 22 may include, for example, but not limited to, at least one of a silicon oxide membrane, a silicon nitride membrane, and a silicon oxynitride membrane. Figure 4 and Figure 6 Although the unit element separation membrane 105 is shown as being formed of a single insulating film, this is for ease of explanation only, and the embodiments are not limited thereto. Depending on the width of the unit element separation membrane 105 and the unit region separation membrane 22, each of the unit element separation membrane 105 and the unit region separation membrane 22 may be formed of one or more insulating films.

[0049] Although the upper side of the unit element separation membrane 105 and the upper side of the substrate 100 are shown as in Figure 4 and Figure 6 The components are placed on the same plane, but this is only for ease of explanation, and the embodiments are not limited thereto. In some embodiments, the upper side of the component may refer to the upper surface of the component, and the lower side of the component may refer to the lower surface of the component, but is not limited thereto.

[0050] The cell gate structure 110 may be disposed within the substrate 100 and the cell element separation film 105. The cell gate structure 110 may be configured to span the cell element separation film 105 and the cell active region ACT defined by the cell element separation film 105. The cell gate structure 110 may include a cell gate trench 115, a cell gate insulating film 111, a cell gate electrode 112, a cell gate cover pattern 113, and a cell gate cover conductive film 114 formed within the substrate 100 and the cell element separation film 105. Here, the cell gate electrode 112 may correspond to a word line WL. Unlike the example shown, the cell gate structure 110 may not include the cell gate cover conductive film 114.

[0051] The cell gate trench 115 can be relatively deep in the cell element separation film 105 and relatively shallow in the cell active region ACT. The bottom side of the cell gate electrode 112 can be curved. That is, the depth of the cell gate trench 115 in the cell element separation film 105 can be greater than the depth of the cell gate trench 115 in the cell active region ACT.

[0052] The cell gate insulating film 111 may extend along the sidewalls and bottom of the cell gate trench 115. The cell gate insulating film 111 may extend along the contour of at least a portion of the cell gate trench 115. The cell gate insulating film 111 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material having a higher dielectric constant than silicon oxide. The high dielectric constant material may include at least one of, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0053] A unit gate electrode 112 may be formed on a unit gate insulating film 111. The unit gate electrode 112 may fill a portion of a unit gate trench 115. A unit gate covering conductive film 114 may extend along the upper side of the unit gate electrode 112.

[0054] The unit gate electrode 112 may include at least one of the following: metal, conductive metal nitride, conductive metal carbonitride, conductive metal carbide, metal silicide, doped semiconductor material, conductive metal oxynitride, and conductive metal oxide. The unit gate electrode 112 may include, for example, but not limited to, TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, and IrO. x RuO x and at least one of their combinations. The cell gate covering conductive film 114 may include, for example, but not limited to, polycrystalline silicon or polycrystalline silicon germanium.

[0055] A cell gate cover pattern 113 may be disposed on the cell gate electrode 112 and the cell gate cover conductive film 114. The cell gate cover pattern 113 may fill the remaining cell gate trench 115 after the cell gate electrode 112 and the cell gate cover conductive film 114 are formed. Although the cell gate insulating film 111 is shown extending along the sidewall of the cell gate cover pattern 113, the embodiment is not limited thereto.

[0056] The cell gate cover pattern 113 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof.

[0057] Although not shown, impurity-doped regions may be formed on at least one side of the cell gate structure 110. The impurity-doped regions may be the source / drain regions of a transistor.

[0058] Bit line structure 140ST may include cell conductors 140 and cell line cover film 144. In an embodiment, bit line structure 140ST may extend in a second direction D2 on each of cell element separation film 105 and cell active region ACT. Cell conductors 140 may be disposed on substrate 100 in which cell gate structure 110 is disposed and cell element separation film 105.

[0059] The cell conductor 140 may extend in the second direction D2. The cell conductor 140 may intersect with the cell element separation film 105 and the cell active region ACT defined by the cell element separation film 105. The cell conductor 140 may be formed to intersect with the cell gate structure 110. Here, the cell conductor 140 may correspond to the bit line BL.

[0060] The unit conductor 140 may be a multilayer film. The unit conductor 140 may include, for example, a first unit conductive film 141, a second unit conductive film 142, and a third unit conductive film 143. The first to third unit conductive films 141, 142, and 143 may be sequentially stacked on the substrate 100 and the unit element separation film 105. Although the unit conductor 140 is shown as a three-layer film, the embodiment is not limited thereto.

[0061] Each of the first to third conductive films 141, 142, and 143 may include at least one of a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a two-dimensional material (2D material), and a metal. In a semiconductor memory device according to some embodiments, the two-dimensional material may be a metallic material and / or a semiconductor material. The two-dimensional material (2D material) may include two-dimensional allotropes or two-dimensional compounds, and may include, for example, but not limited to, at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2). That is, the two-dimensional materials mentioned above are merely listed as examples, and the two-dimensional materials that may be included in the semiconductor memory device of this disclosure are not limited to those mentioned above.

[0062] For example, the first unit conductive film 141 may include a doped semiconductor material, the second unit conductive film 142 may include at least one of a conductive silicide compound, a conductive metal nitride, and a two-dimensional material, and the third unit conductive film 143 may include, but is not limited to, a metal.

[0063] Bit line contact 146 may be disposed between cell conductor 140 and substrate 100. That is, cell conductor 140 may be disposed on bit line contact 146. For example, bit line contact 146 may be formed at the point where cell conductor 140 intersects with the central portion of cell active region ACT having an elongated island shape. Bit line contact 146 may be disposed between bit line connection region 103a and cell conductor 140.

[0064] Bit line contact 146 can electrically connect unit wire 140 and substrate 100. Here, bit line contact 146 may correspond to direct contact DC. Bit line contact 146 may include at least one of, for example, doped semiconductor material, conductive silicide compound, conductive metal nitride, and metal.

[0065] exist Figure 4 In the configuration, the unit conductor 140 may include a second unit conductive film 142 and a third unit conductive film 143 in the region overlapping with the bit line contact 146. In the region not overlapping with the bit line contact 146, the unit conductor 140 may include a first unit conductive film to a third unit conductive film 141, 142, and 143. The thickness of the unit conductor 140 in the region overlapping with the bit line contact 146 may differ from the thickness in the region not overlapping with the bit line contact 146.

[0066] A cell line cover film 144 may be disposed on the cell conductor 140. The cell line cover film 144 may extend along the upper side of the cell conductor 140 in a second direction D2. In this case, the cell line cover film 144 may include at least one of, for example, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride. In a semiconductor memory device according to some embodiments, the cell line cover film 144 may include, for example, a silicon nitride film. Although the cell line cover film 144 is shown as a single film, the embodiments are not limited thereto. That is, the cell line cover film 144 may be a multilayer film. However, if each film constituting the multilayer film is made of the same material, the cell line cover film 144 may be considered a single film.

[0067] The unit insulating film 130 may be disposed on the substrate 100 and the unit element separation film 105. More specifically, the unit insulating film 130 may be disposed on the substrate 100 and the unit element separation film 105 on which the bit line contact 146 is not formed. The unit insulating film 130 may be disposed between the substrate 100 and the unit wire 140, and between the unit element separation film 105 and the unit wire 140.

[0068] Although the unit insulating film 130 may be a single film, as shown, it may be a multilayer film comprising a first unit insulating film 131 and a second unit insulating film 132. For example, the first unit insulating film 131 may comprise a silicon oxide film, and the second unit insulating film 132 may include, but is not limited to, a silicon nitride film. Needless to say, unlike the example shown, the unit insulating film 130 may comprise three or more insulating films. When the unit insulating film 130 includes a third unit insulating film, the third unit insulating film may be a silicon oxide film.

[0069] In sectional views (such as, Figure 4 In the process, the upper side 100US of the substrate 100 may be defined at the boundary between the unit insulating film 130 and the substrate 100.

[0070] The unit line spacer 150 can be disposed on the sidewalls of the unit line conductor 140 and the unit line cover film 144. The unit line spacer 150 can be disposed on the substrate 100 and the unit element separation film 105 at a portion of the bit line structure 140ST where the bit line contact 146 is provided. The unit line spacer 150 can be disposed on the sidewalls of the unit line conductor 140, the unit line cover film 144, and the bit line contact 146.

[0071] In the remaining portion of the bit line structure 140ST where the bit line contact 146 is not formed, a unit line spacer 150 may be disposed on the unit insulating film 130. The unit line spacer 150 may be disposed on the sidewall of the unit conductor 140 and the unit line cover film 144.

[0072] The unit line spacer 150 can be disposed on the long sidewall of the bit line structure 140ST that extends longitudinally in the second direction D2.

[0073] Although the unit line spacer 150 may be a single film, as shown, it may be a multilayer film comprising first to fourth unit line spacers 151, 152, 153, and 154. For example, the first to fourth unit line spacers 151, 152, 153, and 154 may include, but are not limited to, silicon oxide films, silicon nitride films, silicon oxynitride (SiON) films, silicon carbonitride (SiOCN) films, air, and combinations thereof. For example, the second unit line spacer 152 may not be disposed on the unit insulating film 130, but may instead be disposed on the sidewall of the bit line contact 146.

[0074] A gate pattern 170 may be disposed on the substrate 100 and the cell element separation film 105. The gate pattern 170 may be formed to overlap with a cell gate structure 110 formed within the substrate 100 and the cell element separation film 105. The gate pattern 170 may be disposed between bit line structures 140ST extending in the second direction D2. The gate pattern 170 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0075] Multiple storage contacts 120 may be disposed between adjacent unit conductors 140 in the first direction D1. Storage contacts 120 may be disposed between adjacent fence patterns 170 in the second direction D2. Storage contacts 120 may be stacked with the substrate 100 and the unit element separation membrane 105 between adjacent unit conductors 140. Storage contacts 120 may be connected to the active region ACT. Storage contacts 120 may be connected to the storage connection region 103b of the unit active region ACT. Here, storage contacts 120 may correspond to buried contacts BC.

[0076] The storage contact 120 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, and a metal.

[0077] Multiple storage pad structures 160ST may be disposed on the storage contact 120. The storage pad structures 160ST may be electrically connected to the storage contact 120. Here, the storage pad structures 160ST may correspond to the engagement pad LP.

[0078] The storage pad structure 160ST may include a first storage pad 160 disposed on the storage contact 120 and a second storage pad 165 disposed on the first storage pad 160. The second storage pad 165 may be disposed between the first storage pad 160 and the data storage pattern 190.

[0079] The storage pad structure 160ST can be stacked on a portion of the upper side of the bit line structure 140ST. For example, the storage pad structure 160ST can be stacked on the upper side 144US of the cell line cover film in the thickness direction of the substrate 100.

[0080] The first storage pad 160 may include a first silicide film 161 and a first conductive film 162. The first silicide film 161 may be disposed between the storage contact 120 and the first conductive film 162. In other words, the first silicide film 161 may be disposed on the storage contact 120, and the first conductive film 162 may be disposed on the first silicide film 162. The first silicide film 161 may be connected to the storage contact 120. The first silicide film 161 may include a metal silicide compound. The first silicide film 161 may include at least one of, for example, but not limited to, cobalt (Co), titanium (Ti), and / or nickel (Ni).

[0081] The upper side 162US of the first conductive film may be disposed on the same plane as the upper side 144US of the unit line cover film. In the fourth direction D4, the thickness T1 of the first conductive film 162 may be different from the thickness T2 of the second storage pad 165. For example, in the fourth direction D4, the thickness T1 of the first conductive film 162 may be greater than the thickness T2 of the second storage pad 165.

[0082] The first conductive film 162 and the second storage pad 165 may include conductive materials. The first conductive film 162 may include at least one of, for example, conductive silicide compounds, conductive metal nitrides, conductive metal carbides, conductive metal oxides, and conductive metal carbonitrides. The first conductive film 162 may include, but is not limited to, titanium nitride (TiN). The second storage pad 165 may include a metal. For example, the second storage pad 165 may be formed of a metal. The second storage pad 165 may include, but is not limited to, tungsten (W).

[0083] The pad separation pattern 180 can be formed on the storage pad structure 160ST and the bit line structure 140ST. For example, the pad separation pattern 180 can be provided on the cell line cover film 144.

[0084] The pad separation pattern 180 can define the area of ​​the storage pad structure 160ST that forms multiple isolation regions. The pad separation pattern 180 can separate adjacent storage pad structures 160ST.

[0085] The pad separation pattern 180 does not cover the upper side of the storage pad structure 160ST. The upper side 180US of the pad separation pattern 180 may be disposed on the same plane as the upper side of the storage pad structure 160ST.

[0086] The pad separation pattern 180 includes an insulating material. The pad separation pattern 180 can electrically isolate a plurality of storage pad structures 160ST from each other. For example, the pad separation pattern 180 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon carbonitride film, and a silicon carbonitride film.

[0087] An upper etch stop film 297 may be disposed on the pad separation pattern 180 and the storage pad structure 160ST. The upper etch stop film 297 may extend to the peripheral region 24 and the cell region 20. The upper etch stop film 297 may include, for example, but not limited to, at least one of silicon nitride film, silicon carbonitride film, silicon boron nitride (SiBN) film, silicon oxynitride film, and silicon oxycarbonate film.

[0088] Data storage pattern 190 may be disposed on storage pad structure 160ST. Data storage pattern 190 may be electrically connected to storage pad structure 160ST.

[0089] A portion of the data storage pattern 190 may be disposed within the upper etch stop film 297. The data storage pattern 190 may include, for example, but not limited to, a capacitor. The data storage pattern 190 includes a lower electrode 191, a capacitor dielectric film 192, and an upper electrode 193.

[0090] The lower electrode 191 may be disposed on the storage pad structure 160ST. The lower electrode 191 may contact the second storage pad 165. The lower electrode 191 is shown to have a cylindrical shape, but is not limited thereto. Of course, the lower electrode 191 may have a cylindrical shape.

[0091] A capacitor dielectric film 192 is disposed on the lower electrode 191. The capacitor dielectric film 192 may be formed along the contour of the lower electrode 191. An upper electrode 193 is disposed on the capacitor dielectric film 192. The upper electrode 193 may cover the outer wall of the lower electrode 191.

[0092] For example, the capacitor dielectric film 192 may be disposed in the portion vertically stacked with the upper electrode 193. The capacitor dielectric film 192 may not extend into the peripheral region 24.

[0093] Each of the lower electrode 191 and the upper electrode 193 may include, but is not limited to, doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, niobium nitride or tungsten nitride) or metals (e.g., ruthenium, iridium, titanium, tantalum or niobium).

[0094] For example, the capacitor dielectric film 192 may include at least one of ferroelectric material, antiferroelectric material, and paraelectric material. For example, the capacitor dielectric film 192 may include one of the following: ferroelectric material, antiferroelectric material, paraelectric material, combination of ferroelectric and antiferroelectric material, combination of ferroelectric and paraelectric material, combination of paraelectric and antiferroelectric material, and combination of ferroelectric, antiferroelectric, and paraelectric material.

[0095] As an example, the capacitor dielectric film 192 may include a stacked film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in sequence. As another example, the capacitor dielectric film 192 may include a dielectric film containing hafnium (Hf). The above-mentioned contents regarding the materials of the capacitor dielectric film 192 are merely exemplary, and the technical ideas of this disclosure are not limited thereto.

[0096] Unlike the above, the data storage pattern 190 can be a variable resistance pattern that can switch between two resistance states by an electrical pulse applied to the memory element. For example, the data storage pattern 190 may include a phase change material, perovskite compound, transition metal oxide, magnetic material, ferromagnetic material, or antiferromagnetic material whose crystal state changes according to the amount of current.

[0097] A peripheral component separation film 26 may be formed within the peripheral region 24 of the substrate 100. The peripheral component separation film 26 may define a peripheral active region within the peripheral region 24. The upper side of the peripheral component separation film 26 is shown as being coplanar with the upper side 100US of the substrate, but the embodiment is not limited thereto. The peripheral component separation film 26 may include, for example, but not limited to, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0098] The peripheral gate structure 240ST may be disposed on the peripheral region 24 of the substrate 100. The peripheral gate structure 240ST may be disposed on the peripheral active region defined by the peripheral element separation film 26.

[0099] The peripheral gate structure 240ST may include a peripheral gate insulating film 230, a peripheral gate conductive film 240, and a peripheral cover film 244 sequentially stacked on the substrate 100. The peripheral gate structure 240ST may include peripheral spacers 245 disposed on the sidewalls of the peripheral gate conductive film 240 and the peripheral cover film 244.

[0100] The peripheral gate conductive film 240 may include a first to a third peripheral conductive film 241, 242, and 243 sequentially stacked on the peripheral gate insulating film 230. As an example, an additional conductive film may not be disposed between the peripheral gate conductive film 240 and the peripheral gate insulating film 230. As another example, unlike the example shown, an additional conductive film (such as a work function conductive film) may be disposed between the peripheral gate conductive film 240 and the peripheral gate insulating film 230.

[0101] Although the two peripheral gate structures 240ST are shown disposed between adjacent peripheral element separation films 26, this is only for ease of explanation and the embodiments are not limited thereto.

[0102] For example, the peripheral gate conductive film 240 may have the same stacked structure as the cell wire 140. The thickness of the peripheral gate conductive film 240 may be the same as the thickness of the cell wire 140.

[0103] The first peripheral conductive film 241 may be made of the same material as the first unit conductive film 141. The second peripheral conductive film 242 may be made of the same material as the second unit conductive film 142. The third peripheral conductive film 243 may be made of the same material as the third unit conductive film 143.

[0104] The peripheral gate insulating film 230 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide.

[0105] The peripheral spacer 245 may include at least one of, for example, silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, silicon carbonitride, and combinations thereof. Although the peripheral spacer 245 is shown as a single layer, this is only for ease of explanation, and the embodiments are not limited thereto. Needless to say, the peripheral spacer 245 may be a multilayer film.

[0106] The peripheral cover film 244 may include at least one of, for example, silicon nitride film, silicon oxynitride, and silicon oxide. Furthermore, based on the upper side 100 μs of the substrate, the upper side of the peripheral cover film 244 may be lower than the upper side 144 μs of the unit line cover film.

[0107] A down-etch stop film 250 may be disposed on the substrate 100. The down-etch stop film 250 may be formed along the contour of the peripheral gate structure 240ST. The down-etch stop film 250 may include at least one of, for example, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride.

[0108] The first peripheral interlayer insulating film 290 may be disposed on the lower etch stop film 250. The first peripheral interlayer insulating film 290 may be disposed around the peripheral gate structure 240ST. For example, the first peripheral interlayer insulating film 290 may include a silicon oxide-based insulating material. The first peripheral interlayer insulating film 290 may include, but is not limited to, silicon oxide.

[0109] An interlayer insulating film 291 is disposed on the peripheral gate structure 240ST and the first peripheral interlayer insulating film 290. The interlayer insulating film 291 may cover the peripheral gate structure 240ST and the first peripheral interlayer insulating film 290. The interlayer insulating film 291 may cover the downward etch stop film 250 protruding above the upper side of the first peripheral interlayer insulating film 290.

[0110] The intercalation interlayer insulating film 291 may comprise a material different from that of the first peripheral interlayer insulating film 290. The intercalation interlayer insulating film 291 may comprise, for example, a silicon nitride-based insulating material. For instance, the intercalation interlayer insulating film 291 may comprise silicon nitride.

[0111] Peripheral contact plugs 260 may be disposed on both sides of the peripheral gate structure 240ST. Peripheral contact plugs 260 penetrate the insertion interlayer insulating film 291 and the first peripheral interlayer insulating film 290, and may extend to the peripheral region 24 of the substrate 100. In some embodiments, peripheral contact plugs 260 may be connected to the substrate 100.

[0112] The peripheral contact plug 260 may include a recess 260R, a second silicide film 261, a second conductive film 262, and a third conductive film 263. The recess 260R may extend into the substrate 100 in a fourth direction D4. The bottom side of the recess 260R may expose at least a portion of the substrate 100.

[0113] The second silicide film 261 may be disposed on the bottom side of the recess 260R. The second silicide film 261 may be disposed in the substrate 100. The second silicide film 261 may include a metal silicide compound. The second silicide film 261 may include, for example, but not limited to, at least one of cobalt (Co), titanium (Ti) and / or nickel (Ni).

[0114] The second conductive film 262 may be disposed on the second silicide film 261. The second conductive film 262 may extend along the sidewall of the recess 260R in the fourth direction D4. The second conductive film 262 may be disposed on the upper side 100US of the substrate. The second conductive film 262 may extend along the sidewall of the recess 260R in the fourth direction D4 for a first length T3a. The second conductive film 262 may be formed on the sidewall of the recess 260R in the first direction D1 with a thickness of a second length T3b. The length T3b of the second conductive film 262 in the first direction D1 may be smaller than the width W1 of the first conductive film 162 in the first direction D1.

[0115] The third conductive film 263 may be disposed on the second conductive film 262. The third conductive film 263 may fill the interior of the recess 260R. The upper side 262US of the second conductive film and the upper side 263US of the third conductive film may be located at the same level (or vertically horizontal) in the fourth direction D4.

[0116] The second conductive film 262 and the third conductive film 263 may include conductive materials. The second conductive film 262 may include at least one of, for example, conductive silicide compounds, conductive metal nitrides, conductive metal carbides, conductive metal oxides, and conductive metal carbonitrides. The second conductive film 262 may include, for example, but not limited to, titanium nitride (TiN). The third conductive film 263 may include a metal. For example, the third conductive film 263 may be formed of a metal. The third conductive film 263 may include, for example, but not limited to, tungsten (W).

[0117] Peripheral wiring 265 may be disposed on the interlayer insulating film 291. Peripheral wiring 265 may be disposed on the peripheral gate structure 240ST. Peripheral wiring 265 may be connected to the peripheral contact plug 260. From a cross-sectional view, when peripheral wiring 265 is connected to the peripheral contact plug 260, peripheral wiring 265 may be a portion disposed on the interlayer insulating film 291. Peripheral wiring 265 may be disposed on the upper side 291US of the interlayer insulating film.

[0118] The peripheral wiring 265 can be directly connected to the peripheral contact plug 260. The peripheral wiring 265 can be directly connected to the second conductive film 262 and the third conductive film 263.

[0119] The peripheral wiring 265 may be made of the same material as the third conductive film 263. The peripheral wiring 265 may include at least one of, for example, conductive silicide compounds, conductive metal nitrides, conductive metal carbides, conductive metal oxides, and conductive metal carbonitrides. For example, the peripheral wiring 265 may be formed of a metal. The peripheral wiring 265 may include, for example, but not limited to, tungsten (W).

[0120] The peripheral wiring separation pattern 280 can separate adjacent peripheral wirings 265. The upper side of the peripheral wiring separation pattern 280 may be on the same plane as the upper side 265US of the peripheral wiring. The peripheral wiring separation pattern 280 may contact the sidewall of the peripheral wiring 265. The peripheral wiring separation pattern 280 includes an insulating material. The peripheral wiring separation pattern 280 can electrically separate adjacent peripheral wirings 265 from each other. For example, the peripheral wiring separation pattern 280 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon carbonitride film, and a silicon carbonitride film.

[0121] The upper etch stop film 297 can be disposed on the peripheral wiring separation pattern 280. The upper etch stop film 297 does not contact the sidewall of the peripheral wiring 265.

[0122] A second peripheral interlayer insulating film 293 may be disposed on the upper etch stop film 297. Although not shown, the second peripheral interlayer insulating film 293 may cover the sidewall of the upper electrode 193. The second peripheral interlayer insulating film 293 may include an insulating material.

[0123] In the first direction D1, the width W1 of the first conductive film 162 on the first silicide film 161 may be different from the width W2 of the second conductive film 262 on the second silicide film 261. The width W1 of the first conductive film 162 in contact with the first silicide film 161 may also be different from the width W2 of the second conductive film 262 in contact with the second silicide film 261. For example, in the first direction D1, the width W1 of the first conductive film 162 on the first silicide film 161 may be larger than the width W2 of the second conductive film 262 on the second silicide film 261.

[0124] In the fourth direction D4, the upper side 165US of the second storage pad may be at the same level as the upper side 265US of the peripheral wiring. In the fourth direction D4, the lower side 165BS of the second storage pad may be at the same level as the lower side 265BS of the peripheral wiring.

[0125] In the fourth direction D4, the upper side 162US of the first conductive film may be at the same level as the upper side 262US of the second conductive film. In the fourth direction D4, the upper side 144US of the bit line structure may be at the same level as the upper side 291US of the interlayer insulating film.

[0126] In the fourth direction D4, the thickness T1 of the first conductive film 162 from the first silicide film 161 may be different from the thickness T3a of the second conductive film 262 from the second silicide film 261. For example, in the fourth direction D4, the thickness T1 of the first conductive film 162 from the first silicide film 161 may be smaller than the thickness T3a of the second conductive film 262 from the second silicide film 261. The thickness T1 of the first conductive film 162 from the upper side of the first silicide film 161 may be different from the thickness T3a of the second conductive film 262 from the upper side of the second silicide film 261. In the fourth direction D4, the thickness T1 of the first conductive film 162 from the first silicide film 161 to the lower side 165BS of the second storage pad 165 may be different from the thickness T3a of the second conductive film 262 from the second silicide film 261 to the lower side 265BS of the peripheral wiring 265.

[0127] In the fourth direction D4, the thickness T2 of the second storage pad 165 can be equal to the thickness T5 of the peripheral wiring 265. In the fourth direction D4, the thickness T4 of the third conductive film 263 can be different from the thickness T1 of the first conductive film 162. For example, in the fourth direction D4, the thickness T4 of the third conductive film 263 can be greater than the thickness T1 of the first conductive film 162.

[0128] The first silicide film 161 and the second silicide film 261 may be located at different levels in the fourth direction D4. For example, the first silicide film 161 may be disposed on the upper side 100US of the substrate, and the second silicide film 261 may be disposed below the upper side 100US of the substrate.

[0129] The first conductive film 162 and the second conductive film 262 may comprise the same metallic material. For example, each of the first conductive film 162 and the second conductive film 262 may comprise titanium nitride (TiN). The second storage pad 165, the third conductive film 263, and the peripheral wiring 265 may comprise the same metallic material. For example, the second storage pad 165, the third conductive film 263, and the peripheral wiring 265 may each comprise tungsten (W). The first conductive film 162 and the third conductive film 263 may comprise different metallic materials. For example, the first conductive film 162 may comprise titanium nitride (TiN), and the third conductive film 263 may comprise tungsten (W).

[0130] In a semiconductor memory device according to some embodiments, a first conductive film 162 may be formed of a single titanium nitride (TiN) layer, and a second storage pad 165 may be formed of a single tungsten (W) layer.

[0131] Figure 7 This is a layout diagram used to explain a semiconductor memory device according to some embodiments. Figure 8 This is a perspective view used to explain a semiconductor memory device according to some embodiments. Figure 9 yes Figure 7 A sectional view taken along lines DD and EE.

[0132] For reference, Figure 7 It can be Figure 1 Enlarged view of unit region 20.

[0133] Reference Figures 7 to 9 According to some embodiments, a semiconductor memory device may include a substrate 100, a plurality of first wires 420, a channel layer 430, a gate electrode 440, a gate insulating film 450, and a capacitor 480.

[0134] According to some embodiments, a semiconductor memory device may be a memory device including a vertical channel transistor (VCT). A vertical channel transistor may refer to a structure in which a channel layer 430 extends from a substrate 100 in a vertical direction.

[0135] A lower insulating layer 412 may be disposed on a substrate 100. A plurality of first conductors 420 may be spaced apart from each other in a first direction D1 and extend in a second direction D2 on the lower insulating layer 412. A plurality of first insulating patterns 422 may be disposed on the lower insulating layer 412 to fill the spaces between the plurality of first conductors 420. The plurality of first insulating patterns 422 may extend in the second direction D2. The upper sides of the plurality of first insulating patterns 422 may be disposed at the same horizontal level as the upper sides of the plurality of first conductors 420. The plurality of first conductors 420 may serve as bit lines.

[0136] The multiple first conductive lines 420 may include doped semiconductor materials, metals, conductive metal nitrides, conductive metal silicides, conductive metal oxides, or combinations thereof. For example, the multiple first conductive lines 420 may be made of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x RuO x They may be made of, but are not limited to, the aforementioned materials. The plurality of first conductive lines 420 may comprise a single layer or multiple layers of the aforementioned materials. In an exemplary embodiment, the plurality of first conductive lines 420 may comprise graphene, carbon nanotubes, or combinations thereof.

[0137] The channel layer 430 can be arranged in a matrix, in which the channel layer 430 is spaced apart from each other in a first direction D1 and a second direction D2 on a plurality of first conductors 420. The channel layer 430 may have a first width along the first direction D1 and a first height along a fourth direction D4, and the first height may be greater than the first width. Here, the fourth direction D4 intersects the first direction D1 and the second direction D2, and may be, for example, a direction perpendicular to the upper side of the substrate 100. For example, the first height may be, but is not limited to, about 2 to 10 times the first width. The bottom of the channel layer 430 may be used as a third source / drain region (not shown), the upper part of the channel layer 430 may be used as a fourth source / drain region (not shown), and the portion of the channel layer 430 between the third source / drain region and the fourth source / drain region may be used as a channel region (not shown).

[0138] As an example, the channel layer 430 may include an oxide semiconductor, and the oxide semiconductor may include, for example, In... x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O、Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O、In x Ga yO or combinations thereof. The channel layer 430 may comprise a single layer or multiple layers of oxide semiconductor. In some embodiments, the channel layer 430 may have a bandgap energy greater than that of silicon. For example, the channel layer 430 may have a bandgap energy of about 1.5 eV to 5.6 eV. For example, the channel layer 430 may have optimal channel performance when it has a bandgap energy of about 2.0 eV to 4.0 eV. For example, the channel layer 430 may be, but is not limited to, polycrystalline or amorphous. As another example, the channel layer 430 may comprise graphene, carbon nanotubes, or combinations thereof. As yet another example, the channel layer 430 may comprise a silicon-based semiconductor material. The channel layer 430 may comprise a single-crystal semiconductor material such as, but not limited to, single-crystal silicon or single-crystal silicon germanium.

[0139] The gate electrode 440 may extend in a first direction D1 on both sidewalls of the channel layer 430. The gate electrode 440 may include a first sub-gate electrode 440P1 and a second sub-gate electrode 440P2, the first sub-gate electrode 440P1 facing the first sidewall of the channel layer 430, and the second sub-gate electrode 440P2 facing the second sidewall of the channel layer 430 opposite to the first sidewall. Since a single channel layer 430 is disposed between the first sub-gate electrode 440P1 and the second sub-gate electrode 440P2, the semiconductor device may have a dual-gate transistor structure. However, the technical concept of this disclosure is not limited thereto; the second sub-gate electrode 440P2 is omitted, and only the first sub-gate electrode 440P1 facing the first sidewall of the channel layer 430 may be formed to achieve a single-gate transistor structure. The material included in the gate electrode 440 may be the same as described for the unit gate electrode 112.

[0140] The gate insulating film 450 surrounds the sidewalls of the channel layer 430 and may be disposed between the channel layer 430 and the gate electrode 440. For example, as Figure 9 As shown, the entire sidewall of the channel layer 430 may be surrounded by the gate insulating film 450, and a portion of the sidewall of the gate electrode 440 may contact the gate insulating film 450. In other embodiments, the gate insulating film 450 extends in the extension direction of the gate electrode 440 (i.e., the first direction D1), and only two sidewalls of the channel layer 430 facing the gate electrode 440 may contact the gate insulating film 450. In an exemplary embodiment, the gate insulating film 450 may be made of a silicon oxide film, a silicon oxynitride film, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof.

[0141] Multiple second insulating patterns 432 may extend along a second direction D2 over multiple first insulating patterns 422. A channel layer 430 may be disposed between two adjacent second insulating patterns 432. Furthermore, a first buried layer 434 and a second buried layer 436 may be disposed in the space between two adjacent channel layers 430. The first buried layer 434 may be disposed at the bottom of the space between the two adjacent channel layers 430. The second buried layer 436 may be formed to fill the remaining portion of the space between the two adjacent channel layers 430 over the first buried layer 434. The upper surface of the second buried layer 436 may be disposed at the same level as the upper surface of the channel layers 430, and the second buried layer 436 may cover the upper surface of the gate electrode 440. Alternatively, the multiple second insulating patterns 432 may be formed from a continuous material layer with the multiple first insulating patterns 422, or the second buried layer 436 may be formed from a continuous material layer with the first buried layer 434.

[0142] Capacitor contacts 460 may be disposed on the channel layer 430. The capacitor contacts 460 are configured to be vertically stacked with respect to the channel layer 430 and may be arranged in a matrix, in which the capacitor contacts 460 are spaced apart from each other in a first direction D1 and a second direction D2. The capacitor contacts 460 may be made of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or IrO. x RuO x Or a combination thereof, but not limited thereto. The upper insulating film 462 may surround the sidewalls of the capacitor contact 460 on a plurality of second insulating patterns 432 and a second buried layer 436.

[0143] An etch stop film 470 may be disposed on an upper insulating film 462. A capacitor 480 may be disposed on the etch stop film 470. The capacitor 480 may include a second lower electrode 482, a second capacitor dielectric film 484, and a second upper electrode 486. The second lower electrode 482 penetrates the etch stop film 470 and may be electrically connected to the upper side of the capacitor contact 460. The second lower electrode 482 may be formed in a columnar shape extending in a fourth direction D4, but is not limited thereto. In an exemplary embodiment, the second lower electrode 482 may be configured to be vertically stacked with the capacitor contact 460 and may be arranged in a matrix in which the second lower electrodes 482 are spaced apart from each other in a first direction D1 and a second direction D2. Optionally, a bonding pad (not shown) may be further disposed between the capacitor contact 460 and the second lower electrode 482, and the second lower electrode 482 may be arranged in a hexagonal shape.

[0144] Figure 10 This is a layout diagram used to explain a semiconductor memory device according to some embodiments. Figure 11 This is a perspective view used to explain a semiconductor memory device according to some embodiments. Figure 12 These are diagrams used to explain semiconductor memory devices according to some embodiments.

[0145] Reference Figure 10 and Figure 11 A semiconductor memory device according to some embodiments may include a substrate 100, a plurality of first conductive lines 420A, a channel structure 430A, a contact gate electrode 440A, a plurality of second conductive lines 442A, a capacitor contact 460A, and a capacitor 480. A semiconductor memory device according to some embodiments may be a memory device including a vertical channel transistor (VCT).

[0146] Multiple active regions AC can be defined in the substrate 100 by a first element separation pattern 412A and a second element separation pattern 414A. A channel structure 430A can be disposed in each active region AC. The channel structure 430A may include a first active post 430A1 and a second active post 430A2, both extending in the vertical direction, and a connection portion 430L connected to the bottom of the first active post 430A1 and the bottom of the second active post 430A2. A first source / drain region SD1 can be disposed in the connection portion 430L. A second source / drain region SD2 can be disposed in the top of the first active post 430A1 and the second active post 430A2. Each of the first active post 430A1 and the second active post 430A2 can constitute an independent unit memory cell.

[0147] Multiple first conductors 420A may extend in directions intersecting with each of the multiple active regions AC, and may extend, for example, in a second direction D2. One of the multiple first conductors 420A may be disposed on the connection portion 430L between the first active post 430A1 and the second active post 430A2. One first conductor 420A may be disposed on the first source / drain region SD1. Another first conductor 420A adjacent to one first conductor 420A may be disposed between the two channel structures 430A. One of the multiple first conductors 420A may be used as a common bit line included in two unit memory cells formed by the first active post 430A1 and the second active post 430A2 disposed on either side of the first conductor 420A.

[0148] A single contact gate electrode 440A may be disposed between two adjacent channel structures 430A in the second direction D2. For example, the contact gate electrode 440A may be disposed between a first active post 430A1 included in a channel structure 430A and a second active post 430A2 of the adjacent channel structure 430A in the second direction D2. The single contact gate electrode 440A may be shared by the first active post 430A1 and the second active post 430A2 disposed on two sidewalls of the contact gate electrode 440A. A gate insulating film 450A may be disposed between the contact gate electrode 440A and the first active post 430A1 and between the contact gate electrode 440A and the second active post 430A2. A plurality of second conductors 442A may extend on the upper side of the contact gate electrode 440A in the first direction D1. The plurality of second conductors 442A may be used as word lines of a semiconductor device.

[0149] Capacitor contact 460A may be disposed on channel structure 430A. Capacitor contact 460A may be disposed on second source / drain region SD2, and capacitor 480 (e.g., lower electrode 482 of capacitor 480) may be disposed on capacitor contact 460A.

[0150] Reference Figure 12 According to some embodiments, a semiconductor memory device may have a cell onperi (COP) structure, in which a cell array region CA is disposed on a peripheral structure region PA.

[0151] The peripheral structural region PA can correspond to Figure 1 and Figure 5 The outer region 24. The cell array region CA may include Figures 7 to 11 Vertical channel transistor (VCT).

[0152] Figures 13 to 20 These are intermediate step diagrams used to explain a method for manufacturing a semiconductor memory device according to some embodiments. In the explanation of the manufacturing method, brief explanations or omissions will be used. Figures 1 to 6 The repeated parts of the explanation.

[0153] Reference Figure 1 and Figure 13 The settings include cell areas ( Figure 1 20), peripheral area ( Figure 1 24) and unit region separation membrane ( Figure 1 22) of the base 100.

[0154] In the unit region of substrate 100 ( Figure 1 In 20), a unit active region defined by the unit element separation membrane 105 is formed. Figure 2ACT). Active region of the unit ( Figure 2 The ACT (Active Circuit) may include a bit line connection region 103a and a storage connection region 103b. The cell element separation membrane 105 may include an insulating material and has an STI structure.

[0155] In the unit region of substrate 100 ( Figure 1 A pre-unit insulating film (not shown), a pre-unit conductor (not shown), a pre-positioning line contact (not shown), and a pre-unit line cover film (not shown) are formed on the pre-unit conductor 140. Specifically, the pre-unit insulating film (not shown) may be made of the same material as the pre-unit insulating film 130, the pre-unit conductor (not shown) may be made of the same material as the pre-unit conductor 140, the pre-positioning line contact (not shown) may be made of the same material as the position line contact 146, and the pre-unit line cover film (not shown) may be made of the same material as the pre-unit line cover film 144.

[0156] Reference Figure 14 It can be used in the outer area ( Figure 1 A peripheral gate structure 240ST is formed on the substrate 100 of (24). The peripheral gate structure 240ST may include a peripheral gate insulating film 230, a peripheral gate conductive film 240, a peripheral cover film 244, and a peripheral spacer 245.

[0157] A bottom etch stop film 250 may be formed on the substrate 100. The bottom etch stop film 250 may be formed on the peripheral gate structure 240ST. The bottom etch stop film 250 may be formed along the contour of the peripheral gate structure 240ST.

[0158] A first peripheral interlayer insulating film 290 may be formed on the lower etch stop film 250. The first peripheral interlayer insulating film 290 may completely cover the lower etch stop film 250. The first peripheral interlayer insulating film 290 may include, for example, a silicon oxide-based insulating material.

[0159] An intercalation interlayer insulating film 291 may be formed on the first peripheral interlayer insulating film 290. The intercalation interlayer insulating film 291 may be formed on the lower etch stop film 250.

[0160] Refer again Figure 13 It can be in the cell area ( Figure 1 A bit line structure 140ST extending elongated in the second direction D2 is formed on the bit line structure 140ST. Unit line spacers 150 may be formed on the sidewalls of the bit line structure 140ST. A fence pattern may be formed between adjacent bit line structures 140ST in the first direction D1. Figure 6 (170). After the fence pattern 170 is formed, storage contacts 120 may be formed between adjacent unit conductors 140 and between adjacent fence patterns 170 in the second direction D2.

[0161] Storage contacts 120 may be formed between multiple bit line structures 140ST. Storage contacts 120 may be connected to the active regions of cells (…). Figure 2 The storage connection region 103b of the ACT (Active Technology for Activated Cells). The storage contact 120 may be stacked with the substrate 100 and the cell element separation film 105 between adjacent cell conductors 140. The storage contact 120 may include, for example, but not limited to, at least one of a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal.

[0162] A first silicide film 161 and a first conductive film 162 on the first silicide film 161 may be sequentially formed on the storage contact 120.

[0163] Although not specifically shown, a first silicide metal layer (not shown) may be deposited on the storage contact 120. The first silicide metal layer (not shown) may include, for example, but not limited to, at least one of cobalt (Co), titanium (Ti), and / or nickel (Ni). A silicide process may be performed on the first silicide metal layer (not shown). For example, annealing may be performed on the first silicide metal layer (not shown). Thus, a first silicide film 161 comprising a metal silicide compound may be formed.

[0164] A first conductive film 162 may be formed on the first silicide film 161 between a plurality of bit line structures 140ST. The first conductive film 162 may be formed on at least a portion of the sidewalls of the plurality of bit line structures 140ST. The first conductive film 162 may include, but is not limited to, titanium nitride (TiN).

[0165] Subsequently, chemical mechanical polishing (CMP) and / or etching-back processes can be performed on the first conductive film 162 and the bit line structure 140ST. The upper side 162US of the first conductive film may be coplanar with the upper side 144US of the bit line structure 140ST. The upper side 162US of the first conductive film, the upper side 144US of the bit line structure 140ST, and the upper side 291US of the intercalation insulating film may be coplanar.

[0166] Although not specifically shown, chemical mechanical polishing (CMP) and / or etching back processes can be used to remove the material formed in the peripheral area. Figure 1 The first silicide film 161 and the first conductive film 162 in (24).

[0167] Subsequently, a cell protection film PS can be formed on the first conductive film 162. The cell protection film PS can be formed on the cell region 20, but may not be formed on the peripheral region 24. The cell protection film PS can cover the upper side 162US of the first conductive film and the upper side 144US of the bit line structure 140ST. The cell protection film PS may include a nitride-based material. The cell protection film PS may include, but is not limited to, silicon nitride. When the peripheral region (described later) is formed Figure 1When the peripheral contact plug 260 of (24) is in place, the cell protective film PS can protect the cell area ( Figure 1 (20). As an example, a unit protective film PS can be formed on the first conductive film 162 using a deposition process.

[0168] After that, refer to again Figure 14 A recess 260R can be formed in the intercalation interlayer insulating film 291 and the first peripheral interlayer insulating film 290. The recess 260R can penetrate the intercalation interlayer insulating film 291 and the first peripheral interlayer insulating film 290. The recess 260R can extend into the substrate 100 on both sides of the peripheral gate structure 240ST. The recess 260R can expose the peripheral region of the substrate 100. Figure 1 24).

[0169] Subsequently, a second silicide film 261 is formed on the bottom side of the recess 260R, and a pre-second conductive film P_262 extending along the sidewall of the recess 260R can be formed on the second silicide film 261.

[0170] Although not specifically shown, a second silicide metal layer (not shown) may be deposited on substrate 100. The second silicide metal layer (not shown) may include, for example, but not limited to, at least one of cobalt (Co), titanium (Ti), and / or nickel (Ni). A silicide process may be performed on the second silicide metal layer (not shown). For example, annealing may be performed on the second silicide metal layer (not shown). Thus, a second silicide film 261 comprising a metal silicide compound may be formed.

[0171] The pre-second conductive film P_262 may extend in the fourth direction D4 along the upper side of the second silicide film 261 and the sidewall of the recess 260R. The pre-second conductive film P_262 may extend along the exposed upper side 291US of the intercalation insulating film. The pre-second conductive film P_262 may include, but is not limited to, titanium nitride (TiN).

[0172] Subsequently, a pre-third conductive film P_263 filling the interior of the recess 260R can be formed on the pre-second conductive film P_262. The pre-third conductive film P_263 may include, for example, but not limited to, tungsten (W).

[0173] Subsequently, refer to Figure 15 and Figure 16 The cell protective film PS can be removed using chemical mechanical polishing (CMP) and / or etching-back processes, exposing the upper side 162US of the first conductive film and the upper side 144US of the bit line structure. The pre-second conductive film on the upper side 291US of the intercalation interlayer insulating film can be removed using chemical mechanical polishing (CMP) and / or etching-back processes. Figure 14 P_262) and the pre-third conductive film ( Figure 14(P_263). The upper side 162US of the first conductive film, the upper side 262US of the second conductive film, and the upper side 263US of the third conductive film may be located on the same plane. The upper side 144US of the bit line structure and the upper side 291US of the interlayer insulating film may be located on the same plane. Therefore, the second conductive film 262 and the third conductive film 263 may be formed inside the recess 260R.

[0174] Subsequently, refer to Figure 17 and Figure 18 It can be in the cell area ( Figure 1 A pre-fourth conductive film P_165 is formed on the first conductive film 162 of (20). The pre-fourth conductive film P_165 may include, for example, but is not limited to, tungsten (W). It may be formed in the peripheral region ( Figure 1 A pre-fifth conductive film P_265 is formed on the third conductive film 263 of (24). The pre-fifth conductive film P_265 may include, for example, but not limited to, tungsten (W).

[0175] Chemical mechanical polishing (CMP) and / or etching back processes can be performed on the pre-fourth conductive film P_165 and the pre-fifth conductive film P_265. The upper side P_165US of the pre-fourth conductive film and the upper side P_265US of the pre-fifth conductive film can be located on the same plane.

[0176] Subsequently, refer to Figure 19 and Figure 20 It can divide the unit area ( Figure 1 The pre-fourth conductive film of 20) Figure 17 The P_165 is patterned to form a first recess 180R. A first separation pattern (i.e., pad separation pattern) 180 can be formed in the first recess 180R. Therefore, a fourth conductive film (i.e., a second storage pad) 165 separated by the first separation pattern 180 can be formed. Furthermore, a cell region ( Figure 1 An upper etch stop film 297 is formed on the upper side 165US of the fourth conductive film 165 and the first separation pattern 180.

[0177] The outer area ( Figure 1 The fifth conductive film of (24) Figure 18 The P_265 is patterned to form a second recess 280R. A second separation pattern 280 can be formed inside the second recess 280R. Therefore, a fifth conductive film (i.e., peripheral wiring) 265 separated by the second separation pattern 280 can be formed. In addition, a fifth conductive film (i.e., peripheral wiring) 265 can also be formed in the peripheral region (P_265). Figure 1 An upper etch stop film 297 is formed on the upper side 265US of the fifth conductive film 265 and the second separation pattern 280.

[0178] Next, refer to Figure 4 and Figure 5A data storage pattern 190 is formed on the upper side 165US of the fourth conductive film 165 and on the first separation pattern 180, in a cell region ( Figure 1 An etch stop film 297 is placed on the upper side 165US of the fourth conductive film 165 between the first separation pattern 180 and the data storage pattern 190, and a second peripheral interlayer insulating film 293 can be formed on the upper side 265US of the fifth conductive film 265 and the second separation pattern 280, in the peripheral region ( Figure 1 The upper etch stop film 297 of 24) is placed on the upper side 265US of the fifth conductive film 265 between the second separation pattern 280 and the data storage pattern 190.

[0179] In a semiconductor memory device according to some embodiments, the process of forming cell regions can be performed detachably. Figure 1 The process of the conductive material layer included in the storage pad structure 160ST of (20) and the process for treating the peripheral area ( Figure 1 The process of the conductive material layer included in the peripheral contact plug 260 and peripheral wiring 265 of (24). For example, in forming the cell region ( Figure 1 Following the conductive material layer included in the storage pad structure 160ST of (20), in the cell region ( Figure 1 In 20), a protective film PS is formed in the unit, and then an action can be taken to form the peripheral region ( Figure 1 The process of the conductive material layer included in the peripheral contact plug 260 of (24). Therefore, the cell area ( Figure 1 The storage pad structure of 160ST and the peripheral area (of 20) Figure 1 The horizontal difference between the outer wiring 265 of (24). Furthermore, the unit area ( Figure 1 The conductive material layer and the peripheral area included in the storage pad structure 160ST of (20) Figure 1 The conductive material layers included in the peripheral contact plug 260 and peripheral wiring 265 of (24) may have different structures from each other.

[0180] Although embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and can be made in various different forms. Those skilled in the art will understand that the present disclosure can be implemented in other specific forms without changing the technical spirit or essential characteristics of the present disclosure. Therefore, the above embodiments should be understood in all respects as illustrative and not restrictive.

Claims

1. A semiconductor memory device, comprising: The substrate includes a cell region and a peripheral region defined around the cell region, the cell region including a cell active region defined by a cell element separation membrane; Multiple bitline structures extend in a first horizontal direction on each of the unit element separation membrane and the active region of the unit; Storage contacts are connected to the cell active regions among the plurality of bit line structures; The first storage pad is connected to the storage contact and is on the storage contact; Data storage pattern, connected to the first storage pad; The peripheral gate structure is disposed on the peripheral region of the substrate; as well as Peripheral contact plugs are disposed on both sides of the peripheral gate structure and connected to the substrate. The first storage pad includes: a first silicide film on the storage contact; and a first conductive film on the first silicide film. The peripheral contact plug includes: a recess extending vertically into a substrate; a second silicide film on the bottom side of the recess; a second conductive film extending along the sidewall of the recess on the second silicide film; and a third conductive film filling the interior of the recess on the second conductive film. In a second horizontal direction, which is different from the first horizontal direction, the width of the first conductive film is different from the width of the second conductive film.

2. The semiconductor memory device according to claim 1, further comprising: The second storage pad is connected to the data storage pattern and is on the first storage pad; as well as Peripheral wiring connects to the peripheral contact plug and is on the peripheral contact plug.

3. The semiconductor memory device according to claim 2, in, The upper side of the second storage pad is at the same level as the upper side of the outer wiring in the vertical direction.

4. The semiconductor memory device according to claim 2, in, The lower side of the second storage pad is located at the same level as the lower side of the peripheral wiring in the vertical direction.

5. The semiconductor memory device according to claim 2, in, The second storage pad, the third conductive film, and the peripheral wiring all use the same metallic material.

6. The semiconductor memory device according to claim 1, in, The upper side of the first conductive film is located at the same horizontal level as the upper side of the second conductive film in the vertical direction.

7. The semiconductor memory device according to claim 1, in, The upper side of the first conductive film is located at the same horizontal level as the upper side of the third conductive film in the vertical direction.

8. The semiconductor memory device of claim 1, further comprising: Interlayer insulating film is disposed on the peripheral gate structure. The upper side of the bit line structure is located at the same horizontal level as the upper side of the interlayer insulating film in the vertical direction.

9. The semiconductor memory device according to claim 1, in, In the vertical direction, the thickness of the first conductive film from the first silicide film is different from the thickness of the second conductive film from the second silicide film.

10. The semiconductor memory device according to claim 1, in, The first conductive film and the second conductive film are made of the same metallic material.

11. The semiconductor memory device according to claim 1, in, The first conductive film and the third conductive film are made of different metallic materials.

12. A semiconductor memory device, comprising: The substrate includes a cell region and a peripheral region defined around the cell region, the cell region including a cell active region defined by a cell element separation membrane; Multiple unit wires extend horizontally on each of the unit element separation membrane and the unit active region; Storage contacts are connected to the active area of ​​the unit among the plurality of unit wires; The first storage pad is connected to the storage contact and is on the storage contact; Data storage pattern, connected to the first storage pad; The second storage pad is located between the first storage pad and the data storage pattern; The peripheral gate structure is disposed on the peripheral region of the substrate; Peripheral contact plugs are disposed on both sides of the peripheral gate structure and connected to the substrate; as well as Peripheral wiring connects to peripheral contact plugs and is present on the peripheral gate structure. The first storage pad includes: a first silicide film on the storage contact; and a first conductive film on the first silicide film. The peripheral contact plug includes: a recess extending vertically into a substrate; a second silicide film on the bottom side of the recess; a second conductive film extending along the sidewall of the recess on the second silicide film; and a third conductive film filling the interior of the recess on the second conductive film. In the vertical direction, the thickness of the first conductive film is greater than the thickness of the second storage pad.

13. The semiconductor memory device according to claim 12, in, In the vertical direction, the thickness of the first conductive film from the first silicide film to the underside of the second storage pad is different from the thickness of the second conductive film from the second silicide film to the underside of the peripheral wiring.

14. The semiconductor memory device according to claim 12, in, In the vertical direction, the thickness of the second storage pad is equal to the thickness of the peripheral wiring.

15. The semiconductor memory device according to claim 12, in, In the vertical direction, the thickness of the third conductive film is greater than that of the first conductive film.

16. The semiconductor memory device according to claim 12, in, The first silicide film and the second silicide film are located at different horizontal positions in the vertical direction.

17. The semiconductor memory device according to claim 12, in, Each of the first and second conductive films includes titanium nitride.

18. The semiconductor memory device according to claim 12, in, Each of the second storage pad, the third conductive film, and the peripheral wiring includes tungsten.

19. The semiconductor memory device according to claim 12, in, The first conductive film comprises titanium nitride, and the third conductive film comprises tungsten.

20. A semiconductor memory device, comprising: The substrate includes a cell region and a peripheral region defined around the cell region, the cell region including a cell active region defined by a cell element separation membrane; Multiple bitline structures extend horizontally on each of the unit element separation membrane and the active region of the unit; Storage contacts are connected between the cell active regions of the cell regions and the plurality of bit line structures; A storage pad structure, connected to the storage contact, and on the storage contact; Data storage pattern, connected to the storage pad structure; The peripheral gate structure is disposed on the peripheral region of the substrate; An interlayer insulating film is disposed on the peripheral gate structure; Peripheral contact plugs are disposed on both sides of the peripheral gate structure, penetrate the interlayer insulating film, and connect to the substrate; as well as Peripheral wiring connects to peripheral contact plugs and is present on the peripheral gate structure. The storage pad structure includes: a first storage pad on the storage contact; and a second storage pad between the first storage pad and the data storage pattern. The first storage pad includes: a first silicide film on the storage contact; and a first conductive film on the first silicide film. The peripheral contact plug includes: a recess extending vertically into a substrate; a second silicide film on the bottom side of the recess; a second conductive film extending along the sidewall of the recess on the second silicide film; and a third conductive film filling the interior of the recess on the second conductive film. The upper side of the bit line structure is located at the same vertical level as the upper side of the interlayer insulating film, and The upper side of the second storage pad is located at the same vertical level as the upper side of the peripheral wiring.

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