Semiconductor device and method of manufacturing the same

Abstract

This application discloses a semiconductor device and its fabrication method, including a substrate, a contact pad structure, a composite insulating layer, and a capacitor structure. The contact pad structure is disposed on the substrate and includes a first contact pad, a second contact pad, and a third contact pad. A portion of the composite insulating layer is located on the contact pad structure. The first portion of the composite insulating layer on the first contact pad has a first thickness, the second portion on the second contact pad has a second thickness, and the third portion on the third contact pad has a third thickness. The first thickness is less than the third thickness, and the third thickness is less than the second thickness. The capacitor structure is disposed on the contact pad structure and includes multiple lower electrodes, a capacitor dielectric layer, and an upper electrode layer. A portion of the lower electrodes penetrates the composite insulating layer and contacts the first contact pad. This results in optimized device reliability and component performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] With the trend towards miniaturization in various electronic products, the design of semiconductor devices must also meet the requirements of high aggregation and high density. For dynamic random access memory (DRAM) with a recessed gate structure, it can achieve a longer carrier channel length within the same semiconductor substrate, reducing leakage current caused by capacitor structures. Therefore, under the current mainstream development trend, it has gradually replaced DRAM with only planar gate structures. Generally, DRAM with a recessed gate structure consists of a large number of memory cells clustered into an array area to store information. Each memory cell can be composed of transistor components and capacitor components connected in series to receive voltage information from the word line (WL) and bit line (BL). Due to product demands, the density of memory cells in the array area must continue to increase, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, existing technologies or structures still need further improvement to effectively enhance the performance and reliability of related memory devices. Summary of the Invention

[0003] The purpose of one embodiment of this application is to provide a semiconductor device and a method for manufacturing the same, which involves setting insulating layers with different stacking numbers and / or thicknesses in different regions to form a composite insulating layer, and using the thickness difference to isolate contact pads located in different regions to achieve different insulation effects.

[0004] To achieve the above objectives, one embodiment of this application provides a semiconductor device including a substrate, a contact pad structure, a composite insulating layer, and a capacitor structure. The substrate includes a storage region, a boundary region, and a peripheral region. The contact pad structure is disposed on the substrate and includes a first contact pad located in the storage region, a second contact pad located in the boundary region, and a third contact pad located in the peripheral region. The composite insulating layer is disposed on the substrate and partially located on the contact pad structure. A first portion of the composite insulating layer on the first contact pad has a first thickness, a second portion of the composite insulating layer on the second contact pad has a second thickness, and a third portion of the composite insulating layer on the third contact pad has a third thickness. The first thickness is less than the third thickness, and the third thickness is less than the second thickness. The capacitor structure is disposed on the contact pad structure and includes a plurality of lower electrodes, a capacitor dielectric layer, and an upper electrode layer. A portion of the lower electrodes penetrates the composite insulating layer and contacts the first contact pad.

[0005] To achieve the above objectives, one embodiment of this application provides a method for fabricating a semiconductor device, comprising the following steps: A substrate is provided, the substrate including a storage region, a boundary region, and a peripheral region. A contact pad structure is formed on the substrate, the contact pad structure including a first contact pad formed in the storage region, a second contact pad formed in the boundary region, and a third contact pad formed in the peripheral region. A composite insulating layer is formed on the substrate, partially located on the contact pad structure, the first portion of the composite insulating layer on the first contact pad having a first thickness, a second portion of the composite insulating layer on the second contact pad having a second thickness, and a third portion of the composite insulating layer on the third contact pad having a third thickness, wherein the first thickness is less than the third thickness, and the third thickness is less than the second thickness. A capacitor structure is formed on the contact pad structure, the capacitor structure including a plurality of lower electrodes, a capacitor dielectric layer, and an upper electrode layer, a portion of the lower electrodes penetrating the composite insulating layer and contacting the first contact pad.

[0006] To achieve the above objectives, one embodiment of this application provides another semiconductor device, including a substrate, a first contact pad, a second contact pad, a third contact pad, a first insulating layer, a second insulating layer, and a capacitor structure. The substrate includes a storage region, a boundary region, and a peripheral region. The first contact pad, the second contact pad, and the third contact pad are disposed on the substrate and located in the storage region, the boundary region, and the peripheral region, respectively. The first insulating layer is disposed on the substrate, partially located between the first contact pad, the second contact pad, and the third contact pad, and partially covers and contacts the top surfaces of the second contact pad and the third contact pad. The second insulating layer is disposed on the first insulating layer, and the second insulating layer also contacts the top surface of the first insulating layer located within the storage region. The capacitor structure includes a lower electrode, a capacitor dielectric layer, and an upper electrode layer, wherein the capacitor structure penetrates the second insulating layer and is electrically connected to the first contact pad.

[0007] To achieve the above objectives, one embodiment of this application provides another semiconductor device, including a substrate, a first contact pad, a second contact pad, a third contact pad, a first insulating layer, a second insulating layer, and a capacitor structure. The substrate includes a storage region, a boundary region, and a peripheral region. The first contact pad, the second contact pad, and the third contact pad are disposed on the substrate and located in the storage region, the boundary region, and the peripheral region, respectively. The first insulating layer is disposed on the substrate, partially located between the first contact pad, the second contact pad, and the third contact pad, wherein the top surface of the first insulating layer located in the boundary region is higher than the top surface of the first insulating layer located in the storage region. The second insulating layer is disposed on the first insulating layer and also contacts the top surface of the first insulating layer located in the storage region. The capacitor structure includes a lower electrode, a capacitor dielectric layer, and an upper electrode layer, wherein the capacitor structure penetrates the second insulating layer and is electrically connected to the first contact pad.

[0008] To achieve the above objectives, one embodiment of this application provides another semiconductor device, including a substrate, a first contact pad, a second contact pad, a third contact pad, a first insulating layer, a capping layer, a second insulating layer, a first capacitor structure, and a second capacitor structure. The substrate includes a storage region, a boundary region, and a peripheral region. The first contact pad, the second contact pad, and the third contact pad are disposed on the substrate and located in the storage region, the boundary region, and the peripheral region, respectively. The first insulating layer is disposed on the substrate, partially located between the first contact pad, the second contact pad, and the third contact pad. The capping layer is disposed on the first insulating layer and directly contacts the first insulating layer located in the boundary region and the peripheral region. The second insulating layer is disposed on the capping layer and contacts the first insulating layer located in the storage region and the capping layer located in the boundary region and the peripheral region. The first capacitor structure is disposed on the substrate, penetrates the second insulating layer that contacts the first insulating layer, and directly contacts the first contact pad. The second capacitor structure is disposed on the substrate, penetrates the second insulating layer that contacts the capping layer, and does not contact the second contact pad. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0010] Figures 1 to 2 This is a cross-sectional schematic diagram of a semiconductor device according to the first embodiment of this application; wherein:

[0011] Figure 1 This is a cross-sectional schematic diagram of the semiconductor device of this application;

[0012] Figure 2 for Figure 1 An enlarged schematic diagram along rectangular frame A;

[0013] Figures 3 to 8 This is a schematic diagram of a method for fabricating a semiconductor device according to a preferred embodiment of this application, wherein:

[0014] Figure 3 This is a schematic cross-sectional view of a semiconductor device after shallow trench isolation has been formed.

[0015] Figure 4 This is a schematic cross-sectional view of a semiconductor device after the bit line and gate structure have been formed.

[0016] Figure 5 This is a schematic cross-sectional view of a semiconductor device after the formation of a conductive material layer.

[0017] Figure 6 This is a schematic cross-sectional view of a semiconductor device after the formation of the first insulating material layer.

[0018] Figure 7 This is a schematic cross-sectional view of a semiconductor device after the formation of the second insulating material layer.

[0019] Figure 8 This is a schematic cross-sectional view of a semiconductor device after the formation of the third insulating layer.

[0020] Figure 9 This is a schematic diagram of a semiconductor device according to the second embodiment of this application;

[0021] Figure 10 This is a schematic diagram of a semiconductor device according to the third embodiment of this application.

[0022] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0023] To enable those skilled in the art to further understand this application, preferred embodiments of the application are described below, along with accompanying drawings, to explain in detail the composition and desired effects of the application. It should be understood that the following embodiments can be modified by substituting, recombining, or mixing features from several different embodiments to achieve other embodiments without departing from the spirit of this application.

[0024] Please refer to Figure 1 and Figure 2 The diagram shown is a schematic representation of the semiconductor device 10 according to the first embodiment of this application. Figure 1As shown, the semiconductor device 10 includes a substrate 100, a contact pad structure CP disposed on the substrate 100, a composite insulating layer IL, and a capacitor structure 160 disposed on the contact pad structure CP. The substrate 100 may include, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto. In one embodiment, the substrate 100 further includes a first region with relatively high component density, such as a cell region 100A of the semiconductor device 10; a second region with relatively low component density, such as a peripheral region 100C of the semiconductor device 10; and a third region located between the cell region 100A and the peripheral region 100C, such as a boundary region 100B of the semiconductor device 10. The cell region 100A, the boundary region 100B, and the peripheral region 100C are, for example, as shown in the figure. Figure 1 As shown, they are arranged adjacent to each other, but not limited thereto. Furthermore, at least one shallow trench isolation (STI) 102, 104, and 106 are respectively provided in the substrate 100, and multiple active areas (AA, not shown) are defined in the storage area 100A, the boundary area 100B, and the peripheral area 100C, respectively.

[0025] The contact pad structure CP further includes a plurality of first contact pads 142 located in the storage region 100A, a second contact pad 144 located in the boundary region 100B, and a plurality of third contact pads 146 located in the peripheral region 100C. The capacitor structure 160 is located on both the first contact pads 142 and the second contact pads 144, and includes a plurality of lower electrodes 162 and 164, a capacitor dielectric layer 166, and an upper electrode layer 168 arranged in sequence, which together form a vertically extending capacitor to serve as a storage node (SN) of the semiconductor device 10. The composite insulating layer IL is partially disposed in the storage region 100A, partially disposed in the boundary region 100B, and partially disposed in the peripheral region 100C, and covers a portion of the contact pad structure CP, so that each lower electrode 162 disposed in the storage region 100A must penetrate the composite insulating layer IL to physically contact the top surface of the first contact pad 142. It should be noted that the composite insulating layer IL disposed in different areas has different thicknesses. Specifically, the first portion of the composite insulating layer IL on the first contact pad 142 has a first thickness W1, the second portion on the second contact pad 144 has a second thickness W2, and the third portion on the third contact pad 146 has a third thickness W3. Furthermore, the first thickness W1 is less than the third thickness W3, and the third thickness W3 is less than the second thickness W2. Thus, by disposing of the composite insulating layer IL, the first contact pad 142, the second contact pad 144, and the third contact pad 146 in different areas can be effectively isolated. By utilizing the thickness difference, different insulation effects are achieved in different areas of the semiconductor device 10, thereby improving the structural reliability and operational efficiency of the semiconductor device 10.

[0026] In detail, the composite insulating layer IL further includes a first insulating layer 152, a cover layer 154, and a second insulating layer 156 sequentially disposed in the vertical direction Y. These layers may include, for example, insulating materials with different etching selectivity ratios, such as silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride, but are not limited thereto. The first insulating layer 152 is disposed simultaneously in the storage region 100A, the boundary region 100B, and the peripheral region 100C. The cover layer 154 is disposed partially in the boundary region 100B and partially in the peripheral region 100C. Similarly, the second insulating layer 156 is disposed simultaneously in the storage region 100A, the boundary region 100B, and the peripheral region 100C, and covers the first insulating layer 152a in the storage region 100A and the cover layers 154b and 154c in the boundary region 100B and the peripheral region 100C, respectively. Figure 1As shown. Thus, the composite insulating layer IL, located in the first part within storage area 100A, the second part within boundary area 100B, and the third part within peripheral area 100C, are each composed of different numbers of insulating layers. The first part includes only the first insulating layer 152, while the second and third parts include both the first insulating layer 152, the cover layer 154, and the second insulating layer 156. In other words, the number of insulating layers (first insulating layer 152) constituting the first part is less than the number of insulating layers (first insulating layer 152, cover layer 154, and second insulating layer 156) constituting the second and third parts, such that the top surface t1 of the first part is lower than the top surface t2 of the second part and the top surface t3 of the third part, and also lower than the top surface 154t of the cover layer 154. Figure 2 As shown.

[0027] For example Figure 1 and Figure 2 As shown, the first insulating layer 152a located within the storage area 100A is disposed between adjacent first contact pads 142 and simultaneously disposed within the insulating layer 136, such that the first insulating layer 152a and the first contact pads 142 alternately occupy positions within the insulating layer 136 in the horizontal direction X. Thus, the second insulating layer 156a located within the storage area 100A directly covers the first insulating layer 152a and physically contacts the top surface of the first insulating layer 152a and the capacitor dielectric layer 166 above it. It should be noted that the first insulating layer 152a located within the storage area 100A also additionally covers one of the first contact pads 142 adjacent to the boundary area 100B, serving as the first part of the composite insulating layer IL. In this configuration, the lower electrode 164 adjacent to the boundary region 100B is directly disposed on the first insulating layer 152a, and its bottom surface 164b is in physical contact with the first insulating layer 152a, so that the lower electrode 164, together with the capacitor dielectric layer 166 and the upper electrode layer 168 disposed thereon, form a virtual capacitor, such as Figure 2 As shown.

[0028] On the other hand, the first insulating layer 152b located in the boundary region 100B and the first insulating layer 152c located in the peripheral region 100C are both continuously disposed with the first insulating layer 152a in the first part. Specifically, the first insulating layer 152b in the boundary region 100B is, for example, partially disposed between the second contact pad 144 and its adjacent first contact pad 142, and further covers the second contact pad 144. The cover layer 154b and the second insulating layer 156b located in the boundary region 100B are sequentially disposed on the first insulating layer 152b. The first insulating layer 152b, the cover layer 154b, and the second insulating layer 156b covering the second contact pad 144 together constitute the second part of the composite insulating layer IL. It should be noted that the first insulating layer 152b located within the boundary region 100B has an additional recess RS between the second contact pad 144 and the first contact pad 142. Its lowest point b1 is, for example, lower than the top surface 142t of the first contact pad 142. The cover layer 154b and the second insulating layer 156b covering the recess RS also have a partially recessed morphology. In this configuration, the lower electrode 164 located within the boundary region 100B partially penetrates the second part of the composite insulating layer IL and is located on the first insulating layer 152b, forming a dummy capacitor with the capacitor dielectric layer 166 and the upper electrode layer 168 disposed thereon. Thus, the bottom surface 164b of the lower electrode 164 physically contacts the first insulating layer 152b within the boundary region 100B, while the sidewall 164s of the lower electrode 164 simultaneously contacts the cover layer 154b and the second insulating layer 156b within the boundary region 100B. Figure 2 As shown.

[0029] The first insulating layer 152c located within the peripheral region 100C is partially disposed between adjacent third contact pads 146 and partially covers the third contact pads 146, such that the covering layer 154c and the second insulating layer 156c within the peripheral region 100C sequentially cover the first insulating layer 152c. It should be noted that the thickness th2 of the second insulating layer 156c within the peripheral region 100C is preferably less than the thickness th1 of the second insulating layer 156b within the boundary region 100B, such that the top surface t2 of the second portion of the composite insulating layer IL is higher than the top surface t3 of the third portion, as shown below. Figure 2 As shown. Furthermore, the capacitor structure 160 also includes an insulating layer 170 covering the upper electrode layer 168, and the upper electrode layer 168 further includes an upper protrusion 168a, a middle protrusion 168b, and a lower protrusion 168c located within the boundary region 100B. The upper protrusion 168a and the middle protrusion 168b are, for example, respectively disposed on the upper support layer 174 and the lower support layer 172 between adjacent lower electrodes 162 and 167, while the lower protrusion 168c is disposed on the composite insulating layer IL (i.e., the second portion) covering the second contact pad 144, such as... Figure 1 As shown. It should be noted that the capacitor dielectric layer 166 of the capacitor structure 160 protrudes, for example, from the lower protrusion 168c of the upper electrode layer 168 in the horizontal direction X, and the distance L1 between the middle protrusion 168b and the lower protrusion 168c in the horizontal direction X is preferably not equal to the distance L2 between the middle protrusion 168b and the very end of the capacitor dielectric layer 166 protruding from the lower protrusion 168c. Figure 2 As shown. Thus, the capacitor structure 160, by means of the composite insulating layer IL, allows for the provision of the required dummy capacitors within the boundary region 100B and the storage region 100A adjacent to the boundary region 100B, thereby achieving a more reliable and stable structure. In one embodiment, the lower electrodes 162 and 164, for example, comprise titanium nitride, the upper electrode layer 168 comprises, for example, a composite structure of titanium nitride and silicon-germanium, and the capacitor dielectric layer 166 comprises, for example, a metal oxide material, selected from the group consisting of high dielectric constant dielectric materials such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium oxynitride (HfSiON), zinc oxide (ZrO2), titanium oxide (TiO2), and zirconium oxide-aluminum oxide-zirconia (ZAZ), preferably including zirconium oxide-aluminum oxide-zirconia, but not limited thereto.

[0030] For example Figure 1As shown, the semiconductor device 10 also includes a plurality of bit lines 120, dummy bit lines 220, and a plurality of gate structures 320 disposed on a substrate 100, respectively located within a storage region 100A, a boundary region 100B, and a peripheral region 100C. Specifically, the bit lines 120 and dummy bit lines 220 are disposed, for example, on a dielectric layer 110 above the substrate 100, spaced apart from each other, and alternately disposed in the insulating layer 134 in the horizontal direction X, along with a plurality of plugs 132 also located within the storage region 100A. The bit lines 120 and plugs 132 are both located below a first contact pad 142, and a bit line gap wall 130 is provided between the bit lines 120 and the plugs 132, so that each plug 132 physically contacts its corresponding first contact pad 142 above it and the active region below it. In one embodiment, the plugs 132 include, for example, epitaxial materials such as silicon (Si), silicon-phosphorus (SiP), silicon-germanium (SiGe), or germanium (Ge), but are not limited thereto. Specifically, bit line 120 and dummy bit line 220 are, in principle, located on dielectric layer 110. Each bit line 120 is further electrically connected to the corresponding active region by extending into the substrate 100 through an integrally formed bit line contact (BLC) 120a disposed below it. In one embodiment, dielectric layer 110 includes, for example, a silicon oxide layer 112, a silicon nitride layer 114, and a silicon oxide layer 116 stacked in sequence, having an oxide-nitride-oxide (ONO) structure, but is not limited thereto. No contact is disposed below the dummy bit line 220 located within boundary region 100B, and the dummy bit line 220 has a linewidth relatively larger than that of bit line 120, causing the first insulating layer 152b covering it to additionally exhibit a... Figure 1 and Figure 2 The recessed portion RS is shown.

[0031] The gate structure 320 is disposed on the gate dielectric layer 312 above the substrate 100, and is alternately disposed with a plurality of plugs 332 located in the peripheral region 100C in the horizontal direction X. The gate structure 320 is provided with a gate spacer wall 330 on its sidewall, and both the gate structure 320 and the plugs 332 are located below the third contact pad 146, so that each plug 332 physically contacts the corresponding third contact pad 146 above it. In one embodiment, the fabrication processes of the bit line 120 located in the memory region 100A, the dummy bit line 220 located in the boundary region 100B, and the gate structure 320 located in the peripheral region 100C can be integrated, such that each bit line 120, dummy bit line 220, and each gate structure 320 includes, in sequence, a semiconductor layer 122 (e.g., containing semiconductor materials such as doped polycrystalline silicon or doped amorphous silicon), a barrier layer 124 (e.g., containing conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide), a metal layer 126 (e.g., containing low-resistance metal materials such as tungsten, aluminum, or copper), and a capping layer 128 (e.g., containing insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride), and have the same film structure and materials, but are not limited thereto. In other embodiments, the fabrication processes of the bit line spacer 130 located in the memory region 100A and the gate spacer 330 located in the peripheral region 100C can also be integrated, so that the bit line spacer 130 and the gate spacer 330 can also have the same film structure and material (e.g., including silicon carbonitride or silicon nitride). The fabrication processes of the first contact pad 142 located in the memory region 100A, the second contact pad 144 located in the boundary region 100B, and the third contact pad 146 located in the peripheral region 100C can also be integrated. Furthermore, it can be integrated with the plug 332 of the surrounding area 100C, so that the first contact pad 142, the second contact pad 144 and the third contact pad 146 can also have the same film structure and materials (e.g., including a barrier layer and a metal layer stacked in sequence, the barrier layer including conductive barrier materials such as titanium and / or titanium nitride, and the metal layer including low-resistance metal materials such as copper, aluminum, titanium, and tungsten). In addition, the third contact pad 146 and the plug 332 can further have an integrally formed film structure, but are not limited thereto.

[0032] In this configuration, the plug 132 disposed within the storage region 100A serves as the storage node contact (SN contact) of the semiconductor device 10, while the first contact pad 142 disposed above the plug 132 serves as the storage node pad (SN pad) of the semiconductor device 10. This allows the capacitor disposed above it to be electrically connected to the corresponding active region via the storage node pad and the storage node plug. Thus, the capacitor and the transistor assembly (not shown) disposed within the substrate 100 can form the smallest possible memory cell to receive voltage information from the bit line 120 and the word line (not shown). This enables the semiconductor device 10 of this embodiment to form a dynamic random access memory (DRAM) device. Furthermore, the DRAM and the gate structure 320 within the peripheral region 100C can be electrically connected to different components or devices via connection structures 180 and 182, which are individually connected to the capacitor structure 160 and the third contact pad 146, to perform different operations and achieve more optimized operational performance. The connection structures 180 and 182 are respectively disposed within the interlayer dielectric layer 178, which is disposed as a whole within the storage area 100A, the boundary area 100B, and the peripheral area 100C and covers the capacitor structure 160 and the composite insulating layer IL.

[0033] Please repeat Figures 1 to 2 As shown, in another embodiment, the semiconductor device 10 includes at least the aforementioned substrate 100, a first contact pad 142, a second contact pad 144, and a third contact pad 146 respectively disposed in the storage region 100A, the boundary region 100B, and the peripheral region 100C, a first insulating layer 152, a second insulating layer 156, and a capacitor structure 160. The first insulating layer 152 is partially located between the first contact pad 142, the second contact pad 144, and the third contact pad 146, and partially covers and contacts the top surfaces of the second contact pad 144 and the third contact pad 146. The second insulating layer 156 is disposed on the first insulating layer 152 and directly contacts the top surface 152t of the first insulating layer 152a located in the storage region 100A. It should be noted that the lower electrode 162 of the capacitor structure 160 located in the storage region 100A penetrates the second insulating layer 156 and is electrically connected to the first contact pad 142. Thus, the semiconductor device 10 of this embodiment can effectively isolate the first contact pad 142, the second contact pad 144 and the third contact pad 146 located in different areas by means of the first insulating layer 152 and the second insulating layer 156, and achieve different insulation effects, thereby improving the structural reliability and operational efficiency of the semiconductor device 10.

[0034] Please repeat Figures 1 to 2 As shown, in another embodiment, the semiconductor device 10 includes at least the aforementioned substrate 100, a first contact pad 142, a second contact pad 144, and a third contact pad 146 respectively disposed in the storage region 100A, the boundary region 100B, and the peripheral region 100C, a first insulating layer 152, a second insulating layer 156, and a capacitor structure 160. The first insulating layer 152 is partially located between the first contact pad 142, the second contact pad 144, and the third contact pad 146, while the second insulating layer 156 is disposed on the first insulating layer 152 and directly contacts the top surface 152t of the first insulating layer 152a located in the storage region 100A. It should be noted that the top surface of the first insulating layer 152b located in the boundary region 100B is higher than the top surface of the first insulating layer 152a located in the storage region 100A. Therefore, the semiconductor device 10 of this embodiment can achieve different insulation effects in different regions of the semiconductor device 10 by means of the thickness difference of the first insulating layer 152 in different regions, thereby improving the structural reliability and operational performance of the semiconductor device 10.

[0035] Please repeat Figures 1 to 2 As shown, in another embodiment, the semiconductor device 10 includes at least the aforementioned substrate 100, a first contact pad 142, a second contact pad 144, and a third contact pad 146 respectively disposed in the storage region 100A, the boundary region 100B, and the peripheral region 100C, a first insulating layer 152, a cover layer 154, and a second insulating layer 156. The first insulating layer 152 is partially located between the first contact pad 142, the second contact pad 144, and the third contact pad 146. The cover layer 154 and the second insulating layer 156 are sequentially disposed on the first insulating layer 152, such that the cover layer 154 directly contacts the first insulating layers 152b and 152c located in the boundary region 100B and the peripheral region 100C, and the second insulating layer 156 directly contacts the first insulating layer 152a located in the storage region 100A and the cover layers 154b and 154c located in the boundary region 100B and the peripheral region 100C. It should be noted that the capacitor located in the storage region 100A is disposed on the substrate 100, and its lower electrode 162 penetrates the second insulating layer 156a that contacts the first insulating layer 152a and directly contacts the first contact pad 142. Similarly, the other capacitor located in the boundary region 100B is disposed on the substrate 100, and its lower electrode 164 penetrates the second insulating layer 156b that contacts the cover layer 154b, but does not contact the second contact pad 144. Thus, the semiconductor device 10 of this embodiment can utilize the differences in the placement of the first insulating layer 152 and the second insulating layer 156 in different regions to set the required capacitors and dummy capacitors in different regions of the semiconductor device 10, thereby improving the structural reliability and operational performance of the semiconductor device 10.

[0036] The semiconductor device 10 according to this embodiment is provided with a composite insulating layer IL including at least three insulating layers. By setting different stacked layers and thicknesses in different regions, different insulation effects are achieved in different regions, while optimizing the component structure in the edge region. Therefore, the semiconductor device 10 of this embodiment possesses a more reliable structure and performance while simplifying manufacturing. Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device of this application may have other forms and is not limited to those described above. Furthermore, to enable those skilled in the art to easily understand the semiconductor device 10 of this application, the manufacturing method of the semiconductor device 10 of this application will be further described below.

[0037] Please see Figures 3 to 8 The diagram shown is a schematic representation of a method for fabricating a semiconductor device 10 according to a preferred embodiment of this application. First, as... Figure 3 As shown, a substrate 100 is provided, and shallow trench isolation 102, 104, and 106 are formed in the storage region 100A, boundary region 100B, and peripheral region 100C of the substrate 100, respectively, to define active regions. In one embodiment, the shallow trench isolation 102, 104, and 106 are formed, for example, by first forming at least one trench (not shown) in the substrate 100 using an etching method, and then filling at least one insulating material (e.g., including silicon oxide or silicon oxynitride) into the at least one trench, but are not limited thereto.

[0038] Next, as Figure 4 As shown, a dielectric layer 110 (including a silicon oxide layer 112, a silicon nitride layer 114, and a silicon oxide layer 116 formed sequentially) is formed in the storage region 100A and the boundary region 100B of the substrate 100, and a gate dielectric layer 312 is formed in the peripheral region 100C of the substrate 100. In one embodiment, the dielectric layer 110 and the gate dielectric layer 312 are fabricated in a manner including but not limited to the following steps: for example, firstly, a first oxide material layer (not shown), a nitride material layer (not shown), and a second oxide material layer (not shown) are sequentially formed on the substrate 100, which completely cover the storage region 100A, the boundary region 100B, and the peripheral region 100C; then, the second oxide material layer, the nitride material layer, and the first oxide material layer in the storage region 100A and the boundary region 100B are partially removed to form the dielectric layer 110, and multiple openings (not shown) that partially expose the substrate 100 are simultaneously formed in the storage region 100A. Furthermore, the second oxide material layer and nitride material layer in the peripheral region 100C are completely removed, leaving the remaining first oxide material layer to form the gate dielectric layer 312. Alternatively, in another embodiment, the second oxide material layer, nitride material layer, and first oxide material layer formed in the peripheral region 100C may be completely removed, and the gate dielectric layer 312 may be reformed.

[0039] Then, bit lines 120 and dummy bit lines 220 are formed on the dielectric layer 110 in the memory region 100A and the boundary region 100B respectively using a similar process. Furthermore, a gate structure 320 is formed on the gate dielectric layer 312 in the peripheral region 100C. Each bit line 120, dummy bit line 220, and gate structure 320 may include the same film structure and materials, such as a semiconductor layer 122 (e.g., containing doped polycrystalline silicon, doped amorphous silicon, or other semiconductor materials), a barrier layer 124 (e.g., containing titanium and / or titanium nitride, tantalum and / or tantalum oxide, or other conductive barrier materials), a metal layer 126 (e.g., containing tungsten, aluminum, or copper, or other low-resistance metal materials), and a capping layer 128 (e.g., containing silicon oxide, silicon nitride, or silicon oxynitride, or other insulating materials), but is not limited thereto. In one embodiment, the fabrication process of the bit line 120, dummy bit line 220, and gate structure 320 includes, for example, the following steps. First, a semiconductor material layer (not shown, such as doped polycrystalline silicon, doped amorphous silicon, etc.) is sequentially formed on the substrate 100 to cover the memory region 100A, the boundary region 100B, and the peripheral region 100C, filling the opening in the memory region 100A. Then, a barrier material layer (not shown, such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc.), a metal material layer (not shown, such as tungsten, aluminum, or copper, etc., with low resistivity), and a capping material layer (not shown, such as silicon oxide, silicon nitride, or silicon oxynitride, etc., with insulating material) are formed on the semiconductor material layer. Finally, through a patterning process, a bit line 120 is formed in the memory region 100A, a dummy bit line 220 is formed in the boundary region 100B, and a gate structure 320 is formed in the peripheral region 100C. Bit line spacers 130 and gate spacers 330 are then formed on the sidewalls of each bit line 120, dummy bit line 220, and each gate structure 320, respectively. These spacers may contain insulating materials such as silicon carbonitride or silicon nitride, but are not limited thereto. The dummy bit line 220 formed within the boundary region 100B has a linewidth relatively larger than that of the bit line 120 within the memory region 100A, such as... Figure 4 As shown.

[0040] Then, a deposition and etch-back fabrication process is performed sequentially to form an insulating layer 134 between adjacent bit lines 120, dummy bit lines 220, and gate structure 320. The insulating layer 134 on both sides of the bit line 120 and the substrate 100 below it are then removed to form plug vias (not shown) that expose the corresponding active regions. The insulating layer 134 may include, for example, an insulating material etched differently from the bit line spacer 130 and gate spacer 330, such as silicon oxide or silicon oxynitride, but is not limited thereto. Subsequently, an epitaxial process is performed to form plugs 132 within each plug via that can physically contact the active regions. In one embodiment, the plugs 132 may include, for example, epitaxial materials such as silicon, silicon-phosphorus, silicon-germanium, or germanium, but are not limited thereto. Then, an insulating layer 136 is formed that covers the memory region 100A, the boundary region 100B, and the peripheral region 100C, covering the bit line 120, the plug 132, the dummy bit line 220, and the gate structure 320, as follows: Figure 4 As shown.

[0041] like Figure 5 As shown, an etching process is first performed through a mask layer (not shown) to form multiple openings 136a in the insulating layer 136 within the storage region 100A, which expose the plug 132. Furthermore, multiple through-holes TR are formed in the insulating layers 134 and 136 within the peripheral region 100C, which expose a portion of the substrate 100. Then, after removing the mask layer, a deposition process is performed sequentially to form an integrally covering conductive material layer 240 in the storage region 100A, the boundary region 100B, and the peripheral region 100C, filling each opening 136a and each through-hole TR, and further covering the insulating layer 136. In one embodiment, the conductive material layer 240 preferably includes a barrier material layer 242 and a metal material layer 244 formed sequentially. The barrier material layer 242 includes, for example, titanium and / or titanium nitride, tantalum and / or tantalum oxide, and other conductive barrier materials, while the metal material layer 244 includes, for example, low-resistance metal materials such as copper, aluminum, titanium, and tungsten, but is not limited thereto.

[0042] like Figure 6 As shown, a patterning process is first performed using another mask layer (not shown), partially removing elements such as... Figure 5The conductive material layer 240 and the insulating layer 136 below it are shown. Multiple first openings OP1, second openings OP2, and multiple third openings OP3 are formed in the storage region 100A, the boundary region 100B, and the peripheral region 100C, respectively. The second opening OP2 formed in the boundary region 100B has a relatively large linewidth and is located on a dummy bit line 220, which also has a large linewidth. Furthermore, while forming the first openings OP1, OP2, and OP3, a first contact pad 142 is simultaneously formed in the storage region 100A, a second contact pad 144 is formed in the boundary region 100B, and a third contact pad 146 is formed in the peripheral region 100C. The first contact pad 142 formed in the storage area 100A contacts each of the plugs 132 below, the second contact pad 144 formed in the boundary area 100B is entirely located on the insulating layer 136, and a plug 332 is further integrally formed below the third contact pad 146 partially formed in the peripheral area 100C.

[0043] Then, another mask layer is removed, and a deposition process is performed to form a first insulating material layer 252 that integrally covers the first contact pad 142, the second contact pad 144, and the third contact pad 146 within the storage area 100A, the boundary area 100B, and the peripheral area 100C, and fills each of the first openings OP1, the second opening OP2, and each of the third openings OP3. It should be noted that the first insulating material layer 252 completely fills the first opening OP1 in the storage area 100A and the third opening OP3 in the peripheral area 100C, and partially fills the second opening OP2 with a larger linewidth, so that the first insulating material layer 252 formed in the second opening OP2 exhibits the following appearance: Figure 6 The recessed contour is shown. Next, a mask ML1 is formed on the first insulating material layer 252 that simultaneously covers the boundary region 100B, the peripheral region 100C, and the adjacent boundary region 100B. Then, an etching process is performed on the first insulating material layer 252 through the mask ML1 to partially remove the first insulating material layer 252 exposed from the mask ML1.

[0044] like Figure 7As shown, the mask ML1 is removed, forming a first insulating layer 152 that is simultaneously located in the storage area 100A, the boundary area 100B, and the peripheral area 100C. The first insulating layer 152a formed in the storage area 100A is disposed between adjacent first contact pads 142, such that the first insulating layer 152a and the first contact pads 142 alternately occupy positions within the insulating layer 136 in the horizontal direction X. Furthermore, the first insulating layer 152a formed in the storage area 100A additionally covers one of the first contact pads 142 adjacent to the boundary area 100B, and is continuously disposed and connected to the first insulating layer 152b formed in the boundary area 100B and the first insulating layer 152c formed in the peripheral area 100C. The first insulating layer 152b formed in the boundary area 100B is located between the second contact pad 144 and its adjacent first contact pad 142, and further covers the second contact pad 144. It should be noted that the first insulating layer 152a formed between the second contact pad 144 and the first contact pad 142 also has an additional recess RS, wherein the lowest point b1 of the recess RS is, for example, lower than the top surface 142t of the first contact pad 142. Figure 7 As shown. The first insulating layer 152c formed in the peripheral area 100C is partially located between adjacent third contact pads 146 and partially covers the third contact pads 146, and has an overall flat top surface.

[0045] Then, a deposition process is performed again to form a cover material layer 254 that integrally covers the first insulating layer 152 and the first contact pad 142 within the storage region 100A, the boundary region 100B, and the peripheral region 100C. In one embodiment, the cover material layer 254 may include, for example, an insulating material with an etch selectivity different from that of the first insulating material layer 252, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., but is not limited thereto. Next, a mask ML2 is formed on the cover material layer 254 that simultaneously covers the boundary region 100B, the peripheral region 100C, and one first contact pad 142 adjacent to the boundary region 100B. Then, an etching process is performed on the cover material layer 254 through the mask ML2 to completely remove the cover material layer 254 exposed from the mask ML2.

[0046] like Figure 8As shown, mask ML2 is removed to form a cover layer 154, which is located within the boundary region 100B and the peripheral region 100C. It should be noted that the cover layer 154 is not formed on the first insulating layer 152a within the storage region 100A, exposing the first insulating layer 152a and the first contact pad 142 formed within the storage region 100A. The cover layer 154b formed in the boundary region 100B and the cover layer 154c formed in the peripheral region 100C respectively cover the first insulating layer 152b formed in the boundary region 100B and the first insulating layer 152c formed in the peripheral region 100C. The cover layer 154b formed in the boundary region 100B also conformally covers the recessed portion RS of the first insulating layer 152b, and also has a partially recessed morphology, while the cover layer 154c formed in the peripheral region 100C has a completely flat top surface. Then, a deposition process is performed again to form a second insulating material layer 256 that integrally covers the first insulating layer 152a, the first contact pad 142, and the cover layer 154 within the storage region 100A, the boundary region 100B, and the peripheral region 100C. In one embodiment, the second insulating material layer 256 may include, for example, an insulating material with an etch selectivity different from that of the first insulating material layer 252 and the cover material layer 254, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., but is not limited thereto.

[0047] Then, the second insulating material layer 256 formed in the storage area 100A is partially removed, and a layer such as is formed in the storage area 100A and the boundary area 100B. Figure 1 The capacitor structure 160 shown can form a capacitor like this. Figure 1 The second insulating layer 156 is shown to be located simultaneously in the storage area 100A, the boundary area 100B, and the peripheral area 100C. The second insulating layer 156a formed in the storage area 100A directly covers the first insulating layer 152a, while the second insulating layer 156b formed in the boundary area 100B and the second insulating layer 156c formed in the peripheral area 100C directly cover the cover layer 154b in the boundary area 100B and the cover layer 154c in the peripheral area 100C.

[0048] It should be noted that when forming the lower electrodes 162 and 164 of the capacitor structure 160, the second insulating material layer 256 in the storage region 100A is partially removed, exposing the underlying first contact pad 142. Similarly, the second insulating material layer 256 and the cover layer 154b in the boundary region 100B are partially removed, exposing the underlying first insulating layer 152b. This allows the lower electrode 162 formed in the storage region 100A to directly contact the first contact pad 142, while the lower electrode 164 formed in the boundary region 100B contacts the first insulating layer 152b within the boundary region 100B. Furthermore, when forming the lower electrode 164 adjacent to the boundary region 100B, the second insulating material layer 256 covering the first insulating layer 152a is also partially removed, but the first insulating layer 152a covering the first contact pad 142 is not removed. This allows the subsequently formed lower electrode 164 to directly contact the first insulating layer 152a formed in the storage region 100A, as described above. Figure 1 As shown. Thus, when forming the lower electrodes 162 and 164, the second insulating layer 156a located in the storage region 100A and the second insulating layer 156b located in the boundary region 100B are also formed.

[0049] It should also be noted that when the capacitor dielectric layer 166, upper electrode layer 168, and insulating layer 170 of the capacitor structure 160 are subsequently formed using a patterning process, the second insulating material layer 256 in the peripheral region 100C is partially removed. This results in the thickness th2 of the second insulating layer 156c finally formed in the peripheral region 100C being less than the thickness th1 of the second insulating layer 156b formed in the boundary region 100B. Therefore, the first insulating layer 152 formed simultaneously in the storage region 100A, boundary region 100B, and peripheral region 100C, the cover layer 154 formed simultaneously in the boundary region 100B and peripheral region 100C, and the second insulating layer 156 formed simultaneously in the storage region 100A, boundary region 100B, and peripheral region 100C together form... Figure 1 The composite insulating layer IL shown is composed of insulating layers of different numbers and / or thicknesses in the storage area 100A, boundary area 100B, and peripheral area 100C, respectively, to effectively isolate the first contact pad 142 formed in the storage area 100A, the second contact pad 144 formed in the boundary area 100B, and the third contact pad 146 formed in the peripheral area 100C, and to achieve different insulation effects.

[0050] Subsequently, an interlayer dielectric layer 178 is formed that covers the capacitor structure 160 and the composite insulating layer 11. Connection structures 180 and 182, respectively connecting the capacitor structure 160 and the third contact pad 146, are formed within the interlayer dielectric layer 178. This completes the fabrication method of the semiconductor device 10 in the preferred embodiment. In this operation, the plug 132 formed in the storage region 100A serves as the storage node plug of the semiconductor device 10, and the first contact pad 142 formed above the plug 132 serves as the storage node pad of the semiconductor device 10, electrically connecting the capacitor of the capacitor structure 160 above it to the corresponding active region through the storage node pad and the storage node plug. Thus, the capacitor and the transistor assembly (not shown) disposed in the substrate 100 can form the smallest possible storage cell to receive voltage information from the bit line 120 and the word line (not shown), enabling the semiconductor device 10 of this embodiment to form a dynamic random access memory device, and electrically connected to different components or devices through the connection structure 180 to perform different operations.

[0051] Those skilled in the art to which this application pertains will readily understand that, to meet actual product requirements, the semiconductor device of this application may have other forms and is not limited to those described above. Further embodiments or variations of the semiconductor device of this application will be described below. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the embodiments of this application are designated with the same reference numerals to facilitate comparison between embodiments.

[0052] Please refer to Figure 9 The diagram shown is a cross-sectional view of the semiconductor device 20 in the second embodiment of this application. The structure and fabrication method of the semiconductor device 20 in this embodiment are largely the same as those of the semiconductor device 10 in the previous embodiment, and the similarities will not be repeated here. The main difference between the semiconductor device 20 in this embodiment and the previous embodiment is that at least the sidewall 364s of the lower electrode 364 simultaneously physically contacts the first insulating layer 152, the capping layer 154, and the second insulating layer 156.

[0053] In detail, in the capacitor structure 360 ​​of this embodiment, when forming the lower electrode 364 within the boundary region 100B, the second insulating material layer 256, the cover layer 154b, and the underlying first insulating layer 152b within the boundary region 100B are partially removed, so that the lower electrode 364 still partially extends into the first insulating layer 152b. Thus, the bottom surface 364b of the lower electrode 364 still contacts the first insulating layer 152b within the boundary region 100B, while its sidewalls 364s simultaneously contact the second insulating layer 156b, the cover layer 154b, and the first insulating layer 152b within the boundary region 100B. In this operation, the semiconductor device 20 still has a composite insulating layer IL formed by a first insulating layer 152 simultaneously formed in the storage region 100A, the boundary region 100B, and the peripheral region 100C, a cover layer 154 simultaneously formed in the boundary region 100B and the peripheral region 100C, and a second insulating layer 156 simultaneously formed in the storage region 100A, the boundary region 100B, and the peripheral region 100C. This effectively isolates the first contact pad 142 formed in the storage region 100A, the second contact pad 144 formed in the boundary region 100B, and the third contact pad 146 formed in the peripheral region 100C, achieving different insulation effects. Furthermore, the capacitor structure 360 ​​of this embodiment can obtain a more reliable and stable structure by using the composite insulating layer IL to set the required dummy capacitor in the boundary region 100B and the storage region 100A adjacent to the boundary region 100B.

[0054] Please refer to Figure 10 The diagram shown is a cross-sectional view of the semiconductor device 30 in the third embodiment of this application. The structure and fabrication method of the semiconductor device 30 in this embodiment are largely the same as those of the semiconductor device 10 in the previous embodiment, and the similarities will not be repeated here. The main difference between the semiconductor device 30 in this embodiment and the previous embodiment is that at least the bottom surface 464b of the lower electrode 464 is in physical contact with the second insulating layer 456.

[0055] In detail, in the capacitor structure 460 of this embodiment, when forming the lower electrode 464 within the boundary region 100B, the second insulating material layer 256 and the underlying cover layer 454b within the boundary region 100B are not removed. This ensures that both the second insulating layer 456b and the cover layer 454b formed within the boundary region 100B have a continuous film layer covering the first insulating layer 152b. Furthermore, the lower electrode 464 formed within the boundary region 100B is directly located on the second insulating layer 456b. Thus, the bottom surface 464b of the lower electrode 464 still contacts the second insulating layer 156b within the boundary region 100B. Figure 10As shown. In another embodiment, when forming the lower electrode 464, it is also possible to remove only the second insulating material layer 256 within the boundary region 100B without removing the cover layer 454b. In this way, its bottom surface (not shown) can selectively contact the cover layer 454b below the second insulating layer 456b.

[0056] In this operation, the semiconductor device 30 still has a composite insulating layer IL formed by a first insulating layer 152 simultaneously formed in the storage region 100A, the boundary region 100B, and the peripheral region 100C, a cover layer 454 simultaneously formed in the boundary region 100B and the peripheral region 100C, and a second insulating layer 456 simultaneously formed in the storage region 100A, the boundary region 100B, and the peripheral region 100C. This effectively isolates the first contact pad 142 formed in the storage region 100A, the second contact pad 144 formed in the boundary region 100B, and the third contact pad 146 formed in the peripheral region 100C, achieving different insulation effects. Furthermore, the capacitor structure 460 of this embodiment can also obtain a more reliable and stable structure by using the composite insulating layer IL to set the required dummy capacitor in the boundary region 100B and the storage region 100A adjacent to the boundary region 100B.

[0057] In general, this application involves forming composite insulating layers with varying stacked layers and / or thicknesses in different regions of a semiconductor device. These thickness differences isolate contact pads located in different regions, achieving different insulation effects. Furthermore, the composite insulating layer allows for the creation of dummy capacitances at the edge regions of the semiconductor device, thereby improving component reliability and resulting in more stable device performance.

[0058] The foregoing has outlined the features of several embodiments to enable those skilled in the art to fully understand various aspects of this application. Those skilled in the art should recognize that this application provides a basis for designing or modifying other processes and structures to achieve substantially the same functionality and / or substantially the same results as the embodiments described above. Furthermore, such equivalent configurations do not depart from the spirit and scope of this application, and various changes, substitutions, and modifications can be made without departing from that spirit and scope.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes the storage region, the boundary region, and the peripheral region; A contact pad structure is disposed on the substrate, including a first contact pad located in the storage area, a second contact pad located in the boundary area, and a third contact pad located in the peripheral area; A composite insulating layer is disposed on the substrate and partially located on the contact pad structure. The first portion of the composite insulating layer on the first contact pad has a first thickness W1, the second portion of the composite insulating layer on the second contact pad has a second thickness W2, and the third portion of the composite insulating layer on the third contact pad has a third thickness W3. The first thickness W1 is less than the third thickness W3, and the third thickness W3 is less than the second thickness W2. A capacitor structure is disposed on the contact pad structure. The capacitor structure includes multiple lower electrodes, a capacitor dielectric layer, and an upper electrode layer. Part of the lower electrodes penetrates the composite insulation and contacts the first contact pad.

2. The semiconductor device according to claim 1, characterized in that, The top surface of the first portion of the composite insulating layer is lower than the top surface of the third portion of the composite insulating layer, and the top surface of the second portion of the composite insulating layer is higher than the top surface of the third portion of the composite insulating layer.

3. The semiconductor device according to claim 1, characterized in that, The composite insulating layer further includes at least three insulating layers, wherein the first part has fewer layers than the second part and the third part.

4. The semiconductor device according to claim 2, characterized in that, The composite insulating layer further includes a first insulating layer, a cover layer, and a second insulating layer sequentially disposed on the substrate, wherein the first part includes the first insulating layer, the second part includes the first insulating layer, the cover layer, and the second insulating layer, and the third part includes the first insulating layer, the cover layer, and the second insulating layer.

5. The semiconductor device according to claim 4, characterized in that, The thickness of the second insulating layer in the second part is greater than the thickness of the second insulating layer in the third part.

6. The semiconductor device according to claim 4, characterized in that, Part of the second insulating layer directly contacts the top surface of the first insulating layer.

7. The semiconductor device according to claim 4, characterized in that, The top surface of the first part is lower than the top surface of the cover layer of the second part.

8. The semiconductor device according to claim 4, characterized in that, The first insulating layer of the second part further includes a recess located within the boundary region, the lowest point of which is lower than the top surface of the first contact pad.

9. The semiconductor device according to claim 8, characterized in that, Also includes: A dummy bit line is disposed on the substrate and located within the boundary region, and the recessed portion is above the dummy bit line.

10. The semiconductor device according to claim 1, characterized in that, Also includes: Multiple bit lines and multiple plugs are alternately arranged within the storage area of ​​the substrate; The plug is located below the first contact pad and makes physical contact with the first contact pad. The gate structure is located within the peripheral region and below the third contact pad.

11. The semiconductor device according to claim 4, characterized in that, At least one of the lower electrodes has its bottom surface in physical contact with the first insulating layer.

12. The semiconductor device according to claim 4, characterized in that, At least one of the lower electrodes has its sidewall in physical contact with the first insulating layer, the cover layer, and the second insulating layer simultaneously.

13. The semiconductor device according to claim 4, characterized in that, The bottom surface of at least one of the lower electrodes is in physical contact with the cover layer or the second insulating layer.

14. The semiconductor device according to claim 10, characterized in that, The upper electrode layer includes an upper protrusion, a middle protrusion, and a lower protrusion, which correspond to the upper support layer, the lower support layer, and the portion adjacent to the composite insulating layer, respectively. The distance between the lower protrusion and the middle protrusion in the horizontal direction is L1, and the distance between the end of the capacitor dielectric layer and the middle protrusion is L2. L1 is not equal to L2.

15. A method for fabricating a semiconductor device, characterized in that... include: A substrate is provided, the substrate including a storage region, a boundary region, and a peripheral region; A contact pad structure is formed on the substrate, the contact pad structure including a first contact pad formed in the storage area, a second contact pad formed in the boundary area, and a third contact pad formed in the peripheral area; A composite insulating layer is formed on the substrate, partially located on the contact pad structure. The first portion of the composite insulating layer on the first contact pad has a first thickness W1, the second portion of the composite insulating layer on the second contact pad has a second thickness W2, and the third portion of the composite insulating layer on the third contact pad has a third thickness W3. The first thickness W1 is less than the third thickness W3, and the third thickness W3 is less than the second thickness W2. A capacitor structure is formed on the contact pad structure. The capacitor structure includes multiple lower electrodes, a capacitor dielectric layer, and an upper electrode layer. Part of the lower electrodes penetrates the composite insulating layer and contacts the first contact pad.

16. The method for fabricating a semiconductor device according to claim 15, characterized in that, The top of the first portion of the composite insulation layer is lower than the top of the third portion of the composite insulation layer, and the top of the second portion of the composite insulation layer is higher than the top of the third portion of the composite insulation layer.

17. The method for fabricating a semiconductor device according to claim 15, characterized in that, The composite insulating layer further includes a first insulating layer, a cover layer, and a second insulating layer sequentially disposed on the substrate, wherein the first part includes the first insulating layer, the second part includes the first insulating layer, the cover layer, and the second insulating layer, and the third part includes the first insulating layer, the cover layer, and the second insulating layer.

18. The method for fabricating a semiconductor device according to claim 17, characterized in that, The formation of the composite insulating layer further includes: A first insulating material layer is formed in the storage area, the boundary area and the peripheral area, covering the first contact pad, the second contact pad and the third contact pad; Partial removal of the first insulating material layer formed in the storage area to form the first insulating layer, wherein the first insulating layer is partially formed between the first contact pad, the second contact pad and the third contact pad, and partially covers the second contact pad and the third contact pad.

19. The method for fabricating a semiconductor device according to claim 18, characterized in that, The formation of the composite insulating layer further includes: A second insulating material layer is formed in the storage area, the boundary area, and the peripheral area, covering the first contact pad and the first insulating layer; Remove the second insulating material layer formed in the storage area to form the cover layer.

20. The method for fabricating a semiconductor device according to claim 19, characterized in that, The formation of the composite insulating layer further includes: A second insulating layer is formed within the storage area, the boundary, and the peripheral area, covering the first insulating layer and the cover layer, wherein the thickness of the second insulating layer in the second portion is greater than the thickness of the second insulating layer in the third portion.

21. A semiconductor device, characterized in that... include: The substrate includes the storage region, the boundary region, and the peripheral region; The first contact pad, the second contact pad, and the third contact pad are disposed on the substrate and are located in the storage area, the boundary area, and the peripheral area, respectively. A first insulating layer is disposed on the substrate, partially located between the first contact pad, the second contact pad and the third contact pad, and partially covering and contacting the top surfaces of the second contact pad and the third contact pad; A second insulating layer is disposed on the first insulating layer, and the second insulating layer also contacts the top surface of the first insulating layer located in the storage area; A capacitor structure includes a lower electrode, a capacitor dielectric layer, and an upper electrode layer, wherein the lower electrode of the capacitor structure penetrates the second insulating layer and is electrically connected to the first contact pad.

22. A semiconductor device, characterized in that... include: The substrate includes the storage region, the boundary region, and the peripheral region; The first contact pad, the second contact pad, and the third contact pad are disposed on the substrate and are located in the storage area, the boundary area, and the peripheral area, respectively. A first insulating layer is disposed on the substrate and partially located between the first contact pad, the second contact pad and the third contact pad, wherein the top surface of the first insulating layer located in the boundary region is higher than the top surface of the first insulating layer located in the storage region. A second insulating layer is disposed on the first insulating layer, and the second insulating layer also contacts the top surface of the first insulating layer located in the storage area; A capacitor structure includes a lower electrode, a capacitor dielectric layer, and an upper electrode layer, wherein the lower electrode of the capacitor structure penetrates the second insulating layer and is electrically connected to the first contact pad.

23. A semiconductor device, characterized in that... include: The substrate includes the storage region, the boundary region, and the peripheral region; The first contact pad, the second contact pad, and the third contact pad are disposed on the substrate and are located in the storage area, the boundary area, and the peripheral area, respectively. A first insulating layer is disposed on the substrate, and is partially located between the first contact pad, the second contact pad and the third contact pad; A cover layer is disposed on the first insulating layer and directly contacts the first insulating layer located in the boundary area and the peripheral area; A second insulating layer is disposed on the cover layer and contacts the first insulating layer located in the storage area and the cover layer located in the boundary area and the peripheral area; A first capacitor is disposed on the substrate, penetrates the second insulating layer that contacts the first insulating layer, and directly contacts the first contact pad; A second capacitor is disposed on the substrate, penetrates the second insulating layer that contacts the cover layer, and does not contact the second contact pad.

24. The semiconductor device according to any one of claims 21 to 23, characterized in that, The thickness of the second insulating layer located in the boundary region is greater than the thickness of the second insulating layer located in the peripheral region.

25. The semiconductor device according to any one of claims 21 to 23, characterized in that, The first insulating layer further includes a recess located within the boundary region, the lowest point of which is lower than the top surface of the first contact pad.

26. The semiconductor device according to claim 25, characterized in that, Also includes: A dummy bit line is disposed on the substrate and located within the boundary region, and the recessed portion is above the dummy bit line.

27. The semiconductor device according to any one of claims 21 to 23, characterized in that, Also includes: A plug is disposed within the storage area of ​​the substrate, located below the first contact pad, and in physical contact with the first contact pad; The gate structure is located within the peripheral region and below the third contact pad.

Images