Semiconductor device, layout and method of forming a memory device

Abstract

Embodiments of this disclosure relate to a semiconductor device, a method of layout, and forming a memory device. Embodiments of this disclosure relate to a one-time programmable (OTP) memory device including double-sided bit lines and front-side word lines. In some embodiments, the bit lines may be configured over a first front-side interconnect layer (MO) and a first back-side interconnect layer (BM0). In some embodiments, the memory device includes back-side power rails configured on one or more back-side interconnect layers. In some embodiments, the back-side bit lines and back-side power rails within the first back-side interconnect layer (BM0) are arranged parallel to the word lines within the first front-side interconnect layer (MO). This double-sided bit line layout can reduce local bit line resistance. The parallel arrangement of bit lines / power lines and word lines allows the memory device to achieve a read window and improve performance.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of semiconductors, and more specifically, to semiconductor devices, layouts, and methods of forming memory devices. Background Technology

[0002] In the evolution of integrated circuits (ICs), functional density (i.e., the number of interconnects per unit chip area) has continuously increased, while geometric dimensions (i.e., the smallest components or linewidths that a process can fabricate) have continuously shrunk. This miniaturization process has significantly increased the complexity of IC processes and manufacturing. For some memory devices, as device size continues to shrink, the size of metal lines is also forced to shrink, which may lead to increased parasitic resistance and capacitance, increased process risks, and / or deterioration of connection quality. In addition, some signal lines may be placed in metal lines far from the memory cells, which not only reduces the operating speed of the memory device but also increases the complexity of circuit design. Summary of the Invention

[0003] An embodiment of the present invention provides a semiconductor device, comprising: a device layer including transistors for a row of fuse memory cells and a first cladding unit; a first interconnect structure disposed on a first side of the device layer, wherein the first interconnect structure includes: a first bit line connected to the row of fuse memory cells; and a fuse resistor connected to the transistors of the row of fuse memory cells; and a second interconnect structure disposed on a second side of the device layer, wherein the second interconnect structure includes a second bit line, and the first bit line and the second bit line are interconnected through a conductive path within the first cladding unit.

[0004] Another embodiment of the present invention provides a layout of a semiconductor device, comprising: an array of one-time programmable (OTP) memory cells arranged in a plurality of rows and a plurality of columns, wherein the plurality of rows extend along a first direction and the plurality of columns extend along a second direction; a plurality of word line (WL) rails, wherein each word line rail is connected to a row of the OTP memory cells; a plurality of control gate (CG) rails, wherein each control gate rail is connected to a row of the OTP memory cells; a plurality of first bit lines extending along the second direction, wherein each first bit line is disposed along a column of the OTP memory cells; and a plurality of second bit lines extending along the second direction, wherein each second bit line is disposed along a column of the OTP memory cells, and the second bit lines disposed along a column of the OTP memory cells are electrically connected to the first bit lines.

[0005] Another embodiment of the present invention provides a method for forming a memory device, comprising: forming a device layer on a first side of a substrate, wherein the device layer includes transistors and cladding units, the transistors being used for a column of fuse memory cells; forming a front interconnect structure above the device layer, wherein the front interconnect structure includes a first bit line and a fuse resistor, the first bit line being used for the column of memory cells, and the fuse resistor being used for the column of fuse memory cells; and forming a back interconnect structure on the device layer, wherein the back interconnect structure includes a second bit line, the second bit line being used for the column of fuse memory cells, and the first bit line being connected to the second bit line through a conductive path formed within the cladding unit. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 The diagram shows a block diagram of a storage device according to certain embodiments of the present disclosure.

[0008] Figure 2A A schematic diagram including a storage device portion is shown as an electric fuse memory cell according to certain embodiments of the present disclosure.

[0009] Figures 2B to 2E The circuit diagram is schematic and shows read and write operations of an electric fuse memory cell according to certain embodiments of the present disclosure.

[0010] Figure 3A The circuit diagram is schematically shown as a storage device according to certain embodiments of the present disclosure.

[0011] Figure 3B This is a schematic layout of a storage device according to certain embodiments of the present disclosure.

[0012] Figure 3C for Figure 3B A magnified view of the layout.

[0013] Figure 3D for Figure 3B A magnified view of the layout.

[0014] Figure 3E for Figure 3C A partially enlarged schematic diagram of the layout shows a fuse resistor according to certain embodiments of the present disclosure.

[0015] Figures 4A to 4H They are respectively Figure 3CThe middle line includes AA, BB, CC, DD, EE, and FF lines, as well as... Figure 3D A cross-sectional view of the layout shown along lines GG and HH.

[0016] Figure 5 The circuit diagram is schematically shown as a storage device according to certain embodiments of the present disclosure.

[0017] Figure 6A This is a schematic partial layout of a storage device according to certain embodiments of the present disclosure.

[0018] Figure 6B for Figure 6A Partial cross-sectional view of the layout along the BB line.

[0019] Figure 7 This is a flowchart of a method for forming a storage device according to certain embodiments of the present disclosure. Detailed Implementation

[0020] This invention provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 64 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0022] The foregoing provides a general overview of certain aspects of the embodiments described in this disclosure. While some embodiments described herein are set in the context of planar transistors (FETs), implementations of certain aspects of this disclosure can be applied to other processes and / or other devices, such as FinFETs, Gate All-Around FETs (GAA FETs) (e.g., Horizontal Gate All Around (HGAA) transistors and Vertical Gate All-Around (VGAA) transistors), and other suitable devices. Those skilled in the art will readily understand that other possible modifications are covered by this disclosure. Furthermore, although method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order, and may have fewer or more steps than those described herein. Source / drain regions may refer to a single source or drain, or, depending on the context, a combination of both.

[0023] Embodiments of this disclosure relate to non-volatile memory (NVM) devices, such as one-time programmable (OTP) memory devices. The memory device according to this disclosure includes double-sided bit lines with front-side word lines. In some embodiments, the bit lines may be arranged between a first front-side interconnect layer (M0) and a first back-side interconnect layer (BM0). In some embodiments, the memory device includes back-side power rails. The back-side power rails are arranged in one or more back-side interconnect layers. In some embodiments, the back-side bit lines and back-side power rails within the first back-side interconnect layer (BM0) are arranged parallel to the word lines in the first front-side interconnect layer (M0). This double-sided bit line arrangement can reduce local bit line resistance. The parallel arrangement of the bit lines / power lines with the word lines allows the memory device to implement read windows and improve performance.

[0024] Figure 1 The diagram shown is a block diagram of a storage device 100 according to certain embodiments of the present disclosure. Figure 1 As shown, the storage device 100 includes a memory cell array 102, a row decoder 104, a column decoder 106, input / output (I / O) circuitry 108, and control logic circuitry 112. Although not explicitly stated... Figure 1 As shown, all components of the storage device 100 can be interconnected and connected to the control logic circuit 112. Although Figure 1 In the illustrated embodiment, each element is drawn as a separate block for clarity, but in other embodiments, Figure 1 Some or all of the components shown can be integrated into one unit.

[0025] The memory cell array 102 is a hardware element for storing data. In some embodiments, the memory cell array 102 is implemented as a semiconductor memory device. The memory cell array 102 includes a plurality of memory cells (or other storage cells) 103. The memory cell array 102 includes several rows R1, R2, R3…RM, each row extending along a first direction (e.g., the X direction); and several columns C1, C2, C3…CN, each column extending along a second direction (e.g., the Y direction). Each column and each row may include one or more conductive structures (e.g., metal) that function as access lines. Each memory cell 103 is disposed at the intersection of the corresponding column and the corresponding row and can be operated by applying voltage or current through the conductive structures of the row and column respectively. For example, each row may include a corresponding word line (WL), and each column may include a corresponding bit line (BL) and multiple corresponding control gate (CG) lines.

[0026] In some embodiments, each memory cell 103 is implemented as a fuse memory cell, which may include a fuse resistor, a control / cascaded gate (CG) selector / transistor, and a word line (WL) selector transistor. The fuse resistor, CG transistor, and WL transistor are interconnected in series. Furthermore, the corresponding WL may be connected to the respective gate of one or more WL transistors, the corresponding bit line (BL) may be connected to each terminal of the fuse resistor, and the corresponding CG may be connected to the gate of the cascaded gate transistor.

[0027] Although in various embodiments of this disclosure, memory cell 103 is implemented as a fuse memory cell comprising a plurality of fuse resistors, each fuse resistor being formed on a metal rail in a corresponding metallization layer, the fuse resistors of memory cell 103 may also be implemented based on other resistive memory configurations. For example, memory cell 103 may be configured as resistive random access memory (RRAM), phase change random access memory (PCRAM or PRAM), or magnetoresistive random access memory (MRAM). In some embodiments, the fuse resistors of memory cell 103 may be implemented based on a through-hole structure or a polysilicon structure. Furthermore, in other embodiments, memory cell 103 may be implemented as an electrically fused memory cell comprising a plurality of fuse capacitors, wherein each fuse capacitor may be formed as a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor.

[0028] Row decoder 104 is a hardware component that receives the row address of memory cell array 102 and establishes a conductive structure (e.g., WL) at the row address. Column decoder 106 is a hardware component that receives the column address of memory cell array 102 and establishes multiple conductive structures (e.g., BL and one or more CG lines) at the column address. I / O circuit 108 is a hardware component that can access (e.g., read, program) each memory cell 103 through row decoder 104 and column decoder 106. Control logic circuit 112 is a hardware component that can control the connected components (e.g., 102 to 108).

[0029] Figure 2A A schematic diagram including a storage device 100 portion is shown as an electric fuse memory cell 103 according to certain embodiments of the present disclosure. Figure 2A The figure shows fuse memory cells 103A-103H (collectively referred to as memory cells 103) in memory cell array 102, each of which contains a fuse resistor. Although only eight fuse memory cells 103A-103H are shown in the figure, it should be understood that memory cell array 102 may contain any number of similar fuse memory cells, and this configuration is still within the scope of this disclosure.

[0030] The fuse memory cells 103 can be configured as an array. Memory cells 103A, 103B, 103C, and 103D can be configured in the same row but in different columns. Memory cells 103E, 103F, 103G, and 103H can be configured in the same row but in different columns. For example, memory cells 103A, 103B, 103C, and 103D are located in row R0 but in columns C0, C1, C2, and C3, respectively. Memory cells 103E, 103F, 103G, and 103H are located in row R1 but in columns C0, C1, C2, and C3, respectively. In this configuration, each memory cell can establish an operational connection with the access lines of the corresponding column and row. In some embodiments, along each row direction, a plurality of fuse memory cells 103 are connected to corresponding WL lines. Along each column direction, a plurality of fuse memory cells 103 are connected to corresponding BL lines and a plurality of corresponding CG lines. For example, fuse memory cells 103A, 103B, 103C, and 103D are all connected to WL0 located in row R0, and are respectively connected to BL0 and CG0 located in column C0, BL1 and CG1 located in column C1, BL2 and CG2 located in column C2, and BL3 and CG3 located in column C3. Fuse memory cells 103E, 103F, 103G, and 103H are all connected to WL1 located in row R1, and are respectively connected to BL0 and CG0 located in column C0, BL1 and CG1 located in column C1, BL2 and CG2 located in column C2, and BL3 and CG3 located in column C3.

[0031] In some embodiments, the fuse memory cell 103 may include a fuse resistor 210, a CG transistor 230, and a WL transistor 250. The fuse resistor 210, CG transistor 230, and WL transistor 250 are connected in series between BL0 and ground. The source / drain region of the CG transistor 230 is connected to ground through the WL transistor 250. Figure 2A The design of the shown fuse memory cell 103 is sometimes referred to as a dual-transistor-1-resistor (2T1R) configuration. Figure 2A In this embodiment, both CG transistor 230 and WL transistor 250 are implemented as n-type transistors. However, it should be understood that these transistors can also be implemented as p-type transistors, and would still fall within the scope of this disclosure.

[0032] Taking the fuse memory cell 103A as a representative example, the first end (or termination) of the fuse resistor 210 is connected to BL0, and the second end (or termination) is connected to the first source / drain region of the CG transistor 230. The second source / drain region of the CG transistor 230 is connected to the first source / drain region of the WL transistor 250, which is connected to ground. The gate of the WL transistor 250 is connected to WL0. The gate of the CG transistor 230 is connected to CG0.

[0033] To program the fuse memory cell 103, the corresponding WL and CG transistors must first be activated. In an example where each transistor is implemented using an n-type transistor, the WL and CG transistors can be activated (e.g., turned on) by applying logic high-level signals to the WL and CG lines respectively. Then, a programming signal (e.g., voltage) is applied to the BL line. Figure 2B As shown, to write logic 1 into the fuse memory cell 103, a high programming voltage can be applied to the BL line. With transistors WL and CG conducting, the high programming voltage is applied across the fuse resistor, causing current to flow and ultimately blowing the fuse resistor. After the fuse resistor blows, the fuse memory cell 103 becomes open-circuit, thus completing the programming of logic 1. Figure 2C As shown, to write logic 0 into the fuse memory cell 103, a low programming voltage can be applied to the BL line. Even if the WL transistor and the CG transistor are both turned on, the low programming voltage still cannot allow current to flow through the fuse resistor. When the programming period ends, the fuse resistor remains on, and the fuse memory cell 103 is then programmed with logic 0.

[0034] To read the fuse memory cell 103, the corresponding WL transistor and CG transistor are first activated. In some embodiments, the selected activated CG transistors remain constant throughout the entire memory array. For example, in all columns of the memory array, only one CG line is activated during the read process. A read signal (e.g., voltage) is then applied to BL. If the fuse resistor has been programmed or blown (e.g.) Figure 2D As shown), a conduction path cannot be established from BL through the blown fuse resistor, the selected (start-up) CG transistor, and the WL transistor to ground. If the fuse resistor is not programmed or is blown, a conduction path can be established from BL through the fuse resistor, the CG transistor, and the WL transistor to ground, as shown. Figure 2EAs shown. In some embodiments: if no conduction path is established (i.e., the fuse resistor connected to the selected CG transistor has blown), the electric fuse memory cell 103 is determined to be in a first logic state (e.g., logic 1); while when the conduction path is established (i.e., the fuse resistor connected to the selected CG transistor has not blown), the electric fuse memory cell 103 is determined to be in a second logic state (e.g., logic 0).

[0035] Figure 3A A circuit diagram 300a schematically illustrates a memory device according to certain embodiments of the present disclosure. At least a portion of the memory cells in the memory device 300 are connected to two bit lines. In some embodiments, the two bit lines are configured on opposite sides of the memory cell, for example, front and back sides. In some embodiments, the two bit lines are connected in parallel to the same driving transistor. In some embodiments, the two bit lines are interconnected through one or more wrapper cells. This two-bit-line configuration can reduce wiring resistance, thereby achieving excellent programming performance at low voltages.

[0036] Figure 3A A partial circuit diagram 300a including the storage device 300. Figure 3A Contains a column of electric fuse memory cells 1030, 1031, 1032, 1033, ... 103 n The series of fuse memory units 1030, 1031, 1032, 1033, ... 103 n Connect to the same bit line BL and multiple word lines WL0, WL1, WL2, WL3, ... WLn. The number is an integer representing the row number in the memory cell array, for example... Figure 1 The memory cell array 102 is shown. In some embodiments, the value n is between approximately 4 and 32. In some embodiments, the bit line BL includes a first bit line 304 and a second bit line 306. The first bit line 304 and the second bit line 306 may be connected in parallel. The first bit line 304 and the second bit line 306 are driven by a bit line driving transistor 302. In some embodiments, the bit line driving transistor 302 may include one or more P-type transistors configured to withstand a high voltage to perform read or write operations on the first bit line 304 and the second bit line 306.

[0037] In some embodiments, each column of electric fuse memory cells 1030, 1031, 1032, 1033, ... 103 n All are connected to the first bit line 304. The first bit line 304 and the second bit line 306 are coupled to each other through covering units 308 and 310. In some embodiments, covering units 308 and 310 are disposed in fuse memory cells 1030, 1031, 1032, 1033, ... 103 nThe two ends of the column. For example, the covering unit 308 is disposed between the bit line drive transistor 302 and the first fuse memory cell 1030, while the covering unit 310 is disposed at the last fuse memory cell 103. n Subsequently, in some embodiments, the fuse memory cells 1030, 1031, 1032, 1033, ... 103... n An additional wrapping unit is added to the middle position of the column.

[0038] Figure 3B The diagram shows a schematic layout 300b for a storage device 300 according to certain embodiments of the present disclosure. Layout 300b implements circuit diagram 300a. Circuit diagram 300a can be implemented by other layout designs. A first bit line 304 is disposed on the front side of the fuse memory cells 1030, 1031, 1032, and 1033, while a second bit line 306 is disposed on the rear side of the fuse memory cells 1030, 1031, 1032, and 1033.

[0039] The first bit line 304 and the second bit line 306 may be connected in parallel. The first bit line 304 and the second bit line 306 are driven by a bit line driving transistor 302. In some embodiments, the bit line driving transistor 302 may include one or more P-type transistors configured to withstand high voltages to perform read or write operations on the first bit line 304 and the second bit line 306. In some embodiments, cover units 308 and 310 are disposed at both ends of a column of the fuse memory cells 1030, 1031, 1032, and 1033.

[0040] Figure 3C This is a magnified view of a portion of layout 300b. Figure 3C The diagram shown illustrates a single electric fuse memory cell 103 implemented according to certain embodiments of the present disclosure. The electric fuse memory cell 103 is based on... Figure 2A , Figure 3A The circuit design shown is implemented using a 2T1R configuration. For example, layout 300b is used to form... Figure 2A and Figure 3A The electric fuse memory unit 103 shown. Figure 3D This is a magnified view of a portion of layout 300b. Figure 3D The diagram shown is a schematic representation of a single electric fuse memory unit 103 and a covering unit 308 implemented according to certain embodiments of the present disclosure. Figures 4A to 4H They are respectively Figure 3C The middle line includes AA, BB, CC, DD, EE, and FF lines, as well as... Figure 3D A cross-sectional view of the layout shown along lines GG and HH.

[0041] like Figure 3CAs shown, the fuse memory cell 103 in layout 300b includes multiple patterns, each configured to form active regions (hereinafter referred to as active regions 412, 414, 416, 418), and multiple patterns, each configured to form gate structures (hereinafter referred to as "WL gate structure 406", "CG gate structure 408", and "pseudo gate structure 410", respectively). In some embodiments, such active regions and gate structures are formed along the main front surface of substrate 402 (sometimes referred to as part of the "front-end process (FEOL) processing / network"). On the front surface of substrate 402, multiple front-side metallization layers (sometimes referred to as part of the "back-end process (BEOL) processing / network") may be formed, while on the back surface of substrate, multiple back-side metallization layers may be formed, which will be discussed below.

[0042] The active regions 412, 414, 416, and 418 may each extend along a first lateral direction (e.g., the X direction), while the gate structures 406, 408, and 410 may each extend along a second different lateral direction (e.g., the Y direction). The active regions 412, 414, 416, and 418, together with the gate structures 406, 408, and 410, constitute multiple WL transistors and multiple CG transistors.

[0043] The transistor can be a planar transistor, a fin field-effect transistor, a multi-channel transistor, a gate-all-around transistor, or any suitable transistor type. In some embodiments, active regions 412, 414, 416, and 418 include channel regions and epitaxially grown source / drain regions. The channel regions are formed inside and / or above the substrate 402. The epitaxially grown source / drain regions are connected to the channel regions. Active regions 412, 414, 416, and 418 are connected by an isolation region 404 (e.g., Figures 4A to 4H (As shown) they are separated from each other, for example, by shallow trench isolation.

[0044] In some embodiments, such as Figures 4A to 4HAs shown, active regions 412, 414, 416, and 418 include channels and source / drain regions. The channels are formed from doped regions in the substrate. The source / drain regions are formed adjacent to the channels. In other embodiments, each active region 412, 414, 416, and 418 is composed of a fin structure protruding from the main surface of substrate 402 to form a FinFET or GAA transistor. The fin structure may comprise a single layer of semiconductor material or may comprise multiple semiconductor nanostructures (e.g., nanosheets) extending along the X direction and perpendicularly separated from each other. A portion of the semiconductor structure covered by gate structures 406, 408, and 410 within the doped regions or fin structures is retained, while the remaining portion is replaced by multiple epitaxial structures. The retained portion of the semiconductor structure can be configured as the channel of the corresponding transistor, the epitaxial structures connected to both sides (or endpoints) of the retained portion of the semiconductor structure can be configured as the source / drain regions of the transistor, and the gate structure portion covering (e.g., spanning) the retained portion of the semiconductor structure can be configured as the gate of the transistor.

[0045] like Figure 3C In the representative example shown, the active regions 412, 414, 416, and 418 covered by the WL gate structure 406 can serve as the channel of the WL transistor 250. The active regions 412, 414, 416, and 418 located on both sides of the WL gate structure 406 serve as the source / drain regions of the WL transistor 250. For example... Figure 3C In the illustrated embodiment, eight WL gate structures 406 span four active regions 412, 414, 416, and 418, thereby forming 32 WL transistors 250. These 32 WL transistors 250 are connected in parallel and operate collectively as a single WL transistor. Depending on performance requirements, the fuse memory cell 103 may contain more parallel-connected WL transistors, or only a single WL transistor may be required.

[0046] Similarly, portions of the active regions 412, 414, 416, and 418 covered by the CG gate structure 408 can serve as the channel of the CG transistor 230. The portions of the active regions 412, 414, 416, and 418 located on either side of the CG gate structure 408 serve as the source / drain regions of the CG transistor 230. For example... Figure 3C In the illustrated embodiment, eight CG gate structures 408 span four active regions 412, 414, 416, and 418, thereby forming 32 CG transistors 230. These 32 CG transistors 230 are connected in parallel and operate together as a single CG transistor. Depending on performance requirements, the fuse memory cell 103 may contain more CG transistors connected in parallel, or it may contain only a single CG transistor.

[0047] In some embodiments, such as Figure 3CAs shown, pairs of CG gate structures 408 and pairs of WL gate structures 406 are arranged alternately along the X direction, such that transistors formed along each active region 412, 414, 416, 418 are arranged alternately with CG transistor 230 and WL transistor 250. Adjacent CG transistors 230 and WL transistors 250 share a source / drain and are therefore connected in series.

[0048] The CG gate structure 408 and WL gate structure 406 can be arranged in other ways depending on the circuit design. The CG gate structure 408 and WL gate structure 406 are interleaved with the active regions 412, 414, 416, and 418 within transistor regions 420 and 422. The active regions 412, 414, 416, and 418 extend beyond transistor regions 420 and 422 at both ends along the x-direction. A dummy gate structure 410 is formed on the active regions 412, 414, 416, and 418 outside transistor regions 420 and 422. The dummy gate structure 410 is disposed on both sides of transistor regions 420 and 422 along the x-direction. The arrangement of the dummy gate structure 410 aims to maintain the pattern density of the WL gate structure 406 or CG gate structure 408 in the edge region and improve process uniformity.

[0049] Layout 300b further includes source / drain contact structures formed on the source / drain regions in active regions 412, 414, 416, and 418. These source / drain contact structures are sometimes referred to as mid-level interconnect structures, or simply MD. The source / drain contact structures can connect the corresponding source / drain regions to the upper interconnect structure via mid-level via structures (i.e., source / drain contact vias, sometimes abbreviated as VD). Furthermore, the gate structure can also be connected to the upper interconnect structure via another mid-level via structure (i.e., gate contact via, sometimes abbreviated as VG).

[0050] In some embodiments, substrate 402, active regions 412, 414, 416, 418, gate structures 406, 408, 410, source / drain contact structures, source / drain contact vias, and gate contact vias can be collectively referred to as device layer 430, such as Figure 4A As shown. After the device layer 430 is formed, a front interconnect structure 432 is formed above the device layer 430 during a back-end process. In some embodiments, after forming the front interconnect structure 432, a back interconnect structure 434 may be formed on the back side of the substrate 402. The front interconnect structure 432 and the back interconnect structure 434 include conductive lines and vias to provide power lines and signal lines to the transistors within the device layer 430.

[0051] In some embodiments, layout 300b includes source / drain contact structures 426, 428, and 429 formed on the source / drain regions of WL transistor 250 and CG transistor 230, respectively. In some embodiments, the source / drain contact structures are formed on all source / drain regions. For example, source / drain contact structure 426 is formed over a source / drain region shared by two adjacent WL transistors 250, source / drain contact structure 428 is formed over a source / drain region shared by two adjacent CG transistors 230, and source / drain contact structure 429 is formed over a source / drain region shared between adjacent WL transistors 250 and CG transistors 230. Source / drain contact structure 429 is a pseudo-contact and will not be further connected to signal lines or power lines in the subsequently formed interconnect structure. Pattern density can be maintained by forming source / drain contact structure 429, thereby promoting process uniformity. In other embodiments, the source / drain contact structure 429 may be omitted.

[0052] In some embodiments, the source / drain contact structure 426 may be connected to the source / drain contact via 436, which in turn connects to conductive lines formed in the front interconnect structure 432. The conductive lines ultimately connect the source / drain contact structure 426 and the source / drain region of the WL transistor 250 to a power source (e.g., VSS). In some embodiments, layout 300b further includes a back source / drain contact via 438 formed from the back side of the substrate 402. The back source / drain contact via 438 provides electrical connections to subsequent lines in the back interconnect structure 434, ultimately connecting the source / drain contact structure 426 and the source / drain region of the WL transistor 250 to a power source (e.g., VSS). In some embodiments, layout 300b includes both the source / drain contact via 436 and the back source / drain contact via 438 to connect the source / drain region to a power source with lower resistance. In some embodiments, the source / drain contact structures 426 and 428 of adjacent active regions 412 / 414 and 416 / 418 can be first formed as a continuous circuit and then isolated by a cut contact structure 427 (also known as CMD). The cut contact structure 427 is made of insulating material to provide independent electrical connections to the transistors formed on the active regions 412 / 414 and 416 / 418.

[0053] In some embodiments, the device layer 430 of layout 300b includes a gate via 448 and a gate via 450. The gate via 448 is connected to the gate structure 408 of the CG transistor 230, while the gate via 450 is connected to the gate structure 406 of the WL transistor 250.

[0054] The front interconnect structure 432 may include multiple metallization layers, such as M0, M1, M2, M3, etc. Each layer contains multiple metal rails or lines embedded in the corresponding dielectric material (e.g., intermetallic dielectric layer (IMD) / interlayer dielectric layer (ILD)).

[0055] In some embodiments, the metallization layer M0 (i.e., the first layer immediately adjacent to the device layer in the front interconnect structure 432) includes various metal lines extending in the x-direction, or various metal lines in the direction parallel to the active regions 412, 414, 416, 418.

[0056] like Figure 3C and Figure 4C As shown, the metallization layer M0 includes a CG rail 440. The CG rail 440 is configured to connect to the gate structure 408 of the CG transistor 230 via a gate via 448. The CG rail 440 is configured to provide a CG signal to the gate of the CG transistor 230. Figure 3C and Figure 4B As shown, the metallization layer M0 includes a WL rail 446. The WL rail 446 is configured to connect to the gate structure 406 of the WL transistor 250 via a gate via 450. The WL rail 446 is configured to provide word line signals to the gate of the WL transistor 250. Figure 3C and Figure 4A As shown, the metallization layer M0 includes a VSS rail 442. The VSS rail 442 is configured to connect to a source / drain contact structure 426 on the source / drain region of the WL transistor 250 via a source / drain contact via 436. The VSS rail 442 is configured to provide a VSS voltage to the source / drain region of the WL transistor 250. The metallization layer M0 further includes a landing pad 444. The landing pad 444 is connected to a source / drain contact structure 428 of the CG transistor 230 via a source / drain contact via 437. The landing pad 444 is configured to connect to a fuse resistor 210 formed in the upper metal layer.

[0057] In some embodiments, such as Figure 3C , Figure 4D and Figure 4E As shown, fuse resistor 210 is formed on metallization layer M2. In some embodiments, fuse resistor 210 may be formed at a position offset from active regions 412, 414, 416, 418, so that heat generated during programming (e.g., when fuse resistor 210 melts) does not affect the conductive lines and vias directly above the transistor. In some embodiments, fuse resistor 210 is formed between transistor regions 420, 422 to achieve a substantially symmetrical layout.

[0058] In some embodiments, the fuse resistor 210 includes an elongated conductive wire extending in the x-direction. Figure 3EThe enlarged schematic diagram of layout 300b shows a fuse resistor 210 according to certain embodiments of the present disclosure. The fuse resistor 210 may include an elongated conductor 454 extending in the x-direction. In some embodiments, the elongated conductor 454 may extend along the length of transistor regions 420, 422. In some embodiments, the elongated conductor 454 has a length 454x in the x-direction and a width 454y in the y-direction. The length 454x is much larger than the width 454y. The fuse resistor 210 has a first terminal 454bl and a second terminal 454cg. The first terminal 454bl is used to connect to the BL line, and the second terminal 454cg is used to connect to the source / drain region of the CG transistor 230. The fuse resistor 210 is designed to melt under the action of a programming voltage applied to the BL line, thereby breaking the connection between the first terminal 454bl and the second terminal 454cg.

[0059] In some embodiments, the fuse resistor 210 further includes a dummy conductor 456. The dummy conductor 456 is disposed adjacent to a first end 454bl and a second end 454cg of the elongated conductor 454. The dummy conductor 456 may be arranged parallel to both sides of the elongated conductor 454. The dummy conductor 456 can serve as a heat dissipation path between the first end 454bl and the second end 454cg, thereby promoting localized heat accumulation in the central region of the elongated conductor 454 to facilitate melting during the programming process. In some embodiments, the dummy conductor 456 may be a rectangular conductive pad with a length 456x extending along the x-direction and a width 456y extending along the y-direction. In some embodiments, the ratio of the length 456x of the dummy conductor 456 to the length 454x of the elongated conductor 454 is between about 0.1 and about 0.33. In some embodiments, the width 456y of the dummy conductor 456 is approximately similar to the width 454y of the elongated conductor 454. In some embodiments, the width 456y of the dummy conductor 456 is greater than the width 454y of the elongated conductor 454. For example, the ratio of width 456y to width 454y ranges from approximately 1.0 to 5.0. In some embodiments, the dummy conductor 456 is electrically connected to the elongated conductor 454 at one of the corresponding ends 454bl and 454cg.

[0060] like Figure 3C and Figure 4DAs shown, the second end 454cg of the elongated conductor 454 is connected to the source / drain region of the CG transistor 230 via the source / drain contact structure 428, the source / drain contact via 437, the landing pad 440 of the M0 layer, the via 458 connected to the landing pad 440, the landing pad 460 of the M1 layer, and the via 462 connecting the landing pad 460 and the second end 454cg of the elongated conductor 454. The landing pad 460 of the M1 layer may be a conductive line extending along the Y direction. In some embodiments, layout 300b includes a plurality of landing pads 460 arranged along the Y direction. The plurality of landing pads 460 may extend along the length of the second end 454cg (e.g., a length similar to the length 456x of the pseudo conductor 456), thereby connecting to the elongated conductor 454 via the plurality of vias 462. Multiple landing pads 460 provide multiple parallel conductive paths between the CG transistor 230 and the fuse resistor 210, thereby reducing the resistance value. In some embodiments, a dummy conductor 456 at the second end 454cg is electrically connected to the landing pads 460 through a via 462.

[0061] like Figure 3C and Figure 4E As shown, the first end 454bl of the elongated conductor 454 is connected to one or more BL lines 466 formed on the M3 layer. In some embodiments, one or more BL lines 466 implement... Figure 3A The first line 304 is shown. Layout 300b includes a via 464. The via 464 connects the BL line 466 of layer M3 to the elongated conductor 454 of layer M2. In some embodiments, layout 300b includes multiple BL lines 466 arranged along the Y direction. The multiple BL lines 466 may extend along the length of the first end 454bl (e.g., a length similar to the length 456x of the dummy conductor 456) and are connected to the elongated conductor 454 through the multiple vias 464. The multiple BL lines 466 provide multiple parallel conductive paths for the BL signal to the fuse resistor 210, thereby reducing resistance and improving performance. In some embodiments, the dummy conductor 456 at the first end 454bl is electrically connected to the BL line 466 through the via 464.

[0062] In some embodiments, the memory cell 103 in layout 300b includes a tap unit 470. The tap unit 470 may be arranged along the directions of the active regions 412, 414, 416, 418, for example as... Figure 3C The tap unit 470 is located on the side of transistor regions 420 and 422. It may include conductive paths to facilitate the addition of power lines and / or signal lines.

[0063] In some embodiments, tap unit 470 may enable rear power lines, such as rear VSS lines. Figure 4FAs shown, in device layer 430, tap unit 470 may include a plurality of active regions 476 extending along the directions of active regions 412, 414, 416, 418, but the plurality of active regions 476 are electrically isolated from active regions 412, 414, 416, 418. A pseudo-gate structure 472 and a pseudo-source / drain contact structure 474 are formed above the plurality of active regions 476. In some embodiments, layout 300b includes a back-side VSS rail 478. The back-side VSS rail 478 is formed within the back-side interconnect structure 434 (e.g., the BMO layer). The back-side VSS rail 478 of the BMO layer extends in the x-direction across tap unit 470 and transistor regions 420 / 422. The VSS rail 442 of the BMO layer also extends across tap unit 470 and transistor regions 420 / 422. The back VSS rails 478 and 442 can be electrically connected to each other via conductive paths formed within the tap unit 470. In some embodiments, the conductive paths may include source / drain contact vias 436, source / drain contact structures 474, multiple active regions 476, and the back source / drain contact via 438. Other conductive structures (e.g., vias penetrating the device layer) may be formed to replace the back source / drain contact via 438 and the multiple active regions 476.

[0064] The conductive path within the tap unit 470 allows both the VSS rail 442 and the rear VSS rail 478 to be connected to a VSS power supply. In some embodiments, the VSS power supply may be connected to the VSS rail 442 first, and then supply power to the rear VSS rail 478 via the VSS rail 442. In other embodiments, the VSS power supply may be connected to the rear VSS rail 478 first, and then supply power to the VSS rail 442 via the rear VSS rail 478.

[0065] Reference Figure 4A The source / drain regions of the WL transistor 250 are simultaneously powered by both the rear VSS rails 478 and 442. Specifically, the source / drain regions of the WL transistor 250 are connected to the rear VSS rail 478 via via 438, and to the VSS rail 442 via source / drain contact structure 426 and source / drain contact via 436. This dual VSS power supply improves the performance stability of the memory device.

[0066] In some embodiments, layout 300b includes a backside bit line 480 for implementing Figure 3A The second bit line 306 is shown. In some embodiments, the back bit line 480 is formed below the tap cell 470, for example, in the BM1 layer of the tap cell 470. In some embodiments, the remote bit line or global bit line can be connected to the fuse memory cell 103 via the back bit line 480.

[0067] Reference Figure 3B and Figure 3D Layout 300b includes wrapper units 308. Wrapper units 308 are formed at both ends of a column of fuse memory cells 103. In some embodiments, wrapper units 308 are configured to connect a first bit line 304 (i.e., BL line 466) and a second bit line 306 (i.e., back bit line 480). In some embodiments, wrapper units 308 may include conductive paths to facilitate the addition of power lines and / or signal lines. In some embodiments, the back bit line 480 may have a larger dimension (e.g., a wider width and a thicker thickness) to achieve a lower resistance value.

[0068] like Figure 3D , Figure 4G and Figure 4H As shown, in device layer 430, the cover unit 308 includes a conductive path 312. The conductive path 312 is formed between the BL line 466 of the M3 layer and the back bit line 480 of the BM1 layer. Both the BL line 466 and the back bit line 480 extend along the y-direction, passing through the column of memory cells 103 and the cover units 308 disposed at both ends of the column of memory cells 103. The BL line 466 and the back bit line 480 are located in different vertical layers. In some embodiments, the BL line 466 and the back bit line 480 are also laterally offset in the x-direction. Figure 3D As shown, the back bit line 480 is positioned above the tap unit 470, while the BL line 466 is positioned above the first end 454bl of the fuse resistor 210. Therefore, the conductive path 312 may contain both vertical and lateral connections.

[0069] Encapsulation unit 308 may include one or more active regions 484, which are parallel to and extend across the encapsulation unit 308, along with multiple active regions 412, 414, 416, and 418. A dummy gate structure 488 and a dummy source / drain contact structure 486 are formed on the active regions 484. In some embodiments, the vertical portion of conductive path 312 includes conductive lines and vias formed between the BM1 layers of the back interconnect structure 434, extending through device layer 430 to the M3 layer of layout 300b. Layout 300b includes a back VSS rail 478 formed within the back interconnect structure 434 (e.g., the BM0 layer). Specifically, BL line 466 is connected to the back bit line 480 via conductive path 312. The conductive path 312 includes: a via 464 between layers M3 and M2, a conductive line 496 within layer M2, a via 462 between layers M2 and M1, a landing pad 494 within layer M1, a via 458 between layers M1 and M0, a conductive line 492 within layer M0, source / drain contact vias 436 and 437, a source / drain contact structure 486, multiple active regions 484, vias 438 between the multiple active regions 484 and layer BM0, a conductive line 490 within layer BM0, and a via 482 between layers BM0 and BM1. The horizontal portion of the conductive path 312 is jointly implemented by the conductive line 490 within layer BM0, the conductive line 492 within layer M0, and the conductive line 496 within layer M2.

[0070] Return to reference Figure 3A The conductive path 312 within the encapsulation unit 308 electrically connects the first bit line 304 and the second bit line 306. In some embodiments, the encapsulation unit 310 also includes a conductive path connecting the first bit line 304 and the second bit line 306. During operation, the bit line signal from the bit line driving transistor 302 is simultaneously transmitted along the first bit line 304 and the second bit line 306 through the encapsulation unit 308 to the encapsulation unit 310. Since the first bit line 304 is directly connected to the fuse resistor 210 in the column of fuse memory cells 103, while the second bit line 306 is not connected to any fuse memory cell 103, the load on the second bit line 306 is smaller and its impedance is lower than that of the first bit line 304. The BL signal can be transmitted to the encapsulation unit 310 via the second bit line 306, and then the encapsulation unit 310 drives the fuse memory cells 103n, 103n-1 belonging to the encapsulation unit 310. Therefore, when using a dual-bit-line configuration, access to the fuse memory cells 103n, 103n-1, etc., can be faster compared to a single-bit-line configuration. Thus, the dual-bit-line configuration reduces bit-line load, decreases timing latency, and improves the access speed of memory devices.

[0071] Figure 5The circuit diagram is schematically shown as a memory device 500a according to certain embodiments of the present disclosure. The memory device 500a includes a first bit line and a second bit line for each column of memory cells. In some embodiments, a portion of the memory cells in one column are connected to the first bit line, while another portion of the memory cells in the same column are connected to both the first bit line and the second bit line. In some embodiments, the first bit line and the second bit line are disposed on opposite sides of the memory cells, for example, the front and back sides. In some embodiments, the first bit line and the second bit line are connected to two separate driving transistors.

[0072] Figure 5 Contains a column of electric fuse memory cells 1030, 1031, 1032, 1033, ..., 103 n Electric fuse memory units 1030, 1031, 1032, 1033, ..., 103 n Connected to the same far bit line (FBL) and multiple word lines WL0, WL1, WL2, WL3, ..., WLn. The number is an integer representing the memory cell array (e.g., ...). Figure 1 The number of rows in the memory cell array 102. In some embodiments, the first local bit line 504 and the second local bit line 506 are connected to the FBL and configured to connect to the fuse memory cells 1030, 1031, 1032, 1033, ..., 103 n Programming and reading are performed. A first local bit line 504 and a second local bit line 506 are connected in parallel. In some embodiments, the first local bit line 504 is driven by a bit line driving transistor 502a, and the second local bit line 506 is driven by a bit line driving transistor 502b. In some embodiments, bit line driving transistors 502a and 502b may include one or more P-type transistors configured to withstand high voltages for read or write operations in the first local bit line 504 and the second local bit line 506, respectively.

[0073] In some embodiments, a first local bit line 504 is disposed in fuse memory cells 1030, 1031, 1032, 1033, ..., 103 n The first side (e.g., the front side), while the second local bit line 506 is provided in the fuse memory cells 1030, 1031, 1032, 1033, ..., 103 n The second side (e.g., the back side). In some embodiments, the fuse memory cells 1030, 1031, 1032, 1033, ..., 103 nis connected to the first local bit line 504. In some embodiments, the first local bit line 504 is divided into two segments (a first segment 504a and a second segment 504b). The two segments 504a and 504b are isolated from each other. The first segment 504a is connected to the FBL through the bit line driving transistor 502a. A portion of the eFuse memory cells 103₀, ..., 103 m (where m < n-1) are connected to the first segment 504a, while the eFuse memory cells 103 m+1 , ..., 103 n are connected to the second segment 504b.

[0074] The second local bit line 506 extends along the entire column of the eFuse memory cells 103₀, 103₁, 103₂, 103₃, ..., 103 n and is connected to the eFuse memory cells 103 m+1 , ..., 103 n . In other words, the eFuse memory cells close to the FBL (e.g., the eFuse memory cells 103₀, ..., 103 m ) are connected to one local bit line, while the eFuse memory cells far away (e.g., the eFuse memory cells 103 m+1 , ..., 103 n ) are connected to two local bit lines. In some embodiments, one or more dummy cells, such as dummy cells 508, 510 (similar to dummy cells 308, 310), may be configured to connect the second local bit line 506 to the second segment 504b of the first local bit line 504.

[0075] Figure 6A is a schematic partial layout 500b of a memory device 500 in accordance with some embodiments of the present disclosure. The memory device 500 may be implemented by other layout designs. The layout 500b implements one of the eFuse memory cells in the circuit diagram 500a, which is connected to two local bit lines, such as the eFuse memory cells 103 m+1 , ..., 103 n . Figure 6B is a partial cross-sectional view of the layout 500b taken along line B-B in Figure 6A . The layout 500b is similar to the layout 300b in Figure 2C , with the difference that the layout 500b includes a conductive path connected between the front-side bit line and the back-side bit line.

[0076] As shown in Figure 6A and Figure 6BAs shown, the first local bit line 504 is implemented by a BL line 466 formed on the M3 layer, while the second local bit line 506 is implemented by a back bit line 480 formed on the BM1 layer. In some embodiments, layout 500b includes one or more active regions 584. These active regions 584 are parallel to active regions 412, 414, 416, and 418 and extend across tap cell 470. Active regions 584 are formed in regions adjacent to the first end 454bl of elongated conductor 454 or fuse resistor 210. A pseudo-gate structure 588 and a pseudo-source / drain contact structure 586 are formed above the active regions 584. In some embodiments, conductive paths are formed between the back bit line 480 and the elongated conductor 454 or fuse resistor 210. In some embodiments, conductive paths include conductive lines and vias. Conductive lines and vias are formed on the BM1 layer of the back interconnect structure 434 and penetrate between the device layer 430 and the M2 layer of the front interconnect structure 432. Specifically, the conductive path includes via 462, landing pad 594, via 458, conductive line 592, source / drain vias 436 and 437, source / drain contact structure 586, active region 584, via 438, conductive line 590, and via 482. Via 462 is located between layers M2 and M1. Landing pad 594 is located in layer M1. Via 458 is located between layers M1 and M0. Conductive line 592 is located in layer M0. Via 438 is located between active region 584 and layer BMO. Conductive line 590 is located in layer BMO. Via 482 is located between layers BMO and BM1. In some embodiments, landing pad 594 is a conductive line extending along the y-direction to align with the orientation of other conductive lines in layer M1 (e.g., landing pad 460). In some embodiments, the landing pad 594 may extend over the dummy conductor 456 and connect the dummy conductor 456 to the elongated conductor 454 of the fuse resistor 210. In some embodiments, the conductive line 590 in the BMO layer extends from the tap unit 470 to the region of the fuse resistor 210. Figure 6B As shown, the elongated conductor 454 or the fuse resistor 210 is also connected to the second segment 504b of the BL line 466 or the first local bit line 504.

[0077] Figure 7 This is a flowchart of a method 700 for forming a storage device according to certain embodiments of the present disclosure. According to the present disclosure, method 700 can be used to manufacture storage devices, such as storage devices 100, 300, and 500.

[0078] In operation 702 of method 700, a device layer comprising transistors for multiple memory cells may be formed on the substrate. For example, device layer 430 is as follows: Figures 4A to 4HThe device layer 430 is formed on substrate 402. In some embodiments, device layer 430 may include transistors for multiple memory cells, such as the fuse memory cell 103 in some embodiments of this disclosure. In some embodiments, device layer 430 may include dummy transistors for covering cells (e.g., covering cell 308). In some embodiments, device layer 430 may also include circuit elements for logic circuitry, such as row decoder 104, column decoder 106, I / O circuitry 108, and control logic circuitry 112.

[0079] In operation 704, a front-side interconnect structure, such as front-side interconnect structure 432, is formed on the device layer. In some embodiments, front-side interconnect structure 432 may include paths for connecting signal lines and power lines to transistors in memory cells and overlay cells within the device layer. In some embodiments, a first line, such as first line 304 or BL line 466, is formed in the front-side interconnect structure. In some embodiments, the front-side interconnect structure includes conductive paths for connecting front-side power lines and / or signal lines to power lines and / or signal lines formed on the back side. In some embodiments, when the memory cell is a fuse memory cell, a fuse resistor or equivalent element may be formed in the front-side interconnect structure.

[0080] In operation 706, a carrier wafer may be attached to the front-side interconnect structure of the substrate. The carrier wafer and the substrate are then flipped to allow fabrication from the back side of the substrate. In some embodiments, the substrate may be polished prior to back-side fabrication.

[0081] In operation 708, a back contact structure (e.g., drain contact via 438) may be formed on the back side of the substrate. The back contact structure is used to connect the transistors of the memory cell and the overlay cell. In some embodiments, vias (device layer vias) may be formed to provide a conductive path from the front side of the substrate to the back side of the substrate.

[0082] In operation 710, a back-side interconnect structure, such as back-side interconnect structure 434, is formed on the back side of the substrate. In some embodiments, back-side interconnect structure 434 may include paths for signal lines and power lines for connecting transistors in the device layer of the memory cell and the overlay cell. In some embodiments, a second bit line, such as second bit line 306 or back-side bit line 480, is formed in the back-side interconnect structure. The second bit line may be connected to the memory cell and / or the first bit line. In some embodiments, back-side interconnect structure 434 includes a back-side power rail. The back-side power rail may be directly connected to the transistors in the device layer, or it may be connected to power lines formed in the front-side interconnect structure via conductive paths in the device layer.

[0083] The various embodiments or examples described herein offer several advantages over existing technologies. Embodiments of this disclosure provide a memory device (e.g., a memory device with fuse memory cells) employing back-side partial bitline connections. Moving the partial bitline connections from the front to the back reduces wiring resistance, thereby achieving good programming capability at low voltages. Some embodiments employ double-sided bitlines, further reducing partial bitline resistance. Furthermore, these embodiments also employ back-side power lines and a conventional word line configuration on the M0 layer, thereby achieving a good read window and improving performance.

[0084] It should be understood that this document does not necessarily discuss all advantages, nor does it require that all embodiments or examples have specific advantages; other embodiments or examples may offer different advantages.

[0085] Embodiments of this disclosure provide a semiconductor device including a device layer, a first interconnect structure, and a second interconnect structure. The device layer includes a plurality of transistors for a row of fuse memory cells and a first cover unit. The first interconnect structure is disposed on a first side of the device layer, wherein the first interconnect structure includes a first bit line and a plurality of fuse resistors. The first bit line is connected to a row of fuse memory cells. The plurality of fuse resistors are connected to the transistors of the row of fuse memory cells. The second interconnect structure is disposed on a second side of the device layer, wherein the second interconnect structure includes a second bit line, and the first bit line and the second bit line are interconnected through a conductive path within the first cover unit.

[0086] In some embodiments, with respect to a semiconductor device, the device layer further includes a second covering unit. The first covering unit and the second covering unit are respectively disposed at opposite ends of a row of fuse memory cells.

[0087] In some embodiments, with respect to a semiconductor device, a first line is connected to the fuse resistor of each fuse memory cell in a row of fuse memory cells.

[0088] In some embodiments, relating to a semiconductor device, the first bit line includes a first segment and a second segment. The second segment is electrically isolated from the first segment. A first portion of the fuse memory cell is connected to the first bit line, and a second portion of the fuse memory cell is connected to both the first bit line and the second bit line.

[0089] In some embodiments, regarding a semiconductor device, a row of fuse memory cells and a first overlay cell are arranged along a first direction, and a first interconnect structure includes a plurality of control gate rails and a plurality of word line rails. The plurality of control gate rails extend along a second direction. The plurality of word line rails extend along the second direction, wherein the control gate rails and the word line rails are disposed in a first conductive layer immediately above the device layer.

[0090] In some embodiments, regarding a semiconductor device, the fuse resistor is disposed in a second conductive layer above a first conductive layer, and the first bit line is disposed in a third conductive layer above the second conductive layer.

[0091] In some embodiments, with respect to a semiconductor device, the first interconnect structure further includes a plurality of first power rails disposed in a first conductive layer.

[0092] In some embodiments, with respect to a semiconductor device, the second interconnect structure further includes a plurality of second power rails.

[0093] Another embodiment of this disclosure provides a layout of a semiconductor device including an array of multiple one-time programmable memory cells, multiple word line rails, multiple control gate rails, multiple first bit lines, and multiple second bit lines. The array of multiple one-time programmable memory cells is arranged in multiple rows and multiple columns, wherein the rows extend along a first direction and the columns extend along a second direction. Each word line rail is connected to one row of the one-time programmable memory cells. Each control gate rail is connected to one row of the one-time programmable memory cells. The multiple first bit lines extend along the second direction, wherein each first bit line is disposed along one column of the one-time programmable memory cells. The multiple second bit lines extend along the second direction, wherein each second bit line is disposed along one column of the one-time programmable memory cells, and the second bit lines disposed along one column of the one-time programmable memory cells are electrically connected to each other with the first bit lines.

[0094] In some embodiments, regarding the layout of the semiconductor device, a plurality of first bit lines are disposed in a front interconnect structure, and a plurality of second bit lines are disposed in a back interconnect structure.

[0095] In some embodiments, regarding the layout of the semiconductor device, the word line rails and the control gate rails are disposed in a front-side interconnect structure.

[0096] In some embodiments, the layout of the semiconductor device further includes a plurality of first cover units. Each first cover unit is aligned with a column of the one-time programmable memory cell, and each first cover unit includes a conductive path. The conductive path connects a first bit line and a second bit line and extends along the corresponding column of the one-time programmable memory cell.

[0097] In some embodiments, the layout of the semiconductor device further includes a plurality of second cover units. Each second cover unit is aligned with a column of the one-time programmable memory cell, and the first cover unit and the second cover unit are respectively located at opposite ends of the column of the one-time programmable memory cell.

[0098] In some embodiments, regarding the layout of the semiconductor device, the first bit line is connected to a plurality of fuse resistors corresponding to the column in the one-time programmable memory cell.

[0099] In some embodiments, regarding the layout of the semiconductor device, the second bit line is connected to a plurality of fuse resistors corresponding to the column in the one-time programmable memory cell.

[0100] In some embodiments, regarding the layout of the semiconductor device, each of the one-time programmable memory cells includes a transistor region and a tap cell region. The tap cell region is arranged side-by-side with the transistor region. A first bit line is disposed within the transistor region, and a second bit line is disposed within the tap cell region.

[0101] Another embodiment of this disclosure provides a method for forming a memory device, comprising: forming a device layer on a first side of a substrate, forming a front interconnect structure over the device layer, and forming a back interconnect structure on the device layer. The device layer includes a plurality of transistors and a cladding unit. The transistors are used for a row of fuse memory cells. The front interconnect structure includes a first bit line and a plurality of fuse resistors. The first bit line is used for a row of memory cells, and the fuse resistors are used for a row of fuse memory cells. The back interconnect structure includes a second bit line. The second bit line is used for a row of fuse memory cells, and the first bit line is connected to the second bit line through a conductive path formed within the cladding unit.

[0102] In some embodiments, regarding the method, the operation of forming the device layer includes: forming a plurality of active regions along a first direction, and forming a plurality of gate structures along a second direction perpendicular to the first direction. The column of fuse memory cells is arranged along the second direction.

[0103] In some embodiments, regarding the method, the operation of forming the front interconnect structure includes forming a first front conductive layer. The first front conductive layer includes a plurality of control gate rails, a plurality of word line rails, and a plurality of first power rails along a first direction.

[0104] In some embodiments, regarding the method, the operation of forming the back-side interconnect structure includes: forming a first back-side conductive layer and forming a second back-side conductive layer. The first back-side conductive layer includes a plurality of second power rails. The second back-side conductive layer includes second bit lines.

[0105] As used herein, the terms “about” and “approximately” generally refer to a given number of values ​​that vary depending on the specific process node associated with the semiconductor device in question. Based on a specific process node, “about” can mean that a given number of values ​​varies within, for example, 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0106] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: The device layer includes transistors for a row of electric fuse memory cells and a first encapsulation cell; A first interconnect structure is disposed on a first side of the device layer, wherein the first interconnect structure includes: a first bit line connected to the fuse memory cell of the column; and a fuse resistor connected to the transistor of the fuse memory cell of the column; and A second interconnect structure is disposed on the second side of the device layer, wherein the second interconnect structure includes a second bit line, and the first bit line and the second bit line are interconnected through a conductive path within the first covering unit.

2. The semiconductor device according to claim 1, wherein the device layer further comprises a second coating unit, the first coating unit and the second coating unit being respectively disposed at opposite ends of the electric fuse memory unit of the column.

3. The semiconductor device of claim 1, wherein the first bit line is connected to the fuse resistor of each fuse memory cell in the column of fuse memory cells.

4. The semiconductor device of claim 1, wherein the first bit line includes a first segment and a second segment, the second segment being electrically isolated from the first segment, a first portion of the fuse memory unit being connected to the first bit line, and a second portion of the fuse memory unit being connected to the first bit line and the second bit line.

5. An arrangement of a semiconductor device, comprising: An array of one-time programmable (OTP) memory cells arranged in multiple rows and multiple columns, wherein the multiple rows extend along a first direction and the multiple columns extend along a second direction; Multiple word line (WL) rails, wherein each word line rail is connected to a row in the one-time programmable memory cell; Multiple control gate (CG) rails, wherein each control gate rail is connected to a row in the one-time programmable memory cell; Multiple first-bit lines extend along the second direction, wherein each first-bit line is arranged along a column of the one-time programmable memory cells; as well as A plurality of second bit lines extend along the second direction, wherein each second bit line is arranged along a column of the OTP memory cell, and the second bit lines arranged along a column of the one-time programmable memory cell are electrically connected to the first bit lines.

6. The layout of the semiconductor device according to claim 5, wherein the plurality of first bit lines are disposed in a front interconnect structure and the plurality of second bit lines are disposed in a back interconnect structure.

7. The layout of claim 6, wherein the plurality of word line rails and the plurality of control gate rails are disposed in the front interconnect structure.

8. The layout of the semiconductor device according to claim 5, further comprising: A plurality of first cover units, wherein each first cover unit is aligned with a column of the one-time programmable memory cell, and each first cover unit includes a conductive path connecting the first bit line and the second bit line and extending along the corresponding column of the one-time programmable memory cell.

9. A method of forming a storage device, comprising: A device layer is formed on a first side of a substrate, wherein the device layer includes transistors and cladding units, the transistors being used for a row of fuse memory cells; A front-side interconnect structure is formed above the device layer, wherein the front-side interconnect structure includes a first bit line and a fuse resistor, the first bit line being used for memory cells in the column, and the fuse resistor being used for electrically fused memory cells in the column; and A back-side interconnect structure is formed on the device layer, wherein the back-side interconnect structure includes a second bit line for the electric fuse memory cell of the column, and the first bit line is connected to the second bit line through a conductive path formed in the cover unit.

10. The method of claim 9, wherein forming the device layer comprises: An active region is formed along the first direction; as well as A gate structure is formed along a second direction perpendicular to the first direction, wherein the columns of electric fuse memory cells are arranged along the second direction.

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