Semiconductor memory device and method of manufacturing the semiconductor memory device

Abstract

This application relates to a semiconductor memory device and a method of manufacturing the semiconductor memory device. A semiconductor memory device includes: an insulating layer; a gate stack located above the insulating layer; and a semiconductor pillar extending in a stacking direction, including a first segment extending through a first insulating layer and a second segment extending through the gate stack. Each of the first and second segments of the semiconductor pillar includes a first channel portion forming a first sidewall, a second channel portion forming a second sidewall and spaced apart from the first channel portion, and the first segment of the semiconductor pillar further includes a connection portion connecting the first channel portion and the second channel portion within the first segment of the semiconductor pillar.

Description

Technical Field

[0001] Embodiments of this disclosure may relate to semiconductor memory devices, and more specifically, to a semiconductor memory device including a three-dimensional memory cell array and a method for manufacturing the semiconductor memory device. Background Technology

[0002] Semiconductor memory devices are used in electronic systems across a variety of fields, such as automobiles, medical devices, data centers, and small electronic devices. As a result, the demand for semiconductor memory devices is increasing.

[0003] A semiconductor memory device includes a memory cell array, and the memory cell array includes a plurality of memory cells for storing data. The semiconductor memory device can be a two-dimensional semiconductor memory device including a two-dimensional memory cell array or a three-dimensional semiconductor memory device including a three-dimensional memory cell array.

[0004] In a three-dimensional memory cell array, multiple memory cells are arranged along the X, Y, and Z axes. In a two-dimensional memory cell array, multiple memory cells are arranged along the X and Y axes. Due to this structural difference, three-dimensional memory cell arrays are more advantageous for the mass production of semiconductor memory devices compared to two-dimensional memory cell arrays.

[0005] A three-dimensional memory cell array may include semiconductor pillars and multiple conductive layers stacked along the semiconductor pillars. To improve the integration density of a three-dimensional memory cell array, the semiconductor pillars may be divided into channel portions. However, dividing the semiconductor pillars into channel portions may increase the process complexity and process defects of the semiconductor memory device. Summary of the Invention

[0006] According to embodiments of the present disclosure, a semiconductor memory device may include: a first insulating layer including a first surface extending parallel to an XY plane; a gate stack disposed above the first surface of the first insulating layer and including a plurality of conductive layers and a plurality of second insulating layers, the plurality of conductive layers and the plurality of second insulating layers being alternately arranged in a stacking direction intersecting the XY plane; a semiconductor pillar extending in the stacking direction and including a first segment extending through the first insulating layer and a second segment extending through the gate stack, the semiconductor pillar having a major axis and a minor axis in the XY plane and including a first sidewall and a second sidewall defined on opposite sides of the minor axis; a first memory pattern located between the first sidewall of the semiconductor pillar and the gate stack; and a second memory pattern located between the second sidewall of the semiconductor pillar and the gate stack. Each of the first segment and the second segment of the semiconductor pillar may include a first channel portion forming the first sidewall, a second channel portion forming the second sidewall and spaced apart from the first channel portion, and the first segment of the semiconductor pillar may further include a connection portion connecting the first channel portion and the second channel portion of the first segment of the semiconductor pillar.

[0007] According to embodiments of the present disclosure, a method of manufacturing a semiconductor memory device may include the following steps: forming a lower insulating layer extending parallel to an XY plane; alternately stacking a plurality of first material layers and a plurality of second material layers above the lower insulating layer in a stacking direction intersecting the XY plane; forming a hole including a first segment passing through the lower insulating layer and a second segment extending from the first segment through the plurality of first material layers and the plurality of second material layers, the hole having a major axis and a minor axis in the XY plane; forming a memory layer on a sidewall of the lower insulating layer adjacent to the hole, the memory layer extending into the second segment of the hole; forming a recess by etching a portion of the memory layer overlapping the minor axis of the hole; forming a channel layer on an inner wall of the memory layer, the channel layer including protrusions projecting into the recess; removing the plurality of first material layers to form a plurality of openings; replacing the protrusions of the channel layer through the plurality of openings using a channel separation structure; and forming a plurality of conductive layers in the plurality of openings respectively. Attached Figure Description

[0008] Figure 1 This is a circuit diagram illustrating a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure;

[0009] Figure 2A and Figure 2B This is a diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure;

[0010] Figure 3 Is it like this? Figure 2A and Figure 2B A three-dimensional view of the semiconductor pillars shown;

[0011] Figure 4A , Figure 4B , Figure 4C and Figure 4D It is shown as follows Figure 2A and Figure 2B A plan view of the cross-section of the unit column structure shown;

[0012] Figure 5 It is shown as follows Figure 2A and Figure 2B An exploded perspective view of the semiconductor memory device shown.

[0013] Figure 6A It shows along such Figures 4A to 4C The diagram shows cross-sectional views of various configurations of a semiconductor memory device according to embodiments of the present disclosure, taken along the long axis of the hole. Figure 6B It shows along such Figures 4A to 4C Cross-sectional views of various configurations of a semiconductor memory device taken along the short axis of the hole shown;

[0014] Figure 7A It shows along such Figures 4A to 4C The diagram shows cross-sectional views of various configurations of a semiconductor memory device according to embodiments of the present disclosure, taken along the long axis of the hole. Figure 7B It shows along such Figures 4A to 4C Cross-sectional views of various configurations of a semiconductor memory device taken along the short axis of the hole shown;

[0015] Figure 8A and Figure 8B This is a plan view showing the cross-section of a unit column structure according to an embodiment of the present disclosure;

[0016] Figure 9A , Figure 9B and Figure 9C This is a diagram illustrating a preliminary laminate and holes according to an embodiment of the present disclosure;

[0017] Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B and Figure 14C This is a diagram illustrating various configurations formed in the holes using a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure;

[0018] Figure 15A , Figure 15B , Figure 15C , Figure 15D and Figure 15E This is a diagram showing a channel separation structure formed using a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure, as well as the connection portion and dummy portion of the channel layer;

[0019] Figure 16 This is a cross-sectional view showing a plurality of conductive layers formed using a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure;

[0020] Figure 17A , Figure 17B , Figure 17C and Figure 17D This is a diagram illustrating various configurations formed using a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure;

[0021] Figure 18A , Figure 18B , Figure 18C and Figure 18D This is a plan view illustrating various configurations formed using a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure; and

[0022] Figure 19 This is a block diagram illustrating an electronic system according to an embodiment of the present disclosure. Detailed Implementation

[0023] The specific structural or functional descriptions illustrating examples of embodiments based on the concepts disclosed in this specification are merely for the purpose of describing examples of embodiments based on these concepts, which can be implemented in various forms, but the descriptions are not limited to the examples of embodiments described in this specification.

[0024] Terms such as “first” and “second” are used to distinguish between various elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be named the second element, and in another example, the second element may be named the first element. Terms such as “top,” “above,” “on,” “side,” “up,” “down,” “row,” “column,” “inner,” and “outer,” as well as other terms that imply relative spatial relationships or orientations, are used only for ease of description or reference to the accompanying drawings and are not intended to be limiting. Crosshairs running through the drawings indicate corresponding or similar areas between the drawings and do not indicate the material associated with these areas. It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “attached to” another element or layer, it may be directly on, directly connected to, or directly attached to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly attached to” another element or layer, there are no intermediate elements or layers.

[0025] Various embodiments of this disclosure relate to a semiconductor memory device and a method of manufacturing the semiconductor memory device, which can reduce process complexity and process defects.

[0026] Figure 1 This is a circuit diagram illustrating a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0027] Reference Figure 1 The memory cell array of the semiconductor memory device includes multiple memory cell strings CS1 to CSn, where n is a natural number equal to or greater than 2. The multiple memory cell strings CS1 to CSn are connected to the gate array GAR, the bit line array BAR, and the common source layer CSR.

[0028] Each of the plurality of memory cell strings CS1 to CSn includes at least one source-select transistor SST, a plurality of memory cells MC, and at least one drain-select transistor DST. The plurality of memory cells MC are stacked between the source-select transistor SST and the drain-select transistor DST. The source-select transistor SST, the plurality of memory cells MC, and the drain-select transistor DST are connected via corresponding channel portions (e.g., Figures 4A to 4D (CH1 or CH2 in the middle) are connected in series.

[0029] The gate array (GAR) includes a source select line (SSL), multiple word lines (WL), and a drain select line (DSL). The source select line (SSL) can be used as the gate electrode of the source select transistor (SST), each word line (WL) can be used as the gate electrode corresponding to a memory cell (MC), and the drain select line (DSL) can be used as the gate electrode of the drain select transistor (DST).

[0030] The bit line array (BAR) comprises multiple bit lines BL1 to BLn, where n is a natural number equal to or greater than 2. Each of the multiple bit lines BL1 to BLn is connected to a corresponding memory cell string CS1 to CSn. Each of the multiple bit lines BL1 to BLn is connected to the channel portion of the corresponding memory cell string to selectively control the channel portion of the corresponding memory cell string. A voltage can be applied to each of the multiple bit lines BL1 to BLn to precharge the corresponding channel portion.

[0031] Multiple memory cell strings CS1 to CSn are connected in parallel to a common source layer CSR. A voltage can be applied to the common source layer CSR to discharge multiple channel portions of the multiple memory cell strings CS1 to CSn.

[0032] Figure 2A and Figure 2B This is a diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0033] Reference Figure 2A and Figure 2B A semiconductor memory device includes a gate array (GAR), a bit line array (BAR), multiple cell pillar structures (CPI), doped semiconductor structures (DPS), and a peripheral circuit structure (PCS). The gate array (GAR), bit line array (BAR), and doped semiconductor structures (DPS) are arranged above the peripheral circuit structure (PCS). The gate array (GAR) is located between the bit line array (BAR) and the doped semiconductor structures (DPS). The multiple cell pillar structures (CPI) may extend through the gate array (GAR).

[0034] The gate array (GAR) includes multiple conductive layers CL1, CL2, and CL3 of a gate stack (GST). Each of the multiple conductive layers CL1, CL2, and CL3 may extend parallel to the XY plane. The multiple conductive layers CL1, CL2, and CL3 may be spaced apart from each other in a stacking direction intersecting the XY plane (e.g., the Z-axis direction). Each of the multiple conductive layers CL1, CL2, and CL3 may include various conductive materials such as doped semiconductor layers, metal layers, etc. The doped semiconductor layer may include a doped silicon layer. The metal layer may include tungsten, copper, molybdenum, etc. Each of the multiple conductive layers CL1, CL2, and CL3 may also include a metal nitride layer. The metal nitride layer may include titanium nitride, tantalum nitride, etc.

[0035] Multiple conductive layers CL1, CL2, and CL3 may include at least one first conductive layer CL1, multiple second conductive layers CL2, and at least one third conductive layer CL3. The multiple second conductive layers CL2 are spaced apart from each other in the stacking direction between the first conductive layer CL1 and the third conductive layer CL3. The first conductive layer CL1 is closer to the doped semiconductor structure DPS than the multiple second conductive layers CL2, and the third conductive layer CL3 is closer to the bit line array BAR than the multiple second conductive layers CL2. The first conductive layer CL1 can be used as... Figure 1 As shown, the source selection line SSL, multiple second conductive layers CL2 can be used as such Figure 1 The multiple word lines WL shown can be used as such. Figure 1 The drain selection line DSL is shown.

[0036] A gate stack GST may be disposed above a first surface SU1 of a first insulating layer IL1. The first surface SU1 of the first insulating layer IL1 may extend parallel to the XY plane. The gate stack GST may include a plurality of second insulating layers IL2 arranged alternately with a plurality of conductive layers CL1, CL2, and CL3 in the stacking direction. A third insulating layer IL3 may be disposed above the surface of the gate stack GST opposite to the first insulating layer IL1. The first insulating layer IL1 is adjacent to the first conductive layer CL1 of the gate stack GST, and the third insulating layer IL3 is adjacent to the third conductive layer CL3 of the gate stack GST. The plurality of second insulating layers IL2 are spaced apart from each other in the stacking direction between the first insulating layer IL1 and the second insulating layer IL2. Each of the first insulating layer IL1, the plurality of second insulating layers IL2, and the third insulating layer IL3 may include an insulating material layer such as a silicon oxide layer, a silicon oxynitride layer, etc. In the stacking direction, each of the thickness D1 of the first insulating layer IL1 and the thickness D3 of the third insulating layer IL3 may be greater than the thickness D2 of each of the plurality of second insulating layers IL2.

[0037] Multiple unit pillar structures CPI extend through a first insulating layer IL1, multiple second insulating layers IL2, and a third insulating layer IL3 in the stacking direction. In the XY plane, each of the first conductive layer CL1, multiple second conductive layers CL2, and third conductive layer CL3 can be formed as a fully enclosed structure surrounding the sidewalls of the respective unit pillar structure CPI.

[0038] Each cell pillar structure CPI may include a semiconductor pillar SP, which may be segmented to form two or more memory cell strings. In one embodiment, the semiconductor pillar SP of the cell pillar structure CPI may include two or more channel portions and two or more cover portions. The two or more cover portions of the semiconductor pillar SP may be arranged in a third insulating layer IL3 and may be separated from each other by an isolation insulating structure SIS. In one embodiment, the semiconductor pillar SP may include a first cover portion CAP1 and a second cover portion CAP2 segmented by the isolation insulating structure SIS. The isolation insulating structure SIS may extend into the third insulating layer IL3 between the first cover portion CAP1 and the second cover portion CAP2.

[0039] Multiple bit lines (e.g., BL1 and BL2) of a bit line array (BAR) may extend adjacent to each other in the XY plane. In an embodiment, the multiple bit lines (e.g., BL1 and BL2) may extend in the X-axis direction and may be spaced apart in the Y-axis direction.

[0040] Two or more coverage portions are electrically connected to different bit lines of the bit line array (BAR). In one embodiment, the first coverage portion CAP1 is electrically connected to the first bit line BL1, and the second coverage portion CAP2 is electrically connected to the second bit line BL2.

[0041] The bit line array (BAR) can be separated from the gate stack (GST) by a third insulating layer (IL3). Although Figure 2A and Figure 2B As not shown, a fourth insulating layer may be disposed between the bit line array BAR and the third insulating layer IL3, and the fourth insulating layer may be penetrated by multiple conductive bit line connection structures. Each conductive bit line connection structure may be designed in various configurations to connect the corresponding bit line (e.g., BL1) to the covered portion of the corresponding semiconductor pillar SP (e.g., CAP1).

[0042] A doped semiconductor structure DPS is disposed in the Z direction below a second surface SU2 of a first insulating layer IL1. The second surface SU2 is opposite to the first surface SU1. The doped semiconductor structure DPS is spaced apart from a first conductive layer CL1 of a gate stack GST by the first insulating layer IL1. The doped semiconductor structure DPS includes at least one doped semiconductor layer extending along the XY plane. The doped semiconductor layer of the doped semiconductor structure DPS may include n-type impurities or p-type impurities. In an embodiment, the doped semiconductor structure DPS may include one or both of a first conductivity type doped semiconductor layer containing n-type impurities as majority carriers and a second conductivity type doped semiconductor layer containing p-type impurities as majority carriers. The first conductivity type doped semiconductor layer may be provided as shown in the reference. Figure 1 The described common source layer (CSR) can provide a second conductivity type doped semiconductor layer as a well region.

[0043] One of the doped semiconductor structure (DPS) and the bit line array (BAR) can be closer to the peripheral circuit structure (PCS) than the other. In an implementation, such as... Figure 2A As shown, the doped semiconductor structure DPS can be positioned closer to the peripheral circuit structure PCS than the bit line array (BAR). In an implementation, as... Figure 2B As shown, the bit line array (BAR) can be positioned closer to the peripheral circuit structure (PCS) than the doped semiconductor structure (DPS). The doped semiconductor structure (DPS) can form a contact surface with the semiconductor pillars (SP) of the unit pillar structure (CPI). The contact surface can be formed on a portion of the sidewall of the semiconductor pillar (SP), the end of the semiconductor pillar (SP), etc.

[0044] The peripheral circuit structure PCS may include input / output circuits, control circuits, voltage generation circuits, row decoders, column decoders, page buffers, etc., and may include multiple transistor PTRs constituting at least some of these components, as well as multiple interconnect ICs connected to the multiple transistor PTRs.

[0045] Each of the plurality of transistors PTRs is disposed on an active region of a semiconductor substrate SUB separated by an isolation layer ISO. The semiconductor substrate SUB comprises a semiconductor material. In embodiments, the semiconductor material may include one or more of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. Group IV semiconductors may include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon-germanium (SiGe). Group III-V compound semiconductors may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. Group II-VI compound semiconductors may include ZnS, ZnO, or CdS.

[0046] The semiconductor substrate SUB may also include a dielectric layer. In some embodiments, the semiconductor substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The semiconductor substrate SUB may also include organic materials. In some embodiments, the semiconductor substrate SUB may include graphene.

[0047] The semiconductor substrate SUB can be a bulk wafer or an epitaxial layer grown by selective epitaxial growth (SEG). Alternatively, the semiconductor substrate SUB can be a layer formed by metal-induced lateral crystallization (MILC) and may partially include metal.

[0048] The semiconductor substrate SUB can be monocrystalline, polycrystalline, or amorphous. The semiconductor substrate SUB may include Group II, III, IV, V, or VI impurities. In some embodiments, the semiconductor substrate SUB may include an n-well region doped with n-type impurities, a p-well region doped with p-type impurities, or both an n-well region and a p-well region.

[0049] The transistor PTR is covered by a peripheral insulating structure (PIS) above the semiconductor substrate SUB. Multiple interconnect ICs can be formed in the peripheral insulating structure PIS and may include multiple wires and multiple conductive contacts for electrical connection.

[0050] Reference Figure 2A The doped semiconductor structure DPS can be placed above the peripheral insulating structure PIS.

[0051] Reference Figure 2B The semiconductor memory device may further include a bonding structure BS. The bonding structure BS may be disposed between a bit line array (BAR) and a peripheral circuit structure (PCS). The bonding structure BS may include a first insertion insulating structure IS1, a second insertion insulating structure IS2, a first conductive bonding pattern BDP1, and a second conductive bonding pattern BDP2. The first insertion insulating structure IS1 is placed between the bit line array (BAR) and the peripheral insulating structure (PCS), and the second insertion insulating structure IS2 is placed between the first insertion insulating structure IS1 and the peripheral insulating structure (PCS). The first insertion insulating structure IS1 is bonded to the second insertion insulating structure IS2. The first conductive bonding pattern BDP1 is disposed in the first insertion insulating structure IS1, and the second conductive bonding pattern BDP2 is disposed in the second insertion insulating structure IS2. The first conductive bonding pattern BDP1 is bonded to and electrically connected to the second conductive bonding pattern BDP2.

[0052] Semiconductor pillars (SPs) can be formed as a single structure, rather than being divided into two or more parts in a doped semiconductor structure (DPS). See below for reference. Figure 3 , Figure 4A , Figure 4B , Figure 4C and Figure 4D Describe the semiconductor pillar SP in detail.

[0053] Figure 3 Is it like this? Figure 2A and Figure 2B The diagram shows a three-dimensional view of the semiconductor pillar SP.

[0054] Reference Figure 2A , Figure 2B and Figure 3A semiconductor pillar SP is disposed in a via H. The via H extends through a first insulating layer IL1 and a gate stack GST in the stacking direction (e.g., the Z-axis direction). The via H includes a first segment H[S1] extending through the first insulating layer IL1 and a second segment H[S2] extending through the gate stack GST. Because the semiconductor pillar SP is disposed in the via H, it includes a first segment extending through the first insulating layer IL1 and a second segment extending through the gate stack GST. The first segment H[S1] extends from the second surface SU2 through the first insulating layer IL1 to the first surface SU1. The second segment H[S2] extends through the third conductive layer CL3 of the gate stack GST and is connected to the first segment H[S1]. The first segment of the semiconductor pillar SP is disposed in the first segment H[S1] of the via H, and the second segment of the semiconductor pillar SP is disposed in the second segment H[S2] of the via H. The semiconductor pillar SP extends into the doped semiconductor structure DPS and the third insulating layer IL3.

[0055] The semiconductor pillar SP includes a first cover portion CAP1, a second cover portion CAP2, a first channel portion CH1, a second channel portion CH2, and a connection portion. For example... Figure 3 The connecting portion shown is a first side pattern CHC[S1] that is part of the connecting portion. Each of the first cover portion CAP1, the second cover portion CAP2, the first channel portion CH1, the second channel portion CH2, and the connecting portion (e.g., CHC[S1]) includes a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof.

[0056] Each of the first and second segments of the semiconductor pillar SP includes a first channel portion CH1 and a second channel portion CH2, and the first segment of the semiconductor pillar SP also includes a connection portion (e.g., CHC[S1]). Each of the first channel portion CH1 and the second channel portion CH2 includes a serial channel region CH1[SC] or CH2[SC], a first end CH1[E1] or CH2[E1], and a second end CH1[E2] or CH2[E2]. Each of the serial channel region CH1[SC] of the first channel portion CH1 and the serial channel region CH2[SC] of the second channel portion CH2 is disposed in the second segment H[S2] of the via H. Each of the serial channel region CH1[SC] of the first channel portion CH1 and the serial channel region CH2[SC] of the second channel portion CH2 can be used as a channel region for a corresponding memory cell string. Each of the first end CH1[E1] of the first channel portion CH1 and the first end CH2[E1] of the second channel portion CH2 extends from the corresponding channel region CH1[SC] or CH2[SC] and may extend through such... Figure 2A and Figure 2BThe third insulating layer IL3 is shown. Each of the second ends CH1[E2] of the first channel portion CH1 and the second ends CH2[E2] of the second channel portion CH2 extends from the corresponding string channel region CH1[SC] or CH2[SC] in a direction opposite to the first end CH1[E1] or CH2[E1]. The second ends CH1[E2] of the first channel portion CH1 and the second ends CH2[E2] of the second channel portion CH2 can extend to, as shown... Figure 2A and Figure 2B In the doped semiconductor structure DPS shown, the second end CH1[E2] of the first channel portion CH1 and the series channel region CH1[SC] can be connected to each other in the first insulating layer IL1. The second end CH2[E2] of the second channel portion CH2 and the series channel region CH2[SC] can be connected to each other in the first insulating layer IL1.

[0057] The first cover portion CAP1 and the second cover portion CAP2 extend through the third insulating layer IL3. The first cover portion CAP1 and the second cover portion CAP2 are arranged between the first end CH1[E1] of the first channel portion CH1 and the first end CH2[E1] of the second channel portion CH2. The first cover portion CAP1 is connected to the first end CH1[E1] of the first channel portion CH1, and the second cover portion CAP2 is connected to the first end CH2[E1] of the second channel portion CH2.

[0058] A connecting portion (e.g., CHC[S1]) connects the second end CH1[E2] of the first channel portion CH1 and the second end CH2[E2] of the second channel portion CH2 in the first segment H[S1] of the aperture H. The connecting portion (e.g., CHC[S1]) may extend into the doped semiconductor structure DPS and may connect the second end CH1[E2] of the first channel portion CH1 and the second end CH2[E2] of the second channel portion CH2 in the doped semiconductor structure DPS.

[0059] Each of the first covering portion CAP1, the second covering portion CAP2, the first end CH1[E1] and the second end CH1[E2] of the first channel portion CH1, the first end CH2[E1] and the second end CH2[E2] of the second channel portion CH2, and the connecting portion (e.g., CHC[S1]) may include an n-type impurity or both an n-type impurity and a p-type impurity. In an embodiment, each of the first covering portion CAP1, the second covering portion CAP2, the first end CH1[E1] and the second end CH1[E2] of the first channel portion CH1, the first end CH2[E1] and the second end CH2[E2] of the second channel portion CH2, and the connecting portion (e.g., CHC[S1]) may include an n-type impurity as a majority carrier and may be provided as a junction of a memory cell string.

[0060] Figure 4A , Figure 4B , Figure 4C and Figure 4D It is shown as follows Figure 2A and Figure 2B The diagram shows a plan view of the cross-section of the unit column structure CPI. Figure 4A It is shown as follows Figure 2A and Figure 2B The diagram shows a plan view of the cross-section of the unit column structure CPI at the first height where the first insulating layer IL1 is set. (See diagram for reference.) Figure 2A and Figure 2B As shown, the first height is closer to the second surface SU2 than the first surface SU1. Figure 4B It is shown as follows Figure 2A and Figure 2B The plan view of the cross-section of the unit column structure CPI at the second height where the first conductive layer CL1, each of the second conductive layers CL2 or the third conductive layer CL3 is set. Figure 4C It is shown as follows Figure 2A and Figure 2B The plan view of the cross-section of the unit column structure CPI at the third height where each of the second insulating layers IL2 is set. Figure 4D It is shown as follows Figure 2A and Figure 2B The diagram shows a plan view of the cross-section of the unit column structure CPI at the fourth height where the third insulating layer IL3 is set.

[0061] Reference Figure 3 , Figure 4A , Figure 4B and Figure 4CThe hole H has a structure comprising a minor axis AX1 and a major axis AX2 that intersect each other in the XY plane. In an embodiment, each of the first segment H[S1] and the second segment H[S2] of the hole H may have an elliptical shape in the XY plane. One of the directions of the minor axis AX1 and the major axis AX2 of the elliptical shape may be the X-axis direction, which is as follows: Figure 2A and Figure 2B The extension directions of the multiple bit lines shown (e.g., BL1 and BL2). In one embodiment, the direction of the major axis AX2 can be the X-axis direction. Embodiments of this disclosure are not limited thereto. In another embodiment, the direction of the major axis AX2 can be the Y-axis direction, or a diagonal direction between the X-axis and Y-axis in the XY plane.

[0062] The first channel portion CH1 and the second channel portion CH2 of the semiconductor pillar SP are defined based on the minor axis AX1 and spaced apart from each other. In an embodiment, the first channel portion CH1 and the second channel portion CH2 may be symmetrical about the minor axis AX1. The first channel portion CH1 forms a first sidewall SW1 of the semiconductor pillar SP, and the second channel portion CH2 forms a second sidewall SW2 of the semiconductor pillar SP. The first sidewall SW1 and the second sidewall SW2 may be defined on opposite sides of the minor axis AX1. Each of the first channel portion CH1 and the second channel portion CH2 may form a convex open curve in the XY plane facing outwards towards the hole H. The open curve formed by each of the first channel portion CH1 and the second channel portion CH2 may have a vertex intersecting the major axis AX2.

[0063] The connecting portion of the semiconductor pillar SP includes a first side pattern CHC[S1] and a second side pattern CHC[S2]. The first side pattern CHC[S1] and the second side pattern CHC[S2] are spaced apart from each other in the direction of the minor axis AX1. The first side pattern CHC[S1] and the second side pattern CHS[S2] may be defined based on the major axis AX2. In an embodiment, the first side pattern CHC[S1] and the second side pattern CHS[S2] may be symmetrical about the major axis AX2. The first side pattern CHC[S1] and the second side pattern CHS[S2] extend in the XY plane from the second end CH1[E2] of the first channel portion CH1 toward the second end CH2[E2] of the second channel portion CH2, and can connect the first channel portion CH1 and the second channel portion CH2 in the first segment H[S1] of the hole H. The first side pattern CHC[S1] and the second side pattern CHC[S2] may extend through the second surface SU2 of the first insulating layer IL1. A portion of each of the first side pattern CHC[S1] and the second side pattern CHC[S2] located in the first insulating layer IL1 has a height HE in the Z-axis direction that is less than the thickness D1 of the first insulating layer IL1, and is spaced apart from the first surface SU1 of the first insulating layer IL1. The first side pattern CHC[S1] and the second side pattern CHC[S2] may protrude toward the outside of the hole H in the direction of the minor axis AX1 relative to the first channel portion CH1 and the second channel portion CH2.

[0064] Reference Figure 3 and Figure 4D The first covering portion CAP1 and the second covering portion CAP2 of the semiconductor pillar SP are arranged spaced apart from each other in the direction of the major axis AX2 of the hole H. Each of the first covering portion CAP1 and the second covering portion CAP2 includes a convex curved surface in the direction of the major axis AX2. The curved surface of the first covering portion CAP1 is connected to the first end CH1[E1] of the first channel portion CH1, and the curved surface of the second covering portion CAP2 is connected to the first end CH2[E1] of the second channel portion CH2. The first covering portion CAP1 and the first end CH1[E1] of the first channel portion CH1 can be integrally formed, and the second covering portion CAP2 and the first end CH2[E1] of the second channel portion CH2 can be integrally formed. The first covering portion CAP1 and the first end CH1[E1] of the first channel portion CH1 can form a first doped semiconductor pattern DP1, and the second covering portion CAP2 and the first end CH2[E1] of the second channel portion CH2 can form a second doped semiconductor pattern DP2. In an embodiment, each of the first doped semiconductor pattern DP1 and the second doped semiconductor pattern DP2 can have a semi-elliptical shape in the XY plane.

[0065] The isolation insulation structure SIS is located between the first cover portion CAP1 and the second cover portion CAP2. The isolation insulation structure SIS may extend in the direction of the short axis AX1 to be located between the first end CH1[E1] of the first channel portion CH1 and the first end CH2[E1] of the second channel portion CH2. The isolation insulation structure SIS may extend into the third insulation layer IL3.

[0066] Figure 5 It is shown as follows Figure 2A and Figure 2B An exploded perspective view of the semiconductor memory device shown.

[0067] Reference Figure 5 The first insulating layer IL1 includes a first portion IL1[P1] adjacent to the first surface SU1 and a second portion IL1[P2] adjacent to the second surface SU2. For example... Figure 4A and Figure 5 The cross-section of the unit column structure CPI in the first insulating layer IL1 shown corresponds to the cross-section of the unit column structure CPI in the second part IL1[P2] of the first insulating layer IL1.

[0068] Reference Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 5 The cell pillar structure CPI extends in the stacking direction (i.e., the Z-axis direction) through a first insulating layer IL1, multiple second insulating layers IL2 and multiple conductive layers (e.g., CL2 and CL3) of the gate stack GST, and a third insulating layer IL3. The cell pillar structure CPI includes a semiconductor pillar SP, a first memory pattern ML1, a second memory pattern ML2, a first channel separation structure CSI1, a second channel separation structure CSI2, and a core insulating layer CO.

[0069] The core insulating layer CO of the unit pillar structure CPI is disposed in the central region of the via H. Semiconductor pillars SP of the unit pillar structure CPI may surround the core insulating layer CO. A first channel portion CH1 and a second channel portion CH2 of the semiconductor pillars SP each extend along the sidewall of the core insulating layer CO and may extend through the first insulating layer IL1 and the gate stack GST in the Z-axis direction. Each of the first channel portion CH1 and the second channel portion CH2 protrudes further relative to the core insulating layer CO in the Z-axis direction and extends through the third insulating layer IL3. The first channel portion CH1, the second channel portion CH2, and the core insulating layer CO may extend through the first insulating layer IL1.

[0070] Each of the first covering portion CAP1 and the second covering portion CAP2 of the semiconductor pillar SP overlaps with the core insulating layer CO in the Z-axis direction. The first side pattern CHC[S1] and the second side pattern CHC[S2] of the semiconductor pillar SP are arranged on the sidewall of the core insulating layer CO in the second portion IL1[P2] of the first insulating layer IL1.

[0071] The first channel separation structure CSI1 of the unit column structure CPI overlaps with the first side pattern CHC[S1] in the Z-axis direction, and the second channel separation structure CSI2 of the unit column structure CPI overlaps with the second side pattern CHC[S2] in the Z-axis direction. The first channel separation structure CSI1 and the second channel separation structure CSI2 comprise an insulating material such as silicon oxide. The first channel separation structure CSI1 and the second channel separation structure CSI2 are arranged between the serial channel region CH1[SC] of the first channel portion CH1 and the serial channel region CH2[SC] of the second channel portion CH2 in the second segment H[S2] of the hole H. The first channel separation structure CSI1 and the second channel separation structure CSI2 may protrude relative to the first channel portion CH1 and the second channel portion CH2 in the direction of the minor axis AX1. The first channel separation structure CSI1 and the second channel separation structure CSI2 may extend in the first portion IL1[P1] of the first insulating layer IL1. Each of the first channel separation structure CSI1 and the second channel separation structure CSI2 overlaps with the isolation insulation structure SIS in the Z-axis direction.

[0072] The isolation insulation structure SIS can be formed as a linear shape extending in the direction of the short axis AX1 to overlap with the first channel separation structure CSI1, the second channel separation structure CSI2 and the core insulation layer CO.

[0073] A first memory pattern ML1 of a cell pillar structure CPI is disposed between a first sidewall SW1 of a semiconductor pillar SP and a gate stack GST, and a second memory pattern ML2 of the cell pillar structure CPI is disposed between a second sidewall SW2 of the semiconductor pillar SP and a gate stack GST. The first memory pattern ML1 extends between a first insulating layer IL1 and a first channel portion CH1, and the second memory pattern ML2 extends between the first insulating layer IL1 and a second channel portion CH2. The first memory pattern ML1 and the second memory pattern ML2 may extend through a third insulating layer IL3 in the Z-axis direction. Each of the first memory pattern ML1 and the second memory pattern ML2 may include a tunnel insulating layer, a data storage layer, and a barrier insulating layer BI.

[0074] The tunnel insulating layer may include an oxide such as silicon dioxide (SiO2). The tunnel insulating layer is located between the semiconductor pillar SP and the gate stack GST. The tunnel insulating layer is separated in the second segment H[S2] of the via H and the first portion IL1[P1] of the first insulating layer by a first channel separation structure CSI1 and a second channel separation structure CSI2 into a first tunnel insulating pattern TI1 for a first memory pattern ML1 and a second tunnel insulating pattern TI2 for a second memory pattern ML2. The first tunnel insulating pattern TI1 and the second tunnel insulating pattern TI2 may extend through the second portion IL1[P2] of the first insulating layer and the third insulating layer IL3. The first tunnel insulating pattern TI1 and the second tunnel insulating pattern TI2 may be separated from each other in the second portion IL1[P2] of the first insulating layer by a first side pattern CHC[S1] and a second side pattern CHC[S2]. The first tunnel insulating pattern TI1 and the second tunnel insulating pattern TI2 may be separated from each other in the third insulating layer IL3 by an isolation insulating structure SIS.

[0075] The data storage layer can be formed as a material layer capable of storing data altered by utilizing Fowler-Nordheim tunneling. In an embodiment, the data storage layer can be formed as a charge-trapping insulating layer or an insulating layer comprising conductive nanodots. The charge-trapping insulating layer may comprise a silicon nitride layer. The data storage layer is located between the tunnel insulating layer and the gate stack GST. The data storage layer is separated in the second segment H[S2] of the aperture H and the first portion IL1[P1] of the first insulating layer by a first channel separation structure CSI1 and a second channel separation structure CSI2 into a first data storage pattern DS1 of a first memory pattern ML1 and a second data storage pattern DS2 of a second memory pattern ML2. The first data storage pattern DS1 and the second data storage pattern DS2 may extend through the second portion IL1[P2] of the first insulating layer and the third insulating layer IL3. The first data storage pattern DS1 and the second data storage pattern DS2 may be separated from each other in the second portion IL1[P2] of the first insulating layer by a first side pattern CHC[S1] and a second side pattern CHC[S2]. The first data storage pattern DS1 and the second data storage pattern DS2 can be separated from each other in the third insulating layer IL3 by an isolation insulating structure SIS.

[0076] The barrier insulating layer BI may include oxides, such as silicon dioxide (SiO2), or high-dielectric insulating materials with a higher dielectric constant compared to silicon dioxide. High-dielectric insulating materials may include aluminum oxide layers, hafnium oxide layers, etc. The barrier insulating layer BI is located between the data storage layer and the gate stack GST. The barrier insulating layer BI may extend continuously along the outer walls of the first data storage pattern DS1, the second data storage pattern DS2, the first channel separation structure CSI1, and the second channel separation structure CSI2 in each of the second segment H[S2] of the via H and the first portion IL1[P1] of the first insulating layer IL1. The barrier insulating layer BI may extend through the second portion IL1[P2] of the first insulating layer and the third insulating layer IL3 in the Z-axis direction. The barrier insulating layer BI may extend continuously along the outer walls of the first data storage pattern DS1, the second data storage pattern DS2, the first side pattern CHC[S1], and the second side pattern CHC[S2] in the second portion IL1[P2] of the first insulating layer. In one embodiment, the barrier insulating layer BI may be formed in a ring shape in the XY plane in each of the first segment H[S1] and the second segment H[S2] of the hole H. The isolation insulating structure SIS may extend through the barrier insulating layer BI in the direction of the short axis AX1.

[0077] Semiconductor pillars SP may include, for example, Figure 2A or Figure 2B The diagram shows the contact surface of a DPS contact in a doped semiconductor structure. The contact surface can have various designs. See below for reference. Figure 6A , Figure 6B , Figure 7A and Figure 7B Describes the contact surface according to embodiments of this disclosure.

[0078] Figure 6A It shows along such Figures 4A to 4C The diagram shows cross-sectional views of various configurations of a semiconductor memory device according to embodiments of the present disclosure, taken along the long axis of the hole. Figure 6B It shows along such Figures 4A to 4C Cross-sectional views of various configurations of a semiconductor memory device taken along the short axis of the hole are shown.

[0079] Figure 7A It shows along such Figures 4A to 4C The diagram shows cross-sectional views of various configurations of a semiconductor memory device according to embodiments of the present disclosure, taken along the long axis of the hole. Figure 7B It shows along such Figures 4A to 4C Cross-sectional views of various configurations of a semiconductor memory device taken along the short axis of the hole are shown.

[0080] Reference Figure 6A , Figure 6B , Figure 7A and Figure 7B The first surface SU1 of the first insulating layer IL1 is configured as a first portion IL1[P1], and the second surface SU2 of the first insulating layer IL1 is configured as a second portion IL1[P2]. ​​The gate stack GST is disposed above the first surface SU1, and the doped semiconductor structure DPS is disposed above the second surface SU2.

[0081] The core insulating layer CO and semiconductor pillar SP of the CPI unit pillar structure extend through the first surface SU1 and the second surface SU2 of the gate stack GST and the first insulating layer IL1. The core insulating layer CO and semiconductor pillar SP can extend into the interior of the doped semiconductor structure DPS.

[0082] The first channel portion CH1 and the second channel portion CH2 of the semiconductor pillar SP extend in the Z-axis direction through the gate stack GST and the first insulating layer IL1. The first channel portion CH1 and the second channel portion CH2 may extend into the doped semiconductor structure DPS. The first side pattern CHC[S1] and the second side pattern CHC[S2] constituting the connection portion of the semiconductor pillar SP extend from the interior of the doped semiconductor structure DPS to the exterior of the second portion IL1[P2] of the first insulating layer IL1. The semiconductor pillar SP may also include a horizontal portion CHH. The horizontal portion CHH may extend parallel to the XY plane from each of the first channel portion CH1, the second channel portion CH2, the first side pattern CHC[S1], and the second side pattern CHC[S2]. The horizontal portion CHH may be surrounded by the first channel portion CH1, the second channel portion CH2, the first side pattern CHC[S1], and the second side pattern CHC[S2]. Figure 5 As shown, the horizontal portion CHH can be disposed on a surface of the core insulation layer CO opposite to the isolation insulation structure SIS, the first covering portion CAP1, and the second covering portion CAP2.

[0083] The first channel separation structure CSI1 and the second channel separation structure CSI2 of the unit pillar structure CPI are respectively arranged on the first side pattern CHC[S1] and the second side pattern CHC[S2]. The first channel separation structure CSI1 and the second channel separation structure CSI2 extend through the first portion IL1[P1] of the first insulating layer IL1 and the gate stack GST in the Z-axis direction.

[0084] A first tunnel insulating pattern TI1 and a first data storage pattern DS1 of a first memory pattern ML1 are disposed between a first channel portion CH1 and a gate stack GST. The first tunnel insulating pattern TI1 and the first data storage pattern DS1 extend between the first channel portion CH1 and a first insulating layer IL1. A second tunnel insulating pattern TI2 and a second data storage pattern DS2 of a second memory pattern ML2 are disposed between a second channel portion CH2 and a gate stack GST. The second tunnel insulating pattern TI2 and the second data storage pattern DS2 extend between the second channel portion CH2 and the first insulating layer IL1. In an embodiment, each of the first tunnel insulating pattern TI1 and the first data storage pattern DS1 may extend between the first channel portion CH1 and each of the first portion IL1[P1] and the second portion IL1[P2] of the first insulating layer IL1, and each of the second tunnel insulating pattern TI2 and the second data storage pattern DS2 may extend between the second channel portion CH2 and each of the first portion IL1[P1] and the second portion IL1[P2] of the first insulating layer IL1. The barrier insulating layer BI extends along the outer wall of each of the first data storage pattern DS1, the second data storage pattern DS2, the first channel separation structure CSI1, and the second channel separation structure CSI2. The barrier insulating layer BI also extends along the outer wall of each of the first channel portion CH1, the second channel portion CH2, the first side pattern CHC[S1], and the second side pattern CHC[S2] in the second portion IL1[P2] of the first insulating layer IL1.

[0085] The doped semiconductor structure DPS can form a contact surface CTS with at least one of the first channel portion CH1, the second channel portion CH2, the first side pattern CHC[S1], the second side pattern CHC[S2], and the horizontal portion CHH of the semiconductor pillar SP.

[0086] Reference Figure 6A and Figure 6B In this embodiment, the doped semiconductor structure (DPS) may include an n-type impurity region or both an n-type impurity region and a p-type impurity region. The contact surface (CTS) of the doped semiconductor structure (DPS) may include various n-type impurities as majority carriers. The doped semiconductor structure (DPS) may include, for example,... Figure 3 and Figure 4A The second end CH1[E2] of the first channel portion CH1 shown is as follows: Figure 3 and Figure 4A The second end CH2[E2] of the second channel portion CH2 shown, the first side pattern CHC[S1], the second side pattern CHC[S2], and the contact surface CTS of the horizontal portion CHH are in contact.

[0087] Reference Figure 7A and Figure 7BIn one embodiment, the doped semiconductor structure DPS may include a first doped semiconductor layer L1, a second doped semiconductor layer L2, and a third doped semiconductor layer L3 stacked in the Z-axis direction. The unit pillar structure CPI may extend through the third doped semiconductor layer L3 of the doped semiconductor structure DPS and may extend into the first doped semiconductor layer L1.

[0088] Each of the first doped semiconductor layer L1, the second doped semiconductor layer L2, and the third doped semiconductor layer L3 may include an n-type impurity, a p-type impurity, or a mixture thereof. In an embodiment, each of the first doped semiconductor layer L1, the second doped semiconductor layer L2, and the third doped semiconductor layer L3 may include an n-type impurity as the majority carrier. Embodiments of this disclosure are not limited thereto. In an embodiment, the doped semiconductor structure DPS may form an n-type impurity region containing an n-type impurity as the majority carrier and a p-type impurity region containing a p-type impurity as the majority carrier. For example, the second doped semiconductor layer L2 may form an n-type impurity region, and one or both of the first doped semiconductor layer L1 and the third doped semiconductor layer L3 may form a p-type impurity region.

[0089] The unit pillar structure CPI may include a dummy memory pattern DML located between a first doped semiconductor layer L1 and a semiconductor pillar SP of a doped semiconductor structure DPS. The dummy memory pattern DML may include: a dummy tunnel insulating layer TI' comprising the same material as the first tunnel insulating pattern TI1 and the second tunnel insulating pattern TI2; a dummy data storage layer DS' comprising the same material as the first data storage pattern DS1 and the second data storage pattern DS2; and a dummy barrier insulating layer BI' comprising the same material as the barrier insulating layer BI. The dummy memory pattern DML may be located between a horizontal portion CHH of the semiconductor pillar SP and the first doped semiconductor layer L1. The horizontal portion CHH of the semiconductor pillar SP may extend through the dummy tunnel insulating layer TI' and the dummy data storage layer DS' of the dummy memory pattern DML to contact the dummy barrier insulating layer BI'. Figures 4A to 4C As shown, the contact surface between the horizontal portion CHH and the dummy barrier insulation layer BI' can extend along the short axis AX1 of the hole.

[0090] Each of the first memory pattern ML1 and the second memory pattern ML2 of the unit pillar structure CPI can extend between the semiconductor pillar SP and the third doped semiconductor layer L3 of the doped semiconductor structure DPS. The barrier insulating layer BI of the unit pillar structure CPI can extend between each of the first side pattern CHC[S1] and the second side pattern CHC[S2] of the semiconductor pillar SP and the third doped semiconductor layer L3 of the doped semiconductor structure DPS.

[0091] The contact surface CTS of the doped semiconductor structure DPS can be formed on the second doped semiconductor layer L2. The second doped semiconductor layer L2 may include the contact surface CTS that contacts the first channel portion CH1, the second channel portion CH2, the first side pattern CHC[S1], and the second side pattern CHC[S2]. The contact surface CTS may be located between the first doped semiconductor layer L1 and the third doped semiconductor layer L3.

[0092] Figure 8A and Figure 8B This is a plan view showing a cross-section of the unit column structure CPI' according to an embodiment of the present disclosure.

[0093] Reference Figure 8A and Figure 8B As shown above Figures 4A to 4C As described, the unit column structure CPI' includes a core insulating layer CO, a first channel portion CH1, a second channel portion CH2, a first side pattern CHC[S1'], and a second side pattern CHC[S2']. See above reference. Figures 4A to 4C As described, the first memory pattern ML1' of the unit column structure CPI' includes a first tunnel insulation pattern TI1 and a first data storage pattern DS1, and the second memory pattern ML2' of the unit column structure CPI' includes a second tunnel insulation pattern TI2 and a second data storage pattern DS2.

[0094] Reference Figure 8A Each of the first channel separation structure CSI1' and the second channel separation structure CSI2' in the unit column structure CPI' is located between the first channel portion CH1 and the second channel portion CH2 in the XY plane. Each of the first channel separation structure CSI1' and the second channel separation structure CSI2' is located within the short axis of the hole in the XY plane. Figure 4A Extending in the direction of AX1), it is disposed between the first tunnel insulation pattern TI1 and the second tunnel insulation pattern TI2, and between the first data storage pattern DS1 and the second data storage pattern DS2, and protrudes through the barrier insulation layer of the unit pillar structure CPI'. The barrier insulation layer can be separated by the first channel separation structure CSI1' and the second channel separation structure CSI2' into the first barrier insulation pattern BI1 of the first memory pattern ML1' and the second barrier insulation pattern BI2 of the second memory pattern ML2'.

[0095] Reference Figure 8B Each of the first side pattern CHC[S1'] and the second side pattern CHC[S2'] constituting the connecting portion of the semiconductor pillar is located between the first channel portion CH1 and the second channel portion CH2 in the XY plane. Each of the first side pattern CHC[S1'] and the second side pattern CHC[S2'] is located within the short axis of the hole in the XY plane. Figure 4AExtending in the direction of AX1), it is disposed between the first tunnel insulation pattern TI1 and the second tunnel insulation pattern TI2 and between the first data storage pattern DS1 and the second data storage pattern DS2, and protrudes through the barrier insulation layer of the unit pillar structure CPI'. The barrier insulation layer can be separated by the first side pattern CHC[S1'] and the second side pattern CHC[S2'] into the first barrier insulation pattern BI1 of the first memory pattern ML1' and the second barrier insulation pattern BI2 of the second memory pattern ML2'.

[0096] Various methods for manufacturing a semiconductor memory device according to embodiments of the present disclosure are described below.

[0097] Figure 9A , Figure 9B and Figure 9C This is a diagram illustrating a preliminary laminate and holes according to an embodiment of the present disclosure.

[0098] Figure 9A This is a plan view showing the preliminary laminate 100 and the plurality of holes 111. Figure 9B Is it like this? Figure 9A An enlarged view of region AR1 shown.

[0099] Reference Figure 9A and Figure 9B The initial laminate 100 can be penetrated by a plurality of holes 111. Each hole 111 has a structure including a minor axis AX1 and a major axis AX2 that intersect each other in the XY plane. In an embodiment, the holes 111 may have an elliptical shape in the XY plane.

[0100] Figure 9C This shows the initial stacked material 100 and, as shown, through... Figure 9B The cross-sectional view shown is of the hole 111 cut along the long axis AX2 of the preliminary laminate 100.

[0101] Reference Figure 9A , Figure 9B and Figure 9C In one embodiment, forming the preliminary laminate 100 includes: forming a lower insulating layer 101 extending parallel to the XY plane; stacking a plurality of first material layers 103 and a plurality of second material layers 105 in a stacking direction intersecting the XY plane (e.g., the Z-axis direction); and forming an upper insulating layer 107 above the laminate of the plurality of first material layers 103 and the plurality of second material layers 105. Each of the plurality of first material layers 103 is stacked alternately with each of the plurality of second material layers 105 in the stacking direction.

[0102] Although not shown, a lower insulating layer 101 may be formed above a lower structure (not shown). In embodiments, the lower structure may include, for example, Figure 2AThe semiconductor substrate SUB, peripheral circuit structure PCS, and doped semiconductor structure DPS are shown. In another embodiment, the following structure may include, for example... Figure 2A The diagram shows a semiconductor substrate (SUB), peripheral circuit structure (PCS), and a preliminary semiconductor structure. The preliminary semiconductor structure may include... Figure 7A and Figure 7B The diagram shows the first doped semiconductor layer L1, the third doped semiconductor layer L3, and the sacrificial structure between them. The sacrificial structure can be utilized in subsequent processes, such as... Figure 7A and Figure 7B The second doped semiconductor layer L2 shown is replaced. In another embodiment, the lower structure may be a sacrificial substrate formed using a silicon wafer or the like.

[0103] Each of the plurality of first material layers 103 and the plurality of second material layers 105 extends in the XY plane. The plurality of first material layers 103 may include a sacrificial insulating material having etch selectivity to the lower insulating layer 101, the plurality of second material layers 105, and the upper insulating layer 107. In one embodiment, the sacrificial insulating material may include a silicon nitride layer. Each of the lower insulating layer 101, the plurality of second material layers 105, and the upper insulating layer 107 may include an insulating material such as a silicon oxide layer and a silicon oxynitride layer. In the Z-axis direction, which is the stacking direction, each of the lower insulating layer 101 and the upper insulating layer 107 may be thicker than the respective second material layer 105.

[0104] The process of forming the hole 111 includes forming a mask pattern (not shown) using photolithography and using the mask pattern as an etching barrier to etch the preliminary stack 100. The mask pattern can be removed after forming the preliminary unit pillar structure in a subsequent process. The hole 111 includes a first segment 111S1, a second segment 111S2 connected to the first segment 111S1, and a third segment 111S3 connected to the second segment 111S2. The first segment 111S1 extends through the lower insulating layer 101. The second segment 111S2 extends through a plurality of first material layers 103 and a plurality of second material layers 105. The third segment 111S3 extends through the upper insulating layer 107. Each of the first segment 111S1, the second segment 111S2, and the third segment 111S3 of the hole 111 may have an elliptical shape in the XY plane.

[0105] Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B and Figure 14CThis is a diagram illustrating various configurations formed in the holes using a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0106] Figure 10A It is shown that by, as Figure 9B The diagram shows cross-sectional views of various configurations of the preliminary laminate 100 formed in the hole by cutting along the long axis AX2 of the hole 111. Figure 10B It shows that by along Figure 10A Plan view of various configurations formed in the holes by the line I-I' cutting the preliminary laminate 100.

[0107] Reference Figure 10A and Figure 10B A memory layer 120 and a seed barrier layer 131 can be formed sequentially inside the hole 111.

[0108] A memory layer 120 may be disposed on the sidewall of the lower insulating layer 101 adjacent to the via 111, and may extend into the second segment 111S2 and the third segment 111S3 of the via 111. The memory layer 120 may include a barrier insulating layer 121, a data storage layer 123, and a tunnel insulating layer 125. The barrier insulating layer 121 is disposed on the sidewall of the lower insulating layer 101 and extends into the second segment 111S2 and the third segment 111S3 of the via 111. The barrier insulating layer 121 may include one or both of silicon dioxide and a high-dielectric insulating material having a higher dielectric constant than silicon dioxide. The data storage layer 123 is disposed on the inner wall of the barrier insulating layer 121. The data storage layer 123 may include a charge-trapping insulating layer such as silicon nitride. The tunnel insulating layer 125 is disposed on the inner wall of the data storage layer 123. The tunnel insulating layer 125 may include silicon dioxide or the like.

[0109] A seed barrier layer 131 is formed along the surface of the tunnel insulating layer 125. The seed barrier layer 131 may have etch selectivity for the tunnel insulating layer 125. In an embodiment, the seed barrier layer 131 may comprise silicon. When depositing the seed barrier layer 131, the deposition thickness is controlled such that the thickness is greater in the direction of the major axis AX2 of the via 111 than in the direction of the minor axis AX1.

[0110] Figure 11A and Figure 11B It shows along Figure 10A The plan view of the various configurations formed in the hole is taken by line I-I'.

[0111] Reference Figure 11A Remove such as through hole 111 Figure 10BA portion of the seed barrier layer 131 shown is divided into a first seed barrier pattern 131A and a second seed barrier pattern 131B. The first seed barrier pattern 131A and the second seed barrier pattern 131B are defined based on the minor axis AX1 of the hole 111 and are spaced apart from each other in the direction of the major axis AX2. A portion of the memory layer 120 overlapping with the minor axis AX1 is exposed between the first seed barrier pattern 131A and the second seed barrier pattern 131B.

[0112] Reference Figure 11B A first growth barrier pattern 133A and a second growth barrier pattern 133B are formed on the inner walls of the first seed barrier pattern 131A and the second seed barrier pattern 131B, respectively. The first growth barrier pattern 133A and the second growth barrier pattern 133B can be formed by a selective growth method. In an embodiment, the first growth barrier pattern 133A and the second growth barrier pattern 133B can be selectively grown from the inner walls of the first seed barrier pattern 131A and the second seed barrier pattern 131B toward the intersection of the short axis AX1 and the long axis AX2, respectively, by a selective polysilicon growth method. The first growth barrier pattern 133A and the second growth barrier pattern 133B are defined based on the short axis AX1 of the hole 111 and are spaced apart from each other in the direction of the long axis AX2. A portion of the memory layer 120 overlapping with the short axis AX1 is exposed between the first growth barrier pattern 133A and the second growth barrier pattern 133B.

[0113] Figure 12A and Figure 12B It is along Figure 10A The diagram shows a plan view of the recess formed in the hole, taken by line I-I'.

[0114] Reference Figure 12A It can be achieved through etching Figure 11B The first recess 113A and the second recess 113B are formed by exposing a portion of the memory layer 120 between the first growth barrier pattern 133A and the second growth barrier pattern 133B. In an embodiment, the first recess 113A and the second recess 113B can be formed by etching some regions of the tunnel insulating layer that overlap with the short axis AX1 of the hole 111 and some regions of the data storage layer. A portion of the inner wall of the barrier insulating layer 121 can be exposed through the first recess 113A and the second recess 113B.

[0115] The tunnel insulation layer is separated into a first tunnel insulation pattern 125A and a second tunnel insulation pattern 125B by the first recess 113A and the second recess 113B. The data storage layer is separated into a first data storage pattern 123A and a second data storage pattern 123B by the first recess 113A and the second recess 113B. Therefore, as Figure 11BThe memory layer 120 shown can be divided into a first memory pattern 120A including a first tunnel insulating pattern 125A and a first data storage pattern 123A, and a second memory pattern 120B including a second tunnel insulating pattern 125B and a second data storage pattern 123B. The barrier insulating layer 121 may not be separated by the first recess 113A and the second recess 113B. The barrier insulating layer 121 may extend continuously in the XY plane to surround the outer wall of the first data storage pattern 123A and the outer wall of the second memory pattern 120B.

[0116] Reference Figure 12B Selectively remove such as Figure 12A The first seed barrier pattern 131A, the second seed barrier pattern 131B, the first growth barrier pattern 133A, and the second growth barrier pattern 133B are shown. As a result, the inner walls of the first memory pattern 120A and the second memory pattern 120B can be exposed through the hole 111.

[0117] Figure 13A , Figure 13B and Figure 13C This is a diagram showing the channel layer 137 in the hole 111. Figure 13A It is along Figure 13B Plan view of various configurations intercepted by line I-I' in the middle. Figure 13B It is along Figure 13A Cross-sectional views of various configurations taken from the long axis AX2. Figure 13C It is along Figure 13A Cross-sectional views of various configurations taken from the short axis AX1.

[0118] Reference Figure 13A , Figure 13B and Figure 13C A channel layer 137 is formed on the exposed inner wall of each of the first memory pattern 120A, the barrier insulating layer 121, and the second memory pattern 120B. The channel layer 137 may include silicon (Si), germanium (Ge), or a mixture thereof.

[0119] The channel layer 137 includes a first channel portion 137A, a second channel portion 137B, a first protrusion 137P1, and a second protrusion 137P2. The first channel portion 137A is the portion of the channel layer 137 disposed on the inner wall of the first tunnel insulating pattern 125A of the first memory pattern 120A. The second channel portion 137B is the portion of the channel layer 137 disposed on the inner wall of the second tunnel insulating pattern 125B of the second memory pattern 120B. The first protrusion 137P1 is a portion of the channel layer 137 between the first channel portion 137A and the second channel portion 137B and protrudes as shown in the image. Figure 12BThe first recess 113A is shown as a portion therein. The second protrusion 137P2 is between the first channel portion 137A and the second channel portion 137B of the channel layer 137 and protrudes as shown. Figure 12B The portion shown is in the second recess 113B. Each of the first protrusion 137P1 and the second protrusion 137P2 is disposed on the inner wall of the barrier insulating layer 121.

[0120] Figure 14A , Figure 14B and Figure 14C This is a diagram illustrating various configurations of the penetrating preliminary laminate 100 according to embodiments of the present disclosure.

[0121] Figure 14A This is a plan view showing the initial unit column structure 130 and the slit 145 passing through the initial stack 100. Figure 14B Is it like this? Figure 14A The enlarged view of region AR1 shown. Figure 14C This shows the initial stack 100 and the process along... Figure 14B A cross-sectional view of the preliminary unit column structure 130 of the preliminary laminate 100 cut by the short axis AX1.

[0122] Reference Figure 14A , Figure 14B and Figure 14C A core insulating layer 139 and a cover semiconductor layer 141 are formed in the central region of the hole surrounded by the channel layer 137. As a result, a preliminary unit pillar structure 130 including a first memory pattern 120A, a second memory pattern 120B, a channel layer 137, a core insulating layer 139, and a cover semiconductor layer 141 can be formed.

[0123] In one embodiment, the core insulating layer 139 may fill the central region of each of the first segment 111S1 and the second segment 111S2 of the aperture surrounded by the channel layer 137, and the overlay semiconductor layer 141 may fill the central region of the third segment 111S3 of the aperture surrounded by the channel layer 137. Each of the core insulating layer 139 and the overlay semiconductor layer 141 may include extensions such as Figure 13A The portion of the first recess 113A and the second recess 113B shown.

[0124] Forming the core insulating layer 139 includes: filling the central region of each of the first segment 111S1, the second segment 111S2, and the third segment 111S3 of the hole with an insulating material; and etching a portion of the insulating material to open the central region of the third segment 111S3 of the hole. A cover semiconductor layer 141 is located in the area where a portion of the insulating material is etched. According to an embodiment of this disclosure, in the process of etching a portion of the insulating material, the channel layer 137 is not divided into channel portions, but rather continues to surround the central region of each of the first segment 111S1, the second segment 111S2, and the third segment 111S3 of the hole in the XY plane. Therefore, in the process of etching a portion of the insulating material, the first tunnel insulating pattern 125A, the second tunnel insulating pattern 125B, and the barrier insulating layer 121 can be protected by the first protrusion 137P1 and the second protrusion 137P2 of the channel layer 137. For example, a portion of the trench layer 137 can be etched to divide the trench layer 137 into trench portions before forming the insulating material for the core insulating layer 139. The etched trench area of ​​the portion of the trench layer 137 can be filled with the insulating material for the core insulating layer 139 and then left open during a process in which a portion of the insulating material is etched to open the central region of the third segment 111S3 of the via. When a portion of the insulating material is etched, the first tunnel insulating pattern 125A, the second tunnel insulating pattern 125B, and the barrier insulating layer 121 may be damaged through the open trench etched area. Therefore, in order to protect the first tunnel insulating pattern 125A, the second tunnel insulating pattern 125B, and the barrier insulating layer 121, additional processes can be performed in the via after dividing the trench layer 137 into trench portions and before forming the core insulating layer 139, such as forming a protective layer in each of the first segment 111S1, the second segment 111S2, and the third segment 111S3 of the via. According to embodiments of this disclosure, since the core insulation layer 139 is formed while the trench layer 137 is not divided into trench portions, the first tunnel insulation pattern 125A, the second tunnel insulation pattern 125B, and the barrier insulation layer 121 can be protected by the first protrusion 137P1 and the second protrusion 137P2 of the trench layer 137, even without additional processes such as forming a protective layer in the holes.

[0125] The overlay semiconductor layer 141 includes a doped semiconductor material. The overlay semiconductor layer 141 may include silicon (Si), germanium (Ge), or a mixture thereof, and may be doped with n-type impurities or both n-type and p-type impurities. In one embodiment, the overlay semiconductor layer 141 may include doped silicon containing n-type impurities as majority carriers. The n-type or p-type impurities in the overlay semiconductor layer 141 may diffuse into the channel layer 137 adjacent to the overlay semiconductor layer 141. The overlay semiconductor layer 141 and the channel layer 137 may be integrated by a heat treatment such as laser annealing.

[0126] The initial stack 100 can be penetrated by the slit 145.

[0127] Figure 15A , Figure 15B , Figure 15C , Figure 15D and Figure 15E This is a diagram showing a channel separation structure formed using a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure, as well as the connection portion and dummy portion of the channel layer.

[0128] Figure 15A It shows along Figure 14B A cross-sectional view of the first channel separation structure 153A, the second channel separation structure 153B, the first side pattern 137P1A and the second side pattern 137P2A of the connecting portion, and the first dummy pattern 137P1B and the second dummy pattern 137P2B of the dummy portion, taken from the short axis AX1. Figure 15B It shows along Figure 15A Plan view of the first channel separation structure 153A and the second channel separation structure 153B, taken from line I-I' in the diagram. Figure 15C It shows along Figure 15A Plan view of the first channel separation structure 153A and the second channel separation structure 153B, taken from line II-II' in the figure. Figure 15D It shows along Figure 15A Plan view of the first side pattern 137P1A and the second side pattern 137P2A cut from line III-III'. Figure 15E It shows along Figure 15A Plan view of the first dummy pattern 137P1B and the second dummy pattern 137P2B intercepted by line IV-IV' in the middle.

[0129] Reference Figure 15A , Figure 15B , Figure 15C , Figure 15D and Figure 15E It can be achieved through, for example Figure 14A The slit 145 shown selectively removes, as Figure 14C Multiple first material layers 103 are used to form multiple openings OP. Subsequently, through the multiple openings OP, the first channel separation structure 153A and the second channel separation structure 153B are used to replace, respectively, the openings OP. Figure 14B and Figure 14C The first protrusion 137P1 and the second protrusion 137P2 are shown.

[0130] In one embodiment, the oxidant 151 introduced through multiple openings OP can be used to... Figure 14B and Figure 14CThe first protrusion 137P1 and the second protrusion 137P2 shown are oxidized to form the first channel separation structure 153A and the second channel separation structure 153B. In an embodiment, the first channel separation structure 153A and the second channel separation structure 153B can be formed via a wet oxidation process. Utilizing, as shown... Figure 14B and Figure 14C The first protrusion 137P1 and the second protrusion 137P2, which are blocked by the blocking insulating layer 121, are subjected to an oxidation process. The blocking insulating layer 121 comprises an oxide and does not block the oxidant 151. Figure 14B and Figure 14C The reaction of each of the first protrusion 137P1 and the second protrusion 137P2 shown. The tunnel insulation layer is separated into a first tunnel insulation pattern 125A and a second tunnel insulation pattern 125B, and as shown... Figure 14B and Figure 14C The oxidation process is performed with the first protrusion 137P1 and the second protrusion 137P2 protruding between them. Therefore, the oxidation rate delay caused by the tunnel insulation layer can be reduced. The first data storage pattern 123A and the second data storage pattern 123B can respectively block the reaction between the oxidant 151 and the first channel portion 137A and the second channel portion 137B.

[0131] A portion of a first protrusion and a portion of a second protrusion formed on the sidewall of a lower insulating layer 101, which is relatively thicker than the plurality of second material layers 105, can form a connecting portion without being oxidized. The connecting portion includes a first side pattern 137P1A formed by the first protrusion of that portion and a second side pattern 137P2A formed by the second protrusion of that portion. The first side pattern 137P1A and the second side pattern 137P2A connect the first channel portion 137A and the second channel portion 137B in the lower insulating layer 101. According to an embodiment of the present disclosure, the first side pattern 137P1A and the second side pattern 137P2A are arranged in the regions where the tunnel insulating layer and the data storage layer are respectively removed, such that the first channel portion 137A and the second channel portion 137B can protrude in the direction of the minor axis AX1 of the hole.

[0132] Another portion of the first protrusion and another portion of the second protrusion formed on the sidewall of the upper insulating layer 107, which is relatively thicker than the plurality of second material layers 105, may not be oxidized to form a dummy portion. The dummy portion includes a first dummy pattern 137P1B formed by the other portion of the first protrusion and a second dummy pattern 137P2B formed by the other portion of the second protrusion.

[0133] The first channel separation structure 153A extends continuously from the first side pattern 137P1A toward the first dummy pattern 137P1B, and the second channel separation structure 153B extends continuously from the second side pattern 137P2A toward the second dummy pattern 137P2B. Therefore, each of the first channel separation structure 153A and the second channel separation structure 153B is as follows: Figure 14C The second segment 111S2 of the hole shown extends continuously in the Z-axis direction (stack direction). Each of the first channel separation structure 153A and the second channel separation structure 153B is in contact with the barrier insulating layer 121.

[0134] The first channel portion 137A and the second channel portion 137B can be separated by the first channel separation structure 153A and the second channel separation structure 153B. Figure 14C The second section 111S2 of the hole shown is spaced apart from each other in the direction of the long axis AX2 of the hole.

[0135] Figure 16 This is a cross-sectional view showing a plurality of conductive layers formed using a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0136] Reference Figure 16 , can Figure 15A and Figure 15B Multiple conductive layers 161 are formed in the multiple openings OP shown. Each conductive layer 161 may include various conductive materials such as doped semiconductor layers, metal layers, etc. The doped semiconductor layer may include a doped silicon layer. The metal layer may include tungsten, copper, molybdenum, etc. The conductive layer 161 may also include a metal nitride layer. The metal nitride layer may include titanium nitride, tantalum nitride, etc. The metal nitride layer may be disposed at the junction of the barrier insulating layer 121 and the... Figure 15A and Figure 15B The opening OP is shown on the surface adjacent to the opening OP, and may extend over the surface of the lower insulating layer 101, the surface of the second material layer 105, or the surface of the upper insulating layer 107 adjacent to the opening OP.

[0137] Figure 17A , Figure 17B , Figure 17C and Figure 17D This is a diagram illustrating various configurations formed using a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. Figure 17A Cross-sections of various configurations taken along the major axis AX2 of the hole are shown. Figure 17B Cross-sections of various configurations taken along the short axis AX1 of the hole are shown. Figure 17C It is along Figure 17B Plan view of various configurations intercepted by line I-I' in the middle. Figure 17D It is along Figure 17BPlan view of various configurations intercepted by line IV-IV' in the middle.

[0138] Reference Figure 17A , Figure 17B , Figure 17C and Figure 17D ,pass Figure 16 The semiconductor layer 141 shown forms an isolation insulating structure 171. The isolation insulating structure 171 will... Figure 16 The illustrated cover semiconductor layer 141 is separated into a first cover portion 141A and a second cover portion 141B. An insulating isolation structure 171 extends in the direction of the short axis AX1 of the aperture to extend through... Figure 16 The first dummy pattern 137P1B and the second dummy pattern 137P2B of the channel layer are shown. As a result, the first channel portion 137A and the second channel portion 137B can be separated from each other in the upper insulating layer 107 by the insulating isolation structure 171. Compared with the short axis AX1 of the hole, the insulating isolation structure 171 extends further in the direction of the short axis AX1 and can extend through the upper insulating layer 107.

[0139] In the XY plane, each conductive layer 161 may extend continuously to surround the first channel portion 137A and the second channel portion 137B, which are separated by the first channel separation structure 153A and the second channel separation structure 153B.

[0140] Figure 18A , Figure 18B , Figure 18C and Figure 18D This is a plan view illustrating various configurations formed using a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0141] In formation Figure 18A Before configuring as shown, you can execute the above reference. Figure 9A , Figure 9B and Figure 9C The described process, the above reference Figure 10A and Figure 10B The described process and the above reference Figure 11A and Figure 11B The described process. As a result, it can form products including, for example... Figure 11A The first material layer 103 shown is a preliminary laminate, and a hole 111 penetrating the preliminary laminate in the Z-axis direction can be formed. The hole 111 has a minor axis AX1 and a major axis AX2 that intersect each other in the XY plane. Furthermore, as... Figure 11BAs shown, a memory layer 120, including a barrier insulating layer 121, a data storage layer 123, and a tunnel insulating layer 125, can be formed on the sidewall of the first material layer 103 adjacent to the hole 111. Additionally, a first seed barrier pattern 131A and a second seed barrier pattern 131B, spaced apart from each other in the direction of the long axis AX2 of the hole 111, can be formed on the inner wall of the memory layer 120. Furthermore, a first growth barrier pattern 133A and a second growth barrier pattern 133B can be formed on the inner walls of the first seed barrier pattern 131A and the second seed barrier pattern 131B, respectively.

[0142] Subsequently, as Figure 18A As shown, it can be etched as Figure 11B A portion of the exposed memory layer 120 between the first growth barrier pattern 133A and the second growth barrier pattern 133B is used to form the first recess 113A' and the second recess 113B'.

[0143] Figure 18A This is a plan view showing the first material layer 103 cut along the XY plane. Figure 18B , Figure 18C and Figure 18D It is shown that... Figure 18A A plan view of the various configurations at the corresponding heights.

[0144] Reference Figure 18A The first recess 113A' and the second recess 113B' can be formed by etching some areas of the tunnel insulation layer, some areas of the data storage layer, and some areas of the barrier insulation layer that overlap with the short axis AX1 of the hole 111. The first material layer 103 can be exposed through the first recess 113A' and the second recess 113B'.

[0145] The tunnel insulation layer is separated into a first tunnel insulation pattern 125A and a second tunnel insulation pattern 125B by the first recess 113A' and the second recess 113B'. The data storage layer is separated into a first data storage pattern 123A and a second data storage pattern 123B by the first recess 113A' and the second recess 113B'. The barrier insulation layer is separated into a first barrier insulation pattern 121A and a second barrier insulation pattern 121B by the first recess 113A' and the second recess 113B'. Therefore, Figure 11BThe memory layer 120 shown can be divided into a first memory pattern 120A' including a first tunnel insulating pattern 125A, a first data storage pattern 123A, and a first barrier insulating pattern 121A, and a second memory pattern 120B' including a second tunnel insulating pattern 125B, a second data storage pattern 123B, and a second barrier insulating pattern 121B. After forming the first memory pattern 120A' and the second memory pattern 120B', the first seed barrier pattern, the second seed barrier pattern, the first growth barrier pattern, and the second growth barrier pattern are selectively removed. As a result, as Figure 18A As shown, the inner walls of the first memory pattern 120A' and the second memory pattern 120B' can be exposed through the hole 111.

[0146] Reference Figure 18B A channel layer 137' is formed in the hole. The channel layer 137' is formed on the exposed inner wall of each of the first memory pattern 120A', the second memory pattern 120B', and the first material layer 103. The channel layer 137' may include silicon (Si), germanium (Ge), or a mixture thereof.

[0147] The channel layer 137' includes a first channel portion 137A, a second channel portion 137B, a first protrusion 137P1', and a second protrusion 137P2'. The first channel portion 137A is the portion of the channel layer 137' on the inner wall of the first tunnel insulating pattern 125A of the first memory pattern 120A'. The second channel portion 137B is the portion of the channel layer 137' on the inner wall of the second tunnel insulating pattern 125B of the second memory pattern 120B'. The first protrusion 137P1' is the portion of the channel layer 137' between the first channel portion 137A and the second channel portion 137B and protrudes into the first recess 113A'. The second protrusion 137P2' is the portion of the channel layer 137' between the first channel portion 137A and the second channel portion 137B and protrudes into the second recess 113B'. Each of the first protrusion 137P1' and the second protrusion 137P2' is disposed on the inner wall of the first material layer 103. Each of the first protrusion 137P1' and the second protrusion 137P2' can be disposed on the inner wall of the first material layer 103. Figure 13C It extends above the inner walls of the lower insulating layer 101, each of the second material layers 105, and the upper insulating layer 107, as shown. (Similar to...) Figure 13C Compared to the first protrusion 137P1 and the second protrusion 137P2 shown, as Figure 18B Each of the first protrusion 137P1' and the second protrusion 137P2' shown can access the inner wall of each of the lower insulating layer 101, the first material layer 103, the second material layer 105, and the upper insulating layer 107 of the preliminary laminate 100 without the need for the insertion of the blocking insulating layer 121.

[0148] In the formation of such Figure 18B After the channel layer 137' shown, the following can be used as referenced. Figure 14A , Figure 14B and Figure 14C The described process forms a core insulating layer 139 and a cover semiconductor layer in the central region of the hole surrounded by the channel layer 137'. Subsequently, a process such as... Figure 14A The slit 145 is shown.

[0149] Reference Figure 18C By selectively removing via slits Figure 18B The first material layer 103 shown can form an opening OP. For example... Figure 18B The first protrusion 137P1' and the second protrusion 137P2' of the channel layer 137' shown can be exposed through the opening OP. Subsequently, through the opening OP, the first channel separation structure 153A' and the second channel separation structure 153B' are respectively replaced. Figure 18B The first protrusion 137P1' and the second protrusion 137P2' are shown.

[0150] In the implementation method, as referred to Figure 15A , Figure 15B , Figure 15C , Figure 15D and Figure 15E The described method involves opening the OP as follows: Figure 18B The first protrusion 137P1' and the second protrusion 137P2' shown are oxidized to form the first channel separation structure 153A' and the second channel separation structure 153B'. In another embodiment, the first channel separation structure is formed by etching through an opening OP, as shown in the figure. Figure 18B After the first protrusion 137P1' and the second protrusion 137P2' shown, the first channel separation structure 153A' and the second channel separation structure 153B' can be formed by filling the etched areas of the first protrusion 137P1' and the second protrusion 137P2' with an oxide layer.

[0151] Reference Figure 18D , can Figure 18C A conductive layer 161 is formed in the opening OP shown. Then, the procedure described above can be performed. Figure 17A , Figure 17B , Figure 17C and Figure 17D The process described.

[0152] Figure 19 This is a block diagram illustrating an electronic system 1000 according to an embodiment of the present disclosure.

[0153] Reference Figure 19The electronic system 1000 may be a computing system, a medical device, a communication device, a wearable device, a memory system, etc. The electronic system 1000 may include a host 1100 and a storage device 1200.

[0154] Host 1100 can store data in storage device 1200 or retrieve data stored in storage device 1200 based on an interface. The interface may include one or more of the following: Double Data Rate (DDR) interface, Universal Serial Bus (USB) interface, Multimedia Card (MMC) interface, Embedded MMC (eMMC) interface, Peripheral Component Interconnect (PCI) interface, High-Speed ​​PCI (PCI-E) interface, Advanced Technology Attachment (ATA) interface, Serial ATA interface, Parallel ATA interface, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Device (IDE) interface, Firewire interface, Universal Flash Memory (UFS) interface, and High-Speed ​​Non-Volatile Memory (NVMe) interface.

[0155] Storage device 1200 may include storage controller 1210 and semiconductor memory device 1220. In some embodiments, storage device 1200 may be a storage medium such as a solid-state drive (SSD), a universal serial bus (USB) memory, etc.

[0156] The host 1100 can control the storage controller 1210 to store data in the semiconductor memory device 1220 or to read data stored in the semiconductor memory device 1220.

[0157] Semiconductor memory device 1220 may include one or more memory chips. Semiconductor memory device 1220 may store or output stored data in response to control by memory controller 1210.

[0158] Semiconductor memory device 1220 may be a non-volatile memory device. Semiconductor memory device 1220 may include: an aperture having a cross-sectional structure including a major axis and a minor axis and extending longitudinally to include a first segment through an insulating layer and a second segment through a gate stack above the insulating layer; and a semiconductor pillar extending from the first segment of the aperture to the second segment of the aperture and including a first sidewall and a second sidewall defined based on the minor axis. The semiconductor pillar may include a first channel portion forming the first sidewall, a second channel portion forming the second sidewall and spaced apart from the first channel portion, and a connection portion connecting the first channel portion and the second channel portion in the first segment of the aperture.

[0159] According to embodiments of this disclosure, a channel separation structure that divides a semiconductor pillar into channel portions can be formed within a hole using a process performed outside the hole, without the need for in-hole processing. Therefore, a channel separation structure can be formed without the need for in-hole processing, which is difficult to control precisely, thereby reducing the process complexity and defects of dividing a semiconductor pillar into channel portions and improving the operational reliability of the semiconductor memory device.

[0160] Cross-references to related applications

[0161] This application claims priority to Korean Patent Application No. 10-2025-0046903, filed with the Korean Intellectual Property Office on April 10, 2025, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A first insulating layer, the first insulating layer including a first surface extending parallel to the XY plane; A gate stack located above the first surface of the first insulating layer and comprising a plurality of conductive layers and a plurality of second insulating layers, the plurality of conductive layers and the plurality of second insulating layers being arranged alternately in a stacking direction intersecting the XY plane; A semiconductor pillar extending in the stacking direction and including a first segment extending through the first insulating layer and a second segment extending through the gate stack, the semiconductor pillar having a major axis and a minor axis in the XY plane and including a first sidewall and a second sidewall defined on opposite sides of the minor axis; A first memory pattern is located between the first sidewall of the semiconductor pillar and the gate stack; as well as A second memory pattern is located between the second sidewall of the semiconductor pillar and the gate stack. Each of the first segment and the second segment of the semiconductor pillar includes: A first channel portion, the first channel portion forming the first sidewall; and The second channel portion forms the second sidewall and is spaced apart from the first channel portion, and The first section of the semiconductor pillar further includes a connecting portion that connects the first channel portion and the second channel portion within the first section of the semiconductor pillar.

2. The semiconductor memory device of claim 1, further comprising a third insulating layer located above the gate stack. in, The semiconductor pillar also includes a first covering portion and a second covering portion extending through the third insulating layer, and The first covering portion and the second covering portion are spaced apart from each other in the direction of the long axis.

3. The semiconductor memory device according to claim 2, wherein, The end of the first channel portion extends through the third insulating layer and is integral with the first covering portion, and The end of the second channel portion extends through the third insulating layer and is integral with the second covering portion.

4. The semiconductor memory device according to claim 3, wherein, The end of the first channel portion and the first cover portion are formed with a first doped semiconductor pattern having a semi-elliptical shape in the XY plane, and The end portion of the second channel portion and the second cover portion are formed into a second doped semiconductor pattern having a semi-elliptical shape in the XY plane.

5. The semiconductor memory device of claim 2, further comprising an isolation insulating structure located between the first cover portion and the second cover portion, the isolation insulating structure extending in the direction of the short axis.

6. The semiconductor memory device according to claim 1, wherein, Each of the first and second segments of the semiconductor pillar has an elliptical shape in the XY plane.

7. The semiconductor memory device according to claim 1, wherein, The connecting portion of the semiconductor pillar includes a first side pattern and a second side pattern, and The first side pattern and the second side pattern are spaced apart from each other in the direction of the short axis and extend from the first channel portion to the second channel portion.

8. The semiconductor memory device of claim 7, further comprising: A first channel separation structure overlaps with the first side pattern in the stacking direction; as well as A second channel separation structure overlaps with the second side pattern in the stacking direction. The first channel separation structure and the second channel separation structure are arranged in the second section of the semiconductor pillar between the first channel portion and the second channel portion.

9. The semiconductor memory device according to claim 1, wherein, The first memory pattern extends between the first channel portion of the semiconductor pillar and the first insulating layer. Wherein, the second memory pattern extends between the second channel portion of the semiconductor pillar and the first insulating layer, and The connecting portion of the semiconductor pillar protrudes relative to the first channel portion and the second channel portion in the direction of the short axis and is located between the first memory pattern and the second memory pattern.

10. The semiconductor memory device according to claim 1, wherein, Each of the first memory pattern and the second memory pattern includes: A tunnel insulating layer is located between the semiconductor pillar and the gate stack, and the tunnel insulating layer extends into the first segment of the semiconductor pillar; A data storage layer located between the tunnel insulating layer and the gate stack, the data storage layer extending within the first segment of the semiconductor pillar; and A barrier insulating layer is located between the data storage layer and the gate stack, and the barrier insulating layer extends into the first segment of the semiconductor pillar.

11. The semiconductor memory device of claim 10, further comprising a channel separation structure located in the second segment of the semiconductor pillar between the first channel portion and the second channel portion, the channel separation structure overlapping the connecting portion of the semiconductor pillar in the stacking direction. in, The tunnel insulation layer is separated into a first tunnel insulation pattern and a second tunnel insulation pattern by the connection portion of the trench separation structure and the semiconductor pillar, and The data storage layer is separated into a first data storage pattern and a second data storage pattern by the connection portion of the channel separation structure and the semiconductor pillar.

12. The semiconductor memory device according to claim 11, wherein, The barrier insulating layer extends along the outer wall of each of the first data storage pattern, the second data storage pattern, the channel separation structure, and the connection portion of the semiconductor pillar, and the barrier insulating layer has a ring shape in the XY plane.

13. The semiconductor memory device according to claim 11, wherein, The connection portion of the channel separation structure and the semiconductor pillar extends through the barrier insulating layer in the direction of the short axis, and The barrier insulating layer is separated into a first barrier insulating pattern and a second barrier insulating pattern by the connection portion of the channel separation structure and the semiconductor pillar.

14. The semiconductor memory device of claim 1, further comprising a doped semiconductor structure located above the second surface of the first insulating layer. in, The second surface of the first insulating layer is opposite to the first surface of the first insulating layer. Wherein, each of the first channel portion, the second channel portion, and the connecting portion of the semiconductor pillar extends into the doped semiconductor structure, and The semiconductor pillar further includes a horizontal portion extending from the connection portion parallel to the XY plane.

15. The semiconductor memory device according to claim 14, wherein, The doped semiconductor structure includes a contact surface that contacts each of the first channel portion, the second channel portion, the connection portion, and the horizontal portion.

16. The semiconductor memory device of claim 14, further comprising a dummy memory pattern located between the horizontal portion of the semiconductor pillar and the doped semiconductor structure, and in, The doped semiconductor structure includes a contact surface that contacts each of the first channel portion, the second channel portion, and the connection portion.

17. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A lower insulating layer is formed that extends parallel to the XY plane; Multiple first material layers and multiple second material layers are alternately stacked above the lower insulating layer in a stacking direction intersecting the XY plane; A hole is formed, the hole including a first segment passing through the lower insulating layer and a second segment extending from the first segment through the plurality of first material layers and the plurality of second material layers, the hole having a major axis and a minor axis in the XY plane; A memory layer is formed on the sidewall of the lower insulating layer adjacent to the hole, and the memory layer extends into the second section of the hole; The recess is formed by etching a portion of the memory layer that overlaps with the short axis of the hole; A channel layer is formed on the inner wall of the memory layer, the channel layer including protrusions that project toward the recess; Remove the plurality of first material layers to form a plurality of openings; The protrusions of the channel layer are replaced by the channel separation structure through the multiple openings; as well as Multiple conductive layers are formed in the multiple openings respectively.

18. The method according to claim 17, wherein, Each of the plurality of second material layers includes an insulating material.

19. The method of claim 17, further comprising the step of: Before forming the holes, an upper insulating layer is formed over the plurality of first material layers and the plurality of second material layers. The hole includes a third segment that extends from the second segment and through the upper insulating layer in the stacking direction. The memory layer extends into the third segment of the hole.

20. The method of claim 19, further comprising the step of: Before removing the plurality of first material layers A portion of each of the first and second segments of the hole surrounded by the channel layer is filled using a core insulating layer; as well as A portion of the third section of the hole surrounded by the channel layer is filled using a cover semiconductor layer.

21. The method according to claim 20, wherein, Each of the overlay semiconductor layer and the core insulating layer includes a portion extending into the recess.

22. The method of claim 20, further comprising the step of: This forms an insulating structure that separates the covered semiconductor layer into a first covered portion and a second covered portion. The insulating structure extends through the channel layer in the direction of the short axis.

23. The method according to claim 17, wherein, Each of the first and second segments of the hole has an elliptical shape in the XY plane.

24. The method of claim 17, wherein, The memory layer includes a barrier insulation layer located on the sidewall of the lower insulation layer and extending into the second section of the hole, a data storage layer located on the inner wall of the barrier insulation layer, and a tunnel insulation layer located on the inner wall of the data storage layer.

25. The method according to claim 24, wherein, The step of forming the recess is performed by etching a portion of each of the tunnel insulation layer and the data storage layer that overlap with the short axis of the hole to expose a portion of the inner wall of the barrier insulation layer, and The step of replacing the protrusions of the trench layer with the trench separation structure through the plurality of openings is performed by oxidizing the protrusions of the trench layer through the plurality of openings when the protrusions of the trench layer are blocked by the barrier insulating layer.

26. The method according to claim 24, wherein, The step of forming the recess is performed by etching a portion of each of the tunnel insulation layer, the data storage layer, and the barrier insulation layer that overlap with the short axis of the hole to expose the plurality of first material layers.

27. The method according to claim 26, wherein, The step of replacing the protrusions of the channel layer through the multiple openings using the channel separation structure is performed by oxidizing the protrusions of the channel layer through the multiple openings.

28. The method according to claim 26, wherein, The step of replacing the protrusions of the channel layer using the channel separation structure through the plurality of openings includes the following steps: The protrusions of the channel layer are etched through the plurality of openings; and The etched area of ​​the protrusion is filled with an oxide layer.

29. The method according to claim 17, wherein, The channel separation structure extends continuously in the stacking direction in the second section of the hole, and The channel layer is separated in the second section of the hole into a first channel portion and a second channel portion spaced apart in the direction of the long axis by the channel separation structure.

30. The method according to claim 29, wherein, A portion of the protrusions in the channel layer of the first section of the hole were not replaced by the channel separation structure, and The channel layer includes a connecting portion that extends from the first section of the hole into the recess and overlaps with the channel separation structure in the stacking direction.

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