A method for fabricating an embedded flash memory device

Abstract

This invention provides a method for fabricating an embedded flash memory device. The method includes providing a semiconductor structure, comprising a substrate with a tunneling oxide layer on its front side, and a floating gate layer, a control gate dielectric layer, a control gate layer, and a silicon nitride layer covering opposite sides of the substrate. The silicon nitride layer, control gate layer, control gate dielectric layer, floating gate layer, and tunneling oxide layer on one side of the tunneling oxide layer constitute a gate structure. A sidewall structure film and a sacrificial layer are formed on opposite sides of the semiconductor structure, and the sidewall structure film and silicon nitride layer on the back side of the substrate are removed by wet etching. The sacrificial layer is removed, and the sidewall structure is formed. A gate oxide layer of a predetermined thickness is formed on the front side of the substrate by a rapid thermal oxidation process. This method for fabricating an embedded flash memory device avoids misjudgments by the pyrometer in furnace tube equipment, ensuring that the thickness of the subsequently grown oxide layer reaches the target value, thereby reducing deviations in the device's electrical parameters and improving the device yield.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and relates to a method for preparing an embedded flash memory device. Background Technology

[0002] In the fabrication process of embedded super flash (ESF), due to the complexity of the ESF structure, the density of the thin film in the process flow is very important. Therefore, the thin film used to build the ESF structure is mostly grown using furnace tube process. The furnace tube process has the characteristic of growing thin films on the front and back sides of the wafer at the same time. At present, in the process from control gate (CG) to control gate oxide silicon nitride spacer (CGON spacer) of ESF structure, furnace tube is used to grow silicon nitride (SIN) thin film. After dry etching, only a small amount of SIN is retained on the front side of the wafer in the flash area, while all the SIN thin film on the back side of the wafer is retained.

[0003] Subsequently, during the gate oxide growth process in the Rapid Thermal Oxidation (RTO) step, a pyrometer in the furnace tube equipment uses closed-loop control of the heating lamp output power by monitoring the thermal radiation from the back of the wafer. The pyrometer calculates the temperature by measuring the thermal radiation emitted by the wafer. Since the infrared emissivity of the SiN film is typically higher than that of bare silicon, at the same physical temperature, a wafer with a fully preserved SiN film on the back will emit a stronger thermal radiation signal than a wafer with bare silicon on the back. When the pyrometer monitoring the back receives this enhanced signal, it misjudges that the wafer has reached the set process temperature faster. To maintain the target temperature displayed by the equipment, the control system automatically reduces the lamp output power. As a result, although the temperature curve displayed by the equipment is consistent with the preset value, the actual physical temperature of the wafer does not actually reach the set value, but is somewhat lower. Because the growth rate of the oxide layer is extremely sensitive to temperature and follows an exponential relationship according to the Arrhenius equation, even a small decrease in actual temperature will cause the oxide layer growth rate to slow down significantly. This will result in the gate oxide layer thickness on the front side of the wafer being significantly thinner than the target value, leading to problems such as deviations in electrical parameters and low yield of the device.

[0004] Therefore, how to provide a method for fabricating embedded flash memory devices to avoid the actual temperature being lower than expected due to misjudgment by the pyrometer in the furnace tube equipment, so that the thickness of the subsequently grown oxide layer reaches the target value, thereby reducing the deviation of the device's electrical parameters and improving the device yield, has become an important problem that urgently needs to be solved by those skilled in the art.

[0005] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating embedded flash memory devices, which solves the problem that in the prior art, the high temperature gauge of the furnace tube equipment is prone to misjudgment due to the presence of silicon nitride film on the back of the wafer, which leads to the actual temperature being lower than expected. This results in the gate oxide layer thickness grown on the front of the wafer being significantly thinner than the target value, thus causing the device to have deviations in electrical parameters and low yield.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating an embedded flash memory device, comprising the following steps:

[0008] A semiconductor structure is provided, the semiconductor structure including a substrate, a tunneling oxide layer, a floating gate layer, a control gate dielectric layer, a control gate layer, and a silicon nitride layer. The substrate includes a logic region and a memory region. A preset gate region is disposed in the memory region. The tunneling oxide layer covers the preset gate region. The floating gate layer covers the tunneling oxide layer and the bottom surface of the substrate. The control gate dielectric layer, the control gate layer, and the silicon nitride layer are stacked sequentially on the tunneling oxide layer and the floating gate layer on the bottom surface of the substrate along the direction from the substrate to the floating gate layer. The tunneling oxide layer, the floating gate layer, the control gate dielectric layer, the control gate layer, and the silicon nitride layer located above the preset gate region constitute a gate structure.

[0009] A sidewall structure film is formed on two opposite sides of the semiconductor structure using a furnace tube growth process. The sidewall structure film covers the gate structure and the silicon nitride layer on one side of the back of the substrate.

[0010] A sacrificial layer is formed on the sidewall structure film layer on the front side of the substrate;

[0011] The sidewall structure film and the silicon nitride layer on the back side of the substrate are removed by wet etching.

[0012] Remove the sacrificial layer and etch the sidewall structure film layer on one side of the front side of the substrate to form a sidewall structure;

[0013] A gate oxide layer is formed on the front side of the substrate by a rapid thermal oxidation process. The gate oxide layer covers the sidewall structure and the exposed area on the front side of the substrate and has a predetermined thickness.

[0014] Optionally, forming the semiconductor structure includes the following steps:

[0015] A substrate having the tunneling oxide layer frontally covered is provided;

[0016] The floating gate layer, the control gate dielectric layer, the control gate layer, and the silicon nitride layer are sequentially formed on opposite sides of the substrate using a furnace tube growth process.

[0017] The silicon nitride layer, the control gate layer, the control gate dielectric layer, the floating gate layer, and the tunneling oxide layer located outside the preset gate region on the front side of the substrate are sequentially etched away to form the gate structure on the memory region.

[0018] Optionally, multiple shallow trench isolation structures are provided at intervals within the logic area.

[0019] Optionally, the control gate dielectric layer includes a first silicon nitride layer and oxide layers located on opposite sides of the first silicon nitride layer. The thickness of the first silicon nitride layer is in the range of 40 Å to 50 Å, the thickness of the oxide layer on the side away from the substrate is in the range of 40 Å to 50 Å, and the thickness of the oxide layer on the side closer to the substrate is in the range of 50 Å to 60 Å.

[0020] Optionally, the thickness of the silicon nitride layer ranges from 1100 Å to 1300 Å.

[0021] Optionally, the thickness of the sacrificial layer ranges from 400 Å to 600 Å.

[0022] Optionally, there may be multiple gate structures, and the multiple gate structures are spaced apart on the memory region along the direction from the logic region to the memory region.

[0023] Optionally, the sidewall structure membrane is an oxide layer or an oxide-nitride stack.

[0024] Optionally, the floating gate layer is a polysilicon layer, and the control gate layer is a polysilicon layer.

[0025] Optionally, the substrate is a P-type substrate.

[0026] As described above, the method for fabricating the embedded flash memory device of the present invention includes the following steps: providing a semiconductor structure, the semiconductor structure including a substrate, a tunneling oxide layer, a floating gate layer, a control gate dielectric layer, a control gate layer, and a silicon nitride layer, the substrate including a logic region and a memory region, a preset gate region being disposed in the memory region, the tunneling oxide layer covering the preset gate region, the floating gate layer covering the bottom surface of the tunneling oxide layer and the substrate, the control gate dielectric layer, the control gate layer, and the silicon nitride layer being sequentially stacked on the floating gate layer on the bottom surface of the tunneling oxide layer and the substrate along the direction from the substrate to the floating gate layer, and the tunneling oxide layer located above the preset gate region. A gate structure is formed by a floating gate layer, a control gate dielectric layer, a control gate layer, and a silicon nitride layer. Sidewall structure films are formed on opposite sides of the semiconductor structure using a furnace tube growth process, covering the gate structure and the silicon nitride layer on the back side of the substrate. A sacrificial layer is formed on the sidewall structure film on the front side of the substrate. The sidewall structure film and silicon nitride layer on the back side of the substrate are removed by wet etching. The sacrificial layer is removed, and the sidewall structure film on the front side of the substrate is etched to form the sidewall structure. A gate oxide layer is formed on the front side of the substrate using a rapid thermal oxidation process, covering the sidewall structure and having a predetermined thickness. In this method of fabricating an embedded flash memory device, before growing the gate oxide layer in a furnace tube, the removal of the SiN film on the back side of the substrate by wet etching avoids the actual temperature being lower than expected due to misjudgment by the pyrometer in the furnace tube equipment. This ensures that the thickness of the subsequently grown oxide layer reaches the target value, thereby reducing deviations in the device's electrical parameters and improving the device yield. Attached Figure Description

[0027] Figure 1 The diagram shows a semiconductor structure provided in a method for fabricating a flash memory device.

[0028] Figure 2 This diagram illustrates the structure obtained after forming a sidewall structure film layer in a method for fabricating a flash memory device.

[0029] Figure 3 This diagram illustrates the structure obtained after forming the sidewall structure in a method for fabricating a flash memory device.

[0030] Figure 4 This diagram illustrates the structure obtained after forming a gate oxide layer in a method for fabricating a flash memory device.

[0031] Figure 5 The diagram shown is a process flow diagram of the method for fabricating the embedded flash memory device of the present invention.

[0032] Figure 6 The diagram shown illustrates the semiconductor structure provided in the method for fabricating the embedded flash memory device of the present invention.

[0033] Figure 7The diagram shown is a schematic of the structure obtained after forming the sidewall structure film layer in the fabrication method of the embedded flash memory device of the present invention.

[0034] Figure 8 The diagram shown is a schematic of the structure obtained after forming the sacrificial layer in the fabrication method of the embedded flash memory device of the present invention.

[0035] Figure 9 The diagram shows the structure obtained after removing the sidewall structure film and silicon nitride layer on one side of the back side of the substrate in the fabrication method of the embedded flash memory device of the present invention.

[0036] Figure 10 The diagram shown is a schematic of the structure obtained after forming the sidewall structure in the fabrication method of the embedded flash memory device of the present invention.

[0037] Figure 11 The diagram shown is a schematic of the structure obtained after forming the gate oxide layer in the fabrication method of the embedded flash memory device of the present invention.

[0038] Explanation of reference numerals in the figures: 101, silicon substrate; 102, tunneling silicon oxide layer; 103, polysilicon floating gate layer; 104, control gate silicon oxide layer; 1041, lower silicon nitride layer; 1042, silicon oxide layer; 105, control gate polysilicon layer; 106, upper silicon nitride layer; 107, upper gate structure; 108, sidewall structure oxide film layer; 1081, first oxide; 1082, first nitride; 109, upper sidewall structure; 110, upper gate oxide layer; 301, substrate; 302, tunneling oxide layer; 303, floating gate layer; 30... 4. Control gate dielectric layer, 3041, first silicon nitride layer, 3042, oxide layer, 305, control gate layer, 306, silicon nitride layer, 307, gate structure, 309, sidewall structure film layer, 3091, oxide, 3092, nitride, 311, sidewall structure, 312, gate oxide layer, 308, shallow trench isolation structure, 310, sacrificial layer, I, first logic region, II, first memory region, III, logic region, IV, memory region, a, first preset gate region, b, preset gate region, S1~S6, steps. Detailed Implementation

[0039] Please see Figures 1 to 4 The diagram shows a structural schematic of each step in a method for fabricating a flash memory device, which includes the following steps:

[0040] (1) Please refer to Figure 1A semiconductor structure is provided, comprising a silicon substrate 101 with a tunneling silicon oxide layer 102 on its front side, a polysilicon floating gate layer 103, a control gate silicon oxide layer 104, a control gate polysilicon layer 105, and an upper silicon nitride layer 106. The silicon substrate 101 includes a first logic region I and a first memory region II. A first preset gate region a is disposed in the first memory region II. The polysilicon floating gate layer 103, the control gate silicon oxide layer 104, the control gate polysilicon layer 105, and the upper silicon nitride layer 106 are provided. The silicon nitride layer 106 is sequentially formed on opposite sides of the silicon substrate 101 using a furnace tube growth process, and the upper silicon nitride layer 106, the control gate polysilicon layer 105, the control gate silicon oxide layer 104, the polysilicon floating gate layer 103, and the tunneling silicon oxide layer 102 are sequentially etched to form an upper gate structure 107 on the first memory region II. The control gate silicon oxide layer 104 includes a lower silicon nitride layer 1041 and silicon oxide layers 1042 located on opposite sides of the lower silicon nitride layer 1041.

[0041] (2) Please refer to Figure 2 A sidewall oxide film layer 108 is formed on two opposite sides of the semiconductor structure by a furnace tube growth process. The sidewall oxide film layer 108 covers the upper gate structure 107 and the upper silicon nitride layer 106. The sidewall oxide film layer 108 may be a stack of a first oxide 1081 and a first nitride 1082.

[0042] (3) Please refer to Figure 3 The sidewall structure oxide film layer 108 on one side of the front side of the silicon substrate 101 is etched to form the upper sidewall structure 109.

[0043] (4) Please refer to Figure 4 An upper gate oxide layer 110 is formed on the front side of the silicon substrate 101, and the upper gate oxide layer 110 covers the upper sidewall structure 109.

[0044] The above fabrication steps utilize furnace tube growth combined with dry etching to define the structure. After dry etching, only a small amount of the upper silicon nitride layer 106 on the front side of the silicon substrate 101 remains in the flash memory region, while the upper silicon nitride layer 106 on the back side of the silicon substrate 101 is completely preserved. Because the upper silicon nitride layer 106 has a high infrared emissivity, during the growth of the upper gate oxide layer 110 in the furnace tube equipment, the presence of the upper silicon nitride layer 106 on the back side of the silicon substrate 101 triggers the device's automatic power reduction mechanism—the device prematurely reduces the lamp output power due to misinterpretation (interpreting the high emissivity signal as a higher physical temperature). At this point, although the temperature curve displayed by the device is consistent with the set value, the actual physical temperature of the silicon substrate 101 is lower than the set value. The growth rate of the upper gate oxide layer 110 is extremely sensitive to temperature (following the Arrhenius equation, showing an exponential relationship). The decrease in actual temperature will cause the oxidation rate to be significantly lower than that of the silicon substrate 101 with bare silicon on the back side. Ultimately, the film thickness of the upper gate oxide layer 110 grown by rapid thermal oxidation is thinner than the target thickness, which severely restricts the film thickness control capability and process window of rapid thermal oxidation growth, and easily causes device electrical parameter drift and yield problems.

[0045] Based on this, the present invention provides a method for fabricating an embedded flash memory device. By removing the SIN film on the back side of the substrate using wet etching before growing the gate oxide layer in the furnace tube equipment, the actual temperature caused by misjudgment by the pyrometer in the furnace tube equipment can be avoided, so that the thickness of the subsequently grown oxide layer reaches the target value, thereby reducing the deviation of the device's electrical parameters and improving the device yield.

[0046] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0048] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0049] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0050] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0051] In the context of this invention, the described structure of the first feature "above" the second feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0052] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] Please see Figure 5 The diagram shows a process flow chart of the method for fabricating the embedded flash memory device of the present invention, which includes at least the following steps:

[0054] S1: A semiconductor structure is provided, the semiconductor structure including a substrate, a tunneling oxide layer, a floating gate layer, a control gate dielectric layer, a control gate layer, and a silicon nitride layer. The substrate includes a logic region and a memory region. A preset gate region is disposed in the memory region. The tunneling oxide layer covers the preset gate region. The floating gate layer covers the bottom surface of the tunneling oxide layer and the substrate. The control gate dielectric layer, the control gate layer, and the silicon nitride layer are stacked sequentially on the floating gate layer on the bottom surface of the tunneling oxide layer and the substrate along the direction from the substrate to the floating gate layer. The tunneling oxide layer, the floating gate layer, the control gate dielectric layer, the control gate layer, and the silicon nitride layer located above the preset gate region constitute a gate structure.

[0055] S2: A sidewall structure film is formed on two opposite sides of the semiconductor structure using a furnace tube growth process. The sidewall structure film covers the gate structure and the silicon nitride layer on one side of the back of the substrate.

[0056] S3: A sacrificial layer is formed on the sidewall structure film layer on the front side of the substrate;

[0057] S4: Wet etching is used to remove the sidewall structure film and the silicon nitride layer on one side of the back side of the substrate;

[0058] S5: Remove the sacrificial layer and etch the sidewall structure film layer on one side of the front side of the substrate to form a sidewall structure;

[0059] S6: A gate oxide layer is formed on the front side of the substrate by a rapid thermal oxidation process. The gate oxide layer covers the sidewall structure and has a preset thickness.

[0060] The following section, using a structural diagram, details the specific implementation methods for each of the above steps.

[0061] Please refer to the following first. Figure 6 Step S1: Provide a semiconductor structure, the semiconductor structure including a substrate 301, a tunneling oxide layer 302, a floating gate layer 303, a control gate dielectric layer 304, a control gate layer 305, and a silicon nitride layer 306. The substrate 301 includes a logic region III and a memory region IV. A preset gate region b is disposed in the memory region IV. The tunneling oxide layer 302 covers the preset gate region b. The floating gate layer 303 covers the tunneling oxide layer 302 and the bottom surface of the substrate 301. The control gate dielectric layer 304, the control gate layer 305, and the silicon nitride layer 306 are stacked sequentially on the floating gate layer 303 on the bottom surface of the substrate 301 along the direction from the substrate 301 to the floating gate layer 303. The tunneling oxide layer 302, the floating gate layer 303, the control gate dielectric layer 304, the control gate layer 305, and the silicon nitride layer 306 located above the preset gate region b constitute a gate structure 307.

[0062] As an example, forming the semiconductor structure includes the following steps:

[0063] (1) A substrate 301 with the tunneling oxide layer 302 covered on the front side is provided;

[0064] (2) The floating gate layer 303, the control gate dielectric layer 304, the control gate layer 305 and the silicon nitride layer 306 are sequentially formed on opposite sides of the substrate 301 by furnace tube growth process;

[0065] (3) The silicon nitride layer 306, the control gate layer 305, the control gate dielectric layer 304, the floating gate layer 303 and the tunneling oxide layer 302 located outside the preset gate region b on the front side of the substrate 301 are sequentially etched away to form the gate structure 307 on the memory region IV.

[0066] As an example, multiple shallow trench isolation structures 308 are spaced apart within the logic region III.

[0067] As an example, the floating gate layer 303 is a polysilicon layer, and the control gate layer 305 is a polysilicon layer.

[0068] As an example, the substrate 301 is a P-type substrate.

[0069] As an example, the thickness of the floating gate layer 303 ranges from 250 Å to 350 Å, and the thickness of the control gate layer 305 ranges from 400 Å to 600 Å. In this embodiment, the thickness of the floating gate layer 303 is 290 Å, and the thickness of the control gate layer 305 is 500 Å.

[0070] As an example, the control gate dielectric layer 304 includes a first silicon nitride layer 3041 and an oxide layer 3042 located on opposite sides of the first silicon nitride layer 3041. The thickness of the first silicon nitride layer 3041 ranges from 40 Å to 50 Å, the thickness of the oxide layer 3042 on the side away from the substrate 301 ranges from 40 Å to 50 Å, and the thickness of the oxide layer 3042 on the side closer to the substrate 301 ranges from 50 Å to 60 Å. In this embodiment, the thickness of the first silicon nitride layer 3041 is 47 Å, the thickness of the oxide layer 3042 on the side away from the substrate 301 ranges from 45 Å, and the thickness of the oxide layer 3042 on the side closer to the substrate 301 ranges from 53 Å.

[0071] As an example, the thickness of the silicon nitride layer 306 ranges from 1100 Å to 1300 Å. In this embodiment, the thickness of the silicon nitride layer 306 is 1200 Å.

[0072] As an example, there are multiple gate structures 307, and the multiple gate structures 307 are spaced apart on the memory region IV along the direction from the logic region III to the memory region IV.

[0073] Please see again Figure 7 Step S2: A sidewall structure film 309 is formed on two opposite sides of the semiconductor structure by furnace tube growth process. The sidewall structure film 309 covers the silicon nitride layer 306 on the back side of the gate structure 307 and the substrate 301.

[0074] As an example, the sidewall structure film layer 309 is an oxide layer or an oxide-nitride stack. In this embodiment, the sidewall structure film layer 309 includes oxide 3091 and nitride 3092 stacked sequentially along the direction from the substrate 301 to the floating gate layer 303. The thickness of the oxide 3091 is in the range of 70 Å to 90 Å, and the thickness of the nitride 3092 is in the range of 150 Å to 250 Å. In this embodiment, the thickness of the oxide 3091 is 80 Å, and the thickness of the nitride 3092 is 200 Å.

[0075] Please see again Figure 8 Step S3: Form a sacrificial layer 310 on the sidewall structure film layer 309 on the front side of the substrate 301.

[0076] As an example, the thickness of the sacrificial layer 310 ranges from 400 Å to 600 Å, and the material of the sacrificial layer 310 includes silicon dioxide. In this embodiment, the thickness of the sacrificial layer 310 is 500 Å.

[0077] Specifically, the sacrificial layer 310 is formed using a chemical vapor deposition process.

[0078] Please see again Figure 9 Step S4: Use wet etching to remove the sidewall structure film 309 and the silicon nitride layer 306 on one side of the back of the substrate 301.

[0079] Specifically, when the sidewall structural film layer 309 is a silicon oxide layer, the silicon oxide layer is removed using a hydrofluoric acid etching solution or a buffered hydrofluoric acid etching solution. The concentration of hydrofluoric acid in the hydrofluoric acid etching solution is 0.1% to 5%, the concentration of ammonium fluoride in the buffered hydrofluoric acid etching solution is 20% to 40%, and the concentration of hydrofluoric acid is 0.1% to 10%. Then, a hot phosphoric acid solution with a phosphoric acid concentration of 80% to 90% is used to remove the silicon nitride layer 306. When the sidewall structural film layer 309 is a stack of oxide and nitride layers, the nitride layer is removed using a hot phosphoric acid solution with a phosphoric acid concentration of 80% to 90%, followed by the removal of the oxide layer using a hydrofluoric acid etching solution with a hydrofluoric acid concentration of 0.1% to 5%, and finally, the removal of the silicon nitride layer 306 using a hot phosphoric acid solution with a phosphoric acid concentration of 80% to 90%.

[0080] During the wet etching process described above, the front side of the substrate 301 is protected by the sacrificial layer 310. The wet etching solution mainly acts on the film layer to be removed on the back side of the substrate 301, without directly contacting the gate structure 307 and sidewall structure film layer 309 on the front side of the substrate 301. Even if a small amount of etching solution, reaction byproducts, or particles are present at the wafer edge, contaminants will preferentially adhere to the surface of the sacrificial layer 310, rather than directly adhering to the device structure on the front side of the substrate 301. When the sacrificial layer 310 is subsequently removed, the contaminants attached to the sacrificial layer 310 can be removed as well, thereby preventing contamination of the structure on the front side of the substrate 301.

[0081] Please see again Figure 10 Step S5: Remove the sacrificial layer 310 and etch the sidewall structure film layer 309 on the front side of the substrate 301 to form the sidewall structure 311.

[0082] Specifically, the sacrificial layer 310 is removed by wet etching with a hydrofluoric acid aqueous solution of 0.1% to 5%. After removing the sacrificial layer 310, the sidewall structure film layer 309 on one side of the front side of the substrate 301 is etched by an anisotropic dry etching process to remove the sidewall structure film layer 309 located on the top of the gate structure 307 and on the horizontal area of ​​the front side of the substrate 301, while retaining the sidewall structure film layer 309 located on the sidewall of the gate structure 307, thereby forming the sidewall structure 311.

[0083] It should be noted that, Figure 10 The sidewall structure is not formed on the horizontal region of the front side of the substrate 301 because the sidewall structure film layer 309 in this region is a horizontally extending portion and is removed during the anisotropic dry etching process. However, the sidewall structure film layer 309 located on the sidewall of the gate structure 307, being in a vertical sidewall position, is retained after etching, thus forming the sidewall structure 311. In other words, the sidewall structure 311 refers only to the film layer portion retained on the sidewall of the gate structure 307 and does not include the film layer portion removed during etching on the horizontal region of the front side of the substrate 301.

[0084] Please see again Figure 11 Step S6: A gate oxide layer 312 is formed on the front side of the substrate 301 by a rapid thermal oxidation process. The gate oxide layer 312 covers the sidewall structure 311 and the exposed area on the front side of the substrate 301 that is not covered by the gate structure 307 and the sidewall structure 311. The gate oxide layer 312 has a preset thickness.

[0085] Through the above steps S1 to S6, before forming the gate oxide layer 312 through the rapid thermal oxidation process, the sacrificial layer 310 is used to cover and protect the structure on the front side of the substrate 301. Then, the sidewall structure film layer 309 and the silicon nitride layer 306 on the back side of the substrate 301 are removed by wet etching. This avoids the high temperature of the furnace tube equipment from misjudging the temperature due to the high infrared emissivity of the silicon nitride layer 306 without affecting the device structure, and avoids the interference of the thermal radiation signal of the silicon nitride layer 306. This ensures that the actual physical temperature of the substrate 301 in the subsequent rapid thermal oxidation process reaches the set value, and finally grows the gate oxide layer 312 with the same thickness as the target thickness. This reduces the deviation of the device's electrical parameters and improves the device yield and process stability.

[0086] In summary, the method for fabricating the embedded flash memory device of the present invention includes the following steps: providing a semiconductor structure, the semiconductor structure including a substrate, a tunneling oxide layer, a floating gate layer, a control gate dielectric layer, a control gate layer, and a silicon nitride layer, the substrate including a logic region and a memory region, a preset gate region being disposed in the memory region, the tunneling oxide layer covering the preset gate region, the floating gate layer covering the bottom surface of the tunneling oxide layer and the substrate, the control gate dielectric layer, the control gate layer, and the silicon nitride layer being sequentially stacked on the floating gate layer on the bottom surface of the tunneling oxide layer and the substrate along the direction from the substrate to the floating gate layer, and the tunneling oxide layer located above the preset gate region. A gate structure is formed by a floating gate layer, a control gate dielectric layer, a control gate layer, and a silicon nitride layer. Sidewall structure films are formed on opposite sides of the semiconductor structure using a furnace tube growth process, covering the gate structure and the silicon nitride layer on the back side of the substrate. A sacrificial layer is formed on the sidewall structure film on the front side of the substrate. The sidewall structure film and silicon nitride layer on the back side of the substrate are removed by wet etching. The sacrificial layer is removed, and the sidewall structure film on the front side of the substrate is etched to form the sidewall structure. A gate oxide layer is formed on the front side of the substrate using a rapid thermal oxidation process, covering the sidewall structure and having a predetermined thickness. The method for fabricating the embedded flash memory device of this invention removes the SiN film on the back side of the substrate by wet etching before growing the gate oxide layer in the furnace tube equipment. This avoids the actual temperature being lower than expected due to misjudgment by the pyrometer in the furnace tube equipment, ensuring that the thickness of the subsequently grown oxide layer reaches the target value, thereby reducing deviations in the device's electrical parameters and improving the device yield. Therefore, this invention effectively overcomes various shortcomings of the prior art and has high industrial applicability.

[0087] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating an embedded flash memory device, characterized in that, Includes the following steps: A semiconductor structure is provided, the semiconductor structure including a substrate, a tunneling oxide layer, a floating gate layer, a control gate dielectric layer, a control gate layer, and a silicon nitride layer. The substrate includes a logic region and a memory region. A preset gate region is disposed in the memory region. The tunneling oxide layer covers the preset gate region. The floating gate layer covers the tunneling oxide layer and the bottom surface of the substrate. The control gate dielectric layer, the control gate layer, and the silicon nitride layer are stacked sequentially on the tunneling oxide layer and the floating gate layer on the bottom surface of the substrate along the direction from the substrate to the floating gate layer. The tunneling oxide layer, the floating gate layer, the control gate dielectric layer, the control gate layer, and the silicon nitride layer located on the preset gate region constitute a gate structure. A sidewall structure film is formed on two opposite sides of the semiconductor structure using a furnace tube growth process. The sidewall structure film covers the gate structure and the silicon nitride layer on one side of the back of the substrate. A sacrificial layer is formed on the sidewall structure film layer on the front side of the substrate; The sidewall structure film and the silicon nitride layer on the back side of the substrate are removed by wet etching. Remove the sacrificial layer and etch the sidewall structure film layer on one side of the front side of the substrate to form a sidewall structure; A gate oxide layer is formed on the front side of the substrate by a rapid thermal oxidation process. The gate oxide layer covers the sidewall structure and the exposed area on the front side of the substrate and has a predetermined thickness.

2. The method for fabricating an embedded flash memory device according to claim 1, characterized in that, Forming the semiconductor structure includes the following steps: A substrate having the tunneling oxide layer frontally covered is provided; The floating gate layer, the control gate dielectric layer, the control gate layer, and the silicon nitride layer are sequentially formed on opposite sides of the substrate using a furnace tube growth process. The silicon nitride layer, the control gate layer, the control gate dielectric layer, the floating gate layer, and the tunneling oxide layer located outside the preset gate region on the front side of the substrate are sequentially etched away to form the gate structure on the memory region.

3. The method for fabricating an embedded flash memory device according to claim 1, characterized in that: The logic area is provided with multiple shallow trench isolation structures at intervals.

4. The method for fabricating an embedded flash memory device according to claim 1, characterized in that: The control gate dielectric layer includes a first silicon nitride layer and oxide layers located on opposite sides of the first silicon nitride layer. The thickness of the first silicon nitride layer ranges from 40 Å to 50 Å. The thickness of the oxide layer on the side away from the substrate ranges from 40 Å to 50 Å. The thickness of the oxide layer on the side closer to the substrate ranges from 50 Å to 60 Å.

5. The method for fabricating an embedded flash memory device according to claim 1, characterized in that: The thickness of the silicon nitride layer ranges from 1100 Å to 1300 Å.

6. The method for fabricating an embedded flash memory device according to claim 1, characterized in that: The thickness of the sacrificial layer ranges from 400 Å to 600 Å.

7. The method for fabricating an embedded flash memory device according to claim 1, characterized in that: The number of gate structures is multiple, and the multiple gate structures are distributed at intervals on the memory region along the direction from the logic region to the memory region.

8. The method for fabricating an embedded flash memory device according to claim 1, characterized in that: The sidewall structural membrane is an oxide layer or an oxide-nitride stack.

9. The method for fabricating an embedded flash memory device according to claim 1, characterized in that: The floating gate layer is a polysilicon layer, and the control gate layer is a polysilicon layer.

10. The method for fabricating an embedded flash memory device according to claim 1, characterized in that: The substrate is a P-type substrate.

Images