Non-volatile memory device and method of manufacturing the same

Abstract

This application provides a non-volatile memory device and its fabrication method. The memory cell includes an isolation structure, two semi-floating gate structures located on both sides of the isolation structure, and a bottom connection structure passing through a portion of the isolation structure. The bottom connection structure makes conductive contact with the two semi-floating gate bodies, forming a continuously conductive memory node. The semi-floating gate bodies contact a second doped layer of a different doping type at the contact window to form a window PN junction structure, and form a sidewall parasitic MOS transistor structure with the drain, the second doped layer between them, the floating gate isolation layer, and the control gate. The fabrication method includes forming two floating gate trenches, filling and etching back sacrificial material to expose the isolation structure, partially etching the isolation structure and filling and etching back conductive material to form the bottom connection structure, backfilling isolation material on top of it, forming two semi-floating gate bodies in contact with the bottom connection structure, and forming a contact window, a floating gate isolation layer, and a control gate that are separated from each other.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory device technology, specifically to a non-volatile memory device and its fabrication method. Background Technology

[0002] Semi-floating gate memory devices can distinguish different storage states using the charge state in the semi-floating gate. The writing and erasing of related semi-floating gate memory cells usually rely on the same semi-floating gate and its adjacent local interface region. This local interface repeatedly undertakes the carrier entry and removal process in multiple write and erase cycles, which may affect the charge retention and write / erase reliability of the device. Summary of the Invention

[0003] In view of this, this application provides a non-volatile memory device and a method for fabricating the same, so as to at least improve the memory node organization and fabrication problems of the two semi-floating gate bodies in a semi-floating gate memory cell.

[0004] On one hand, this application provides a non-volatile memory device, including a semiconductor substrate and a plurality of memory cells formed on the semiconductor substrate. Within the memory cells, a first doped layer and a second doped layer of different doping types are formed on the semiconductor substrate along a bottom-to-top stacking direction. The memory cell includes: an isolation structure disposed within the semiconductor substrate and at least isolating the second doped layer; a first half-floating gate structure and a second half-floating gate structure respectively disposed on opposite sides of the isolation structure; and a bottom connection structure. The bottom connection structure is located below the top of the isolation structure, passes through a portion of the isolation structure, and makes conductive contact with the half-floating gate body of the first half-floating gate structure and the half-floating gate body of the second half-floating gate structure, respectively; the isolation structure isolates the first half-floating gate structure and the second half-floating gate structure outside the area through which the bottom connection structure passes. Each of the first half-floating gate structure and the second half-floating gate structure includes a half-floating gate body, a control gate, and a floating gate isolation layer. The half-floating gate body includes an embedded portion embedded in the second doped layer and an extension portion extending from the embedded portion to the surface side of the second doped layer; the control gate is disposed above the extension portion; the floating gate isolation layer is disposed between the half-floating gate body and the control gate, and is disposed in the area between the half-floating gate body and the second doped layer excluding the contact window. The conductivity types of the semi-floating gate body and drain are different from those of the second doped layer; the drain is formed in the second doped layer and spaced apart from the semi-floating gate body; the contact window is located between the extension and the second doped layer. The semi-floating gate body contacts the second doped layer at the contact window to form a window PN junction structure; the semi-floating gate body, drain, the second doped layer located between them, the floating gate isolation layer, and the control gate form a sidewall parasitic MOS transistor structure. The first semi-floating gate structure and the second semi-floating gate structure together form a continuously conductive storage node through a bottom connection structure.

[0005] On the other hand, this application provides a method for fabricating a non-volatile memory device. The method includes: providing a semiconductor substrate, the semiconductor substrate including a first doped layer and a second doped layer with different doping types distributed along a bottom-to-top stacking direction, and an isolation structure at least isolating the second doped layer; forming a hard mask layer on the semiconductor substrate; etching the second doped layer on both sides of the isolation structure using the hard mask layer as a mask to form floating gate trenches on both sides, and forming an oxide layer on the surface of the floating gate trenches; filling and etching back sacrificial material in the floating gate trenches to expose the isolation structure; etching the exposed isolation structure so that the upper surface of the remaining isolation structure is located within the second doped layer, and forming a receiving space above it that communicates with the floating gate trenches on both sides; filling and etching back floating gate conductive material in the receiving space, so that a portion of the floating gate conductive material remains in the receiving space and communicates with the floating gate trenches on both sides to form a bottom connection structure; filling the bottom connection structure with isolation material and removing the hard mask layer and sacrificial material. Excess isolation material above the sacrificial material is used to form an isolation structure together with the residual isolation structure and the backfill isolation material. The hard mask layer and sacrificial material are removed to form a trench isolation portion on the non-contact surface of the floating gate trench. Two semi-floating gate bodies are formed by filling the floating gate trenches on both sides with a semi-floating gate semiconductor material with a different conductivity type than the second doped layer. The two semi-floating gate bodies are made to make conductive contact with the two contact interfaces of the bottom connection structure, respectively. The trench isolation portion between the two semi-floating gate bodies and the second doped layer is partially removed, and the semi-floating gate semiconductor material is filled into the formed opening to form a contact window. A control gate dielectric portion and a control gate material are formed. The control gate material is patterned into two separate control gates, and two drain terminals corresponding to the two semi-floating gate bodies are formed in the second doped layer. The trench isolation portion and the control gate dielectric portion together constitute the floating gate isolation layer.

[0006] Based on the above device structure, the two semi-floating gate bodies are electrically connected through the bottom connection structure to jointly form a storage node, and the functional structures on different sides can be used to establish carrier entry and removal conditions. The above fabrication method utilizes the local etching of floating gate trenches, sacrificial materials, and isolation structures to form the bottom connection structure and its insulating boundary, providing a technological basis for the formation of a continuous conductive storage node on both sides of the semi-floating gate bodies. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a semi-floating gate memory device in related technologies; Figure 1 (a) is a top view of a semiconductor memory device; Figure 1 (b) is a partial sectional view along the cutting line x0.

[0008] Figure 2 This is a schematic diagram of a non-volatile storage device in some embodiments of this application; Figure 2 (a) is a top view of a semiconductor memory device; Figure 2 (b) is a cross-sectional view of regions X1 and X2 along the cutting lines x1 and x2; Figure 2 (c) is a cross-sectional view of region Y1 along the cutting line y1; Figure 2 (d) is a cross-sectional view of region Y2 along section line y2; where, Figure 2 (b), (c), and (d) show continuously conductive storage nodes.

[0009] Figure 3 This is a schematic diagram of the fabrication process of a non-volatile storage device in some embodiments of this application.

[0010] Figure 4 This provides a schematic diagram of the process state after the semiconductor substrate is installed; Figure 4 (a) is a top view of the process; Figure 4 (b) is a cross-sectional view of regions X1 and X2 along the cutting lines x1 and x2; Figure 4 (c) is a cross-sectional view of region Y1 along the cutting line y1.

[0011] Figure 5 A schematic diagram of the process state after forming the floating gate trench, the oxide layer on the trench surface, and the hard mask layer; Figure 5 (a) is a top view of the process; Figure 5 (b) is a cross-sectional view of regions X1 and X2 along the cutting lines x1 and x2; Figure 5 (c) is a cross-sectional view of region Y1 along the cutting line y1.

[0012] Figure 6 A schematic diagram of the process state after filling the floating gate trench with sacrificial material; Figure 6 (a) is a top view of the process; Figure 6 (b) is a cross-sectional view of regions X1 and X2 along the cutting lines x1 and x2; Figure 6 (c) is a cross-sectional view of region Y1 along the cutting line y1.

[0013] Figure 7 A schematic diagram of the process state after the sacrificial material is re-etched and the isolation structure is exposed; Figure 7 (a) is a top view of the process; Figure 7 (b) is a cross-sectional view of regions X1 and X2 along the cutting lines x1 and x2; Figure 7 (c) is a cross-sectional view of region Y1 along the cutting line y1.

[0014] Figure 8 This is a schematic diagram of the process input state before local etching of the exposed isolation structure; Figure 8 (a) is a top view of the process; Figure 8(b) is a cross-sectional view of regions X1 and X2 along the cutting lines x1 and x2; Figure 8 (c) is a cross-sectional view of region Y1 along the cutting line y1.

[0015] Figure 9 This is a schematic diagram of the process state after the isolation structure is partially etched and an open area is formed above the residual isolation structure. Figure 9 (a) is a top view of the process; Figure 9 (b) is a cross-sectional view of regions X1 and X2 along the cutting lines x1 and x2; Figure 9 (c) is a cross-sectional view of region Y1 along the cutting line y1.

[0016] Figure 10 A schematic diagram of the process state when forming a receiving space that communicates with the floating grid trenches on both sides and preparing to fill it with the floating grid conductive material; Figure 10 (a) is a top view of the process; Figure 10 (b) is a cross-sectional view of regions X1 and X2 along the cutting lines x1 and x2; Figure 10 (c) is a cross-sectional view of region Y1 along the cutting line y1.

[0017] Figure 11 This is a schematic diagram of the process state after the floating grid conductive material is filled into the containment space; Figure 11 (a) is a top view of the process; Figure 11 (b) is a cross-sectional view of regions X1 and X2 along the cutting lines x1 and x2; Figure 11 (c) is a cross-sectional view of region Y1 along the cutting line y1.

[0018] Figure 12 A schematic diagram of the process state after the bottom connection structure and its upper isolation cover are formed, and the hard mask layer and sacrificial material are removed and the floating gate trenches on both sides are reopened; Figure 12 (a) is a top view of the process; Figure 12 (b) is a cross-sectional view of regions X1 and X2 along the cutting lines x1 and x2; Figure 12 (c) is a cross-sectional view of region Y1 along the cutting line y1.

[0019] Figure 13 A schematic diagram of the process state after the two semi-floating gate bodies are formed to make conductive contact with the bottom connection structure; Figure 13 (a) is a top view of the process; Figure 13 (b) is a cross-sectional view of regions X1 and X2 along the cutting lines x1 and x2; Figure 13 (c) is a cross-sectional view of region Y1 along the cutting line y1.

[0020] Figure 14This is a schematic diagram of the process state when the contact window position is defined by a window photolithography pattern. Figure 14 (a) is a top view of the process; Figure 14 (b) is a cross-sectional view of regions X1 and X2 along the cutting lines x1 and x2; Figure 14 (c) is a cross-sectional view of region Y1 along the cutting line y1.

[0021] Figure 15 A schematic diagram of the process state after an opening is formed by partially removing the isolation portion of the trench; Figure 15 (a) is a top view of the process; Figure 15 (b) is a cross-sectional view of regions X1 and X2 along the cutting lines x1 and x2; Figure 15 (c) is a cross-sectional view of region Y1 along the cutting line y1.

[0022] Among them, 10 is a non-volatile memory device; 101 is a memory cell; 102 is an isolation structure; 110 is a semiconductor substrate; 111 is a first doped layer; 112 is a second doped layer; 121 is a semi-floating gate body; 121a is a first semi-floating gate body; 121b is a second semi-floating gate body; 122 is a control gate; 122a is a first control gate; 122b is a second control gate; 123 is a floating gate isolation layer; 130 is a window PN junction structure; 140 is a sidewall parasitic MOS transistor structure; 141 is a drain terminal; 141a is a first drain terminal; 141b is a second drain terminal; 142 is a source terminal; 142a is a first source terminal; 142b is a second source terminal; 150 is a bottom connection structure; 160 is a hard mask layer; 170 is a sacrificial material; and 180 is a window patterning layer. Detailed Implementation

[0023] The technical solution of this application will be described below with reference to the accompanying drawings. The shapes, proportions, and relative dimensions of the structures in the drawings are used to indicate structural relationships and should not be construed as limitations on actual dimensions. Terms such as "first" and "second" in this document are used to distinguish similar objects and do not indicate a necessary order of precedence or importance; directional terms such as "upper," "lower," "side," and "bottom" refer to the directions shown in the accompanying drawings.

[0024] The term "non-volatile memory device" as used herein refers to a semiconductor device that retains information using the charge state of the memory node after the power supply is removed. A non-volatile memory device may include multiple memory cells arranged in an array and peripheral circuitry for applying potential to the memory cells and detecting responses. This application focuses on the semi-floating gate structure within the memory cells and their interconnections; the peripheral circuitry can be implemented using circuitry suitable for driving the corresponding terminals.

[0025] like Figure 1As shown, the non-volatile storage device 10 in the related art may include a plurality of storage cells 101 distributed in an array, with adjacent storage cells 101 separated by an isolation structure 102. Figure 1 (a) shows a top view of the non-volatile storage device 10, where region X0 represents the region where a storage cell 101 is located; Figure 1 (b) shows a partial cross section of the region along the cutting line x0.

[0026] The memory cell 101 may include a semiconductor substrate 110, a semi-floating gate body 121, a control gate 122, and a floating gate isolation layer 123. The semiconductor substrate 110 is the foundation for carrying the semiconductor regions and gate structure of the memory cell, and may include a first doped layer 111 and a second doped layer 112 formed along the stacking direction. The doped layer is a semiconductor region of a predetermined conductivity type obtained by introducing impurities into the semiconductor material; the first doped layer 111 and the second doped layer 112 have different doping types to provide the conductivity type foundation required for adjacent junction regions and gate-controlled semiconductor regions.

[0027] The semi-floating gate body 121 is a semiconductor structure involved in maintaining and storing charge. To achieve charge retention and controlled exchange, the semi-floating gate body 121 should be insulated from the surrounding semiconductor region in non-target contact areas and retain local contact interfaces. The semi-floating gate body 121 can be formed using doped polysilicon. The control gate 122 is a conductive structure that receives a control potential and adjusts the potential state of the adjacent semiconductor region through dielectric coupling; it can be formed using polysilicon or other gate conductive materials.

[0028] The floating gate isolation layer 123 is a dielectric structure disposed between the semi-floating gate body 121 and the surrounding non-target conductive structures. The floating gate isolation layer 123 includes at least a control gate dielectric portion located between the semi-floating gate body 121 and the control gate 122, and a trench isolation portion located in the non-contact window region between the semi-floating gate body 121 and the second doped layer 112. The control gate dielectric portion allows the control gate electric field to couple to the region near the semi-floating gate body 121 while preventing direct conductive contact between the control gate 122 and the semi-floating gate body 121; the trench isolation portion defines the local contact position between the semi-floating gate body 121 and the second doped layer 112.

[0029] The semi-floating gate body 121 contacts the second doped layer 112 at a local opening in the floating gate isolation layer 123. This contact interface forms a window PN junction structure 130 when the conductivity types of the two layers are different. The window PN junction structure 130 is not an additionally manufactured independent entity, but a functional structure formed by the semi-floating gate body 121, the second doped layer 112, and their local contact relationship. Under a corresponding forward bias, the window PN junction structure 130 allows charge carriers to cross the contact interface, while under a cutoff state, it restricts the migration of charge carriers through this interface.

[0030] The drain 141 is a doped region formed in the second doped layer 112, and its conductivity type is different from that of the second doped layer 112. The drain is spaced apart from the semi-floating gate body 121, so that a region of the second doped layer 112 regulated by the control gate 122 is retained between them. The drain 141 can be formed by ion implantation, diffusion or other local doping processes; in a specific implementation where the semi-floating gate body 121 and the drain 141 are P-type doped and the second doped layer 112 is N-type doped, the drain 141 is a P-type doped region formed in the N-type second doped layer 112.

[0031] Similar to drain 141, the non-volatile memory device 10 also includes source 142, with drain 141 and source 142 respectively disposed on opposite sides of the semi-floating gate body 121. Source 142 is typically connected to a reference voltage (e.g., 0V) during device operation. Therefore, its technical mechanism will not be elaborated upon in subsequent descriptions.

[0032] The semi-floating gate body 121, drain 141, second doped layer 112 located between them, floating gate isolation layer 123, and control gate 122 together form a sidewall parasitic MOS transistor structure 140. The sidewall parasitic MOS transistor structure 140 is a functional structure formed by existing physical materials, locations, and electrical relationships, rather than a physical entity generated only under bias. When a control gate bias is applied, the control gate electric field changes the carrier distribution in the region adjacent to the second doped layer 112 between the semi-floating gate body and drain 141, causing the functional structure to be in a conducting or non-conducting state.

[0033] In related technologies, carrier writing and removal can be repeatedly performed via the same half-floating gate body 121 and its adjacent window interface. Thus, the same local interface may repeatedly undergo carrier migration and bias switching during the erase / write cycle.

[0034] In view of the technical considerations of the above-mentioned local interface repeatedly undertaking the process of carrier entry and removal, this application adopts two semi-floating gate bodies to form a storage node, and provides functional structures on both sides that can participate in carrier entry and removal.

[0035] like Figure 2 As shown, the non-volatile storage device 10 may include a plurality of storage cells 101 and an isolation structure 102 located between adjacent storage cells 101. Wherein, Figure 2 The top view in (a) shows two adjacent storage cells 101 and the isolation structure 102 between them; regions X1, X2 and Y1, Y2 are used to indicate different sectioning positions, and the combined identifier X1 (X2) indicates that the two corresponding sections have a structural relationship that can be explained together, respectively corresponding to Figure 2 The cross-sectional positions of (b), (c), and (d) in the middle. That is... Figure 2(a) is a top view, (b) is a cross-sectional view of regions X1 and X2, (c) is a cross-sectional view of region Y1, and (d) is a cross-sectional view of region Y2. Considering the similarity between interfaces X1 and X2, the structures under interface X1 are used as the reference for labeling in the corresponding sub-figures, with the labels on the other side attached in parentheses. Specifically, the suffix 'a' corresponds to the first semi-floating gate structure in region X1, and the suffix 'b' corresponds to the second semi-floating gate structure in region X2; the figure labels without suffixes represent the general reference numerals for the corresponding structures.

[0036] Each memory cell 101 includes a semiconductor substrate 110, a first half-floating gate structure, a second half-floating gate structure, and a bottom connection structure 150. The semiconductor substrate 110 includes a first doped layer 111 and a second doped layer 112. The first half-floating gate structure and the second half-floating gate structure are located on both sides of the isolation structure 102, respectively; the isolation structure 102 maintains the isolation between the two side structures outside the local area through which the bottom connection structure 150 passes.

[0037] Taking the first semi-floating gate structure of the X1 interface as an example, the first semi-floating gate structure includes a first semi-floating gate body 121a, a first control gate 122a, and a floating gate isolation layer 123. Furthermore, the memory cell 101 also includes a drain terminal 141 and a source terminal 142. The first drain terminal 141a and the first source terminal 142a of the first semi-floating gate structure are shown in the X1 interface. The first drain terminal 141a and the first source terminal 142a are respectively disposed in the second doped layers 112 on both sides of the first semi-floating gate body 121a.

[0038] Similarly, in the X2 interface, the second semi-floating gate structure includes a second semi-floating gate body 121b and a second control gate 122b. The storage unit 101 also includes a second drain terminal 141b and a second source terminal 142b disposed on both sides of the second semi-floating gate body 121b.

[0039] The first half-floating gate body 121a and the second half-floating gate body 121b each include an embedded portion embedded in the second doped layer 112 and an extension portion extending to the surface side of the second doped layer 112. The floating gate isolation layer 123 is located between the half-floating gate body and the control gate, and is located in the area between the half-floating gate body and the second doped layer 112 excluding the contact window. The two half-floating gate bodies contact the second doped layer 112 at their respective contact windows, forming window PN junction structures 130 respectively; each half-floating gate body, the corresponding drain terminal, the second doped layer 112 between them, the floating gate isolation layer 123, and the corresponding control gate form a sidewall parasitic MOS transistor structure 140.

[0040] The bottom connection structure 150 is located below the top of the isolation structure 102, passes through a portion of the isolation structure 102, and makes conductive contact with the first semi-floating gate body 121a and the second semi-floating gate body 121b, respectively. The bottom connection structure 150 is a structure used to establish a conductive bridge between the two semi-floating gate bodies inside the isolation structure 102, and can be formed of doped polysilicon or other conductive materials compatible with the semi-floating gate bodies. The bottom connection structure 150, together with the first semi-floating gate body 121a and the second semi-floating gate body 121b, forms a continuously conductive memory node. The memory node is a combination of the above conductive structures and is not a third floating gate entity added outside the two semi-floating gate bodies; therefore, it is not given a separate reference numeral.

[0041] In a write state, a first control gate bias voltage can be applied to the first control gate 122a, a second control gate bias voltage can be applied to the second control gate 122b, and a drain drive voltage can be applied to the first drain terminal 141a. The source terminal 142 (such as the first source terminal 142a and the second source terminal 142b) is grounded or maintained at 0V, which turns on the parasitic MOS transistor structure 140 on the first side and turns off the PN junction structure 130 on both sides. Carriers enter the first semi-floating gate body 121a from the first drain terminal 141a through the parasitic MOS transistor structure 140 on the first side, and are distributed in the memory node through the bottom connection structure 150.

[0042] In an erase state, a third control gate bias voltage can be applied to the first control gate 122a, and a fourth control gate bias voltage can be applied to the second control gate 122b, causing the first drain terminal 141a to receive a drain driving voltage and the second drain terminal 141b to be at a reference potential. As a result, the second side window PN junction structure 130 is forward-biased, and the carriers in the storage node flow out to the second doped layer 112 via the bottom connection structure 150, the second semi-floating gate body 121b, and the second side window PN junction structure 130.

[0043] The first, second, and third control gate bias voltages can have the same polarity, while the third and fourth control gate bias voltages can have opposite polarities. The amplitude of the first control gate bias voltage is greater than that of the second control gate bias voltage, ensuring that the control gate electric field on the write side is sufficient to adjust the second doped layer 112 region between the semi-floating gate body and the drain, thereby turning on the parasitic MOS transistor structure 140 on the first side, while simultaneously preventing the establishment of identical carrier writing conditions on the second side. The amplitude of the first control gate bias voltage is also greater than that of the third control gate bias voltage, enabling the establishment of different gate control conditions on the first side in the write and erase states, respectively. The third and fourth control gate bias voltages have opposite polarities, thus establishing different potential states on both sides in the erase state, allowing the second-side window PN junction structure 130 to conduct forward at the corresponding junction voltage. The above amplitudes are the magnitudes of the absolute values ​​of the corresponding bias voltages. The specific voltage values ​​can be determined based on the conductivity type and device threshold of the semi-floating gate body, the second doped layer 112, and the drain terminal.

[0044] In one specific conductivity type implementation, the first doped layer 111 can be a P-well, the second doped layer 112 can be an N-well, the semi-floating gate body and drain can be P-type doped structures, the sidewall parasitic MOS transistor structure 140 is a sidewall parasitic PMOS transistor structure, and the charge carriers are holes. This implementation is used to specifically illustrate the bias and carrier migration principles; when using complementary conductivity types, the conductivity type, carrier type, and bias polarity can be changed accordingly without changing the structural concept that the two semi-floating gate bodies together form a storage node through the bottom connection structure 150.

[0045] In the specific implementations of the P-well, N-well, and P-type semi-floating gate bodies described above, the first control gate bias voltage, the second control gate bias voltage, and the third control gate bias voltage can be negative control gate bias voltages, and the fourth control gate bias voltage can be a positive control gate bias voltage. The amplitude of the first control gate bias voltage is greater than the amplitude of the second control gate bias voltage and also greater than the amplitude of the third control gate bias voltage. When the first control gate bias voltage turns on the parasitic PMOS transistor structure 140 on the first side, holes, acting as charge carriers, enter the first semi-floating gate body 121a through the first drain 141a and the parasitic PMOS transistor structure 140 on the first side, and are stored in the storage node through the bottom connection structure 150. When the second side window PN junction structure 130 is forward-biased in the erase state, holes in the storage node flow out through the second semi-floating gate body 121b and the second side window PN junction structure 130 to the second doped layer 112 of the N-type. The above-mentioned conductivity type, carrier type, and bias polarity are specific implementations; when using complementary conductivity types, complementary carrier types and bias polarities can be used accordingly.

[0046] In some embodiments, a portion of the isolation structure 102 is located below the bottom connection structure 150, which extends laterally above this portion of the isolation structure 102 and contacts the first semi-floating gate body 121a and the second semi-floating gate body 121b, respectively. The bottom connection structure 150, except for the two areas contacting the first and second semi-floating gate bodies 121a and 121b, is surrounded by an insulating material. The insulating material may include a residual isolation structure located below the bottom connection structure 150 and a dielectric material filling the area above the bottom connection structure 150 and around other non-contact surfaces to collectively form an electrical isolation boundary. This specific isolation method can limit non-targeted conductive contact between the bottom connection structure 150 and the surrounding second doped layer 112 or other conductive structures. In other embodiments, other isolation structures capable of isolating non-targeted contacts while maintaining conductive continuity between the two semi-floating gate bodies may also be employed.

[0047] To illustrate the fabrication process of the aforementioned device in detail, this application also provides a method for fabricating a non-volatile memory device. For example... Figure 3 As shown, the preparation method may include the following steps: S310 provides a semiconductor substrate.

[0048] S320. A hard mask layer is formed on the semiconductor substrate, and the second doped layer on both sides of the isolation structure is etched using the hard mask layer as a mask to form floating gate trenches on both sides of the isolation structure, and an oxidation process is performed to form an oxide layer on the surface of the floating gate trenches.

[0049] S330. Fill the floating gate trench with sacrificial material and etch back the sacrificial material to expose the isolation structure.

[0050] S340, the etched exposed isolation structure is such that the upper surface of the residual isolation structure after etching is located within the second doped layer, and a receiving space communicating with the floating gate trenches on both sides is formed above the residual isolation structure.

[0051] S350. Fill the receiving space with floating grid conductive material and etch back the floating grid conductive material so that a portion of the floating grid conductive material remains in the receiving space and connects the floating grid grooves on both sides to form a bottom connection structure.

[0052] S360. Fill the spacer material above the bottom connection structure and remove the spacer material above the hard mask layer and the sacrificial material so that the spacer material covers the upper surface of the bottom connection structure.

[0053] S370. Remove the hard mask layer and sacrificial material to expose the floating gate trenches on both sides. Form trench isolation portions on the surface of each floating gate trench and fill the floating gate trenches on both sides with a semi-floating gate semiconductor material with a conductivity type different from the second doped layer to form two semi-floating gate bodies respectively.

[0054] S380. Remove a portion of the trench isolation between the two semi-floating gate bodies and the second doped layer to form two openings that expose the second doped layer respectively; fill each opening with a semi-floating gate semiconductor material, such that the semi-floating gate semiconductor material filled in each opening contacts the corresponding semi-floating gate body and the second doped layer respectively, so as to form contact windows between the portions of the two semi-floating gate bodies extending to the surface side of the second doped layer and the second doped layer respectively.

[0055] S390. Control gate dielectric portions are formed on the two semi-floating gate bodies respectively, and control gate material is formed on the two control gate dielectric portions. The control gate material is patterned to form two control gates that are separated from each other, and two drain terminals corresponding to the two semi-floating gate bodies are formed in the second doped layer respectively.

[0056] The following is combined Figures 4 to 15 The above steps are explained sequentially. Each process diagram shows an intermediate state of the corresponding step; multiple diagrams can correspond to the same step to represent the structural changes before and after filling, etching back, pattern transfer, or material removal. Furthermore, multiple sub-diagrams can correspond to the same step: Figures 4 to 15 (a) is a top view of the process, (b) is a cross-sectional view of regions X1 and X2, and (c) is a cross-sectional view of region Y1.

[0057] In step S310, provide Figure 4 The semiconductor substrate 110 is shown. The semiconductor substrate 110 includes a first doped layer 111 and a second doped layer 112, distributed along a bottom-to-top stacking direction and having different doping types, and an isolation structure 102 that at least isolates the second doped layer 112. The stacking direction, as used herein, refers to the thickness direction from the bulk of the semiconductor substrate 110 toward the device formation surface; the first doped layer 111 is located below this direction, and the second doped layer 112 is located above the first doped layer 111. The first doped layer 111 and the second doped layer 112 can be formed by epitaxial growth, ion implantation, diffusion, or a combination thereof. In one embodiment, the first doped layer 111 is a P-type doped layer and the second doped layer 112 is an N-type doped layer; in another complementary embodiment, the first doped layer 111 is an N-type doped layer and the second doped layer 112 is a P-type doped layer. The isolation structure 102 is a dielectric structure formed in the semiconductor substrate 110 to restrict non-targeted conductive connections between adjacent active semiconductor regions; it penetrates at least the portion of the second doped layer 112 that needs to be isolated in the depth direction. The isolation structure 102 can be implemented by filling the trench with insulating material, or by using other isolation structures that can form an insulating boundary between adjacent active regions. Figure 4 In the specific implementation shown, the isolation structure 102 is a shallow trench isolation structure, and the filling material includes silicon dioxide. Figure 4This shows the initial process state after step S310 is completed, and serves as the input structure for step S320 to form the floating gate trench and the oxide layer on the trench surface.

[0058] based on Figure 4 The structure shown is executed in step S320 to obtain... Figure 5 The process state is shown. The hard mask layer 160 is a process aid layer formed on the surface of the semiconductor substrate 110 and provides pattern transfer and etching resistance during the etching of the second doped layer 112. The hard mask layer 160 should have a thickness and mechanical continuity capable of maintaining the floating gate trench opening pattern and etch resistance relative to the second doped layer 112 suitable for the corresponding etching process. The hard mask layer 160 can be formed using silicon nitride, silicon oxide, a composite dielectric layer, or other materials capable of maintaining the pattern during trench etching. Figure 5 In the specific embodiment shown, silicon nitride is deposited on a semiconductor substrate 110, and photolithography and pattern transfer are performed using a floating gate trench photomask to form a patterned silicon nitride hard mask layer 160; the top surface of the formed silicon nitride hard mask layer 160 is higher than the top surface of the isolation structure 102. This relative height allows the hard mask layer 160 to provide a process barrier boundary above the isolation structure 102 during subsequent sacrificial material filling, planarization, and etch-back processes. In other embodiments, the specific thickness and relative height of the hard mask layer 160 can be determined based on the trench etching and subsequent planarization processes employed.

[0059] Using the patterned hard mask layer 160 as a mask, the second doped layers 112 on both sides of the isolation structure 102 are etched to form floating gate trenches on both sides of the isolation structure 102. The floating gate trenches are trench spaces formed in the second doped layer 112 to accommodate subsequent semi-floating gate bodies; their position relative to the isolation structure 102 defines two semi-floating gate bodies located on both sides of the isolation structure 102, and provides a structural entrance for the subsequent formation of a bottom connection space communicating with the trenches on both sides. The floating gate trenches can be formed using anisotropic dry etching or other semiconductor etching processes capable of obtaining the target trench profile. The floating gate trench photomask is used to define the opening pattern of the hard mask layer 160 and is not a device entity remaining on the wafer.

[0060] After forming the floating gate trench, an oxidation process is performed on the trench to form an oxide layer on the inner wall and bottom of the trench. This oxide layer is a dielectric layer covering the semiconductor surface of the floating gate trench, used to provide an insulating boundary between the semi-floating gate body and the second doped layer 112 in the subsequent non-contact window region. The oxide layer can be formed by thermal oxidation, plasma oxidation, or post-deposition oxidation; its material can include silicon dioxide or other oxide media capable of providing the corresponding insulating effect. Figure 5 The diagram shows the process state after the formation of the hard mask layer 160, the floating gate trenches on both sides, and the oxide layer on the surface of the trenches. This state provides the input structure for filling the sacrificial material 170 in step S330.

[0061] In step S330, sacrificial material 170 is filled into the floating gate trenches on both sides. Sacrificial material 170 is a process aid material that temporarily occupies the floating gate trenches, protects the trench surface during subsequent isolation structure etching, and can be removed before forming the semi-floating gate body. Sacrificial material 170 should be able to fill the floating gate trenches and have a material difference relative to the hard mask layer 160 and the isolation structure 102 to be etched, which can be used to control planarization, etch back, and subsequent removal. Sacrificial material 170 can be a carbon-based sacrificial material, a polymer material, or other materials that can be selectively removed after protecting the trenches. Figure 6 In the specific embodiment shown, amorphous carbon, serving as a sacrificial material 170, is filled into the floating gate trench by plasma-enhanced chemical vapor deposition.

[0062] After filling with amorphous carbon, the amorphous carbon is planarized to remove excess material outside the floating gate trenches and obtain a surface for subsequent etchback. Planarization can be performed using chemical mechanical planarization, etchback planarization, or other processes that can reduce surface height differences. The planarized amorphous carbon can cover the top surface of the isolation structure 102 and fill the floating gate trenches on both sides. Subsequently, the sacrificial material 170 is etched back down along the exposed surface of the amorphous carbon to remove the amorphous carbon above the top surface of the isolation structure 102, so that the top surface of the isolation structure 102 is actually exposed to the subsequent etching environment, rather than just making the isolation structure 102 higher than the etched sacrificial material 170 in height. The etchback endpoint simultaneously satisfies the following: the top surface of the isolation structure 102 to be etched is exposed, and the sacrificial material 170 is still retained in the floating gate trenches on both sides. The retained sacrificial material 170 at least covers the bottom of the trench and the corresponding inner wall area that needs to be protected during step S340, but does not cover the portion of the isolation structure 102 to be removed. The term "re-etching" as used in this article refers to the removal process that removes the material downwards from its exposed surface, with the state of the target structure being exposed and the target material remaining as the process endpoint.

[0063] exist Figures 6 to 7 In the specific embodiment shown, amorphous carbon is selectively etched back based on its etch selectivity relative to the silicon nitride hard mask layer 160. Etching selectivity refers to the difference in etching rates between the two materials under the same or related etching conditions; by selecting etching conditions that allow amorphous carbon to be removed at a higher rate than the silicon nitride hard mask layer 160, the pattern boundary provided by the hard mask layer 160 can be maintained while reducing the surface area of ​​the sacrificial material 170. Etching conditions that suppress the removal of the silicon dioxide isolation structure 102 during amorphous carbon etch-back can also be selected, so that the top surface of the isolation structure 102 remains the structure to be etched in the next step after exposure. Figure 6 This shows the state after the sacrificial material 170 has been filled and planarized. Figure 7 This shows the state after the sacrificial material 170 is engraved and the top surface of the isolation structure 102 is actually exposed. Figure 7The state shown provides an input structure for the isolation structure 102 exposed by selective etching in step S340.

[0064] In step S340, etching Figure 7 The top surface of the isolation structure 102 is actually exposed to remove the upper or middle material of the isolation structure 102, leaving the residual isolation structure below it. This etching primarily targets the exposed isolation structure 102 for removal; the sacrificial material 170 and hard mask layer 160 retained in the floating gate trenches on both sides jointly protect the adjacent trench areas. The isolation structure 102 can be removed using wet etching, dry etching, or a combination of both, as long as the etching can advance from the exposed surface of the isolation structure 102 and form a connected material removal area between the floating gate trenches on both sides. In one specific embodiment, wet etching is performed on the silicon dioxide isolation structure 102, and the etching solution may include a solution containing hydrofluoric acid; the wet etching solution enters along the exposed surface of the isolation structure 102 and removes the corresponding isolation material, causing the material removal area to extend towards the floating gate trenches on both sides.

[0065] The etching endpoint of the isolation structure 102 is defined by the resulting structural state: the upper surface of the remaining isolation structure after etching is located within the second doped layer 112, and a receiving space is formed above the remaining isolation structure that communicates with the floating gate trenches on both sides. This endpoint indicates that the isolation structure 102 has not been completely removed, and the remaining portion is still located below the receiving space; at the same time, the receiving space extends laterally to the floating gate trenches on both sides, allowing subsequent filling material to simultaneously enter the central region and reach the trenches on both sides.

[0066] Specifically, Figure 8 This shows the etching input status of step S340. For example... Figure 8 As shown in (c), in the cross section along the Y1 direction, the isolation structure 102 to be partially removed is still located between the sacrificial materials 170 on both sides, with its upper part facing the etching environment, and the sacrificial materials 170 are still retained in the floating gate trenches on both sides. Figure 8 This clarifies the area to be removed from the isolation structure 102 and the protected area of ​​the floating gate trenches on both sides.

[0067] Figure 9 This shows the state of the isolation structure 102 after local etching. For example... Figure 9 As shown in (c), in the cross-section along the Y1 direction, the upper material of the isolation structure 102 has been removed, while its lower part remains as a residual isolation structure; an open area is formed above the residual isolation structure. This open area extends along the target position between the two floating gate grooves in a top view and communicates with the two floating gate grooves, thereby forming a receiving space.

[0068] Figure 10This shows the state after step S340 is completed and the device is ready to receive the floating gate conductive material. At this time, the residual isolation structure is still located below the receiving space, the upper part of the receiving space maintains an opening for material to enter, and it is laterally connected to the floating gate trenches on both sides. Figure 10 The structural relationship shown is Figure 9 The resulting local etching results are consistent. Figure 10 This is further used to indicate that the result has been used as an input for subsequent filling processes; Figure 10 This does not mean that the isolation structure 102 has been completely removed, nor does it mean that the bottom connection structure 150 has been formed.

[0069] The receiving space is a connected space formed by removing a portion of the material from the isolation structure 102, used to receive the bottom connecting material. Its location and communication with the floating gate trenches on both sides allow subsequent floating gate conductive material to enter the central region and laterally reach the floating gate trenches on both sides during the same filling process, forming a material base connecting the two semi-floating gate bodies after etching back. A residual isolation structure remains below the receiving space to provide a lower insulating boundary after the subsequent bottom connecting structure 150 is formed. The output of step S340 should simultaneously include the residual isolation structure located below the receiving space and the receiving space communicating with the floating gate trenches on both sides, and use this structure as the input to step S350.

[0070] In step S350, the accommodating space is filled with a floating gate conductive material. The floating gate conductive material is a material capable of forming a continuous conductive connection between the two semi-floating gate bodies and compatible with the semi-floating gate body material; it can be doped polysilicon, metal, conductive compound, or other conductive materials suitable for integration into a semiconductor trench. Figure 11 In the specific embodiment shown, polysilicon is deposited in the containment space and the inlet regions of the floating gate trenches on both sides connected thereto by chemical vapor deposition, and the deposited polysilicon is planarized. Figure 11 This shows the filling state of polysilicon after it enters the containment space, at which point the sacrificial materials 170 on both sides are still retained in the floating gate trench and define the filling boundary of the conductive material.

[0071] Subsequently, polysilicon is etched back down from the planarized polysilicon surface, leaving a portion of the polysilicon within the accommodating space above the residual isolation structure. The retained polysilicon extends laterally continuously to the contact entrances of the floating gate trenches on both sides, forming contact interfaces at both ends facing the floating gate trenches, thus forming the bottom connection structure 150. The etching endpoint is defined by the bottom connection structure 150 maintaining lateral continuity, its ends being able to contact subsequent semi-floating gate bodies, and a space filled with isolation material forming above it. The bottom connection structure 150 is a bridging structure located inside the isolation structure 102, used to electrically connect the two subsequently formed semi-floating gate bodies; it is supported and isolated below by the residual isolation structure.

[0072] In step S360, isolation material is filled into the isolation material filling space above the bottom connection structure 150. The isolation material is a dielectric material used to cover the non-contact surface of the bottom connection structure 150 and prevent it from making non-target conductive contact with the surrounding semiconductor region. It can be silicon dioxide, silicon nitride, silicon oxynitride, or other insulating materials compatible with adjacent structures. In one specific embodiment, silicon dioxide is filled using chemical vapor deposition, and the silicon dioxide is planarized or etched back to remove excess silicon dioxide located above the hard mask layer 160 and the sacrificial material 170, leaving silicon dioxide above the bottom connection structure 150.

[0073] During the filling of the insulating material, the sacrificial material 170 in the side floating grid trenches occupies the area subsequently forming the semi-floating grid body and shields the two contact interfaces of the bottom connecting structure 150 facing the side floating grid trenches. This allows the backfill insulating material to cover the area above the bottom connecting structure 150 and other non-contact areas without permanently sealing the two contact interfaces. The residual insulating structure and the backfill insulating material located above the bottom connecting structure 150 together constitute the corresponding part of the insulating structure 102: the residual insulating structure provides the lower insulating boundary, and the backfill insulating material restores the upper insulating boundary.

[0074] After step S360 is completed, the bottom connection structure 150 remains above the residual isolation structure, covered by backfill isolation material, and the two contact interfaces facing the floating gate trenches on both sides remain as subsequent conductive contact positions. This structural result of step S360 forms the basis for the subsequent removal of the hard mask layer 160 and the sacrificial material 170, but the hard mask layer 160 and the sacrificial material 170 can still remain on the wafer when S360 is completed.

[0075] In step S370, based on the bottom connection structure 150 and its isolation cover formed in step S360, the hard mask layer 160 and sacrificial material 170 are removed. The hard mask layer 160 can be removed using a wet or dry removal process adapted to the semiconductor substrate 110 and the isolation structure 102; the sacrificial material 170 can be removed using oxidation ashing, wet removal, or other processes capable of removing sacrificial material from the floating gate trenches while retaining the target isolation structure. After removal, the floating gate trenches on both sides are reopened, the bottom connection structure 150 is exposed facing the two contact interfaces of the floating gate trenches on both sides, and the backfill isolation material above the bottom connection structure 150 and the residual isolation structure below it remain in place. Figure 12 This illustrates the intermediate state after the removal of the auxiliary material in step S370, before the semi-floating gate semiconductor material is filled; therefore, Figure 12 It is neither a direct representation of the state of all process materials when step S360 is completed, nor is it the input state before step S370 begins.

[0076] Before filling the semi-floating gate material, trench isolation portions are formed on the surfaces of each floating gate trench, excluding the contact interface of the bottom connection structure 150. The trench isolation portions are dielectric structures located between the semi-floating gate body and the second doped layer 112, preventing direct conductive contact between the two in the non-contact window region. Their formation covers the inner walls and bottom region of the floating gate trench that need to be kept insulated, but does not cover the contact interface of the bottom connection structure 150 facing the corresponding floating gate trench. The trench isolation portions can be achieved by oxidizing the semiconductor surface of the floating gate trench, selectively removing the deposited dielectric, or other processes that can form the aforementioned insulating boundary while keeping the contact interface exposed.

[0077] Subsequently, semi-floating gate semiconductor material is filled into the floating gate trenches on both sides. The semi-floating gate semiconductor material is a doped semiconductor material capable of forming a semi-floating gate body for maintaining and transferring stored charges, and capable of forming a conductive contact with the bottom connection structure 150. Its conductivity type differs from that of the second doped layer 112, and the target conductivity type can be obtained by in-situ doping deposition, post-deposition ion implantation, diffusion, or other doping methods. In one specific embodiment, chemical vapor deposition is used to fill the floating gate trenches on both sides with doped polysilicon, and the filling material is planarized to form... Figure 13 The first semi-floating gate body 121a and the second semi-floating gate body 121b are shown.

[0078] Figure 13 The first semi-floating gate body 121a and the second semi-floating gate body 121b shown occupy the floating gate trenches on both sides of the isolation structure 102, and are in direct contact with the two contact interfaces of the bottom connection structure 150. Thus, the two semi-floating gate bodies are physically separated on both sides of the isolation structure 102, and form a continuous conductive relationship through the bottom connection structure 150; the trench isolation portion is located in the area between each semi-floating gate body and the second doped layer 112, excluding the contact window formed later. Figure 13 This is the output state after the two semi-floating gate bodies are formed in step S370, and also the input state after the contact window is formed in step S380.

[0079] In one specific process, the preceding trench oxide layer can be removed and the oxidation process performed again to form the final trench isolation portion. In other embodiments, the preceding trench oxide layer that meets the final insulation requirements can be retained, or other processes can be used that can form a dielectric on the non-contact surface while keeping the bottom connection contact interface exposed.

[0080] In step S380, the formation positions of the two contact windows are first defined. The contact windows are formed between each semi-floating gate body and the second doped layer 112, and correspond to the region where the semi-floating gate body extends from the embedding portion towards the surface of the second doped layer 112. Position definition can be achieved using photolithography, hard mask pattern transfer, or other microfabrication methods capable of forming localized opening patterns on the trench isolation portion. Figure 14 In the specific embodiment shown, photolithography is performed using a window photomask to form a window patterning layer 180 on the wafer. The window photomask is an external process board that transfers the window pattern to the photoresist; the window patterning layer 180 represents the window patterning layer formed by photolithography and temporarily retained on the wafer, rather than the window photomask itself.

[0081] Figure 14 This illustrates a state where the window patterning layer 180 covers the non-windowed area and exposes two target windowed areas. The window patterning layer 180 provides the graphic boundary for subsequent material removal, but... Figure 14 The trench isolation portion has not yet been removed, and direct contact between the semi-floating gate body and the second doped layer 112 has not yet been formed.

[0082] Based on the two target opening regions defined by the window patterning layer 180, the local trench isolation portion located between the corresponding semi-floating gate body and the second doped layer 112 is removed to form two openings that expose the second doped layer 112. The main target of this removal step is the trench isolation portion, not the semi-floating gate body; the opening boundary is defined by the window patterning layer 180, and the removal endpoint is determined by the actual exposure of the second doped layer 112 at the two target locations. Figure 15 This shows the opening state after the aforementioned partial removal is completed. Figure 15 The opening in the middle is the process space before the semi-floating gate material is backfilled, and is not yet the final contact window where the semi-floating gate body and the second doped layer 112 have come into contact.

[0083] Subsequently, the unnecessary window patterning layer 180 is removed, and each opening is filled with semi-floating gate semiconductor material. The doping type of the filling material is consistent with the corresponding semi-floating gate body, and it is in direct contact with the corresponding semi-floating gate body and the second doped layer 112, respectively. The filling material can be planarized to remove excess material outside the opening and retain the connection portion inside the opening. Thus, the semi-floating gate semiconductor material inside the opening forms a continuous semi-floating gate structure with the original semi-floating gate body, and a contact window is established in the locally exposed area of ​​the second doped layer 112.

[0084] The contact window, as referred to in this article, is the region within the floating gate isolation boundary that allows for local direct contact between the semi-floating gate body and the second doped layer 112, and its conductive connection relationship, rather than a permanently retained via. When the semi-floating gate semiconductor material at the contact window and the second doped layer 112 have different conductivity types, their local contact forms a window PN junction structure 130. Figure 15 This is used to illustrate the intermediate state of the opening before backfilling; the final structure of the contact window after backfilling is formed by the above-described process and Figure 2 The device structures shown are explained together. The backfill completion state is step S390, which forms the control gate dielectric portion and the control gate input structure.

[0085] In step S390, a control gate dielectric portion, a separate control gate, and two drain terminals corresponding to the two semi-floating gate bodies are formed based on the two semi-floating gate bodies with contact windows. In some embodiments, the two semi-floating gate bodies are first thinned. Thinning involves removing a portion of the semiconductor material from the top of the semi-floating gate body to obtain a processing surface for forming the control gate dielectric portion and the control gate material; the thinning endpoint is defined by a structural state in which the charge storage portion of the semi-floating gate body, the bottom connection relationship, and the contact window are intact, while obtaining a surface suitable for forming a control gate stack. Thinning can be achieved using controlled dry etching, wet etching, planarization, or a combination thereof.

[0086] The control gate dielectric portion is a dielectric structure located between the semi-floating gate body and the corresponding control gate, preventing direct conductive contact between the two and allowing the control gate electric field to couple to the adjacent region of the semi-floating gate body. The control gate dielectric portion can be formed using silicon oxide, silicon nitride, silicon oxynitride, high-dielectric-constant materials, or stacks thereof, and can be deposited on the target surface of the semi-floating gate body using oxidation, chemical vapor deposition, atomic layer deposition, or other dielectric formation processes. In one specific embodiment, the silicon oxynitride control gate dielectric portion is formed on the thinned surfaces of both sides of the semi-floating gate body by chemical vapor deposition.

[0087] Subsequently, control gate material is formed on the two control gate dielectric portions. The control gate material is a conductive material used to receive control gate bias and regulate the potential of adjacent semiconductor regions through the control gate dielectric portions; it can be doped polysilicon, metal, conductive compound, or a stack thereof. In one specific embodiment, the control gate polysilicon is formed by chemical vapor deposition and planarized to obtain a material layer for patterning.

[0088] Photolithography is performed using a control gate patterning photomask to form a control gate pattern on the control gate polysilicon. The control gate polysilicon is then etched according to this pattern to form a first control gate 122a and a second control gate 122b that are separated from each other. The control gate patterning photomask can be a poly mask. Separation means that there is no continuous conductive bridge formed by the control gate material between the two control gates, allowing each control gate to receive a control potential independently. This separation does not change the continuous conductive relationship formed by the two semi-floating gate bodies through the bottom connection structure 150. Figures 4 to 15 This section illustrates the main intermediate process states up to the formation of the contact window opening. The control gate dielectric portion and the control gate formed in step S390 are formed by this process and... Figure 2 The final device structure shown is explained together.

[0089] The trench isolation portion and the control gate dielectric portion together constitute the floating gate isolation layer 123. The trench isolation portion is located in the area between the semi-floating gate body and the second doped layer 112, excluding the contact window; the control gate dielectric portion is located between the semi-floating gate body and the corresponding control gate. The trench isolation portion limits the semi-floating gate body to contact the second doped layer 112 only at the contact window, while the control gate dielectric portion forms the insulating coupling boundary between the semi-floating gate body and the control gate. Thus, the floating gate isolation layer 123 does not necessarily have to be a single material layer formed in a single deposition, but can be jointly constituted by dielectric portions formed at different process stages and respectively undertaking the above-mentioned insulating functions.

[0090] Before or after the formation of the control gate, two drain terminals corresponding to the first semi-floating gate body 121a and the second semi-floating gate body 121b are formed in the second doped layer 112 using ion implantation, diffusion, or other terminal formation processes. The conductivity type of the two drain terminals is different from that of the second doped layer 112; each drain terminal is spaced apart from its corresponding semi-floating gate body, leaving a portion of the second doped layer 112 between them. This reserved portion constitutes the semiconductor region in the sidewall parasitic MOS transistor structure 140 that is modulated by the electric field of the corresponding control gate, thereby enabling the fabricated device to possess a sidewall parasitic MOS transistor structure. The drain terminal formation can be coordinated with control gate patterning, sidewall formation, and thermal processing processes, and the specific implantation energy, dose, and thermal processing conditions can be determined according to the device conductivity type and target electrical parameters. Figures 4 to 15 The formation state of the drain is not shown separately. The final location of the drain and its relationship with the semi-floating gate body, the control gate, and the second doped layer 112 are explained in this section's formation process and... Figure 2 The final device structure shown is explained in detail. Without affecting the formation of the two drain terminals mentioned above, source terminals or other conventional terminal areas can also be formed according to the peripheral circuit and readout method.

[0091] Using the above method, two semi-floating gate bodies can be formed on both sides of the isolation structure 102, and conductive connection can be achieved using the bottom connection structure 150 located inside the isolation structure 102; at the same time, the residual isolation structure below the bottom connection structure 150 and the isolation backfill above it maintain the isolation of the non-connection area. This process uses floating gate trenches, sacrificial materials and existing process boundaries to form the bottom connection structure, and in one embodiment, it is not necessary to add a special photomask for the bottom connection structure.

[0092] In summary, the non-volatile storage device and its fabrication method provided in this application can achieve the following technical effects resulting from the synergy of structure and process.

[0093] First, the first semi-floating gate body 121a and the second semi-floating gate body 121b are continuously conductive through the bottom connection structure 150, while the first control gate 122a and the second control gate 122b are separated from each other. Thus, the two semi-floating gate bodies can jointly store the charge state of the same storage node, while the two control gates can still respectively adjust the operating state of the corresponding sidewall parasitic MOS transistor structure 140 or window PN junction structure 130. This structure enables both common charge storage and separate electrical selection to occur simultaneously, which cannot be achieved by simply connecting two floating gates or simply separating two control gates.

[0094] Second, under the corresponding bias state, charge carriers can enter the storage node through the parasitic MOS transistor structure 140 on the first sidewall and exit the storage node through the window PN junction structure 130 on the second side. Writing and erasing are handled by different functional structures on different sides, eliminating the need for the same interface between the semi-floating gate body and the second doped layer 112 at the contact window to repeatedly undergo charge carrier entry and removal processes with different directions and mechanisms. This reduces the need for charge migration to concentrate on the same interface and provides structural and electrical conditions for improving cycle operation reliability and device uptime.

[0095] Third, the bottom connection structure 150 makes lateral conductive contact with the two semi-floating gate bodies, retains a residual isolation structure below it, and covers the area above it and other non-contact areas with backfill isolation material. Thus, the bottom connection structure 150 can establish a continuous conductive bridge within the isolation structure 102, while maintaining insulation from the second doped layer 112 and other non-target conductive structures. This combination achieves both on-side floating gate conduction and electrical isolation between non-connection areas within a compact isolation structure, reducing the possibility of non-target leakage, short circuits, or interference with the independent control of both sides due to the introduction of the bottom connection.

[0096] Fourth, in the specific embodiment employing a silicon nitride hard mask layer 160, amorphous carbon sacrificial material 170, and silicon dioxide isolation structure 102, selective etching back of amorphous carbon relative to the silicon nitride hard mask layer 160 exposes the surface to be etched on the silicon dioxide isolation structure 102. Subsequently, the exposed silicon dioxide isolation structure 102 is selectively etched to form a receiving space communicating with the floating gate trenches on both sides. The existing hard mask pattern, the protective boundary of the amorphous carbon after etching back, and the exposed area of ​​the silicon dioxide isolation structure 102 together define the receiving space. After the bottom connection structure 150 is formed, its upper insulating boundary is restored by backfilling with the isolation material. Thus, this specific embodiment does not require adding a dedicated photomask for the bottom connection structure 150 and can reduce the process and overlay burden caused by adding a dedicated photomask while introducing common memory connections.

[0097] The above embodiments are used to illustrate the structure, principle, and fabrication process of this application, and are not intended to exhaust all embodiments. Under the condition that the two semi-floating gate bodies are electrically connected through the bottom connection structure, and the non-contact area of ​​the bottom connection structure is insulated and can form a contact window and a separation control gate, the doping concentration, material, etching system, deposition method, and process parameters can be adjusted according to the device conductivity type and integration process. The specific materials and process steps listed herein are only one embodiment of the corresponding technical function; other materials or processes capable of achieving the same technical function can also be used.

Claims

1. A non-volatile memory device, comprising a semiconductor substrate and a plurality of memory cells formed on said semiconductor substrate, characterized in that, Within the memory cell, the semiconductor substrate has a first doped layer and a second doped layer with different doping types formed along a bottom-to-top stacking direction. The memory cell includes: An isolation structure disposed within the semiconductor substrate and at least isolating the second doped layer; The first semi-floating gate structure and the second semi-floating gate structure are respectively disposed on both sides of the isolation structure; and A bottom connection structure is located below the top of the isolation structure, passes through a portion of the isolation structure, and makes conductive contact with the semi-floating gate body of the first semi-floating gate structure and the semi-floating gate body of the second semi-floating gate structure, respectively; wherein, the isolation structure isolates the first semi-floating gate structure and the second semi-floating gate structure outside the area through which the bottom connection structure passes. Both the first and second semi-floating gate structures include a semi-floating gate body, a control gate, and a floating gate isolation layer. The semi-floating gate body includes an embedded portion embedded in the second doped layer and an extension portion extending from the embedded portion to the surface of the second doped layer. The control gate is disposed above the extension portion. The floating gate isolation layer is disposed between the semi-floating gate body and the control gate, and in the area between the semi-floating gate body and the second doped layer excluding the contact window. The conductivity types of the semi-floating gate body and the drain terminal are different from the conductivity type of the second doped layer. The drain terminal is formed in the second doped layer and spaced apart from the semi-floating gate body. The contact window is located between the extension and the second doped layer. The semi-floating gate body contacts the second doped layer at the contact window to form a window PN junction structure. The semi-floating gate body, the drain terminal, the second doped layer located between them, the floating gate isolation layer, and the control gate are configured to form a sidewall parasitic MOS transistor structure. The first semi-floating gate structure and the second semi-floating gate structure together form a continuously conductive memory node through the bottom connection structure.

2. The non-volatile storage device according to claim 1, characterized in that, In the write state, the sidewall parasitic MOS transistor structure of the first half-floating gate structure is turned on, and the window PN junction structures of the first half-floating gate structure and the second half-floating gate structure are both turned off, so that the charge carriers enter the half-floating gate body of the first half-floating gate structure from the drain terminal of the first half-floating gate structure through the sidewall parasitic MOS transistor structure of the first half-floating gate structure, and are stored in the storage node through the bottom connection structure. In the erase state, the window PN junction structure of the second half-floating gate structure is forward-biased, so that the charge carriers stored in the storage node flow out to the second doped layer through the bottom connection structure, the half-floating gate body of the second half-floating gate structure and the window PN junction structure of the second half-floating gate structure.

3. The non-volatile storage device according to claim 2, characterized in that, The first doped layer is a P-well, the second doped layer is an N-well, the semi-floating gate body and the drain are both P-type doped structures, making the sidewall parasitic MOS transistor structure a sidewall parasitic PMOS transistor structure, and the charge carrier is a hole.

4. The non-volatile storage device according to claim 1, characterized in that, A portion of the isolation structure is located below the bottom connection structure, and the bottom connection structure extends laterally above this portion of the isolation structure and respectively contacts the semi-floating grid body of the first semi-floating grid structure and the semi-floating grid body of the second semi-floating grid structure. The bottom connection structure, except for the area in contact with the semi-floating gate body of the first semi-floating gate structure and the semi-floating gate body of the second semi-floating gate structure, is surrounded by insulating material.

5. A method for fabricating a non-volatile storage device, characterized in that, The method for fabricating the non-volatile storage device of claim 1 includes: A semiconductor substrate is provided, the semiconductor substrate including a first doped layer and a second doped layer having different doping types distributed along a bottom-to-top stacking direction, and an isolation structure that at least isolates the second doped layer; A hard mask layer is formed on the semiconductor substrate, and the second doped layer on both sides of the isolation structure is etched using the hard mask layer as a mask to form floating gate trenches on both sides of the isolation structure, and an oxidation process is performed to form an oxide layer on the surface of the floating gate trenches. Sacrificial material is filled into the floating gate trench, and the sacrificial material is etched back to expose the isolation structure; The etched exposed isolation structure is such that the upper surface of the residual isolation structure after etching is located within the second doped layer, and a receiving space communicating with the floating gate trenches on both sides is formed above the residual isolation structure; The space is filled with floating grid conductive material, and the floating grid conductive material is etched back, so that a portion of the floating grid conductive material remains in the space and connects the floating grid grooves on both sides to form a bottom connection structure. An isolation material is filled above the bottom connection structure, and the isolation material located above the hard mask layer and the sacrificial material is removed, so that the isolation material covers the upper surface of the bottom connection structure; wherein, the residual isolation structure and the isolation material covering the bottom connection structure together constitute the isolation structure; Remove the hard mask layer and the sacrificial material to expose the floating gate trenches on both sides, and form a trench isolation portion on the surface of each floating gate trench, so that the two contact interfaces of the bottom connection structure facing the floating gate trenches on both sides are exposed relative to the trench isolation portion; The floating gate trenches on both sides are filled with a semi-floating gate semiconductor material with a conductivity type different from that of the second doped layer to form two semi-floating gate bodies respectively, so that the two semi-floating gate bodies are in conductive contact with the two contact interfaces of the bottom connection structure respectively, and the trench isolation portion is located in the area between each semi-floating gate body and the second doped layer, excluding the contact window formed later. Remove a portion of the trench isolation between the two semi-floating gate bodies and the second doped layer to form two openings that expose the second doped layer respectively; fill each opening with the semi-floating gate semiconductor material such that the semi-floating gate semiconductor material filled in each opening contacts the corresponding semi-floating gate body and the second doped layer respectively, so as to form contact windows between the portions of the two semi-floating gate bodies extending to the surface side of the second doped layer and the second doped layer respectively; Control gate dielectric portions are formed on the two semi-floating gate bodies respectively, and control gate material is formed on the two control gate dielectric portions. The control gate material is patterned to form two control gates that are separated from each other, and two drain terminals corresponding to the two semi-floating gate bodies are formed in the second doped layer respectively; wherein, the trench isolation portion and the control gate dielectric portion together constitute the floating gate isolation layer.

6. The preparation method according to claim 5, characterized in that, The hard mask layer is a silicon nitride hard mask layer, and the top surface of the hard mask layer is higher than the top surface of the isolation structure; Forming the hard mask layer on the semiconductor substrate includes: depositing silicon nitride on the semiconductor substrate; Forming the floating gate trench includes: performing photolithography using a floating gate trench photomask to pattern the hard mask layer, and using the patterned hard mask layer as a mask to etch the second doped layers on both sides of the isolation structure; Forming the oxide layer on the surface of the floating grid trench includes: oxidizing the floating grid trench so that the inner wall and bottom of the floating grid trench are covered with the oxide layer.

7. The preparation method according to claim 5, characterized in that, Forming the contact window includes: Photolithography is performed using a windowed photomask to define the formation positions of the two openings; Based on the pattern formed by photolithography, a portion of the trench isolation portion between the two semi-floating gate bodies and the second doped layer is removed to form two openings that expose the second doped layer respectively; The semi-floating gate semiconductor material is filled into each of the openings, and the semi-floating gate semiconductor material is planarized so that the semi-floating gate semiconductor material filled into each of the openings contacts the corresponding semi-floating gate body and the second doped layer.

8. The preparation method according to claim 6, characterized in that, The sacrificial material is amorphous carbon; Filling the sacrificial material in the floating gate trench includes: filling the amorphous carbon in the floating gate trench by plasma-enhanced chemical vapor deposition, and planarizing the amorphous carbon; The sacrificial material is etched back, based on the etch selectivity of the amorphous carbon relative to the hard mask layer, to expose the isolation structure.

9. The preparation method according to claim 8, characterized in that, The etched-exposed isolation structure includes: The exposed isolation structure is wet-etched to form the receiving space above the residual isolation structure, which communicates with the floating gate trenches on both sides; The process of filling the receiving space with floating gate conductive material and etching back the floating gate conductive material includes: filling the receiving space with polysilicon, planarizing the polysilicon, and etching back the planarized polysilicon, so that the remaining polysilicon connects the floating gate trenches on both sides in the receiving space to form the bottom connection structure, and forming an isolation material filling space above the bottom connection structure. Filling the space above the bottom connection structure with an insulating material includes: filling the space above the insulating material with silicon dioxide and planarizing the silicon dioxide to remove the silicon dioxide located above the hard mask layer and the sacrificial material, so that the silicon dioxide remains above the bottom connection structure.

10. The preparation method according to claim 5, characterized in that, The two control gates that are separated from each other include: The two semi-floating gate bodies on which the contact windows are formed are thinned; Silicon oxynitride control gate dielectric portions are formed on the surfaces of the two thinned semi-floating gate bodies by chemical vapor deposition. Polysilicon control gate is deposited on the dielectric portion of the silicon oxynitride control gate by chemical vapor deposition, and the polysilicon control gate is planarized. Photolithography is performed using a control gate patterning mask, and the retained control gate polysilicon is etched to form two control gates that are separated from each other.

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