Embedded flash memory device and method of manufacturing the same

Abstract

This application provides an embedded flash memory device and its fabrication method. In the embedded flash memory device fabrication method, the semiconductor substrate includes a memory region and a logic region. A gate stack structure and a polysilicon layer are formed on the semiconductor substrate. The gate stack structure is formed on the memory region. The polysilicon layer at the boundary between the memory region and the logic region has a stepped morphology. First, a first photolithography process is performed to form a first mask layer. The first mask layer on the memory region has a first opening. Then, a first etching process is performed to etch the polysilicon layer of the memory region. Next, a second photolithography process is performed to form a second mask layer. The second mask layer fills the first opening. The second mask layer on the logic region has a second opening. Then, a second etching process is performed to etch the polysilicon layer of the logic region. This reduces the influence of the stepped morphology of the polysilicon layer on the etching process and helps to improve product yield.

Description

Technical Field

[0001] This application relates to the field of integrated circuit manufacturing technology, and in particular to an embedded flash memory device and its fabrication method. Background Technology

[0002] Embedded flash memory (eflash) is characterized by its ability to retain stored information for extended periods without power, and it boasts advantages such as high integration, fast access speeds, and ease of erasure and rewriting. Consequently, it has found widespread application in microcomputers, automation control, and many other fields. Embedded flash memory comprises a storage area (flash) and a logic area (logic). A height difference exists between the storage and logic areas after the deposition of the polysilicon thin film. This step difference poses a significant challenge to subsequent photolithography and etching processes, impacting product yield. Summary of the Invention

[0003] This application provides an embedded flash memory device and its fabrication method to address the adverse effects of the height difference of the polysilicon thin film between the storage area and the logic area on product yield.

[0004] This application provides a method for fabricating an embedded flash memory device, including:

[0005] A semiconductor substrate is provided, the semiconductor substrate including a memory region and a logic region, a gate stack structure and a polysilicon layer are formed on the semiconductor substrate, the gate stack structure is formed on the memory region, and the polysilicon layer at the boundary between the memory region and the logic region has a stepped morphology;

[0006] A first photolithography process is performed to form a first mask layer on the storage region and the logic region, wherein the first mask layer on the storage region has a first opening;

[0007] Perform a first etching process, using the first mask layer as a mask, to etch the polysilicon layer of the storage region along the depth direction of the first opening;

[0008] Remove the first mask layer;

[0009] A second photolithography process is performed to form a second mask layer on the storage area and the logic area, the second mask layer filling the first opening, and the second mask layer on the logic area having a second opening;

[0010] Perform a second etching process, using the second mask layer as a mask, to etch the polysilicon layer of the logic region along the depth direction of the second opening; and,

[0011] Remove the second mask layer.

[0012] Furthermore, the first photolithography process includes:

[0013] A first mask layer is formed, the first mask layer covering the storage area and the logic area; and

[0014] Perform a first exposure and development process to form a first opening in the first mask layer of the storage area.

[0015] Furthermore, in the method for fabricating an embedded flash memory device, the second photolithography process includes:

[0016] A second mask layer is formed, which covers the storage area and the logic area and fills the first opening; and a second exposure and development process is performed to form a second opening in the second mask layer of the logic area.

[0017] Furthermore, in the method for fabricating an embedded flash memory device, the thickness of the polysilicon layer on the storage region is 1000Å~1200Å, the thickness of the polysilicon layer on the logic region is 700Å~900Å, and the height difference of the polysilicon layer at the boundary between the storage region and the logic region is 100Å~500Å.

[0018] Furthermore, in the fabrication method of the embedded flash memory device, both the first mask layer and the second mask layer are photoresist layers, and the thickness of the photoresist layer ranges from 2600 Å to 2800 Å.

[0019] Furthermore, in the method for fabricating embedded flash memory devices, the first etching process is a wet etching process.

[0020] Furthermore, in the method for fabricating embedded flash memory devices, the second etching process is a wet etching process.

[0021] Furthermore, in the fabrication method of the embedded flash memory device, the gate stack structure includes a floating gate layer, a gate dielectric layer, a control gate layer, an isolation layer, and a hard mask layer stacked sequentially.

[0022] Furthermore, in the method for fabricating an embedded flash memory device, after performing a first etching process, word lines and erase gates are formed on the storage area.

[0023] This application also provides an embedded flash memory device, which is fabricated using the method described in any one of the above-mentioned embedded flash memory devices.

[0024] In the technical solution provided in this application, the semiconductor substrate includes a memory region and a logic region. A gate stack structure is formed on the memory region. The polysilicon layer at the junction of the memory region and the logic region has a stepped morphology. The polysilicon layer of the memory region is first etched by a first photolithography process and a first etching process, and then the polysilicon layer of the logic region is etched by a second photolithography process and a second etching process. This reduces the influence of the stepped morphology of the polysilicon layer on the etching process. In this improved fabrication process, the polysilicon layer is etched in sections to obtain the final polysilicon pattern, which solves the influence of the polysilicon steps on the etching process and improves the etching process window, which is beneficial to improving product yield. Attached Figure Description

[0025] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic flowchart illustrating a method for fabricating an embedded flash memory device according to an embodiment of this application.

[0027] Figure 2 This is a cross-sectional schematic diagram of step S101 in the method for fabricating the embedded flash memory device provided in the embodiments of this application;

[0028] Figures 3A-3B This is a cross-sectional schematic diagram of step S102 in the method for fabricating the embedded flash memory device provided in the embodiments of this application;

[0029] Figure 4 This is a cross-sectional schematic diagram of step S103 in the method for fabricating the embedded flash memory device provided in the embodiments of this application;

[0030] Figure 5 This is a cross-sectional schematic diagram of step S104 in the method for fabricating the embedded flash memory device provided in the embodiments of this application;

[0031] Figures 6A-6B This is a cross-sectional schematic diagram of step S105 in the method for fabricating the embedded flash memory device provided in the embodiments of this application;

[0032] Figure 7 This is a cross-sectional schematic diagram of step S106 in the method for fabricating an embedded flash memory device provided in the embodiments of this application;

[0033] Figure 8This is a cross-sectional schematic diagram of step S107 in the method for fabricating an embedded flash memory device provided in the embodiments of this application.

[0034] Explanation of icon numbers:

[0035] 100 - Semiconductor substrate, 101 - Memory region, 102 - Logic region, 1011 - First shallow trench isolation structure, 1021 - Second shallow trench isolation structure, 200 - First dielectric layer, 300 - Gate stack structure, 301 - Floating gate layer, 302 - Gate dielectric layer, 303 - Control gate layer, 304 - Isolation layer, 305 - Hard mask layer, 306 - First sidewall, 307 - Second sidewall, 308 - Third sidewall, 400 - Polysilicon layer, 401 - Step morphology, 500 - Second dielectric layer, 600 - First mask layer, A - First opening, 700 - Second mask layer, B - Second opening. Detailed Implementation

[0036] In the photolithography and etching processes of embedded flash memory devices, a height difference (steps) exists between the memory and logic regions after the deposition of polysilicon thin films. If photolithography and etching are performed simultaneously on the polysilicon layers in both regions, the polysilicon layer at the step between the memory and logic regions is prone to problems such as light reflection, focusing deviation, and uneven etching rates. This can easily lead to poor linewidth control, abnormal sidewall angles, and even defects such as polysilicon residue or bridging in the logic region's polysilicon layer. Such defects not only severely compress the etching process window but also affect the consistency and yield of the device's electrical parameters. To avoid these defects, the inventors have attempted to use chemical mechanical polishing (CMP) to planarize the polysilicon layer to eliminate the height difference between the memory and logic regions and to adjust etching parameters to alleviate the step morphology problem. However, these improvements not only increase process complexity and cost but also fail to fundamentally solve the etching selectivity and process window problems caused by the steps.

[0037] Based on the above research, this application provides an embedded flash memory device and its fabrication method. First, a first photolithography process and a first etching process are performed to etch the polysilicon layer of the memory region. Then, a second photolithography process and a second etching process are performed to etch the polysilicon layer of the logic region. This reduces the influence of the step morphology of the polysilicon layer on the etching process. In this improved fabrication process, the polysilicon layer is etched in sections to obtain the final polysilicon pattern. This solves the problem of the influence of polysilicon steps on the etching process and improves the etching process window, which is beneficial to improving product yield.

[0038] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0039] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, used as they are, may be substituted where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, some of the described steps may be omitted and / or some other steps not described herein may be added to the method. Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being “on” a substrate, layer (or film), region, and / or pattern, it may be directly located on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being “under” another layer, it may be directly located under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to “on” and “under” layers may be made based on the accompanying drawings.

[0040] Figure 1 This is a schematic flowchart illustrating the fabrication method of the embedded flash memory device provided in this application embodiment. Please refer to the appendix. Figure 1 The method for fabricating an embedded flash memory device provided in this application includes:

[0041] S101: A semiconductor substrate is provided, the semiconductor substrate including a memory region and a logic region, a gate stack structure and a polysilicon layer are formed on the semiconductor substrate, the gate stack structure is formed on the memory region, and the polysilicon layer at the junction of the memory region and the logic region has a stepped morphology.

[0042] S102: Perform a first photolithography process to form a first mask layer on the storage area and the logic area, wherein the first mask layer on the storage area has a first opening;

[0043] S103: Perform the first etching process, using the first mask layer as a mask, and etch the polysilicon layer of the storage region along the depth direction of the first opening;

[0044] S104: Remove the first mask layer;

[0045] S105: Perform a second photolithography process to form a second mask layer on the storage area and the logic area. The second mask layer fills the first opening, and the second mask layer on the logic area has a second opening.

[0046] S106: Perform the second etching process, using the second mask layer as a mask, and etch the polysilicon layer of the logic region along the depth direction of the second opening;

[0047] S107: Remove the second mask layer.

[0048] In this improved fabrication process, the polysilicon layer is etched in sections to obtain the final polysilicon pattern. This solves the problem of the influence of polysilicon steps on the etching process and improves the etching process window, which is beneficial to improving product yield.

[0049] The following will describe in more detail the method for fabricating the embedded flash memory device according to the embodiments of this application, with reference to the accompanying drawings.

[0050] First, execute step S101, such as... Figure 2 As shown, a semiconductor substrate 100 is provided, which includes a memory region (flash) 101 and a logic region (logic) 102.

[0051] The semiconductor substrate 100 can be one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. It can also be gallium arsenide, gallium silicon compound, etc. Furthermore, it can have a silicon-on-insulator (SMI) or silicon-on-epitaxy (SEE) structure. Other semiconductor materials can also be used, but are not listed here. The semiconductor substrate 100 can be formed with corresponding components according to device requirements. Preferably, the semiconductor substrate 100 is a p-type silicon substrate (p-sub).

[0052] A plurality of first shallow trench isolation structures 1011 are formed in the storage region 101. A plurality of second shallow trench isolation structures 1021 are formed in the logic region 102. The materials of the first shallow trench isolation structures 1011 and the second shallow trench isolation structures 1021 can both be silicon oxide. In one embodiment, the top surface of the first shallow trench isolation structure 1011 in the storage region 101 is higher than the surface of the semiconductor substrate 100 (protruding from the surface of the semiconductor substrate 100), the top surface of the second shallow trench isolation structure 1021 in the logic region 102 is higher than the surface of the semiconductor substrate 100, and the height of the top surface of the second shallow trench isolation structure 1021 is higher than the height of the top surface of the first shallow trench isolation structure 1011.

[0053] A gate stack structure 300 and a polysilicon layer 400 are formed on a semiconductor substrate 100. The gate stack structure 300 is formed above a memory region 101, and the polysilicon layer 400 is formed above both the memory region (flash) 101 and the logic region (logic) 102. The polysilicon layer 400 covers the semiconductor substrate 100 and the gate stack structure 300. The polysilicon layer on the memory region 101 is subsequently used to form word lines (WL) and erase gates (EG).

[0054] like Figure 2 As shown, the polysilicon layer 400 at the boundary (i.e., adjacent area) between storage region 101 and logic region 102 has a stepped morphology 401. The thickness H1 of the polysilicon layer on storage region 101 is, for example, 1000 Å to 1200 Å, and the thickness H2 of the polysilicon layer on logic region 102 is, for example, 700 Å to 900 Å. Therefore, the polysilicon layer at the boundary (adjacent area) between storage region 101 and logic region 102 has a height difference, which is, for example, 100 Å to 500 Å. In this embodiment, the thickness H1 of the polysilicon layer on storage region 101 is, for example, 1100 Å, and the thickness H2 of the polysilicon layer on logic region 102 is, for example, 800 Å, thus the height difference at the boundary between storage region 101 and logic region 102 is 300 Å.

[0055] Optionally, a first dielectric layer 200 is formed on the semiconductor substrate 100, and a polysilicon layer 400 covers the surface of the first dielectric layer 200 and the gate stack structure 300. Specifically, the first dielectric layer 200 can be formed by thermal oxidation, chemical vapor deposition (CVD), or oxynitriding processes. The first dielectric layer 200 may include dielectric materials such as SiO2, SiON, SiON2, and other similar oxides including perovskite oxides. In this embodiment, the material of the first dielectric layer 200 is preferably silicon oxide, and the formation method is preferably thermal oxidation.

[0056] like Figure 2 As shown, the gate stack structure 300 includes a floating gate layer (FG) 301, a gate dielectric layer 302, a control gate layer (CG) 303, an isolation layer 304, and a hard mask layer 305 stacked sequentially. The floating gate layer 301 is formed on the first dielectric layer 200, for example, to store charge. The gate dielectric layer 302 is formed on the floating gate layer 301. The control gate layer 303 is formed on the gate dielectric layer 302, for example, to control data access. The isolation layer 304 is formed on the control gate layer 303. The hard mask layer 305 is formed on the isolation layer 304. The gate dielectric layer 302 is, for example, an ONO structure; specifically, the ONO structure is a stack of silicon oxide layers, silicon nitride layers, and silicon oxide layers. The isolation layer 304 is, for example, silicon oxide. The hard mask layer 305 is, for example, silicon nitride.

[0057] In a preferred embodiment, the lateral width of the floating gate layer (FG) 301 is greater than the lateral width of the control gate layer (CG) 303, in order to increase the coupling area of ​​the floating gate layer 301 and improve coupling efficiency and programming speed. The materials of both the floating gate layer 301 and the control gate layer 303 are, for example, polysilicon.

[0058] The gate stack structure 300 may further include a first sidewall 306, which is located on the top surface and sidewalls of the floating gate layer 301, the sidewalls of the gate dielectric layer 302, the sidewalls of the control gate layer 303, the sidewalls of the isolation layer 304, and the sidewalls of the hard mask layer 305. The material of the first sidewall 306 is, for example, silicon oxide. Further, the gate stack structure 300 also includes a second sidewall 307, which is located outside the first sidewall 306 and on the sidewalls of the control gate layer 303, the isolation layer 304, and the hard mask layer 305. The material of the second sidewall 307 is, for example, silicon nitride. Further, the gate stack structure 300 also includes a third sidewall 308, which is located on the second sidewall 307 on the sidewalls of the control gate layer 303, the isolation layer 304, and the hard mask layer 305. The material of the third sidewall 308 is, for example, silicon oxide.

[0059] In one embodiment, a second dielectric layer 500 is further formed on the semiconductor substrate 100, the second dielectric layer 500 covering the polysilicon layer 400. The material of the second dielectric layer 500 is, for example, silicon oxide.

[0060] Next, proceed to step S102, as shown in the appendix. Figures 3A-3B A first photolithography process is performed to form a first mask layer 600 on the memory region 101 and the logic region 102. The first mask layer 600 on the memory region 101 has a first opening A. The position of the first opening is determined by the pattern of the corresponding mask, which corresponds to the area of ​​the memory region where polysilicon needs to be etched away. This method is a well-known design technique in photolithography processes in the art.

[0061] As an example, the first mask layer 600 is, for instance, a photoresist layer formed using a spin-coating process. The thickness of the photoresist layer ranges from 2600 Å to 2800 Å.

[0062] The first photolithography process includes: such as Figure 3A As shown, a first mask layer 600 is formed, which covers the storage area 101 and the logic area 102; as Figure 3B As shown, a first exposure and development process is performed to form a first opening A in the first mask layer 600 of the storage area 101. Further, a first mask is used to perform the first exposure and development process. The exposure pattern of the first mask corresponds to the storage area 101.

[0063] Next, proceed to step S103, as shown in the appendix. Figure 4 The first etching process is performed, using the first mask layer 600 as a mask, to etch the polysilicon layer 400 of the storage region 101 along the depth direction of the first opening A.

[0064] As an example, the first etching process employs a wet etching process. Wet etching processes can use a mixed acid solution based on hydrofluoric acid (HF) and nitric acid (HNO3), or an alkaline solution (such as KOH, TMAH).

[0065] In another embodiment, the first etching process can also be dry etching. The parameters of the first dry etching process include, for example, etching silicon oxide with a fluorocarbon-based gas (such as CHF3, CF4), and then etching the polysilicon layer 400 with a chlorine-based (such as Cl2) or bromine-based (such as HBr). The purpose of performing the first etching process is to form word lines (WL) and erase gates (EG) on the memory region 101.

[0066] Next, proceed to step S104, as shown in the appendix. Figure 5 The first mask layer 600 is removed to obtain the polysilicon pattern of the memory area 101, forming the floating gate (FG), control gate (CG), erase gate (EG) and word line (WL).

[0067] For example, an ashing process can be used to remove the first mask layer.

[0068] Next, proceed to step S105, referring to the appendix. Figures 6A-6B A second photolithography process is performed to form a second mask layer 700 on the memory region 101 and the logic region 102. The second mask layer 700 fills the first opening A. After the second photolithography process, the second mask layer 700 on the logic region 102 has a second opening B. The position of the second opening is determined by the pattern of the corresponding mask, which corresponds to the area of ​​the logic region where polysilicon needs to be etched away. This method is a well-known design technique in photolithography.

[0069] As an example, the second mask layer 700 is, for instance, a photoresist layer formed using a spin-coating process. The thickness of the photoresist layer ranges from 2600 Å to 2800 Å. Further, the second mask layer 700, being a photoresist layer, completely covers and protects the word lines already formed in the memory region and erases the gate polysilicon pattern after spin-coating. Subsequent removal of the second mask layer employs an oxygen plasma ashing process. By optimizing the ashing power and time parameters, the photoresist filling the first opening and the surface photoresist can be completely removed together without significantly damaging the polysilicon pattern in the memory region. This is a photoresist removal process well-known in the art.

[0070] To further explain, after the first etching completes the polysilicon pattern of the storage region, a new trench step will be formed; the second photolithography process of this application spin-coates to form a second mask layer, which fills the first opening and flattens the trench step, making the upper surface of the photoresist exposed by the second photolithography tend to be flat, thereby suppressing the adverse effects of the new step morphology on the focusing and light reflection of the second photolithography exposure, and achieving the suppression of the new step problem.

[0071] The second photolithography process includes: such as Figure 6A As shown, a second mask layer 700 is first formed, which covers the storage area 101 and the logic area 102, and fills the first opening A; as shown Figure 6B As shown, a second exposure and development process is then performed to form a second opening B in the second mask layer 700 of the logic region 102. Further, a second mask is used to perform the second exposure and development process. The exposure pattern of the second mask is located in the logic region 102.

[0072] Next, proceed to step S106, as shown in the appendix. Figure 7 A second etching process is then performed, using the second mask layer 700 as a mask to etch the polysilicon layer 400 of the logic region 102 along the depth direction of the second opening B. This step transfers the second opening B on the second mask layer 700 to the polysilicon layer 400 of the logic region 102.

[0073] As an example, the second etching process employs a wet etching process. The wet etching process can use a mixed solution based on hydrofluoric acid (HF) and nitric acid (HNO3), or an alkaline solution (such as KOH or TMAH). When the second etching uses wet etching, the photoresist mask exhibits high selectivity for the polysilicon wet etching solution, preventing the etchant from acting on the storage area; after etching, standard wafer cleaning is used to remove residual solution, a process configuration known in the art.

[0074] In another embodiment, the second etching process is dry etching. The second dry etching includes, for example, etching silicon oxide with a fluorocarbon-based gas (CHF3 / CF4) and then etching the polysilicon layer 400 with a chlorine / bromine-based gas (Cl2 / HBr). When the second etching is dry etching, the thickness of the second mask photoresist in this application is set to 2600 Å to 2800 Å, which is sufficient to offset the photoresist consumption during the dry etching process. Simultaneously, a hard mask layer is provided on the gate stack structure of the memory region to further isolate the etching gas and suppress lateral erosion of the polysilicon in the memory region. This method is a process configuration known in the art.

[0075] After performing the second etching process, the polysilicon layer 400 on the logic region 102 is used, for example, to fabricate the device structure (e.g., a CMOS transistor) required for the logic region of the embedded flash memory.

[0076] Next, proceed to step S107, as shown in the appendix. Figure 8 The second mask layer is then removed, thus forming the polysilicon pattern required for logic region 102. In this embodiment, an ashing process can be used to remove the second mask layer.

[0077] In summary, the technical solution provided in this application involves forming a gate stack structure and a polysilicon layer on a semiconductor substrate. The gate stack structure is formed on a memory region, and the polysilicon layer at the boundary between the memory region and the logic region has a stepped morphology. A first photolithography process is then performed to form a first mask layer on the memory region and the logic region. The first mask layer on the memory region has a first opening. A first etching process is then performed, using the first mask layer as a mask, to etch the polysilicon layer of the memory region along the depth direction of the first opening. The first mask layer is then removed. A second photolithography process is then performed to form a second mask layer on the memory region and the logic region. The second mask layer fills the first opening, and the second mask layer on the logic region has a second opening. A second etching process is then performed, using the second mask layer as a mask, to etch the polysilicon layer of the logic region along the depth direction of the second opening. Finally, the second mask layer is removed. This improved fabrication process obtains the final polysilicon pattern by etching the polysilicon layer in sections, which solves the problem of polysilicon steps affecting the etching process and improves the etching process window, thus improving product yield.

[0078] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A method for fabricating an embedded flash memory device, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a memory region and a logic region, a gate stack structure and a polysilicon layer are formed on the semiconductor substrate, the gate stack structure is formed on the memory region, and the polysilicon layer at the boundary between the memory region and the logic region has a stepped morphology; A first photolithography process is performed to form a first mask layer on the storage region and the logic region, wherein the first mask layer on the storage region has a first opening; Perform a first etching process, using the first mask layer as a mask, to etch the polysilicon layer of the storage region along the depth direction of the first opening; Remove the first mask layer; A second photolithography process is performed to form a second mask layer on the storage area and the logic area, the second mask layer filling the first opening, and the second mask layer on the logic area having a second opening; A second etching process is performed, using the second mask layer as a mask, to etch the polysilicon layer of the logic region along the depth direction of the second opening; as well as, Remove the second mask layer.

2. The method for fabricating an embedded flash memory device according to claim 1, characterized in that, The first photolithography process includes: A first mask layer is formed, the first mask layer covering the storage area and the logic area; and, Perform a first exposure and development process to form a first opening in the first mask layer of the storage area.

3. The method for fabricating an embedded flash memory device according to claim 1, characterized in that, The second photolithography process includes: A second mask layer is formed, which covers the storage area and the logic area and fills the first opening; and, A second exposure and development process is performed to form a second opening in the second mask layer of the logic region.

4. The method for fabricating an embedded flash memory device according to claim 1, characterized in that, The thickness of the polysilicon layer on the storage region is 1000Å~1200Å, the thickness of the polysilicon layer on the logic region is 700Å~900Å, and the height difference of the polysilicon layer at the boundary between the storage region and the logic region is 100Å~500Å.

5. The method for fabricating an embedded flash memory device according to claim 1, characterized in that, Both the first mask layer and the second mask layer are photoresist layers, and the thickness of the photoresist layer ranges from 2600 Å to 2800 Å.

6. The method for fabricating an embedded flash memory device according to claim 1, characterized in that, The first etching process is a wet etching process.

7. The method for fabricating an embedded flash memory device according to claim 1, characterized in that, The second etching process is a wet etching process.

8. The method for fabricating an embedded flash memory device according to claim 1, characterized in that, The gate stack structure includes a floating gate layer, a gate dielectric layer, a control gate layer, an isolation layer, and a hard mask layer stacked sequentially.

9. The method for fabricating an embedded flash memory device according to claim 1, characterized in that, After performing the first etching process, word lines and erase gates are formed on the memory area.

10. An embedded flash memory device, characterized in that, It is prepared by the method of any one of claims 1 to 9 for the fabrication of embedded flash memory devices.

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