A method for optimizing the uniformity of the oxide layer on Nord Flash word lines

Abstract

This application relates to the field of semiconductor manufacturing technology, and in particular to a method for optimizing the uniformity of word line oxide layers in Nord Flash. Addressing the problems of poor thickness uniformity, pitting, or high contact resistance in existing processes where a thick oxide layer is deposited followed by planarization and wet etching to thin the word line oxide layer, this invention directly deposits a first oxide layer of the target thickness as the word line oxide layer after forming the word line trench, and sequentially forms a sacrificial protective layer and a second oxide layer. After planarization to expose the protective layer, a first etching is performed using a high etch selectivity ratio between the protective layer and the oxide layer, protecting the word line oxide layer at the bottom of the trench from erosion. Finally, the protective layer is removed in subsequent memory cell manufacturing processes. This invention determines the word line oxide layer thickness solely through a single deposition process, significantly improving thickness uniformity within, between, and between wafers. Furthermore, the protective layer can be removed in situ during existing process steps without requiring additional masking or etching processes, making it highly compatible with existing processes.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for optimizing the uniformity of the word line oxide layer in Nord Flash. Background Technology

[0002] In the manufacturing process of NOR flash memory devices, the uniformity of word line oxide layer thickness is crucial to device performance and yield. Traditional word line oxide layer formation processes typically include: word line etching back to form grooves, chemical vapor deposition to fill the thick oxide layer, chemical mechanical polishing for planarization, and wet etching to thin the oxide layer to the target thickness. This process involves four main steps: etching, deposition, polishing, and wet etching. Process fluctuations in each step can overlap, resulting in poor uniformity of the final word line oxide layer thickness. In areas where the oxide layer is too thin, pitting defects may occur, leading to short circuits or leakage; in areas where the oxide layer is too thick, oxide residue may remain, resulting in higher word line contact resistance, affecting wafer yield and device reliability. Summary of the Invention

[0003] In a first aspect, the present invention provides a method for optimizing the uniformity of the oxide layer on Nord Flash word lines, the specific method being as follows: Provide a base with letter grooves; A first oxide layer is deposited on the substrate to directly form a character line oxide layer of the target thickness located at the bottom of the groove; A silicon nitride protective layer is deposited on the first oxide layer; A second oxide layer is deposited on the silicon nitride protective layer, the second oxide layer filling the groove and covering the word line structure; A planarization process is performed to remove part of the second oxide layer at the top of the word line structure, exposing the silicon nitride protective layer; Perform a first wet etching process to remove the second oxide layer remaining at the top of the word line structure. Utilize the high etching selectivity between the silicon nitride protective layer and the second oxide layer to stop the first wet etching process at the silicon nitride protective layer. In the subsequent memory cell manufacturing process, a second wet etching is performed to remove the silicon nitride protective layer.

[0004] In one possible implementation, the target thickness of the letter oxide layer is 600 Å.

[0005] In one possible implementation, the thickness of the silicon nitride protective layer ranges from 50 Å to 200 Å.

[0006] In one possible implementation, the planarization process employs a chemical mechanical polishing process.

[0007] In one possible implementation, the etching solution used in the first wet etching process has a higher etching rate for silicon oxide than for silicon nitride, causing the etching to automatically stop at the silicon nitride protective layer, and the word line oxide layer at the bottom of the groove is not eroded.

[0008] In one possible implementation, the etching solution used in the first wet etching process is a solution containing hydrofluoric acid.

[0009] In one possible implementation, the second wet etching is combined with the step of removing the word line oxide layer to protect silicon nitride in the original memory cell manufacturing process.

[0010] In one possible implementation, the first oxide layer, the silicon nitride protective layer, and the second oxide layer are all formed using a chemical vapor deposition process.

[0011] In one possible implementation, the method ensures that the thickness of the word line oxide layer is determined solely by the deposition process of the first oxide layer, unaffected by subsequent planarization and wet etching processes.

[0012] In one possible implementation, the subsequent storage cell manufacturing process includes: Removal of oxide layer and silicon nitride in memory cell area; Isotropic etching of polysilicon gates in memory cell regions; Formation of a tunneling oxide layer; Deposit and planarize floating gate polysilicon; Forming an inter-gate dielectric layer and a control gate.

[0013] Secondly, this application provides a NOR flash memory device, including a word line oxide layer formed by the above method, wherein the word line oxide layer has uniform thickness within a single flash memory, within a wafer, and between wafers.

[0014] Due to the adoption of the above technical solutions, this application has the following beneficial effects: 1. This invention significantly improves the uniformity of word line oxide layer thickness within a single device, within a wafer, and between wafers by simplifying the process flow, reducing process variables that affect oxide layer thickness, and introducing a sacrificial protection layer.

[0015] 2. This invention achieves consistency between the final morphology of the Flash cell and the old process while keeping the process steps unchanged in the MCELL loop.

[0016] 3. This invention is applicable to Nord Flash products with WL Ox formed by backfilling process, and has a wide range of applications. Attached Figure Description

[0017] To more clearly illustrate the technical solution of the present invention and facilitate a further understanding of its technical effects, features, and objectives, the present invention will be described in detail below with reference to the accompanying drawings. The drawings constitute an essential part of the specification and are used together with Embodiment 1 of the present invention to illustrate the technical solution of the present invention, but do not constitute a limitation on the present invention.

[0018] The same reference numerals in the attached diagrams represent the same parts, specifically: Figure 1 This is a schematic diagram of the structure after the first oxide layer is deposited in one embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the structure after the protective layer has been deposited in one embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the structure after the deposition of the second oxide layer in one embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the structure after planarization in one embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of the structure after the first wet etching in one embodiment of the present invention.

[0023] Figure 6 This is a schematic diagram of the structure after the protective layer is removed by the second wet etching in one embodiment of the present invention.

[0024] Figure 7 This is a schematic diagram of the subsequent storage cell manufacturing process in one embodiment of the present invention.

[0025] Figure 8 This is a schematic diagram of the overall process of an embodiment of the present invention.

[0026] in: 1. Substrate; 2. Groove; 3. First oxide layer; 4. Protective layer; 5. Second oxide layer. Detailed Implementation

[0027] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention; however, the present invention may be practiced in other ways different from those described herein, and therefore the present invention is not limited to the specific embodiments disclosed below.

[0028] This specification should be understood as teaching and example of the present invention, and not as limiting the invention to the specific embodiments described below. Those skilled in the art can make equivalent substitutions or modifications to the described steps without departing from the core concept of the present invention, and all such substitutions and modifications should be covered within the scope of protection of the present invention.

[0029] This invention provides a method for optimizing the uniformity of the oxide layer on flash memory word lines, such as... Figure 8 As shown, its core steps include: Step S1: Provide a substrate 1, on which a plurality of character line structures are formed, and a groove 2 is provided between adjacent character line structures; Step S2: Deposit a first oxide layer 3 on the substrate 1 to directly form a target thickness letter line oxide layer located at the bottom of the groove 2; Step S3: Deposit a protective layer 4 on the first oxide layer 3; Step S4: Deposit a second oxide layer 5 on the protective layer 4 to fill the groove 2 and cover the letter line structure; Step S5: Perform planarization to remove part of the second oxide layer 5 at the top of the character line structure, exposing the protective layer 4; Step S6: Perform the first etching to remove the second oxide layer 5 remaining at the top of the word line structure. Utilize the high etching selectivity between the protective layer 4 and the second oxide layer 5 to stop the etching at the protective layer 4. Step S7: Perform a second etching to remove the protective layer 4 and expose the word line oxide layer composed of the first oxide layer 3.

[0030] Step S8: Removal of oxide layer and silicon nitride in memory cell area.

[0031] The alternative implementation methods for each step are described in detail below with reference to the accompanying drawings.

[0032] Step S1: Provide substrate 1 like Figure 1 As shown, in embodiments of the present invention, the substrate 1 can be a silicon substrate, a silicon-on-insulator substrate, a germanium-silicon substrate, or other semiconductor substrates. The word line structure can be the word line structure of a NOR flash memory device, including but not limited to stacked gate structures, split gate structures, or word lines in other flash memory architectures. The groove 2 is formed by an etching process of the word line structure, and the groove 2 between adjacent word line structures is used to accommodate the subsequently formed word line oxide layer. It should be understood that the present invention is applicable to any flash memory device that requires the word line oxide layer to be formed by backfilling the groove 2, and is not limited to a specific flash memory type.

[0033] Step S2: Deposit the first oxide layer 3 like Figure 1As shown, in embodiments of the present invention, the process for depositing the first oxide layer 3 can employ furnace tube chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, low-pressure chemical vapor deposition, or other suitable thin film deposition processes. The material of the first oxide layer 3 can be silicon oxide, doped silicon oxide, or other oxygen-containing dielectric materials. A key feature is that the first oxide layer 3 achieves the target thickness of the word line oxide layer at the bottom of the groove 2 during deposition. This target thickness can be selected according to device design requirements, exemplarily approximately 600 angstroms. In other embodiments, the target thickness can be any value between approximately 400 angstroms and approximately 800 angstroms. Compared to the prior art method of first depositing a thick oxide layer and then etching back to thin it, the present invention directly forms an oxide layer of the target thickness at the bottom of the groove 2, fundamentally eliminating the influence of subsequent planarization and wet etching processes on the thickness of the bottom oxide layer, whose thickness is determined solely by the deposition process itself.

[0034] Step S3: Deposit protective layer 4 like Figure 2 As shown, in an embodiment of the present invention, the protective layer 4 is deposited on top of the first oxide layer 3 to protect the word line oxide layer at the bottom of the groove 2 from subsequent etching processes. The material of the protective layer 4 should have a sufficiently high etch selectivity ratio to the first oxide layer 3 and the second oxide layer 5. The preferred material for the protective layer 4 is silicon nitride; other optional materials include, but are not limited to, silicon oxynitride, silicon carbide, silicon carbonitride, aluminum oxide, hafnium oxide, aluminum nitride, or other dielectric materials with a high etch selectivity ratio to silicon oxide. The thickness of the protective layer 4 needs to be sufficient to provide reliable protection during subsequent etching, but should not be too thick to avoid increasing the difficulty of subsequent removal and affecting the morphology. The preferred thickness range is from about 50 angstroms to about 200 angstroms, more preferably from about 80 angstroms to about 150 angstroms. The deposition process for the protective layer 4 can employ chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, low-pressure chemical vapor deposition, or physical vapor deposition, etc. When using protective layer 4 materials other than silicon nitride, the subsequent removal steps need to be adjusted accordingly to ensure that the protective layer 4 can be effectively removed without damaging the surrounding structure.

[0035] Step S4: Deposit the second oxide layer 5 like Figure 3As shown, in an embodiment of the present invention, the second oxide layer 5 is used to fill the remaining space of the groove 2 and cover the word line structure, providing sufficient material thickness for subsequent planarization processes. The material of the second oxide layer 5 can be the same as the first oxide layer 3, for example, silicon oxide; or it can be different, for example, doped silicon oxide, spin-coated glass, or other flowable silicon oxide materials, to obtain better gap-filling capability. The deposition process can employ high-density plasma chemical vapor deposition, atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, spin coating, or other suitable filling processes. The deposition thickness of the second oxide layer 5 should be sufficient to ensure complete filling of the groove 2 without creating voids during the subsequent planarization process.

[0036] Step S5: Flattening Process like Figure 4 As shown, in an embodiment of the present invention, the planarization process is used to remove a portion of the second oxide layer 5 above the top of the character line structure and achieve surface planarization. A preferred planarization process is chemical mechanical polishing (CMP). Alternatively, a reverse etching planarization process, or a combination of CMP and reverse etching, can be used. The planarization process must continue until the portion of the protective layer 4 located at the top of the character line structure is exposed. When using CMP as the planarization process, the protective layer 4 can be used as a polishing stop layer, and a high selectivity polishing ratio can be achieved for both the protective layer 4 and the oxide layer by selecting a suitable polishing solution.

[0037] Step S6: First Etching like Figure 5 As shown, in an embodiment of the present invention, the first etching is used to remove the second oxide layer 5 remaining on the top of the word line structure after planarization. The preferred etching method is wet etching. Alternatively, dry etching or a wet-dry hybrid etching method can also be used. For wet etching, the etching rate of the selected etching solution for silicon oxide should be much greater than the etching rate for the protective layer 4, i.e., it should have a high etching selectivity. When the protective layer 4 is silicon nitride, the etching solution can be a solution containing hydrofluoric acid, such as diluted hydrofluoric acid or a buffered oxide etching solution. When the protective layer 4 is made of other materials, the etching solution formulation should be adjusted accordingly to maintain a high selectivity. When using dry etching, a fluorine-containing gas or a mixture of fluorine-containing gas and oxygen can be used, and a high selectivity etching ratio for silicon oxide and the protective layer 4 can be achieved by adjusting the process parameters. The key to this step is that, regardless of the etching method used, the word line oxide layer covered by the protective layer 4 at the bottom of the groove 2 is effectively protected, and its thickness remains unchanged before and after etching.

[0038] Step S7: Second Etching like Figure 6As shown, in an embodiment of the present invention, the second etching is used to remove the protective layer 4, exposing the word line oxide layer formed by the first oxide layer 3. A preferred etching method is wet etching. When the protective layer 4 is silicon nitride, a phosphoric acid solution, such as hot phosphoric acid, can be used. When the protective layer 4 is other materials, an etching solution capable of effectively removing the material without significantly eroding the exposed oxide layer and word line structure should be selected. For example, if the protective layer 4 is aluminum oxide, an alkaline solution can be used; if the protective layer 4 is silicon carbide, a specific fluorine-containing etching solution can be used. Alternatively, dry etching or atomic layer etching can also be used to remove the protective layer 4. In a preferred embodiment of the present invention, this second etching step is combined with the step in the existing memory cell manufacturing process used to remove the silicon nitride protective layer 4 in other areas, without adding additional photolithography and etching process steps. This achieves minimal disruption and complete compatibility with the existing process flow while maintaining the final morphology of the memory cell consistent with the original process.

[0039] Step S8: Subsequent memory cell manufacturing process In this embodiment, the silicon nitride sacrificial protective layer introduced by the new process can be removed in situ during subsequent memory cell manufacturing processes without requiring additional photolithography or etching steps. This is because the standard memory cell manufacturing process already includes a wet etching step to remove the word line oxide layer protecting the silicon nitride; the protective layer of the new process can be removed in this step, achieving minimal modification and full compatibility with existing processes. Figure 7 As shown, the subsequent processing steps are as follows: S81: Removal of oxide layer and silicon nitride in memory cell area Continuing with the aforementioned structure, the wafer surface is now covered by a word line oxide layer consisting of a first oxide layer, and a silicon nitride sacrificial protection layer above it. A single wet etching process completely removes the oxide layer and all silicon nitride layers (including both the sacrificial protection layer introduced by the new process and the original silicon nitride protection layer already covering the word line oxide layer) from the memory cell region, exposing the underlying word line oxide layer and active region. The etching solution used in this step is typically a hot phosphoric acid solution, which has extremely high etching selectivity for silicon nitride, cleanly removing it without damaging the underlying silicon oxide layer and silicon substrate. S82: Isotropic etching of polysilicon gate in memory cell region After removing the silicon nitride above the word line oxide layer, an isotropic etching process (such as dry etching) is performed to laterally etch back the gate polysilicon of the memory cell region to precisely control the critical dimensions of the floating gate and / or control gate. This step modulates the gate morphology, preparing for the subsequent formation of the tunnel oxide layer and memory node. The isotropic etching characteristic ensures that the gate material is uniformly removed in all directions.

[0040] S83: Formation of tunneling oxide layer A high-quality tunneling oxide layer is grown or deposited on the exposed polysilicon sidewalls of the gate and the oxide layer of the word lines using thermal oxidation or chemical vapor deposition processes. This extremely thin oxide layer is the physical channel through which charge tunnels into or out of the floating gate during programming and erasing operations of the flash memory device.

[0041] S84: Deposit and planarize floating gate polysilicon After forming the tunneling oxide layer, a layer of floating gate polysilicon is deposited to fill the space created by the gate etch-back. Subsequently, the floating gate polysilicon is typically planarized using a chemical mechanical polishing process, with the silicon nitride or oxide layer on top of the word line oxide layer serving as a polishing stop layer, ultimately forming a separate, self-aligned floating gate structure.

[0042] S85: Forming the inter-gate dielectric layer and control gate Above the planarized floating gate, an inter-gate dielectric layer (such as a stacked structure of silicon oxide / silicon nitride / silicon oxide) and a control gate polysilicon layer are deposited sequentially. Subsequently, the control gate, inter-gate dielectric layer, and floating gate are patterned using photolithography and etching processes to form word lines.

[0043] After the core structure of the memory cell is completed, the standard back-end process is entered, including sidewall formation, source / drain injection, metal silicide formation, interlayer dielectric deposition, contact via formation, and metal interconnection, until the entire semiconductor device is manufactured.

[0044] The present invention also provides a NOR flash memory device, wherein the word line oxide layer formed by the above method has uniform thickness within a single flash memory, within a wafer, and between wafers.

[0045] It should be understood that the above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for optimizing the uniformity of the oxide layer on Nord Flash word lines, characterized in that, The specific method is as follows: Provide a base with letter grooves; A first oxide layer is deposited on the substrate to directly form a character line oxide layer of the target thickness located at the bottom of the groove; A silicon nitride protective layer is deposited on the first oxide layer; A second oxide layer is deposited on the silicon nitride protective layer, the second oxide layer filling the groove and covering the word line structure; A planarization process is performed to remove part of the second oxide layer at the top of the word line structure, exposing the silicon nitride protective layer; Perform a first wet etching process to remove the second oxide layer remaining at the top of the word line structure. Utilize the high etching selectivity between the silicon nitride protective layer and the second oxide layer to stop the first wet etching process at the silicon nitride protective layer. In the subsequent memory cell manufacturing process, a second wet etching is performed to remove the silicon nitride protective layer.

2. The method for optimizing the uniformity of the oxide layer on Nord Flash word lines as described in claim 1, characterized in that, The target thickness of the letter oxide layer is 600 Å.

3. The method for optimizing the uniformity of the oxide layer on Nord Flash word lines as described in claim 1, characterized in that, The thickness of the silicon nitride protective layer ranges from 50 Å to 200 Å.

4. The method for optimizing the uniformity of the oxide layer on Nord Flash word lines as described in claim 1, characterized in that, The planarization process employs a chemical mechanical polishing technique.

5. The method for optimizing the uniformity of the oxide layer on Nord Flash word lines as described in claim 1, characterized in that, The etching solution used in the first wet etching process has a higher etching rate for silicon oxide than for silicon nitride, so that the etching automatically stops at the silicon nitride protective layer, and the word line oxide layer at the bottom of the groove is not eroded.

6. The method for optimizing the uniformity of the oxide layer on Nord Flash word lines as described in claim 5, characterized in that, The etching solution used in the first wet etching process is a solution containing hydrofluoric acid.

7. The method for optimizing the uniformity of the oxide layer on Nord Flash word lines as described in claim 1, characterized in that, The second wet etching process is combined with the step of removing the word line oxide layer to protect silicon nitride in the original memory cell manufacturing process.

8. The method for optimizing the uniformity of the oxide layer on Nord Flash word lines as described in claim 1, characterized in that, The first oxide layer, the silicon nitride protective layer, and the second oxide layer are all formed using a chemical vapor deposition process.

9. The method for optimizing the uniformity of the oxide layer on Nord Flash word lines as described in claim 1, characterized in that, The method ensures that the thickness of the word line oxide layer is determined solely by the deposition process of the first oxide layer, and is unaffected by subsequent planarization and wet etching processes.

10. The method for optimizing the uniformity of the word line oxide layer in Nord Flash as described in claim 1, characterized in that, Subsequent storage cell manufacturing processes include: Removal of oxide layer and silicon nitride in memory cell area; Isotropic etching of polysilicon gates in memory cell regions; Formation of a tunneling oxide layer; Deposit and planarize floating gate polysilicon; Forming an inter-gate dielectric layer and a control gate.

11. A NOR flash memory device, characterized in that, Includes a word line oxide layer formed using the method described in any one of claims 1 to 10, wherein the word line oxide layer has uniform thickness within a single flash memory, within a wafer, and between wafers.

Images