Semiconductor device and data storage system including the same

Abstract

A semiconductor device and a data storage system including the semiconductor device are provided. In the semiconductor device according to the present invention, a portion of the multilayer wiring structure located in the wiring region of the peripheral circuit structure can be replaced by a replacement process to form a capacitor structure, thus improving electrical characteristics and reliability due to the increase in the area of ​​the capacitor structure.

Description

Cross-reference of related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0047691, filed on April 11, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present invention relates to a semiconductor device and a data storage system including the semiconductor device, and more specifically, to a semiconductor device including a capacitor structure and a data storage system including the semiconductor device. Background Technology

[0003] To achieve superior performance and cost-effectiveness, it is necessary to increase the integration density of semiconductor devices. In particular, the integration density of memory devices is a crucial factor determining the cost-effectiveness of a product. The integration density of two-dimensional memory devices is primarily determined by the area occupied by a single memory cell and is therefore significantly influenced by the level of fine patterning technology. However, expensive equipment is required to form fine patterns, and the area of ​​the die is limited. Therefore, although the integration density of two-dimensional memory devices is increasing, the increase remains limited. Consequently, technologies capable of improving the integration density of two-dimensional memory devices and technologies for vertical memory devices with three-dimensional structures are needed. Summary of the Invention

[0004] The present invention provides a semiconductor device with improved electrical characteristics and reliability due to the increase in the area of ​​the capacitor structure, and a data storage system including the semiconductor device.

[0005] The purpose of this invention is not limited to the above-described purposes, and other purposes not described herein will be clearly understood by those skilled in the art from the following description.

[0006] According to one aspect of the present invention, a semiconductor device is provided, comprising: a peripheral circuit structure including a substrate having an active region defined by a device isolation region, peripheral circuit devices on the active region, a multilayer wiring structure connected to the peripheral circuit devices, a multilayer insulating structure surrounding the multilayer wiring structure, a capacitor structure horizontally spaced from the multilayer wiring structure and extending at least partially through the multilayer insulating structure, and a first bonding pad connected to the multilayer wiring structure and the capacitor structure; and a memory cell structure including a passivation layer having a cell region and a pad region, gate electrodes stacked in the cell region and spaced apart from each other in a vertical direction, a channel structure extending through the gate electrodes, input / output pads located in the pad region, and a covering cell region. The capacitor structure includes a cover insulating layer for the pad area, a through plug extending through the cover insulating layer in the pad area and connected to the input / output pads, a cell wiring structure connected to the channel structure and the through plug, and a second bonding pad connected to the cell wiring structure. The capacitor structure includes a first electrode layer conformally formed on the inner wall of a recessed region extending at least partially through the multilayer insulating structure, a capacitor dielectric layer conformally formed on the inner wall of the first electrode layer, and a second electrode layer contacting the inner wall of the capacitor dielectric layer and filling the recessed region. At least a portion of a first via contacting the upper surface of the first electrode layer and at least a portion of a second via contacting the upper surface of the second electrode layer are located at substantially the same vertical level.

[0007] According to another aspect of the present invention, a semiconductor device is provided, comprising: a substrate having an active region defined by a device isolation region; peripheral circuitry on the active region; a multilayer wiring structure including a plurality of wiring layers connected to the peripheral circuitry and a plurality of via layers connecting the plurality of wiring layers to each other in a vertical direction; a multilayer insulating structure including a plurality of insulating layers surrounding the plurality of wiring layers and the plurality of via layers; a recessed region including a plurality of recessed patterns spaced horizontally from the multilayer wiring structure and extending at least partially through the multilayer insulating structure; a first electrode layer conformally disposed along the inner wall of the plurality of recessed patterns and the upper surface of the multilayer insulating structure; a capacitor dielectric layer conformally disposed along the inner wall and the upper surface of the first electrode layer; a second electrode layer contacting the inner wall and the upper surface of the capacitor dielectric layer and filling the plurality of recessed patterns; a first trace via contacting the upper surface of the first electrode layer; and a second trace via contacting the upper surface of the second electrode layer, wherein the sidewall of the first electrode layer located in each of the plurality of recessed patterns has a plurality of curved segments in a vertical direction.

[0008] According to another aspect of the present invention, a data storage system is provided, including a motherboard, a semiconductor device on the motherboard, and a controller disposed on the motherboard and electrically connected to the semiconductor device. The semiconductor device includes a peripheral circuit structure and a memory cell structure disposed on the peripheral circuit structure. The peripheral circuit structure includes a substrate having an active region defined by a device isolation region, peripheral circuit devices on the active region, a multilayer wiring structure connected to the peripheral circuit devices, a multilayer insulating structure surrounding the multilayer wiring structure, a capacitor structure horizontally spaced from the multilayer wiring structure and extending at least partially through the multilayer insulating structure, and a first bonding pad connected to the multilayer wiring structure and the capacitor structure. The memory cell structure includes a passivation layer having cell regions and pad regions, gate electrodes stacked in the cell regions and vertically spaced apart from each other, and a passivation layer extending through the gate electrodes. The capacitor structure includes a channel structure, input / output pads located in the pad area, a covering insulating layer covering the cell area and the pad area, a through plug extending through the covering insulating layer in the pad area and connected to the input / output pads, a cell wiring structure connected to the channel structure and the through plug, and a second bonding pad connected to the cell wiring structure. The capacitor structure includes a first electrode layer conformally formed on the inner wall of a recessed region that at least partially extends through a multilayer insulating structure, a capacitor dielectric layer conformally formed on the inner wall of the first electrode layer, and a second electrode layer that contacts the inner wall of the capacitor dielectric layer and fills the recessed region. At least a portion of a first trace via that contacts the upper surface of the first electrode layer and at least a portion of a second trace via that contacts the upper surface of the second electrode layer are located at substantially the same vertical level, and the first bonding pad is bonded to the second bonding pad.

[0009] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: preparing a substrate including a first region and a second region surrounding the first region; sequentially forming a plurality of wiring layers and a plurality of via layers, and a plurality of insulating layers surrounding the wiring layers and via layers, alternately arranged in a vertical direction in the first region and the second region; removing the plurality of wiring layers and the plurality of via layers from the first region; forming a plurality of recessed patterns by expanding the space in the first region from which the plurality of wiring layers and the plurality of via layers have been removed; forming a first electrode layer conformally covering the inner walls of the plurality of recessed patterns and the upper surfaces of the plurality of insulating layers; forming a capacitor dielectric layer conformally covering the inner walls and the upper surface of the first electrode layer; forming a second electrode layer that contacts and fills the plurality of recessed patterns with the inner walls and the upper surface of the capacitor dielectric layer; and forming a first wiring via that contacts the upper surface of the first electrode layer and a second wiring via that contacts the upper surface of the second electrode layer.

[0010] In an embodiment, when forming the first routing via and the second routing via, the uppermost end of the first routing via may be located at a vertical level substantially the same as the uppermost end of the second routing via, and the lowermost end of the first routing via may be located at a vertical level lower than the lowermost end of the second routing via.

[0011] In an embodiment, when forming multiple recessed patterns, the uppermost point of some recessed patterns arranged below the area where the first trace via will be formed may be lower than the uppermost point of other recessed patterns.

[0012] In an embodiment, when forming a plurality of recessed patterns, the sidewalls of each of the plurality of recessed patterns may have a plurality of curved sections in the vertical direction, and the vertical level of the plurality of curved sections in the first region may be substantially the same as the vertical level of the joint interface between the plurality of wiring layers and the plurality of via layers in the second region.

[0013] In an embodiment, when forming multiple recessed patterns, at least some of the multiple curved sections can have rounded corners through a cleaning process and a wet etching process.

[0014] In an embodiment, the semiconductor device manufacturing method may further include: manufacturing a peripheral circuit structure by forming a first bonding pad connected to a first wiring via and a second wiring via; and manufacturing a memory cell structure, wherein the memory cell structure includes a passivation layer having a cell region and a pad region, gate electrodes stacked in the cell region and spaced apart from each other in the vertical direction, a channel structure extending through the gate electrodes, an input / output pad located in the pad region, a cover insulating layer covering the cell region and the pad region, a through plug extending through the cover insulating layer in the pad region and connected to the input / output pad, a cell wiring structure connected to the channel structure and the through plug, and a second bonding pad connected to the cell wiring structure.

[0015] In an embodiment, the semiconductor device manufacturing method may further include bonding a first bonding pad of a peripheral circuit structure to a second bonding pad of a memory cell structure.

[0016] In one embodiment, the first bonding pad can be bonded to the second bonding pad via a metal-to-metal bonding process.

[0017] In this embodiment, the first electrode layer, the capacitor dielectric layer, and the second electrode layer may overlap with the pad area in the vertical direction, but may not overlap with the cell area in the vertical direction.

[0018] In an embodiment, the first trace via and the second trace via can each be electrically connected to the input / output pads via a first bonding pad, a second bonding pad, and a through plug. Attached Figure Description

[0019] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a block diagram illustrating a semiconductor device according to an embodiment; Figure 2 It is shown Figure 1 A circuit diagram of a charge pump circuit in a voltage generator of a semiconductor device; Figure 3 This is a schematic perspective view of a semiconductor device according to an embodiment; Figure 4 This is a plan view illustrating the components of a semiconductor device according to an embodiment; Figure 5 It is along Figure 4 A cross-sectional view of the semiconductor device taken by line CX-CX'; Figure 6 This is a plan view showing the capacitor structure of the semiconductor device according to an embodiment at the LV1, LV2 and LV3 levels; Figure 7 It is along Figure 6 Cross-sectional views of the capacitor structure taken by lines CX1, CX2 and CX3; Figure 8 It is shown Figure 7 A cross-sectional view comparing the wiring area and a portion of the area; Figure 9 yes Figure 7 A magnified view of region BB; Figure 10 yes Figure 7 A magnified view of region CC; Figure 11 yes Figure 7 A magnified view of region DD; Figure 12 yes Figure 7 A magnified view of the EE region; Figures 13 to 15 This is a cross-sectional view of a semiconductor device according to some embodiments; Figure 16 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment; Figures 17 to 27 This is a cross-sectional view showing the process sequence of a semiconductor device manufacturing method according to an embodiment; Figure 28 This is a diagram illustrating a data storage system including a semiconductor device according to an embodiment; Figure 29 This is a perspective view illustrating a data storage system including a semiconductor device according to an embodiment; and Figure 30This is a cross-sectional view showing a semiconductor package including a semiconductor device according to an embodiment. Detailed Implementation

[0020] The embodiments are described in detail below with reference to the accompanying drawings.

[0021] Figure 1 This is a block diagram illustrating a semiconductor device 100 according to an embodiment.

[0022] Reference Figure 1 The semiconductor device 100 may include a memory cell array 20 and peripheral circuitry 30, and the semiconductor device 100 may represent a non-volatile memory device such as flash memory.

[0023] The memory cell array 20 may include a plurality of memory cells. In some embodiments, the memory cell array 20 may include a plurality of memory blocks BLK (see...). Figure 4 ), and memory block BLK (see Figure 4 Each of the following may include multiple memory cells. Here, the multiple memory cells may be connected to the row decoder 32 via multiple word lines WL and to the read / write circuitry 34 via multiple bit lines BL. Multiple memory cells arranged along the same row may be connected to the same word line WL, and multiple memory cells arranged along the same column may be connected to the same bit line BL.

[0024] Peripheral circuitry 30 can receive address ADDR, command CMD, and control signal CTRL from outside semiconductor device 100, and can send data DATA to or receive data DATA from external devices. Peripheral circuitry 30 may include a line decoder 32, read / write circuitry 34, control logic 36, and a voltage generator 38 for generating various voltages required for operation. In some embodiments, peripheral circuitry 30 may also include various sub-circuits, such as input / output circuitry and error correction circuitry for correcting errors in data DATA read from memory cell array 20.

[0025] The row decoder 32 can select some of a plurality of memory cells in response to address ADDR, and can select at least one word line WL. The row decoder 32 can send a voltage for performing memory operations to the selected word line WL.

[0026] The read / write circuit 34 can be connected to the memory cell array 20 via bit line BL. The read / write circuit 34 may include a write driver or a sense amplifier. Specifically, during a read operation, the read / write circuit 34 can operate as a sense amplifier and can read the data DATA stored in the memory cell array 20. Furthermore, during a write operation, the read / write circuit 34 can operate as a write driver and can apply a voltage according to the data DATA to be stored in the memory cell array 20 to the bit line BL.

[0027] Control logic 36 can be connected to line decoder 32, voltage generator 38, and input / output circuitry. Control logic 36 controls all operations of semiconductor device 100. In response to the control signal CTRL, control logic 36 can generate various internal control signals for semiconductor device 100. For example, when performing memory operations such as programming and erasing operations, control logic 36 can adjust the voltage levels supplied to word line WL and bit line BL.

[0028] The voltage generator 38 may include a controller 52, an oscillator 54, and a charge pump circuit 56.

[0029] The controller 52 can control the operation of the oscillator 54. For example, the controller 52 can determine the frequency of the clock signal CLK output from the oscillator 54 to the charge pump circuit 56 based on at least one of the process, voltage, and temperature (PVT) information of the semiconductor device 100 and a target level of the voltage to be output by the charge pump circuit 56. In some embodiments, when the charge pump circuit 56 includes multiple charge pumps, the controller 52 can determine which of the multiple charge pumps is actually operating.

[0030] Oscillator 54 can output a clock signal CLK that turns the switching elements included in charge pump circuit 56 on or off. The clock signal CLK output by oscillator 54 can be determined in response to a control signal VGC provided by controller 52. For example, oscillator 54 can set the frequency and oscillation range of clock signal CLK differently according to the control signal VGC sent by controller 52.

[0031] The charge pump circuit 56 may include a plurality of charge pumps, and each of the plurality of charge pumps may include a switching element and a pump capacitor. The output voltage of the charge pump circuit 56 may be used for operation of the semiconductor device 100. In some embodiments, the line decoder 32 may use the output voltage of the charge pump circuit 56 and input a bias voltage to the word line WL to perform programming operations, erasing operations, and reading operations.

[0032] Figure 2 It is shown Figure 1 The circuit diagram of the charge pump circuit 56 in the voltage generator 38 of the semiconductor device 100.

[0033] Reference Figure 2 The charge pump circuit 56 may include multiple diodes DI, multiple pump capacitors CP, and an output capacitor COUT.

[0034] Multiple diodes DI can be connected in series, and multiple pump capacitors CP can be connected to the nodes between the multiple diodes DI. The first diode DI can receive a power supply voltage VCC with a preset level, and the last diode DI can output the output current IOUT to the output node.

[0035] Each of the multiple pump capacitors CP can be charged or discharged by a clock signal CLK or a complementary clock signal CLKB, which is phase-shifted by an inverter INV so that the complementary clock signal CLKB has an opposite phase to the clock signal CLK. For example, odd-numbered pump capacitors CP can be charged or discharged by the clock signal CLK, and even-numbered pump capacitors CP can be charged or discharged by the complementary clock signal CLKB.

[0036] Figure 3 This is a schematic perspective view of a semiconductor device 100 according to an embodiment.

[0037] Reference Figure 3 The semiconductor device 100 may include a peripheral circuit structure PERI and a memory cell structure CELL.

[0038] In some embodiments, the memory cell structure (CELL) may be disposed above the peripheral circuit structure (PERI). In this case, the memory cell array 20 (see...) Figure 1 ) can be located in the memory cell structure CELL, and the peripheral circuitry 30 (see Figure 1 The memory cell structure (CELL) may be located within the peripheral circuitry (PERI). Conversely, in some embodiments, the CELL may be located below the PERI.

[0039] In some embodiments, the memory cell structure CELL may include a first region R1 and a second region R2. The first region R1 may represent a memory cell array 20 disposed therein (see...). Figure 1 The second region R2 can represent the pad area, used to mount the memory cell array 20 (see [link to image]). Figure 1 The memory cell is electrically connected to the peripheral circuit 30 (see...). Figure 1 The second region R2 may be located at the end of the first region R1 in at least one direction (e.g., in the first horizontal direction X).

[0040] Constructing a charge pump circuit 56 (see Figure 2Multiple pump capacitors CP can be arranged in the peripheral circuit structure PERI. For example, multiple pump capacitors CP can be arranged in the vertical direction Z in the peripheral circuit structure PERI below the second region R2 of the memory cell structure CELL.

[0041] Figure 4 This is a plan view showing the components of a semiconductor device 100 according to an embodiment. Figure 5 It is along Figure 4 A cross-sectional view of the semiconductor device 100 taken by line CX-CX'.

[0042] Reference Figure 4 and Figure 5 The semiconductor device 100 may include a first semiconductor structure S1 and a second semiconductor structure S2.

[0043] The first semiconductor structure S1 can correspond to the peripheral circuit structure PERI (see...). Figure 3 The first semiconductor structure S1 may include a first substrate SS, which includes an active region AC defined by a device isolation region STI, a peripheral circuit device PC disposed on the active region AC of the first substrate SS, a multilayer wiring structure ML connected to the peripheral circuit device PC, a multilayer insulating structure DL surrounding and insulating the multilayer wiring structure ML, and a capacitor structure CS passing through the multilayer insulating structure DL. Furthermore, the first semiconductor structure S1 may include a first bonding via BV1 connected to the multilayer wiring structure ML and the capacitor structure CS, a first bonding pad BP1, and a first bonding insulating layer BD1 surrounding the first bonding pad BP1.

[0044] The first substrate SS may comprise a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate SS may be provided as a bulk wafer or an epitaxial layer. The first substrate SS may have planes extending in a first horizontal direction X and a second horizontal direction Y. The active region AC may be defined within the first substrate SS by a device isolation region STI. An impurity region (not shown) containing impurities may be located within a portion of the active region AC.

[0045] The peripheral circuit device PC may include a planar transistor. Each of the peripheral circuit devices PC may include a gate dielectric layer GD, a gate electrode layer GE, a gate capping layer GC, and gate spacers GS on its two sidewalls. On both sides of the gate electrode layer GE, impurity regions may be arranged as source / drain regions within a first substrate SS.

[0046] A multilayer insulating structure DL can be disposed on a first substrate SS to cover peripheral circuit devices PC. The multilayer insulating structure DL may include multiple insulating layers D0 to D6 formed in different processes. Specifically, the multiple insulating layers D0 to D6 may be referred to as the bottommost insulating layer D0, the first insulating layer D1, the second insulating layer D2, the third insulating layer D3, the fourth insulating layer D4, the fifth insulating layer D5, and the sixth insulating layer D6, arranged in this order in the vertical direction Z. In some embodiments, the number of insulating layers D0 to D6 may be varied. The multilayer insulating structure DL may include an insulating material, such as silicon oxide or a low-k dielectric material.

[0047] Multiple wiring layers M0 to M5 and multiple via layers V0 to V5 can constitute a multilayer wiring structure ML electrically connected to a peripheral circuit device PC. The multilayer wiring structure ML can be referred to as peripheral circuit wiring. Each of the multiple wiring layers M0 to M5 has a line shape, and each of the multiple via layers V0 to V5 can have a column shape. Electrical signals can be applied to the peripheral circuit device PC through the multiple wiring layers M0 to M5 and the multiple via layers V0 to V5.

[0048] Multiple via layers V0 to V5 can connect multiple wiring layers M0 to M5 to each other in the vertical direction Z. Specifically, the multiple wiring layers M0 to M5 can be referred to as the bottommost wiring layer M0, the first wiring layer M1, the second wiring layer M2, the third wiring layer M3, the fourth wiring layer M4, and the fifth wiring layer M5. Furthermore, the multiple via layers V0 to V5 can be referred to as the bottommost via layer V0, the first via layer V1, the second via layer V2, the third via layer V3, the fourth via layer V4, and the fifth via layer V5. In some embodiments, the number of wiring layers M0 to M5 and the number of via layers V0 to V5 can be varied. The multilayer wiring structure ML can include conductive materials, such as tungsten (W), copper (Cu), aluminum (Al), etc.

[0049] In multiple insulating layers D0 to D6, multiple wiring layers M0 to M5, and multiple via layers V0 to V5, the same numbers can indicate that these layers are located in the same layer. For example, the third insulating layer D3, the third wiring layer M3, and the third via layer V3 can all be located in the third layer.

[0050] Above the first substrate SS, the capacitor structure CS may be spaced horizontally (X or Y) from the multilayer wiring structure ML and extend through the multilayer insulating structure DL. In some embodiments, the capacitor structure CS may correspond to a plurality of pump capacitors CP (see...). Figure 2 ) or output capacitor COUT (see Figure 2 ), and can be located in the wiring area MA. The capacitor structure CS is described in detail below.

[0051] The second semiconductor structure S2 can correspond to the memory cell structure CELL (see...). Figure 3 The second semiconductor structure S2 may include a passivation layer 110 having a first region R1 and a second region R2, a stacked structure including a gate electrode 130 and an interlayer insulating layer 140 alternately stacked in the first region R1, a channel structure CH extending through the stacked structure, an input / output pad IOP open to the outside via an opening 110H in the second region R2, and a cover insulating layer 150 covering the first region R1 and the second region R2. Furthermore, the second semiconductor structure S2 may include a contact plug 160 and a through plug 170, wherein the contact plug 160 extends through the cover insulating layer 150 in the first region R1 and connects to the end of the gate electrode 130, and the through plug 170 extends through the cover insulating layer 150 in the second region R2 and connects to the input / output pad IOP. Additionally, the second semiconductor structure S2 may include a cell wiring structure 180 electrically connected to the channel structure CH, the contact plug 160, and / or the through plug 170. In addition, the second semiconductor structure S2 may include a second bonding via BV2 and a second bonding pad BP2 connected to the cell wiring structure 180, and a second bonding insulating layer BD2 surrounding the second bonding pad BP2.

[0052] In the second semiconductor structure S2, the first region R1 may represent the region in which gate electrodes 130 are stacked vertically to form a memory cell or connected to a contact plug 160, and the second region R2 may represent the outer region of the memory cell in which input / output pads IOP are arranged.

[0053] Passivation layer 110 may include a first passivation layer 111 and a second passivation layer 112 stacked on top of each other. The first passivation layer 111 may include an insulating material different from the second passivation layer 112. For example, the first passivation layer 111 may include photosensitive polyimide (PSPI), and the second passivation layer 112 may include silicon oxide, silicon nitride, or silicon carbide. Passivation layer 110 may have an opening 110H, and input / output pads (IOPs) may be exposed to the outside through the opening 110H.

[0054] Gate electrodes 130 may be stacked on conductive plate 120, spaced apart from each other in the vertical direction Z, and together with interlayer insulating layer 140 to form a stacked structure. Gate electrodes 130 may include a lower gate electrode forming a string select transistor, a memory gate electrode forming a plurality of memory cells, and an upper gate electrode forming a ground select transistor. The number of gate electrodes 130 may be determined according to the storage capacity of semiconductor device 100.

[0055] The gate electrode 130 may extend to different lengths in the horizontal direction (X or Y) to form a stepped structure. Due to this stepped structure, contact areas at the ends of the gate electrode 130 can be connected to contact plugs 160 respectively. The gate electrode 130 may comprise a metallic material such as tungsten (W). The gate electrode 130 may comprise the same material.

[0056] Interlayer insulating layer 140 may be disposed between gate electrodes 130. Interlayer insulating layers 140 may be stacked on the upper surface of conductive plate 120 and spaced apart from each other in the vertical direction Z. Interlayer insulating layer 140 may include insulating materials such as silicon oxide and silicon nitride.

[0057] The channel structure CH can extend through the stacked structure in the vertical direction Z and can be connected to the conductive plate 120. Each channel structure CH can form a single memory cell string and can be arranged in rows and columns on the conductive plate 120 while being spaced apart from each other. Each channel structure CH can have a cylindrical shape with a high aspect ratio and can have sloping sidewalls, making the channel structure CH narrower towards the conductive plate 120. Each channel structure CH may include a channel layer, a gate dielectric layer, a channel buried insulating layer, and a channel pad disposed in a channel via.

[0058] The covering insulation layer 150 may cover the stacked structure, contact plug 160, through plug 170, and unit wiring structure 180, etc. The covering insulation layer 150 may include insulating material and may be provided as multiple insulation layers.

[0059] Contact plug 160 may be disposed in the first region R1 and connected to the contact region at the end of the gate electrode 130. Contact plug 160 may extend at least partially through the covering insulating layer 150 in the first region R1 and may be connected to the contact region of the gate electrode 130 respectively. Contact plug 160 may comprise a conductive material, such as at least one of tungsten (W), copper (Cu), aluminum (Al), and alloys thereof.

[0060] A through-plug 170 may be disposed in the second region R2 and may pass through the covering insulation layer 150 to connect to the input / output pad IOP. The through-plug 170 may comprise a conductive material, such as at least one of tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. The through-plug 170 and the contact plug 160 may be formed in the same process, and therefore may comprise the same material and have the same internal structure.

[0061] Cell wiring structure 180 may include wiring electrically connected to memory cells. Cell wiring structure 180 may be electrically connected to channel structure CH, contact plug 160 and / or through plug 170. Cell wiring structure 180 may include a conductive material, such as at least one of tungsten (W), copper (Cu), aluminum (Al) and alloys thereof.

[0062] The first semiconductor structure S1 and the second semiconductor structure S2 can contact and directly bond with each other via a hybrid bonding process, thus forming an electrical connection therebetween. For example, the first bonding pad BP1 and the second bonding pad BP2 can contact and couple with each other via a metal-to-metal bonding process, and the first bonding insulating layer BD1 and the second bonding insulating layer BD2 can contact and couple with each other via a dielectric-to-dielectric bonding process. The first bonding pad BP1 and the second bonding pad BP2 can provide an electrical connection path based on the bonding between the first semiconductor structure S1 and the second semiconductor structure S2.

[0063] The capacitor structure CS in the semiconductor device 100 according to the present invention can correspond to a plurality of pump capacitors CP (see Figure 2 ) or output capacitor COUT (see Figure 2 Furthermore, a portion of the multilayer wiring structure ML can be replaced by a replacement process, thereby increasing the area of ​​the capacitor structure CS and improving its electrical characteristics and reliability. See below for reference. Figures 6 to 12 Describe in detail the technical features of the capacitor structure CS.

[0064] Figure 6 This is a plan view showing the capacitor structure of the semiconductor device according to an embodiment at the LV1, LV2 and LV3 levels. Figure 7 It is along Figure 6 The cross-sectional view of the capacitor structure taken by lines CX1, CX2 and CX3. Figure 8 It is shown Figure 7 A cross-sectional view comparing the wiring area and a portion of the area. Figure 9 yes Figure 7 A magnified view of region BB. Figure 10 yes Figure 7 A magnified view of region CC. Figure 11 yes Figure 7 A magnified view of region DD. Figure 12 yes Figure 7 A magnified view of the EE region.

[0065] Reference Figures 6 to 12 In the semiconductor device 100, the first semiconductor structure S1 may include a capacitor structure CS.

[0066] The capacitor structure CS conceived according to the present invention may include a metal-insulator-metal (MIM) capacitor. The capacitor structure CS may include a first electrode layer EL1 conformally formed along the inner wall of a recessed region RA that at least partially passes through a multilayer insulating structure DL, a capacitor dielectric layer CDL conformally formed along the inner wall of the first electrode layer EL1, and a second electrode layer EL2 that contacts and fills the recessed region RA with the inner wall of the capacitor dielectric layer CDL. In this case, the first electrode layer EL1 may be referred to as the lower electrode, and the second electrode layer EL2 may be referred to as the upper electrode.

[0067] In the capacitor structure CS conceived according to the present invention, a first via RV1 can contact and be electrically connected to a first electrode layer EL1, and a second via RV2 can contact and be electrically connected to a second electrode layer EL2. In this case, at least a portion of the first via RV1 that contacts the upper surface of the first electrode layer EL1 can be located at the same vertical level as at least a portion of the second via RV2 that contacts the upper surface of the second electrode layer EL2.

[0068] Specifically, both the first via RV1 and the second via RV2 can be positioned above the capacitor structure CS. Furthermore, the uppermost point of the first via RV1 can be at substantially the same vertical level as the uppermost point of the second via RV2, and the lowermost point of the first via RV1 can be at a lower vertical level than the lowermost point of the second via RV2. As used herein, and as those skilled in the art will understand, the expression "substantially the same" can mean having the same value relative to other(one or more) values ​​compared with it, and allows for approximations, inaccuracies, and measurement limits in the relevant context. In one or more aspects, the terms "substantially," "about," and "approximately" can provide industry-accepted tolerances and / or relativity between items for their corresponding terms, such as tolerances of ±1%, ±5%, or ±10% of stated actual values, and other suitable tolerances.

[0069] In the capacitor structure CS conceived according to the present invention, the first via RV1 and the second via RV2 each extend through the fifth insulating layer D5 of the multilayer insulating structure DL. The first via RV1 and the second via RV2 are electrically connected to the unit wiring structure 180 via the first bonding via BV1, the first bonding pad BP1, the second bonding pad BP2, and the second bonding via BV2. Subsequently, the first via RV1 and the second via RV2 are electrically connected to the input / output pad IOP via the unit wiring structure 180 and the through-hole plug 170.

[0070] In other words, in the semiconductor device 100 according to the present invention, the capacitor structure CS of the first semiconductor structure S1 can be used as a charge pump circuit 56 via the input / output pad IOP of the second semiconductor structure S2 (see Figure 2 Operate on the components of ).

[0071] In the semiconductor device 100 conceived according to the present invention, the recessed region RA may include a plurality of recessed patterns RP extending in the vertical direction Z and spaced apart from each other in the horizontal direction (X or Y). Here, a connector region TA may exist, wherein the uppermost ends of some of the recessed patterns RP located below the first via RV1 are at a vertical level lower than the uppermost ends of other recessed patterns RP. That is, the uppermost end of the portion of the second electrode layer EL2 located below the first via RV1 may be at a vertical level lower than the uppermost ends of other portions of the second electrode layer EL2. The connector region TA may represent an insulating region for preventing contact between the first via RV1 and the second electrode layer EL2.

[0072] In the capacitor structure CS conceived according to the present invention, the first electrode layer EL1, the capacitor dielectric layer CDL, and the second electrode layer EL2 can completely fill a plurality of recessed patterns RP and extend continuously in the horizontal direction (X or Y) while being connected to each other. Furthermore, the first electrode layer EL1, the capacitor dielectric layer CDL, and the second electrode layer EL2 can extend through the capping insulating layer CL of the multilayer insulating structure DL and extend longitudinally in the vertical direction Z.

[0073] The first electrode layer EL1 located on the sidewall of each of the plurality of recessed patterns RP may have a plurality of curved segments CV spaced apart from each other in the vertical direction Z, and the vertical level of the plurality of curved segments CV may be substantially the same as the vertical level of the bonding interface IF of the multilayer wiring structure ML. In some embodiments, at least some of the plurality of curved segments CV may have a rounded shape.

[0074] Based on these characteristics, in the manufacturing process described below, the interior of the multiple wiring openings MLH can be cleaned, and a wet etching process can be performed on them if necessary. Therefore, the multiple recessed patterns RP can have a relatively wider interior than the multiple wiring openings MLH. Furthermore, the inner walls of the multiple recessed patterns RP can have a relatively smooth (or rounded) shape compared to the inner walls of the multiple wiring openings MLH.

[0075] In some cross-sections of the capacitor structure CS conceived according to the present invention, the first electrode layer EL1, the capacitor dielectric layer CDL, and the second electrode layer EL2 can be separated from each other in the vertical direction Z to form a completely closed curved surface. That is, since the capacitor structure CS is formed to be relatively long in the vertical direction Z, it is necessary to prevent the capacitor structure CS from being skewed. Therefore, the support region SA in which the second insulating layer D2 is continuously and longitudinally formed in the first horizontal direction X can be provided in the middle region of the capacitor structure CS to serve as a support.

[0076] Finally, the capacitor structure CS in the semiconductor device 100 according to the present invention can be formed by partially replacing the multilayer wiring structure ML in the wiring region MA via a replacement process. Therefore, the area of ​​the capacitor structure CS can be increased, and it can be used for various voltage bands depending on the adjustment of the thickness of the capacitor dielectric layer CDL, thereby improving the electrical characteristics and reliability of the semiconductor device 100 including the capacitor structure CS.

[0077] Figures 13 to 15 This is a cross-sectional view showing semiconductor devices 100A, 100B, and 100C according to some embodiments.

[0078] Most of the components constituting the semiconductor devices 100A, 100B, and 100C described below, and the materials constituting these components, are the same as described above. Figures 4 to 12 Those described herein are substantially the same or similar. Therefore, for ease of description, the description focuses on the differences from the semiconductor device 100 described above.

[0079] Reference Figure 13 In the semiconductor device 100A, the first semiconductor structure S1 may include a capacitor structure CS_A.

[0080] In the semiconductor device 100A according to an embodiment, the capacitor structure CS_A may include a first electrode layer EL1 formed conformally along the inner wall of a recessed region RA that at least partially passes through the multilayer insulating structure DL, a capacitor dielectric layer CDL formed conformally along the inner wall of the first electrode layer EL1, and a second electrode layer EL2 that contacts the inner wall of the capacitor dielectric layer CDL and fills the recessed region RA.

[0081] In the semiconductor device 100A according to the embodiment, the recessed region RA may overlap with the peripheral circuit device PC in the vertical direction Z, and the lowermost surface of the recessed region RA may be located at a vertical level lower than the uppermost surface of the peripheral circuit device PC. That is, the first electrode layer EL1 of the capacitor structure CS_A may extend through the circuit gate capping layer GC and may be integrally formed with the circuit gate electrode layer GE. In this case, the peripheral circuit device PC may not operate as a transistor and may constitute part of the capacitor structure CS_A.

[0082] Reference Figure 14 In the semiconductor device 100B, the first semiconductor structure S1 may include a capacitor structure CS_B.

[0083] In the semiconductor device 100B according to an embodiment, the capacitor structure CS_B may include a first electrode layer EL1 formed conformally along the inner wall of a recessed region RA that at least partially passes through the multilayer insulating structure DL, a capacitor dielectric layer CDL formed conformally along the inner wall of the first electrode layer EL1, and a second electrode layer EL2 that contacts the inner wall of the capacitor dielectric layer CDL and fills the recessed region RA.

[0084] In the semiconductor device 100B according to an embodiment, the recessed region RA may overlap with the device isolation region STI in the vertical direction Z, and the lowermost surface of the recessed region RA may be located at a vertical level lower than the uppermost surface of the device isolation region STI. That is, the capacitor structure CS_B may extend through at least a portion (or the upper part) of the device isolation region STI.

[0085] Reference Figure 15 In the semiconductor device 100C, the first semiconductor structure S1 may include a capacitor structure CS_C.

[0086] In the semiconductor device 100C according to an embodiment, the capacitor structure CS_C may include a first electrode layer EL1 formed conformally along the inner wall of a recessed region RA that at least partially passes through the multilayer insulating structure DL, a capacitor dielectric layer CDL formed conformally along the inner wall of the first electrode layer EL1, and a second electrode layer EL2 that contacts the inner wall of the capacitor dielectric layer CDL and fills the recessed region RA.

[0087] In the semiconductor device 100C according to an embodiment, the capacitor structure CS_C may overlap in the vertical direction Z with the lowermost wiring layer M0 and the first wiring layer M1 among a plurality of wiring layers M0 to M5, and the lowermost via layer V0 and the first via layer V1 among a plurality of via layers V0 to V5. In this case, the lowermost end of the capacitor structure CS_C may be located at various vertical levels. That is, the lowermost surface of at least one of the plurality of recessed patterns RP may be located at a vertical level different from the lowermost surfaces of the other recessed patterns RP. Therefore, the multilayer wiring structure ML may be partially located in the internal space IA between the capacitor structures CS_C, thereby increasing the degree of freedom of wiring.

[0088] Figure 16 This is a flowchart illustrating a semiconductor device manufacturing method according to an embodiment.

[0089] Reference Figure 16The semiconductor device manufacturing method S10 may include a first operation S110 to an eighth operation S180.

[0090] When embodiments can be implemented in different ways, the specific process sequence may differ from the sequence described below. For example, two processes described consecutively may be performed substantially simultaneously or in the reverse order of their description.

[0091] The semiconductor device manufacturing method S10 according to the present invention may include: a first operation S110, preparing a substrate including a first region and a second region surrounding the first region; a second operation S120, sequentially forming a plurality of wiring layers, a plurality of via layers, and a plurality of insulating layers, wherein the plurality of wiring layers and the plurality of via layers are alternately arranged in the first region and the second region in a vertical direction, and the plurality of insulating layers surround the wiring layers and the via layers; a third operation S130, removing the plurality of wiring layers and the plurality of via layers from the first region; and a fourth operation S140, forming a plurality of recessed patterns by expanding the space of the first region, wherein... Multiple wiring layers and multiple via layers are removed from the space in the first region; in the fifth operation S150, a first electrode layer is formed that conformally covers the inner wall of multiple recessed patterns and the upper surface of multiple insulating layers; in the sixth operation S160, a capacitor dielectric layer is formed that conformally covers the inner wall and upper surface of the first electrode layer; in the seventh operation S170, a second electrode layer is formed that contacts and fills the multiple recessed patterns with the inner wall and upper surface of the capacitor dielectric layer; and in the eighth operation S180, a first wiring via that contacts the upper surface of the first electrode layer and a second wiring via that contacts the upper surface of the second electrode layer.

[0092] The following reference Figures 17 to 27 The technical features of each of the first operation S110 to the eighth operation S180 are described in detail.

[0093] Figures 17 to 27 This is a cross-sectional view showing the process sequence of a semiconductor device manufacturing method according to an embodiment.

[0094] Reference Figure 17 A first substrate SS on which peripheral circuit devices PC are formed can be prepared.

[0095] The first substrate SS may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0096] Next, multiple wiring layers M0 to M4, multiple via layers V0 to V4, and multiple insulating layers D0 to D4 surrounding the wiring layers M0 to M4 and the via layers V0 to V4 can be sequentially formed on the first substrate SS in the vertical direction Z. A capping insulating layer CL can be formed at each of the interlayer interfaces between the multiple insulating layers D0 to D4.

[0097] Specifically, a bottommost insulating layer D0 and a capping insulating layer CL can be formed on a first substrate SS. Then, the bottommost insulating layer D0 and the capping insulating layer CL are patterned using a dry etching process to form a recess. Next, the bottommost via layer V0 and the bottommost wiring layer M0 can fill the recess. By repeating a process similar to the above, a multilayer wiring structure ML and a multilayer insulating structure DL can be formed on the first substrate SS. Therefore, each of the plurality of wiring layers M0 to M4 and the plurality of via layers V0 to V4 can have a tapered shape with a width decreasing towards the first substrate SS.

[0098] Reference Figure 18 It can partially remove the location located Figure 17 The topmost sealing insulation layer CL in the resulting structure forms a sealing opening CLH that exposes the fourth wiring layer M4.

[0099] A photomask (not shown) can be formed on the topmost capping insulating layer CL using an exposure and development process. Then, by using the photomask as an etching mask, an etching process can be performed on the topmost capping insulating layer CL to form the capping opening CLH.

[0100] The aforementioned exposure, development, and etching processes are well known to those skilled in the art, and therefore, their detailed descriptions are omitted here.

[0101] After the capping opening CLH is formed, the photomask can be removed through ashing and stripping processes.

[0102] Reference Figure 19 It can be removed sequentially and completely in Figure 18 The resulting structure exposes the multilayer wiring structure ML.

[0103] Specifically, the fourth wiring layer M4 and the fourth via layer V4 can be removed; the third wiring layer M3 and the third via layer V3 exposed by removing the fourth wiring layer M4 and the fourth via layer V4 can be removed; the second wiring layer M2 and the second via layer V2 exposed by removing the third wiring layer M3 and the third via layer V3 can be removed; the first wiring layer M1 and the first via layer V1 exposed by removing the second wiring layer M2 and the second via layer V2 can be removed; and the bottommost wiring layer M0 and the bottommost via layer V0 exposed by removing the first wiring layer M1 and the first via layer V1 can be removed.

[0104] As a result, multiple wiring openings MLH can extend longitudinally along the vertical direction Z inside the multilayer insulation structure DL.

[0105] Reference Figure 20 Washable Figure 19The resulting structure contains multiple wiring openings MLH inside, and a wet etching process can be performed on them if necessary. Thus, multiple recessed patterns RP can be formed.

[0106] Depending on the cleaning and wet etching processes, the recessed patterns RP can have a relatively wider interior than the multiple wiring openings MLH. Furthermore, the inner walls of the recessed patterns RP can have a relatively smooth (or rounded) shape compared to the inner walls of the multiple wiring openings MLH.

[0107] Each of the multiple recessed patterns RP may have sidewalls with multiple curved segments spaced apart from each other in the vertical direction Z, and the multiple curved segments may be formed by multiple wiring layers M0 to M4 (see...). Figure 18 ) and multiple via layers V0 to V4 (see Figure 18 The characteristics resulting from the conical shape of the cone and the interface between them.

[0108] Reference Figure 21 , can Figure 20 The resulting structure forms a first electrode layer EL1 to conformally cover the inner wall of multiple recessed patterns RP, the upper surface of the fourth insulating layer D4, and the uppermost capping insulating layer CL.

[0109] The first electrode layer EL1 can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0110] The first electrode layer EL1 may include any one of a metal nitride, a metal, or a combination thereof. For example, the first electrode layer EL1 may include at least one selected from the group consisting of TiN, TaN, WN, Ru, Pt, and Ir.

[0111] Reference Figure 22 , can Figure 21 A capacitor dielectric layer CDL is formed in the resulting structure to conformally cover the inner wall and upper surface of the first electrode layer EL1.

[0112] The capacitor dielectric layer (CDL) may include at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and high-k dielectric materials.

[0113] The capacitor dielectric layer CDL can electrically separate the first electrode layer EL1 from the second electrode layer EL2 formed in a subsequent process, thereby enabling it to be used as a capacitor.

[0114] Reference Figure 23 , can Figure 22 The resulting structure forms a second electrode layer EL2, which contacts the inner wall and upper surface of the capacitor dielectric layer CDL and completely fills the multiple recessed patterns RP.

[0115] The second electrode layer EL2 can be formed by CVD or ALD processes.

[0116] The second electrode layer EL2 may include any one of a metal nitride, a metal, or a combination thereof. For example, the second electrode layer EL2 may include at least one selected from the group consisting of TiN, TaN, WN, Ru, Pt, and Ir.

[0117] Reference Figure 24 ,exist Figure 23 In the resulting structure, a capping insulating layer CL can be formed on the second electrode layer EL2.

[0118] Next, a photomask (not shown) can be formed on the capping insulating layer CL by an exposure process and a development process. Then, an etching process can be performed on the capping insulating layer CL by using the photomask as an etching mask to form the first opening CLH1 and the second opening CLH2.

[0119] The first opening CLH1 can be formed by removing the capping insulating layer CL and the second electrode layer EL2 above the connector area TA. Alternatively, the second opening CLH2 can be formed by removing the capping insulating layer CL, the second electrode layer EL2, the capacitor dielectric layer CDL, and the first electrode layer EL1 on the edge region.

[0120] The aforementioned exposure, development, and etching processes are well known to those skilled in the art, and therefore, their detailed descriptions are omitted here.

[0121] Reference Figure 25 , can Figure 24 A fifth insulating layer D5 is formed in the resulting structure to cover the first opening CLH1 and the second opening CLH2.

[0122] Next, the first via RV1 and the second via RV2 can extend through the fifth insulating layer D5. The first via RV1 can be formed on the connector area TA such that the first via RV1 contacts the upper surface of the first electrode layer EL1, and the second via RV2 can be formed around the connector area TA such that the second via RV2 contacts the upper surface of the second electrode layer EL2.

[0123] In other words, at least a portion of the first trace via RV1 can be formed at the same vertical level as at least a portion of the second trace via RV2.

[0124] Reference Figure 26 The first semiconductor structure S1 may include Figure 25 The resulting structure.

[0125] Specifically, the first bonding via BV1 and the first bonding pad BP1 can be connected to the multilayer wiring structure ML and the capacitor structure CS, and the first bonding insulating layer BD1 can surround the first bonding pad BP1. Therefore, the first semiconductor structure S1 can be fabricated.

[0126] Reference Figure 27 The second semiconductor structure S2 can be set in Figure 26 The resulting structure.

[0127] The details of the second semiconductor structure S2 are substantially the same as those described above, and therefore, its detailed description is omitted here.

[0128] The first bonding pad BP1 of the first semiconductor structure S1 can be aligned with the second bonding pad BP2 of the second semiconductor structure S2 in the vertical direction Z.

[0129] Next, the first semiconductor structure S1 can be contacted and directly bonded to the second semiconductor structure S2 via hybrid bonding. Therefore, a semiconductor device 100 according to the present invention can be manufactured (see...). Figure 5 ).

[0130] Figure 28 This is a diagram illustrating a data storage system 1000 including a semiconductor device according to an embodiment.

[0131] Reference Figure 28 The data storage system 1000 according to the present invention may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100.

[0132] Data storage system 1000 may represent a storage device including a semiconductor device 1100 or an electronic device including a storage device. For example, data storage system 1000 may include a solid-state drive (SSD) device containing at least one semiconductor device 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0133] Semiconductor device 1100 may include a non-volatile vertical memory device. For example, semiconductor device 1100 may represent a device including the above-mentioned references. Figures 1 to 15The semiconductor devices 1100, 100A, 100B, and 100C described herein are NAND flash memory devices. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some embodiments, the first structure 1100F may be located adjacent to the second structure 1100S. The first structure 1100F may represent a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and logic circuitry 1130. The second structure 1100S may include a memory cell structure including a bit line BL, a common-source line CSL, multiple word lines WL, a first gate-up line UL1 and a second gate-up line UL2, a first gate-down line LL1 and a second gate-down line LL2, and multiple memory cell strings CSTRs disposed between the bit line BL and the common-source line CSL.

[0134] In the second structure 1100S, each of the plurality of memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be modified differently depending on the embodiment.

[0135] In some embodiments, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Multiple lower gate lines LL1 and LL2 may each include the gate electrodes of the lower transistors LT1 and LT2. A word line WL may include the gate electrode of a memory cell transistor MCT, and upper gate lines UL1 and UL2 may include the gate electrodes of the upper transistors UT1 and UT2.

[0136] The common-source line CSL, multiple gate lower lines LL1 and LL2, multiple word lines WL, and multiple gate upper lines UL1 and UL2 can be electrically connected to the decoder circuit 1110 via multiple first connection lines 1115 disposed inside the first structure 1100F and extending to the second structure 1100S. Multiple bit lines BL can be electrically connected to the page buffer 1120 via multiple second connection lines 1125 disposed inside the first structure 1100F and extending to the second structure 1100S.

[0137] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one of the plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130.

[0138] Semiconductor device 1100 can communicate with controller 1200 via input / output pads 1101 electrically connected to logic circuit 1130. Input / output pads 1101 can be electrically connected to logic circuit 1130 via input / output connection lines 1135 disposed inside the first structure 1100F and extending to the second structure 1100S.

[0139] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100. In this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0140] Processor 1210 controls all operations of the data storage system 1000, including controller 1200. Processor 1210 operates according to specific firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include NAND interface 1221 for processing communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be written to the plurality of memory cell transistors (MCTs) of semiconductor device 1100, and data read from the plurality of memory cell transistors (MCTs) of semiconductor device 1100 can be sent via NAND interface 1221. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When a control command is received from an external host via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0141] Figure 29 This is a perspective view showing a data storage system 2000 including a semiconductor device according to an embodiment.

[0142] Reference Figure 29 The data storage system 2000 according to an embodiment may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003, and dynamic random access memory (DRAM) 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via a plurality of wiring patterns 2005 formed on the motherboard 2001.

[0143] The motherboard 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In some embodiments, the data storage system 2000 may communicate with the external host via any of an interface such as USB, PCI-Express, Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Memory (UFS). In some embodiments, the data storage system 2000 may be operated by power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0144] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0145] DRAM 2004 may include a buffer memory for reducing the speed difference between an external host and the semiconductor package 2003, which includes data storage space. DRAM 2004 in data storage system 2000 may also operate as a cache memory and provide space for temporarily storing data during operation of the semiconductor package 2003. When data storage system 2000 includes DRAM 2004, controller 2002 may also include a DRAM controller for controlling DRAM 2004, in addition to a NAND controller for controlling semiconductor package 2003.

[0146] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package plate 2100, a plurality of semiconductor chips 2200 on the package plate 2100, an adhesive layer 2300 disposed on the lower surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 electrically connecting the plurality of semiconductor chips 2200 to the package plate 2100, and a molding layer 2500 covering the plurality of semiconductor chips 2200 and the connection structure 2400 on the package plate 2100.

[0147] Package board 2100 may include a printed circuit board including a plurality of package-on-package pads 2130. Each of the plurality of semiconductor chips 2200 may include an input / output pad 2201. Input / output pad 2201 may correspond to input / output pad 1101 (see See Package 2100). Figure 28 Each of the plurality of semiconductor chips 2200 may include the above reference. Figures 1 to 15 At least one of the described semiconductor devices 100, 100A, 100B and 100C.

[0148] In one embodiment, the connection structure 2400 may include bonding wires electrically connecting the input / output pads 2201 to the on-package pads 2130. Therefore, in the first semiconductor package 2003a and the second semiconductor package 2003b, a plurality of semiconductor chips 2200 may be electrically connected to each other using a bonding wire method and may be electrically connected to the on-package pads 2130 of the package board 2100. In some embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, a plurality of semiconductor chips 2200 may be electrically connected to each other using a connection structure including a through-silicon via (TSV) instead of the connection structure 2400 in the bonding wire method.

[0149] In some embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be included in a single package. In some embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be mounted on a separate insert board different from the motherboard 2001, and the controller 2002 and the plurality of semiconductor chips 2200 may be interconnected with each other via wiring formed on the insert board.

[0150] Figure 30 This is a cross-sectional view showing a semiconductor package 2003 including a semiconductor device according to an embodiment.

[0151] Reference Figure 30 In the semiconductor package 2003, the package board 2100 may include a printed circuit board.

[0152] The package board 2100 may include a body 2120 and a package pad 2130 disposed on the upper surface of the body 2120 (see Figure 29 ), and the package lower pad 2125 disposed on or exposed on the lower surface of the body 2120, and the package upper pad 2130 disposed inside the body 2120 (see Figure 29 It is electrically connected to the inner wiring 2135 of the pad 2125 under the package.

[0153] Multiple lower pads 2125 can be connected to the motherboard 2001 via multiple conductive bumps 2800 (see...) Figure 29Multiple wiring patterns 2005 on the semiconductor chip 2200. Each of the multiple semiconductor chips 2200 may include the above reference. Figures 1 to 15 At least one of the described semiconductor devices 100, 100A, 100B and 100C.

[0154] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A peripheral circuit structure includes a substrate having an active region defined by a device isolation region, peripheral circuit devices on the active region, a multilayer wiring structure connected to the peripheral circuit devices, a multilayer insulating structure surrounding the multilayer wiring structure, a capacitor structure spaced horizontally from the multilayer wiring structure and extending at least partially through the multilayer insulating structure, and a first bonding pad connected to the multilayer wiring structure and the capacitor structure. as well as A memory cell structure includes a passivation layer having cell regions and pad regions, gate electrodes stacked in the cell regions and spaced apart from each other in a vertical direction, a channel structure extending through the gate electrodes, input / output pads located in the pad regions, a cover insulating layer covering the cell regions and the pad regions, a through-hole extending through the cover insulating layer in the pad regions and connected to the input / output pads, a cell wiring structure connected to the channel structure and the through-hole, and a second bonding pad connected to the cell wiring structure. The capacitor structure includes a first electrode layer conformally formed on the inner wall of a recessed region extending at least partially through the multilayer insulating structure, a capacitor dielectric layer conformally formed on the inner wall of the first electrode layer, and a second electrode layer contacting and filling the recessed region with the inner wall of the capacitor dielectric layer. At least a portion of the first trace via that contacts the upper surface of the first electrode layer and at least a portion of the second trace via that contacts the upper surface of the second electrode layer are located at the same vertical level.

2. The semiconductor device according to claim 1, wherein, The memory cell structure is stacked on the peripheral circuit structure, and The first bonding pads are bonded to the second bonding pads respectively.

3. The semiconductor device according to claim 2, wherein, The capacitor structure overlaps with the pad area in the vertical direction, while offset from the cell area in the vertical direction.

4. The semiconductor device according to claim 3, wherein, The first trace via and the second trace via are each electrically connected to the input / output pads via one of the first bonding pads, one of the second bonding pads, and the through plug.

5. The semiconductor device according to claim 1, wherein, The recessed area includes a plurality of recessed patterns extending in the vertical direction and spaced apart from each other in the horizontal direction, and The first electrode layer, the capacitor dielectric layer, and the second electrode layer fill the plurality of recessed patterns and extend in the horizontal direction.

6. The semiconductor device according to claim 5, wherein, The first electrode layer, the capacitor dielectric layer, and the second electrode layer extend through the interlayer interfaces of the multiple insulating layers of the multilayer insulating structure and extend longitudinally in the vertical direction.

7. The semiconductor device according to claim 6, wherein, The sidewalls of the first electrode layer located in each of the plurality of recessed patterns have a plurality of curved segments in the vertical direction, and The vertical level of the multiple curved sections is the same as the vertical level of the joint interface of the multiple wiring layers of the multi-layer wiring structure.

8. The semiconductor device according to claim 7, wherein, The capacitor dielectric layer has an uneven shape corresponding to the plurality of curved sections.

9. The semiconductor device according to claim 1, wherein, The lowest point of the first trace via is located at a vertical level that is lower than the lowest point of the second trace via.

10. The semiconductor device according to claim 9, wherein, The uppermost part of the portion of the second electrode layer located below the first trace via is at a vertical level that is lower than the uppermost part of the other portions of the second electrode layer.

11. A semiconductor device, comprising: Substrate having an active region defined by a device isolation region; Peripheral circuit devices, located in the active region; A multilayer wiring structure includes multiple wiring layers connected to the peripheral circuit devices and multiple via layers that connect the multiple wiring layers to each other in the vertical direction. A multilayer insulating structure comprising multiple insulating layers surrounding the plurality of wiring layers and the plurality of via layers; The recessed region includes a plurality of recessed patterns that are spaced apart in the horizontal direction from the multilayer wiring structure and extend at least partially through the multilayer insulation structure; The first electrode layer is conformally arranged along the inner wall of the plurality of recessed patterns and the upper surface of the multilayer insulating structure; A capacitor dielectric layer, which is conformally arranged along the inner wall and upper surface of the first electrode layer; The second electrode layer is in contact with the inner wall and upper surface of the capacitor dielectric layer and fills the plurality of recessed patterns; The first trace via is in contact with the upper surface of the first electrode layer; as well as The second trace via is in contact with the upper surface of the second electrode layer. The sidewall of the first electrode layer in each of the plurality of recessed patterns has a plurality of curved sections in the vertical direction.

12. The semiconductor device according to claim 11, wherein, The vertical horizontal plane of the plurality of curved sections is the same as the vertical horizontal plane of the interface between the plurality of wiring layers and the plurality of via layers, and The capacitor dielectric layer has an uneven shape corresponding to the plurality of curved sections.

13. The semiconductor device according to claim 11, wherein, The uppermost end of the first trace via is located at the same vertical level as the uppermost end of the second trace via, and The lowest point of the first trace via is located at a vertical level that is lower than the lowest point of the second trace via.

14. The semiconductor device according to claim 11, wherein, The first electrode layer extends as a single conductive layer along the plurality of recessed patterns.

15. The semiconductor device according to claim 14, wherein, The first electrode layer overlaps with the peripheral circuit device in the vertical direction, and The lowest surface of the first electrode layer is located at a vertical level that is higher than the highest surface of the peripheral circuit device.

16. The semiconductor device according to claim 14, wherein, The first electrode layer overlaps with the peripheral circuit device in the vertical direction, and The lowest surface of the first electrode layer is located at a vertical level lower than the highest surface of the peripheral circuit device.

17. The semiconductor device according to claim 14, wherein, The first electrode layer extends through the upper part of the isolation region of the device.

18. The semiconductor device according to claim 14, wherein, The first electrode layer overlaps with the lower wiring layer among the plurality of wiring layers and the lower via layer among the plurality of via layers in the vertical direction, and The lowest surface of a portion of the first electrode layer is located at a vertical level different from the lowest surface of the other portions of the first electrode layer.

19. A data storage system, comprising a motherboard, a semiconductor device on the motherboard, and a controller disposed on the motherboard and electrically connected to the semiconductor device. in, The semiconductor device includes a peripheral circuit structure and a memory cell structure disposed on the peripheral circuit structure. The peripheral circuit structure includes a substrate having an active region defined by a device isolation region, peripheral circuit devices on the active region, a multilayer wiring structure connected to the peripheral circuit devices, a multilayer insulating structure surrounding the multilayer wiring structure, a capacitor structure horizontally spaced from and at least partially extending through the multilayer insulating structure, and a first bonding pad connected to the multilayer wiring structure and the capacitor structure. The memory cell structure includes a passivation layer having cell regions and pad regions, gate electrodes stacked in the cell regions and spaced apart from each other in a vertical direction, a channel structure extending through the gate electrodes, input / output pads located in the pad regions, a cover insulating layer covering the cell regions and pad regions, a through-hole plug extending through the cover insulating layer in the pad regions and connected to the input / output pads, a cell wiring structure connected to the channel structure and the through-hole plug, and a second bonding pad connected to the cell wiring structure. The capacitor structure includes a first electrode layer conformally formed on the inner wall of a recessed region extending at least partially through the multilayer insulation structure, a capacitor dielectric layer conformally formed on the inner wall of the first electrode layer, and a second electrode layer contacting the inner wall of the capacitor dielectric layer and filling the recessed region. At least a portion of the first trace via contacting the upper surface of the first electrode layer and at least a portion of the second trace via contacting the upper surface of the second electrode layer are located at the same vertical level, and The first bonding pad is bonded to the second bonding pad respectively.

20. The data storage system according to claim 19, wherein, The motherboard also includes wiring patterns for electrically connecting the semiconductor devices to the controller. The first trace via and the second trace via are each electrically connected to the input / output pads via one of the first bonding pads, one of the second bonding pads, and the through plug, and The input / output pads are electrically connected to the wiring pattern.

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