A method for manufacturing a three-dimensional sidewall cavity ferroelectric memory and a structure thereof

Abstract

This invention discloses a method and structure for fabricating a three-dimensional sidewall cavity ferroelectric memory. Based on standard CMOS back-end processes, it achieves electrical isolation between the vertical stacking of ferroelectric capacitors and the metal circuitry. An alternating stacked structure is fabricated using silicon dioxide as the interlayer dielectric, metal as the interconnect layer, and silicon carbide as the selective sacrificial layer. By composited with a silicon nitride sacrificial layer on each titanium nitride electrode plate, the etching difficulty of deep trenches in multilayer composite structures is reduced, enabling one-time deep trench etching of the multilayer stack. This invention further removes the silicon nitride sacrificial layer through selective lateral etching, forming independent lateral cavities on the sidewalls of each titanium nitride electrode plate. Stacked ferroelectric capacitor units are formed in the sidewall cavities of each layer by atomic deposition of the ferroelectric dielectric and electrode films. The bottom of the trench is etched through and filled with tungsten plugs as a common lead-out for one end of the capacitors in each layer. The other end of the capacitors is independently led out by step-by-step drilling of the titanium nitride electrode plates in each layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor non-volatile memory technology, and in particular to a method for fabricating a three-dimensional sidewall cavity ferroelectric memory and its structure. Background Technology

[0002] Ferroelectric random access memory (FeRAM) has long been considered a key candidate for next-generation high-performance memory technology due to its non-volatility, high-speed read / write, low power consumption, and excellent radiation resistance. Traditional FeRAM, based on perovskite-structured ferroelectric materials (such as PZT and SBT), has been commercialized, but faces challenges such as poor miniaturization, insufficient CMOS process compatibility, and lead contamination, making it difficult to meet the demands of high-density integration. The discovery of hafnium oxide-based ferroelectric materials has changed this situation. Doped hafnium oxide thin films maintain stable ferroelectricity at the sub-nanometer scale and are highly compatible with advanced CMOS processes. They can be fabricated using atomic layer deposition (ALD) to achieve high conformal film fabrication and are naturally suited for three-dimensional capacitor structures. Among these, Hf... 0.5 Zr 0.5 Due to its superior process repeatability and stable ferroelectric properties, O2 (HZO) has become the most widely adopted material system in academia and industry. Based on metal-HZO-metal (MFM) capacitors, which have been extensively studied, three-dimensional trench structure HZO-based ferroelectric capacitors have proven to be one of the most promising technical routes to meet the needs of high-density, low-power storage.

[0003] However, hafnium oxide-based ferroelectric memories still face several key challenges in achieving high-density 3D integration. In 3D stacked architectures, deep trenches need to be fabricated that penetrate multiple alternating dielectric layers and metal electrode plates. However, the etching rates and mechanisms of the multiple metal nitride (e.g., TiN) electrodes and dielectrics (e.g., SiO2) within the stacked layers differ significantly, making it impossible to achieve uniform, one-time penetration of the stacked layers. The metal layers not only obstruct the vertical transport of etching ions but also lead to large differences in trench morphology and insufficient trench bottom openings, severely impacting the step coverage quality of subsequent ALD deposition. Furthermore, existing 3D ferroelectric stacks often employ flat sidewall designs, lacking effective physical isolation structures, resulting in significant interlayer crosstalk and difficulty in ensuring the consistency of ferroelectric polarization across layers. The sidewall curvature strain and ALD step coverage differences introduced by the 3D trenches further exacerbate device performance fluctuations. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating a three-dimensional sidewall cavity ferroelectric memory and its structure, so as to solve the problems in the background art.

[0005] To address the aforementioned technical problems, this invention provides a method for fabricating a three-dimensional sidewall cavity ferroelectric memory, comprising the following steps: S1: A composite layer of silicon oxide, titanium nitride, and silicon nitride is alternately deposited on the wafer surface to form a periodic multilayer stacked structure; S2: Through hard mask dry etching, all silicon oxide and silicon nitride layers are vertically penetrated in one go to form a vertical deep trench, with the bottom of the trench falling on the surface of the silicon substrate; S3: Selective side etching using hot phosphoric acid wet etching is employed to remove silicon nitride from the sidewalls. The etching stops at the surface of titanium nitride, forming lateral cavities in each layer. S4: Ferroelectric capacitors are deposited on the inner wall of the cavity using ALD, wherein the capacitors include at least a lower electrode, a ferroelectric dielectric and an upper electrode; S5: Perform highly anisotropic reverse etching to vertically remove all ALD films at the bottom of the trench, exposing the silicon substrate surface and forming conductive openings at the bottom of the trench; S6: Deposit conductive material in the trench and backfill to level it out, forming a bottom conductive plug; S7: Annealed crystallized ferroelectric layer; S8: Lead out each layer of titanium nitride, deposit an interlayer dielectric layer, and fabricate vertical direct contact holes of different depths, filling them with metal to form independent vertical lead-out electrodes for each layer.

[0006] In one embodiment, step S1 includes: Silicon oxide and silicon nitride are deposited on the wafer surface, and some of the silicon nitride is removed by mask etching. Titanium nitride is deposited on the surface and CMP planarization is performed to expose silicon nitride; this completes one cycle of the multilayer stacked structure. Repeat the above steps to form a periodic multi-layer stacked structure, with the top layer covered by a hard mask layer to protect against subsequent etching.

[0007] In one embodiment, the depth of the cavity is adjusted according to the length of the silicon nitride sacrificial layer in step S1; the silicon oxide in each layer is retained to form upper and lower isolation protrusions, so that the overall trench has a gourd-shaped outline.

[0008] In one embodiment, the selection ratio of hot phosphoric acid for silicon nitride to titanium nitride in step S3 is greater than 100:1.

[0009] In one embodiment, the deposition of ferroelectric capacitors on the inner wall of the cavity using ALD includes: firstly, depositing 5-10 nm of titanium nitride as the lower electrode of the capacitor; then depositing 7-9 nm of HZO as the ferroelectric dielectric layer; and finally depositing 5-10 nm of titanium nitride as the upper electrode of the capacitor.

[0010] A three-dimensional sidewall cavity ferroelectric memory structure based on the above-described fabrication method includes: A multilayer composite stacked layer with periodic alternating stacking, wherein the composite stacked layer is composed of alternating silicon oxide (01) and composite functional layers, wherein the composite functional layers include titanium nitride (02) and silicon nitride (03) as a sacrificial layer. A vertical deep trench (04) runs through all stacked layers, and the bottom of the vertical deep trench (04) is provided with a conductive opening (07) that exposes the surface of the silicon substrate. After selectively etching away the silicon nitride (03) on each sidewall, a lateral cavity (05) is formed on the outside of each titanium nitride (02) layer, and each silicon oxide (01) is retained to form upper and lower isolation convex edges, thus forming a periodic gourd-shaped sidewall structure. Hafnium zirconium oxide deposited on the inner wall of each sidewall cavity (05) serves as a ferroelectric dielectric layer (06), and each layer of titanium nitride (02) forms an independent sidewall ferroelectric capacitor. A bottom conductive plug (08) is filled in the conductive opening (07) at the bottom of the vertical deep trench (04) to form a bottom vertical lead-out end; Each layer of titanium nitride placed on the periphery of the storage array has a stepped area with vertical independent metal contact holes (10) that penetrate to each layer of titanium nitride (02), forming independent vertical electrode leads out of each layer of titanium nitride.

[0011] In one embodiment, the ferroelectric capacitor is composed of a lower titanium nitride electrode layer, an HZO ferroelectric dielectric layer, and an upper titanium nitride electrode layer deposited sequentially by ALD.

[0012] This invention provides a method for fabricating a three-dimensional sidewall cavity ferroelectric memory and its structure. It innovatively introduces a silicon nitride sacrificial layer composite electrode structure, so that the initial etching system is composed entirely of silicon oxide and silicon nitride, avoiding the interference of the metal layer on deep etching. At the same time, physical isolation is achieved through the sidewall cavity, and through-hole and layer-by-layer lead-out schemes are designed to construct a complete three-dimensional architecture of "sidewall storage + vertical common terminal + independent addressing". Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a three-dimensional sidewall cavity ferroelectric memory structure containing a silicon nitride sacrificial layer, provided by the present invention.

[0014] Figure 2 This is a schematic diagram of the deposition and etching of silicon oxide and silicon nitride on the substrate surface.

[0015] Figure 3 A flowchart for completing a multi-layer stacked structure in one cycle.

[0016] Figure 4 A schematic diagram illustrating the formation of a periodic multi-layered stacked structure.

[0017] Figure 5 This is a schematic diagram of a single vertical deep groove etching process.

[0018] Figure 6 This is a schematic diagram of selective lateral erosion forming sidewall cavities.

[0019] Figure 7 This is a schematic diagram of an ALD-deposited ferroelectric capacitor stack.

[0020] Figure 8 This is a schematic diagram of anisotropic reverse engraving to penetrate the bottom of the groove.

[0021] Figure 9 This is a schematic diagram of tungsten plug filling.

[0022] Figure 10 This is a schematic diagram of the first step of the independent vertical lead-out of the layered capacitors.

[0023] Figure 11 This is a schematic diagram of the second step, showing the independent vertical leads of the capacitors layer by layer. Detailed Implementation

[0024] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for fabricating a three-dimensional sidewall cavity ferroelectric memory and its structure according to the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0025] This invention provides a specific method for fabricating a three-dimensional sidewall cavity ferroelectric memory containing a silicon nitride sacrificial layer. The fabricated three-dimensional sidewall cavity ferroelectric memory structure is as follows: Figure 1 As shown, the method includes the following steps: Step S1: Periodic multi-layer stacked deposition.

[0026] like Figure 2 As shown, silicon oxide O1 and silicon nitride O3 are deposited on the surface of an inch silicon substrate using plasma-enhanced chemical vapor deposition, and part of the silicon nitride O3 is removed by mask etching. like Figure 3 As shown, titanium nitride O2 is deposited on the surface and CMP planarization is performed to expose silicon nitride O3; this completes one cycle of the multilayer stacked structure. Repeat the above steps to form a periodic multi-layered stacked structure, with the top layer covered by a hard mask layer to protect against subsequent etching, such as... Figure 4 As shown.

[0027] Step S2: One-time vertical deep trench etching.

[0028] Vertical deep trench regions are defined using photolithography, and all silicon oxide and silicon nitride dielectric layers are etched through in one pass using etching equipment to form vertical deep trench 04, with the trench bottom stopping at the surface of the silicon substrate. Figure 5 As shown.

[0029] In this step, because the etching system contains only two media, SiO2 and SiN, the etching rate is uniform, there is no metal residue or abnormal cone angle, which ensures the high aspect ratio of the trench etching quality.

[0030] Step S3: Selective lateral erosion forms sidewall cavities.

[0031] The above structure was selectively etched using a hot phosphoric acid wet bath. The selectivity ratio of hot phosphoric acid for silicon nitride, silicon oxide, and titanium nitride was greater than 100:1. Each silicon nitride sacrificial layer 03 was laterally hollowed out, and the etching automatically stopped at the surface of the inner titanium nitride electrode 02, forming a sidewall cavity 05. Figure 6 As shown.

[0032] The cavity depth can be adjusted according to the length of the silicon nitride sacrificial layer in step S1. The upper and lower silicon oxide isolation layers 01 are retained to form upper and lower isolation protrusions, making the overall trench have a gourd-shaped outline, providing an independent reaction space for subsequent capacitor deposition.

[0033] Step S4: ALD deposition of ferroelectric capacitor stack.

[0034] After being cleaned with ultrapure water and dried with nitrogen, cavity 05 is placed into the ALD reaction chamber. Capacitor deposition is then performed sequentially: first, 5-10 nm of titanium nitride is deposited as the lower electrode (which can be fused with the existing plate 02 to reduce resistance); then, 7-9 nm of HZO is deposited as the ferroelectric dielectric layer 06; finally, 5-10 nm of titanium nitride is deposited as the upper electrode, as shown below. Figure 7 As shown.

[0035] Step S5: Anisotropic reverse engraving to open the bottom of the groove.

[0036] After the capacitor stack is completed, a highly anisotropic reverse etching process is performed to form deep trenches and trench bottom openings (07), such as... Figure 8 As shown.

[0037] Thanks to the inwardly recessed geometry of the lateral cavities 05 in each layer, vertically incident etching ions cannot bombard the ferroelectric capacitors inside the cavities. The shadowing effect formed by this structure itself ensures that the ferroelectric thin film on the inner wall of the cavity remains largely undamaged during the reverse etching process at the bottom of the trench.

[0038] Step S6: Tungsten plug filling.

[0039] A tungsten (W) thin film was deposited in the trench using chemical vapor deposition (CVD) to completely fill the deep trench and the bottom opening 07. Subsequently, chemical mechanical polishing (CMP) was performed to planarize the surface dielectric layer, forming a bottom vertical tungsten plug 08. Figure 9 As shown.

[0040] The tungsten plug serves as a common lead-out terminal for the silicon substrate potential of the memory array (similar to a common source line), providing a low-resistance vertical common potential lead-out channel for the array.

[0041] Step S7: Ferroelectric thin film annealing and crystallization.

[0042] The sample is placed in a rapid thermal annealing (RTA) furnace for annealing, which crystallizes the HZO ferroelectric thin film to obtain ferroelectric properties. If it is necessary to protect the tungsten plug from high-temperature oxidation, this annealing step can also be flexibly adjusted to be performed before step S6, depending on the specific thermal budget requirements.

[0043] Step S8: Independent vertical lead-out of each layer of capacitors.

[0044] The interlayer dielectric layer 09 is deposited to cover the entire device and planarized; using photolithographic masks corresponding to contact holes of different depths, dry etching is performed to penetrate the interlayer dielectric layer 09 to the corresponding titanium nitride 02 surface, such as... Figure 10 As shown; Further tungsten deposition, followed by CMP planarization, forms independent vertical lead-out contact holes 10 for each electrode layer; Finally, each contact hole 10 is connected to the external decoding circuit via metal interconnection 11, enabling independent selection and read / write operations for each layer of ferroelectric capacitor unit, such as... Figure 11 The fabrication of the three-dimensional stacked ferroelectric memory array is shown in the figure.

[0045] This invention transforms the challenge of metal etching into pure dielectric etching, significantly reducing the difficulty of high aspect ratio etching and greatly expanding the process window; wet selective etching forms smooth cavities without damaging the electrode plates; the gourd-shaped sidewall structure achieves physical isolation, greatly reducing interlayer crosstalk; during reverse etching, thanks to the shadow shielding effect of the cavity structure itself on vertical ion bombardment, the ferroelectric stack on the sidewalls is almost undamaged during the bottom reverse etching process; the bottom tungsten plug provides low-resistivity common source / substrate contact, and the independent vertical direct contact holes of each peripheral layer enable independent addressing layer by layer; the entire process is compatible with CMOS back-end integration.

[0046] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for fabricating a three-dimensional sidewall cavity ferroelectric memory, characterized in that, Includes the following steps: S1: A composite layer of silicon oxide, titanium nitride, and silicon nitride is alternately deposited on the wafer surface to form a periodic multilayer stacked structure; S2: Through hard mask dry etching, all silicon oxide and silicon nitride layers are vertically penetrated in one go to form a vertical deep trench, with the bottom of the trench falling on the surface of the silicon substrate; S3: Selective side etching using hot phosphoric acid wet etching is employed to remove silicon nitride from the sidewalls. The etching stops at the surface of titanium nitride, forming lateral cavities in each layer. S4: Ferroelectric capacitors are deposited on the inner wall of the cavity using ALD, wherein the capacitors include at least a lower electrode, a ferroelectric dielectric and an upper electrode; S5: Perform highly anisotropic reverse etching to vertically remove all ALD films at the bottom of the trench, exposing the silicon substrate surface and forming conductive openings at the bottom of the trench; S6: Deposit conductive material in the trench and backfill to level it out, forming a bottom conductive plug; S7: Annealed crystallized ferroelectric layer; S8: Lead out each layer of titanium nitride, deposit an interlayer dielectric layer, and fabricate vertical direct contact holes of different depths, filling them with metal to form independent vertical lead-out electrodes for each layer.

2. The method for fabricating a three-dimensional sidewall cavity ferroelectric memory as described in claim 1, characterized in that, Step S1 includes: Silicon oxide and silicon nitride are deposited on the wafer surface, and some of the silicon nitride is removed by mask etching. Titanium nitride is deposited on the surface and CMP planarization is performed to expose silicon nitride; this completes one cycle of the multilayer stacked structure. Repeat the above steps to form a periodic multi-layer stacked structure, with the top layer covered by a hard mask layer to protect against subsequent etching.

3. The method for fabricating a three-dimensional sidewall cavity ferroelectric memory as described in claim 1, characterized in that, The depth of the cavity is controlled according to the length of the silicon nitride sacrificial layer in step S1; the silicon oxide in each layer is retained to form upper and lower isolation convex edges, so that the overall trench has a gourd-shaped outline.

4. The method for fabricating a three-dimensional sidewall cavity ferroelectric memory as described in claim 1, characterized in that, In step S3, the selection ratio of hot phosphoric acid for silicon nitride to titanium nitride is higher than 100:

1.

5. The method for fabricating a three-dimensional sidewall cavity ferroelectric memory as described in claim 1, characterized in that, The deposition of ferroelectric capacitors on the inner wall of the cavity using ALD includes: firstly, depositing 5-10 nm titanium nitride as the lower electrode of the capacitor; then depositing 7-9 nm HZO as the ferroelectric dielectric layer; and finally depositing 5-10 nm titanium nitride as the upper electrode of the capacitor.

6. A three-dimensional sidewall cavity ferroelectric memory structure based on the preparation method according to any one of claims 1-5, characterized in that, include: A multilayer composite stacked layer with periodic alternating stacking, wherein the composite stacked layer is composed of alternating silicon oxide (01) and composite functional layers, wherein the composite functional layers include titanium nitride (02) and silicon nitride (03) as a sacrificial layer. A vertical deep trench (04) runs through all stacked layers, and the bottom of the vertical deep trench (04) is provided with a conductive opening (07) that exposes the surface of the silicon substrate. After selectively etching away the silicon nitride (03) on each sidewall, a lateral cavity (05) is formed on the outside of each titanium nitride (02) layer, and each silicon oxide (01) is retained to form upper and lower isolation convex edges, thus forming a periodic gourd-shaped sidewall structure. Hafnium zirconium oxide deposited on the inner wall of each sidewall cavity (05) serves as a ferroelectric dielectric layer (06), and each layer of titanium nitride (02) forms an independent sidewall ferroelectric capacitor. A bottom conductive plug (08) is filled in the conductive opening (07) at the bottom of the vertical deep trench (04) to form a bottom vertical lead-out end; Each layer of titanium nitride placed on the periphery of the storage array has a stepped area with vertical independent metal contact holes (10) that penetrate to each layer of titanium nitride (02), forming independent vertical electrode leads out of each layer of titanium nitride.

7. The three-dimensional sidewall cavity ferroelectric memory structure according to claim 6, characterized in that: The ferroelectric capacitor is composed of a lower titanium nitride electrode layer, an HZO ferroelectric dielectric layer, and an upper titanium nitride electrode layer deposited sequentially by ALD.

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