Integrated chip and method of forming the same

Abstract

The integrated chip includes a barrier layer comprising a first conductive material located above a semiconductor substrate. The integrated chip includes a lower electrode layer comprising a second conductive material different from the first conductive material located above the barrier layer. The integrated chip includes a dielectric layer located above the lower electrode layer. The integrated chip includes an upper electrode layer located above the dielectric layer. The integrated chip includes a sealing layer comprising a first dielectric material sealing the upper electrode layer, dielectric layer, lower electrode layer, and barrier layer. The integrated chip includes a spacer layer comprising a second dielectric material different from the first dielectric material located on the upper surface of the barrier layer. The sealing layer is spaced apart from the sidewalls of the lower electrode layer, the dielectric layer, and the upper electrode layer by the spacer layer. Embodiments of this application also relate to integrated chips and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to integrated chips and methods of forming the same. Background Technology

[0002] Many modern electronic devices contain electronic memory configured to store data. Electronic memory can be volatile or non-volatile. Volatile memory stores data when it is powered on, while non-volatile memory retains data when power is off. Resistive random access memory (RRAM) is a promising candidate for next-generation non-volatile memory due to its simple structure and compatibility with complementary metal-oxide-semiconductor (CMOS) processes. Summary of the Invention

[0003] Some embodiments of this application provide an integrated chip, including: a barrier layer including a first conductive material located above a semiconductor substrate; a lower electrode layer including a second conductive material different from the first conductive material located above the barrier layer; a dielectric layer located above the lower electrode layer; an upper electrode layer located above the dielectric layer; a sealing layer including a first dielectric material sealing the upper electrode layer, the dielectric layer, the lower electrode layer, and the barrier layer; and a spacer layer including a second dielectric material different from the first dielectric material located on the upper surface of the barrier layer, wherein the sealing layer is spaced apart from the sidewalls of the lower electrode layer, the dielectric layer, and the upper electrode layer by the spacer layer.

[0004] Other embodiments of this application provide a method for forming an integrated chip, the method comprising: depositing a barrier layer comprising a first conductive material over a semiconductor substrate; depositing a lower electrode layer comprising a second conductive material different from the first conductive material over the barrier layer; depositing a data storage layer over the lower electrode layer; depositing an upper electrode layer over the data storage layer; etching the upper electrode layer, the data storage layer, and the lower electrode layer; depositing a spacer layer comprising a first dielectric material on the upper surface of the barrier layer, along the sidewalls of the lower electrode layer, along the sidewalls of the data storage layer, along the sidewalls of the upper electrode layer, and over the upper electrode layer; etching the spacer layer to remove the spacer layer from over the upper electrode layer; etching the barrier layer according to the spacer layer; and depositing a sealing layer comprising a second dielectric material different from the first dielectric material over the upper electrode layer, along the sidewalls of the spacer layer, and along the sidewalls of the barrier layer, wherein the spacer layer covers the sidewalls of the upper electrode layer, the sidewalls of the data storage layer, and the sidewalls of the lower electrode layer during the deposition of the sealing layer.

[0005] Some embodiments of this application provide a method for forming an integrated chip, the method comprising: forming a barrier layer comprising a first conductive material over a semiconductor substrate; forming a lower electrode layer comprising a second conductive material different from the first conductive material over the barrier layer; forming a dielectric layer over the lower electrode layer; forming an upper electrode layer over the dielectric layer; forming a spacer layer comprising a first dielectric material on the upper surface of the barrier layer; and sealing the upper electrode layer, the dielectric layer, the lower electrode layer, the barrier layer, and the spacer layer with a sealing layer comprising a second dielectric material different from the first dielectric material, wherein the sealing layer is spaced apart from the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the upper electrode layer by the spacer layer. Attached Figure Description

[0006] Various aspects of embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. The drawings are provided to clearly illustrate relevant aspects of the embodiments. The drawings may illustrate the relationships between various structures and / or elements within the embodiments. It should be noted that the drawings are not necessarily drawn to scale. In some instances, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of a memory cell including a spacer layer covering the sidewalls of the upper electrode layer, the sidewalls of the data storage layer, and the sidewalls of the lower electrode layer are shown.

[0008] Figure 2 Cross-sectional views of some embodiments of a memory cell in which a cover layer is located between an upper electrode layer and a data storage layer and a spacer layer covers the sidewalls of the cover layer are shown.

[0009] Figure 3 A top view of some embodiments of the memory cell is shown.

[0010] Figure 4 Cross-sectional views of some embodiments of an integrated chip including memory cells are shown.

[0011] Figure 5 Cross-sectional views of some embodiments of the memory cell are shown.

[0012] Figure 6 Cross-sectional views of some embodiments of integrated chips, in which the integrated chip includes memory regions and logic regions, are shown.

[0013] Figure 7 Cross-sectional views of some embodiments of an integrated chip in which multiple memory cells are laterally spaced apart in a memory region are shown.

[0014] Figure 8Cross-sectional views of some embodiments of the memory cell are shown.

[0015] Figure 9 and Figure 10 Cross-sectional views of some embodiments of a memory cell in which two spacer layers surround the memory cell are shown.

[0016] Figure 11 and Figure 12 Cross-sectional views are shown of some embodiments of a memory cell in which the lower electrode layer is laterally recessed at the sidewall of the lower electrode layer.

[0017] Figure 13 and Figure 14 Cross-sectional views of some embodiments of a memory cell in which the lower electrode layer has essentially no lateral grooves on the sidewalls of the lower electrode layer are shown.

[0018] Figures 15 to 25 Cross-sectional views of some embodiments of a method for forming an integrated chip including memory cells are shown.

[0019] Figures 26 to 30 Cross-sectional views of some embodiments of methods for forming memory cells are shown.

[0020] Figures 31 to 38 Cross-sectional views of some embodiments of methods for forming memory cells are shown.

[0021] Figure 39 Flowcharts of some embodiments of a method for forming an integrated chip including memory cells are shown. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. In some embodiments, the terms “about” and / or “approximately” may be interpreted as meaning + / - 10% or + / - 5%, while in other embodiments, the terms “about” and / or “approximately” may be interpreted as meaning within the normal manufacturing tolerances of a given manufacturer's manufacturing process.

[0024] The integrated chip includes transistors located above and / or along a semiconductor substrate. Conductive interconnects are located above and coupled to the transistors. Memory cells are located above the conductive interconnects and coupled to the transistors via the conductive interconnects. The memory cell includes a lower electrode layer coupled to the conductive interconnects, a data storage layer (e.g., a memory layer) on the lower electrode layer, and an upper electrode layer on the data storage layer. The data storage layer may be placed in a first state (e.g., a high-resistance state) to store a first logic value (e.g., 0) in the memory cell. The data storage layer may be placed in a second state (e.g., a low-resistance state) to store a second logic value (e.g., 1) in the memory cell.

[0025] The sealing layer is located above the upper electrode layer and extends along the sidewalls of the upper electrode layer, the data storage layer, and the lower electrode layer. In some cases, the sealing layer comprises a dielectric material, including oxygen (e.g., silicon oxide). Therefore, in some cases, portions of the upper electrode layer and / or the lower electrode layer may be oxidized during the formation of the sealing layer. This oxidation may degrade the performance and / or reliability of the memory cell.

[0026] In various embodiments of this disclosure, spacer layers are formed on the sidewalls of the lower electrode layer, the data storage layer, and the upper electrode layer before the sealing layer is formed, to protect the upper and lower electrode layers from oxidation during the formation of the sealing layer. The spacer layers can reduce oxidation of the upper and / or lower electrode layers during the formation of the sealing layer. Therefore, the performance and / or reliability of the memory cell can be improved.

[0027] Figure 1 A cross-sectional view 100 shows some embodiments of a memory cell 106 including a spacer layer 118 covering the sidewalls of the upper electrode layer 114, the sidewalls of the data storage layer 112, and the sidewalls of the lower electrode layer 110. Figure 2A cross-sectional view 200 shows some embodiments of a memory cell 106 in which a cover layer 202 is located between an upper electrode layer 114 and a data storage layer 112 and a spacer layer 118 covers the sidewalls of the cover layer 202. Figure 3 A top view 300 shows some embodiments of the memory cell 106. In some embodiments, Figure 3 The cross-section line A-A' corresponds to Figure 1 and / or Figure 2 The cross-section line A-A'.

[0028] Memory cell 106 is located above conductive interconnect 104 (e.g., wires) and dielectric layer 102. Memory cell 106 includes a barrier layer 108, a lower electrode layer 110, a data storage layer 112 (e.g., a memory layer), an upper electrode layer 114, a hard mask layer 116, and a spacer layer 118. The barrier layer 108 is located on the top surface of dielectric layer 102 and the top surface of conductive interconnect 104, and is coupled to conductive interconnect 104. The lower electrode layer 110 is located on the top surface of barrier layer 108 and is coupled to conductive interconnect 104 through barrier layer 108. Data storage layer 112 is located on the top surface of lower electrode layer 110. Upper electrode layer 114 is located on the top surface of data storage layer 112. Hard mask layer 116 is located on the top surface of upper electrode layer 114. Dielectric layer 122 is located above memory cell 106. Conductive interconnects 124 (e.g., conductive vias) extend through dielectric layer 122 and hard mask layer 116 to upper electrode layer 114.

[0029] Data can be stored by memory cell 106 by adjusting the resistance of data storage layer 112, which can be achieved by applying a voltage across data storage layer 112. For example, a first voltage can be applied across data storage layer 112 to place data storage layer 112 in a first state (e.g., a high-resistance state) to store a first logic value (e.g., 0) in memory cell 106. A second voltage, different from the first voltage, can be applied across data storage layer 112 to place data storage layer 112 in a second state (e.g., a low-resistance state) to store a second logic value (e.g., 1) in memory cell 106.

[0030] Spacer layer 118 is located on the top surface of barrier layer 108, the sidewall of lower electrode layer 110, the sidewall of data storage layer 112, the sidewall of upper electrode layer 114, and the sidewall of hard mask layer 116. In some embodiments, spacer layer 118 laterally surrounds lower electrode layer 110, data storage layer 112, upper electrode layer 114, and hard mask layer 116 in an annular closed path (e.g., as shown in the image). Figure 3 (as shown in the image).

[0031] The sealing layer 120 seals the spacer layer 118, the hard mask layer 116, the upper electrode layer 114, the data storage layer 112, the lower electrode layer 110, and the barrier layer 108. The sealing layer 120 is spaced apart from the sidewalls of the lower electrode layer 110, the data storage layer 112, and the upper electrode layer 114 by the spacer layer 118. Therefore, the spacer layer 118 protects the lower electrode layer 110 and the upper electrode layer 114 from oxidation during the formation of the sealing layer 120.

[0032] By reducing the oxidation of the lower electrode layer 110 and the upper electrode layer 114, the performance and / or reliability of the memory cell 106 can be improved. For example, the effective area of ​​the memory cell 106 (corresponding to the capacitance of the memory cell 106) can be increased, the formation voltage (e.g., the voltage used to write to the memory cell) can be reduced, the bit error rate can be reduced, the set / reset trigger count (e.g., the number of voltage pulses applied to set / reset the memory cell) can be reduced, the set / reset trigger count stability can be improved, the set / reset speed can be improved, the natural yield (e.g., the number of memory cells that work normally without repair) can be improved, the repair rate (e.g., the number of memory cells that work normally after repair), and / or the structural integrity of the memory cell 106 can be improved.

[0033] Spacer layer 118 comprises an oxygen-free or low-oxygen dielectric material to further reduce oxidation of the upper electrode layer 114, capping layer 202, and lower electrode layer 110. For example, in some embodiments, spacer layer 118 comprises a lower percentage of oxygen atoms than sealing layer 120. In some embodiments, the percentage of oxygen atoms in spacer layer 118 is less than 20%, less than 15%, or some other suitable value. In some embodiments, spacer layer 118 is substantially oxygen-free (e.g., the percentage of oxygen atoms in spacer layer 118 is less than 4%, less than 2%, less than 1%, less than 0.5%, or some other suitable value). In some embodiments, the oxygen-free dielectric material is or includes silicon nitride, silicon carbide, silicon carbonitride, or some other suitable material. In some embodiments, the low-oxygen dielectric material is or includes silicon oxynitride, silicon carbonitride, silicon carbonitride, or some other suitable material.

[0034] In some embodiments, memory cell 106 is a resistive random access memory (RRAM) cell, wherein data storage layer 112 comprises a high-k dielectric material. In such embodiments, a first voltage can be applied across the data storage layer to form conductive filaments with oxygen vacancies within the data storage layer 112 to reduce the resistance of the data storage layer 112, thus storing a second logic value (e.g., "1") in memory cell 106. Alternatively, a second voltage can be applied across the data storage layer 112 to disconnect the conductive filaments within the data storage layer 112, thereby increasing the resistance of the data storage layer 112, thus storing a first logic value (e.g., "0") in memory cell 106. In some embodiments where the memory cell is an RRAM cell, memory cell 106 further includes a cover layer 202 located between the data storage layer 112 and the upper electrode layer 114, such as... Figure 2 As shown in the diagram, the capping layer 202 can help provide oxygen vacancies (which form conductive filaments) to the data storage layer 112.

[0035] In some other embodiments, memory cell 106 is a phase-change random access memory (PCRAM) cell, wherein data storage layer 112 comprises a chalcogenide material. In some other embodiments, memory cell 106 is a magnetoresistive random access memory (MRAM) cell, wherein electrode layers 110, 114 comprise a ferromagnetic material, and data storage layer 112 comprises a tunneling barrier dielectric material. In some other embodiments, memory cell 106 is a ferroelectric random access memory (FeRAM) cell, wherein data storage layer 112 comprises a ferroelectric material.

[0036] The barrier layer 108 includes a first conductive material. In some embodiments, the barrier layer 108 includes tantalum, titanium, ruthenium, aluminum, cobalt, molybdenum, rhodium, tantalum nitride, titanium nitride, ruthenium nitride, aluminum nitride, cobalt nitride, molybdenum nitride, rhodium nitride, tungsten nitride, manganese nitride, nickel nitride, tin nitride, magnesium nitride, or some other suitable material. In some embodiments, the thickness of the barrier layer 108 is in the range of about 5 angstroms to about 140 angstroms, about 10 angstroms to about 130 angstroms, about 20 angstroms to about 100 angstroms, or some other suitable thickness.

[0037] The lower electrode layer 110 includes a second conductive material different from the first conductive material. In some embodiments, the lower electrode layer 110 includes: ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; alloys of any one of ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; nitrides of any one of ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; or some other suitable material. In some embodiments, the thickness of the lower electrode layer 110 is in the range of about 20 angstroms to about 200 angstroms, about 75 angstroms to about 200 angstroms, about 100 angstroms to about 200 angstroms, or some other suitable thickness.

[0038] In some embodiments, the data storage layer 112 comprises a high-k dielectric material, such as, for example, hafnium oxide, zirconium oxide, lanthanum oxide, gadolinium oxide, yttrium oxide, aluminum oxide, some other high-k dielectric material, or some other suitable material. In some embodiments, the thickness of the data storage layer 112 is in the range of about 10 angstroms to about 100 angstroms, about 10 angstroms to about 90 angstroms, about 10 angstroms to about 80 angstroms, or some other suitable thickness.

[0039] The capping layer 202 includes a third conductive material. In some embodiments, the capping layer 202 includes titanium, hafnium, platinum, aluminum, tantalum, zirconium, nickel, iridium, or some other suitable material. In some embodiments, the thickness of the capping layer 202 is in the range of about 25 angstroms to about 200 angstroms, about 50 angstroms to about 200 angstroms, about 75 angstroms to about 200 angstroms, or some other suitable thickness.

[0040] The upper electrode layer 114 includes a fourth conductive material different from the third conductive material. In some embodiments, the upper electrode layer 114 includes: ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; alloys of any one of ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; nitrides of any one of ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; or some other suitable material. In some embodiments, the thickness of the upper electrode layer 114 is in the range of about 25 angstroms to about 200 angstroms, about 50 angstroms to about 200 angstroms, about 75 angstroms to about 200 angstroms, or some other suitable thickness.

[0041] In some embodiments, the hard mask layer 116 includes silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, some metal nitrides, or some other suitable materials.

[0042] Sealing layer 120 comprises a dielectric material different from that of spacer layer 118. In some embodiments, sealing layer 120 comprises tetraethyl orthosilicate (TEOS) silica or some other suitable material. In some embodiments, dielectric layer 102 and / or dielectric layer 122 comprises a low-k dielectric material, an extremely low-k dielectric material (e.g., having a dielectric constant k less than 2.5), or some other suitable material. In some embodiments, conductive interconnect 104 and / or conductive interconnect 124 comprises copper, aluminum, tungsten, titanium, tantalum, or some other suitable material.

[0043] Figure 4 A cross-sectional view 400 shows some embodiments of an integrated chip including a memory cell 106.

[0044] Transistor 404 is disposed above and / or along semiconductor substrate 402. Transistor 404 includes a first source / drain, a second source / drain, and a gate structure. The source / drain may refer to a source or a drain, individually or collectively, depending on the context. In some embodiments, the gate structure of transistor 404 (and / or conductive interconnects 412 coupled to the gate structure of transistor 404) forms word lines of a memory array including memory cells 106.

[0045] A dielectric structure 406, comprising multiple dielectric layers, is located above a semiconductor substrate 402. An interconnect structure 408, comprising multiple conductive interconnects (e.g., wires, conductive vias, conductive pads, conductive contacts, etc.), is located within the dielectric structure 406. In some embodiments, conductive interconnects 414 are coupled to a first source / drain of a transistor 404 and form source lines of a memory array.

[0046] A dielectric layer 102 is located above the dielectric structure 406. A conductive interconnect 104 is located above the interconnect structure 408 and coupled to the second source / drain of the transistor 404 via the conductive interconnect structure 408. A plurality of conductive interconnects (including conductive interconnect 410) are located above and coupled to conductive interconnect 124. In some embodiments, conductive interconnect 410 forms bit lines of a memory array.

[0047] In some embodiments, transistor 404 is a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), a bipolar junction transistor (BJT), a fin field-effect transistor (Fin FET), a gate-all-around field-effect transistor (GAA FET), or some other suitable device.

[0048] Figure 5 A cross-sectional view 500 is shown of some embodiments of a memory cell 106 in which a diffusion barrier dielectric layer 502 is located between a sealing layer 120 and a dielectric layer 102.

[0049] A diffusion barrier dielectric layer 502 is located on dielectric layer 102 and conductive interconnect 104. The diffusion barrier dielectric layer 502 helps prevent atoms from diffusing from conductive interconnect 104 into the overlying layers. The diffusion barrier dielectric layer 502 has an opening directly above the conductive interconnect 104, wherein the barrier layer 108 contacts the conductive interconnect 104. The opening is defined by sidewalls 502a and 502b of the diffusion barrier dielectric layer 502.

[0050] A barrier layer 108 is conformally located on the conductive interconnect 104 and the diffusion barrier dielectric layer 502. For example, the barrier layer 108 is located on the first upper surface 502c, the second upper surface 502d, the sidewalls 502a and 502b of the diffusion barrier dielectric layer 502. The barrier layer 108 extends from the sidewall 502a to the sidewall 502b of the diffusion barrier dielectric layer 502 on the upper surface of the conductive interconnect 104.

[0051] The lower electrode layer 110, data storage layer 112, cover layer 202, and upper electrode layer 114 are conformally stacked on top of the barrier layer 108 and therefore have similar shapes. For example, the lower electrode layer 110 is located on the first sidewall (not labeled), the second sidewall (not labeled), and the upper surface (not labeled) of the barrier layer 108 from the first sidewall to the second sidewall. The hard mask layer 116 is consistent with the upper electrode layer 114 but has a substantially flat upper surface.

[0052] The spacer layer 118 is located on a first upper surface of the barrier layer 108 (e.g., on a first protrusion of the barrier layer 108 above a first portion of the diffusion barrier dielectric layer 502) and a second upper surface of the barrier layer 108 (e.g., on a second protrusion of the barrier layer 108 above a second portion of the diffusion barrier dielectric layer 502). In some embodiments, the bottom surface of the spacer layer 118 is located above the upper surface 110a of the lower electrode layer 110. In some embodiments, the bottom surface of the spacer layer 118 is located above the upper surface 112a of the data storage layer 112.

[0053] Figure 6 A cross-sectional view 600 is shown of some embodiments of an integrated chip in which the integrated chip includes a memory region 602 and a logic region 604.

[0054] Memory cell 106 is located within memory region 602 of the integrated chip. In some embodiments, logic region 604 is adjacent to memory region 602. Transistors in logic region 604 are laterally spaced from transistors in memory region 602. For example, transistor 614 is laterally spaced from transistor 404. Similarly, conductive interconnects in logic region 604 are laterally spaced from conductive cell 106 and conductive interconnects in memory region 602. For example, conductive interconnect structure 606 is laterally spaced from conductive interconnect structure 408, wire 608 is laterally spaced from wire 104, conductive via 610 is laterally spaced from conductive via 124 and memory cell 106, and wire 612 is laterally spaced from wire 410. Conductive via 610 extends from wire 612 through dielectric layer 122, through sealing layer 120, and through diffusion barrier dielectric layer 502 to wire 608. In some embodiments, the top surface of conductive via 124 and the top surface of conductive via 610 are substantially perpendicularly aligned. The bottom surface of the conductive via 610 is located below the bottom surface of the conductive via 124.

[0055] Figure 7 A cross-sectional view 700 shows some embodiments of an integrated chip in which multiple memory cells are laterally spaced apart in memory region 602.

[0056] For example, memory cell 702 is located in memory region 602 and is laterally spaced from memory cell 106. Memory cell 106 is formed by (for example, including) a first portion of barrier layer 108 (e.g., a first barrier structure), a first portion of lower electrode layer 110 (e.g., a first lower electrode), a first portion of data storage layer 112 (e.g., a first data storage structure), a first portion of cover layer 202 (e.g., a first cover structure), a first portion of upper electrode layer 114 (e.g., a first upper electrode), a first portion of hard mask layer 116 (e.g., a first hard mask structure), and a first portion of spacer layer 118 (e.g., a first spacer structure). Memory cell 702 is formed by (for example, including) a second portion of barrier layer 108 (e.g., a second barrier structure), a second portion of lower electrode layer 110 (e.g., a second lower electrode), a second portion of data storage layer 112 (e.g., a second data storage structure), a second portion of cover layer 202 (e.g., a second cover structure), a second portion of upper electrode layer 114 (e.g., a second upper electrode), a second portion of hard mask layer 116 (e.g., a second hard mask structure), and a second portion of spacer layer 118 (e.g., a second spacer structure). Sealing layer 120 is conformally located over memory cell 106, memory cell 702, and the diffusion barrier dielectric layer 502 between memory cells 106 and 702.

[0057] Memory cell 702 is located above and coupled to wire 704, which is located above transistor 708 and coupled to it via conductive interconnect structure 710. Conductive via 706 is located above and coupled to memory cell 702. In some embodiments, wire 410 is located above and coupled to conductive vias 124 and 706 (e.g., wire 410 is a shared bit line). In some other embodiments, a separate wire (not shown) is located above and coupled to conductive via 706 and is isolated from wire 410.

[0058] Figure 8 A cross-sectional view 800 shows some embodiments of a memory cell 106 in which the lower electrode layer 110 is located between the spacer layer 118 and the barrier layer 108.

[0059] Spacer layer 118 is located on the upper surfaces 110a, 110b of lower electrode layer 110. Sealing layer 120 covers the sidewalls of lower electrode layer 110. Spacer layer 118 is formed on the upper surfaces 110a, 110b of lower electrode layer 110 before etching lower electrode layer 110. Therefore, spacer layer 118 can protect upper electrode layer 114 and capping layer 202 from oxidation during etching lower electrode layer 110 and subsequent processes. Therefore, the performance and / or reliability of memory cell 106 can be improved.

[0060] Figure 9 A cross-sectional view 900 shows some embodiments of the memory cell 106 in which two spacer layers protect the memory cell 106. Figure 10 Cross-sectional view 1000 shows some other embodiments of the memory cell 106 in which two spacer layers protect the memory cell 106.

[0061] Spacer layer 902 is located between spacer layer 118 and layers 202, 114, 116. In some embodiments (e.g., such as...) Figure 9 As shown in the diagram), the spacer layer 902 is located on the upper surface of the data storage layer 112 and covers the sidewalls of the hard mask layer 116, the sidewalls of the upper electrode layer 114, and the sidewalls of the cover layer 202. In some embodiments (e.g., as shown in the diagram), the spacer layer 902 is located on the upper surface of the data storage layer 112 and covers the sidewalls of the hard mask layer 116, the upper electrode layer 114, and the cover layer 202. Figure 10 As shown in the figure, the spacer layer 902 is located on the upper surface of the lower electrode layer 110 and also covers the sidewall of the data storage layer 112.

[0062] In some embodiments (e.g., such as) Figure 9As shown in the diagram, spacer layer 902 can protect upper electrode layer 114 and capping layer 202 from oxidation during etching of data storage layer 112 and lower electrode layer 110, and spacer layer 118 can protect data storage layer 112 and lower electrode layer 110 during deposition of sealing layer 120. In some embodiments (e.g., as shown in the diagram), spacer layer 902 can protect data storage layer 112 and lower electrode layer 110 from oxidation during etching of data storage layer 112 and lower electrode layer 110. Figure 10 As shown in the diagram, spacer layer 902 can protect upper electrode layer 114, cover layer 202, and data storage layer 112 from oxidation during etching of lower electrode layer 110, and spacer layer 118 can protect lower electrode layer 110 during deposition of sealing layer 120. Therefore, the performance and / or reliability of memory cell 106 can be improved.

[0063] In some embodiments, spacer layer 902 and spacer layer 118 comprise the same dielectric material. In some other embodiments, spacer layer 118 comprises a first dielectric material, and spacer layer 902 comprises a second dielectric material different from the first dielectric material.

[0064] Figure 11 and Figure 12 Cross-sectional views 1100 and 1200 are shown for some embodiments of a memory cell 106 in which the lower electrode layer 110 is laterally recessed at the sidewall of the lower electrode layer 110.

[0065] The lower electrode layer 110 is "undercut" (e.g., laterally recessed) along its sidewalls (as shown at 1102), such that the sidewalls of the lower electrode layer 110 are substantially offset from the sidewalls of the data storage layer 112, the cover layer 202, the upper electrode layer 114, and the hard mask layer 116. The spacer layer 118 extends below the portion of the data storage layer 112 that causes the lower electrode layer 110 to be laterally recessed. This lateral recess of the lower electrode layer 110 can occur during etching of the lower electrode layer 110. In some embodiments, the width 1206 of the undercut (e.g., the lateral offset between the sidewalls of the lower electrode layer 110 and the sidewalls of the data storage layer 112) ranges from about 10 angstroms to about 100 angstroms, from about 20 angstroms to about 100 angstroms, from about 50 angstroms to about 100 angstroms, or some other range.

[0066] In some embodiments, during etching of the lower electrode layer 110, material removed from the lower electrode layer 110 (the laterally recessed "undercut") is deposited (e.g., "re-sputtered") on the sidewalls of the data storage layer 112. In some embodiments, this material forms a layer 1104 (e.g., a metal oxide layer) on the sidewalls of the data storage layer 112. In some embodiments, the lower electrode material can diffuse through the sidewalls of the data storage layer 112 into the data storage layer 112, such that the edge portions 1106 of the data storage layer 112 also include the lower electrode material (e.g., atoms of the lower electrode material) in the dielectric material of the data storage layer 112.

[0067] In some embodiments, in addition to the conductive material of the barrier layer 108, the edge portions 1108 of the barrier layer 108 also include atoms from one or more etching gases used to etch the lower electrode layer 110 (e.g., the edge portions 1108 of the barrier layer 108 also include one or more of oxygen, fluorine, chlorine, bromine, and iodine). In some embodiments, these edge portions 1108 of the barrier layer 108 have an increased thickness due to the added material (e.g., the thickness of the edge portions 1108 is greater than the thickness of the central portion of the barrier layer 108 extending between the edge portions 1108). In some embodiments, the edge portions 1108 of the barrier layer 108 cover portions of the sidewalls of the lower electrode layer 110 due to the increased thickness of the barrier layer 108 at the edge portions 1108, such as... Figure 12 As shown in the figure, the spacer layer 118 contacts the barrier layer 108 at the edge portion 1108 of the barrier layer 108.

[0068] In some embodiments, the edge portions 1110 (e.g., sidewall regions) of the upper electrode layer 114 and the edge portions 1112 of the capping layer 202 are oxidized (e.g., also including oxygen). This may occur during etching of the lower electrode layer 110. In some embodiments, the sidewalls of the upper electrode layer 114 and the capping layer 202 may be oxidized along their sides during etching of the lower electrode layer 110. In some embodiments, the width 1208 of the oxidized portions 1110 and / or oxidized portions 1112 is in the range of about 50 angstroms to about 150 angstroms, about 75 angstroms to 150 angstroms, about 100 angstroms to 150 angstroms, or some other width.

[0069] In some embodiments, the thickness of the lower electrode layer 110 is less than 75 angstroms, less than 50 angstroms, or some other thickness.

[0070] In some embodiments, barrier layer 1202 is located between conductive interconnect 104 and dielectric layer 102. In some embodiments, barrier layer 1204 is located between conductive interconnect 124 and layers 122, 120, 116, 114. In some embodiments, barrier layer 1202 and / or barrier layer 1204 comprises tantalum, tantalum nitride, or some other suitable material.

[0071] In some cases, the width of the undercut (e.g., lateral offset) of the lower electrode layer 110, the width of the oxide portions 1110 and 1112, the thickness of layer 1104, and / or the width of portion 1106 can be determined using transmission electron microscopy (TEM) or some other suitable method.

[0072] Figure 13 and Figure 14 The lower electrode layer 110 is shown to have essentially no "undercut" (e.g., Figure 11 Cross-sectional views 1300 and 1400 of some embodiments of the memory cell 106 (the transverse groove at 1102).

[0073] Therefore, the sidewalls of the lower electrode layer 110 are substantially aligned with the sidewalls of the data storage layer 112, the cover layer 202, the upper electrode layer 114, and the hard mask layer 116. For example, the sidewalls of the lower electrode layer 110 are laterally offset (e.g., by a width of 1306) from the sidewalls of the data storage layer 112, the cover layer 202, the upper electrode layer 114, and the hard mask layer 116 by about 1 angstrom to about 50 angstroms, less than 50 angstroms, less than 30 angstroms, less than 20 angstroms, less than 10 angstroms, less than 5 angstroms, or some other suitable value.

[0074] In some embodiments, the undercut of the lower electrode layer 110 can be reduced by decreasing the exposure of the lower electrode layer 110 to oxygen during etching (e.g., reducing the oxygen exposure time, reducing the oxygen concentration during exposure, etc.), as referenced. Figure 19 More specifically, in some embodiments, reducing the exposure of the lower electrode layer 110 to oxygen during etching of the lower electrode layer 110 can also reduce the oxidation of the capping layer 202 and the upper electrode layer 114 (e.g., reducing the width of the oxidized portion 1110 and the oxidized portion 1112 of the capping layer 202). For example, the width of portion 1110 and / or portion 1112 can be reduced by more than 30%, more than 50%, more than 60%, or some other amount. In some embodiments, the width 1308 of the oxidized portion 1110 and / or the oxidized portion 1112 is less than about 100 angstroms, less than about 75 angstroms, less than about 50 angstroms, less than about 25 angstroms, less than about 5 angstroms, or some other width.

[0075] In some embodiments, the undercut of the lower electrode layer 110 can be reduced by increasing the thickness of the lower electrode layer 110, such that the thickness of the lower electrode layer 110 is substantially large. The thickness of the lower electrode layer 110 is greater than the thickness of the data storage layer 112. In some embodiments, the thickness of the lower electrode layer 110 is greater than or approximately equal to the thickness of the barrier layer 108. In some embodiments, the thickness of the lower electrode layer 110 is greater than 75 angstroms, greater than 90 angstroms, greater than 100 angstroms, in the range of about 75 angstroms to about 200 angstroms, in the range of about 100 angstroms to about 200 angstroms, or some other suitable thickness.

[0076] In some embodiments, reducing the undercut of the lower electrode layer 110 can prevent or reduce the deposition of lower electrode atoms on the data storage layer 112 (e.g., reducing or eliminating layer 1104 and reducing or eliminating portion 1106 of the data storage layer 112). In some embodiments, reducing the undercut of the lower electrode layer 110 can reduce the width of the edge portion 1108 of the barrier layer 108, which includes the etchant.

[0077] Figures 15 to 25 Cross-sectional views 1500-2500 illustrate some embodiments of a method for forming an integrated chip including a memory cell 106. The memory cell 106 includes a spacer layer 118 covering the sidewalls of an upper electrode layer 114, the sidewalls of a data storage layer 112, and the sidewalls of a lower electrode layer 110. Although the method is described... Figures 15 to 25 However, it should be understood that Figures 15 to 25 The structure disclosed in the document is not limited to this method, but can exist independently of the method.

[0078] like Figure 15 As shown in cross-sectional view 1500, transistors are formed above and / or along semiconductor substrate 402. For example, transistors 404 and 708 are formed in memory region 602, and transistor 614 is formed in logic region 604. Furthermore, a dielectric layer is formed above semiconductor substrate 402. For example, dielectric structure 406 and dielectric layer 102 are formed above semiconductor substrate 402. Additionally, conductive interconnects coupled to the transistors are formed above the transistors. For example, an interconnect structure 408 and wire 104 coupled to transistor 404 are formed above transistor 404 in memory region 602. An interconnect structure 710 and wire 704 coupled to transistor 708 are formed above transistor 708 in memory region 602. An interconnect structure 606 and wire 608 coupled to transistor 614 are formed above transistor 614 in logic region 604.

[0079] like Figure 16As shown in the cross-sectional view 1600, a diffusion barrier dielectric layer 502 is deposited over the dielectric layer 102 and the conductors 104, 704. In some embodiments, the diffusion barrier dielectric layer 502 comprises silicon oxide, silicon carbide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, boron nitride, aluminum nitride, or some other suitable material, and is deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or some other suitable process.

[0080] like Figure 17 As shown in cross-sectional view 1700, a diffusion barrier dielectric layer 502 is etched to form an opening 1702 in the diffusion barrier dielectric layer 502 above conductors (e.g., conductors 104, 704) in the memory region 602, thereby exposing portions of the conductors in the memory region 602. In some embodiments, the sidewalls of the diffusion barrier dielectric layer 502 forming the opening 1702 are angled due to etching.

[0081] In some embodiments, a masking layer 1704 is formed over a diffusion barrier dielectric layer 502, and etching is performed based on the masking layer 1704. In some embodiments, the masking layer 1704 includes photoresist, a hard mask material, or some other suitable material. The masking layer may be removed during and / or after etching. In some embodiments, etching includes a dry etching process, such as, for example, a plasma etching process, a reactive ion etching process, an ion beam etching process, or some other suitable process.

[0082] like Figure 18 As shown in cross-sectional view 1800, a barrier layer 108 is conformally deposited on the diffusion barrier dielectric layer 502 and on the conductors (e.g., conductors 104, 704) in memory region 602. A lower electrode layer 110 is conformally deposited on the barrier layer 108. A data storage layer 112 is conformally deposited on the lower electrode layer 110. In some embodiments, a capping layer 202 is conformally deposited on the data storage layer 112. An upper electrode layer 114 is conformally deposited on the capping layer 202.

[0083] In some embodiments, the lower electrode layer 110 is deposited to have a substantially large thickness. Increasing the thickness of the lower electrode layer 110 can reduce the lateral recess of the lower electrode layer 110 (e.g., "undercut") during etching of the lower electrode layer 110, and can reduce the amount of lower electrode material deposited on the data storage layer 112 (e.g., ...) during etching of the lower electrode layer 110. Figure 11The amount of 1104, 1106). Therefore, the performance and / or reliability of the memory cell can be improved. For example, the effective area of ​​the memory cell can be increased, the bit error rate (BER) of the memory cell can be reduced, the natural yield can be improved, the repair rate can be improved, etc. The thickness of the lower electrode layer 110 is greater than the thickness of the data storage layer 112. In some embodiments, the thickness of the lower electrode layer 110 is greater than or approximately equal to the thickness of the barrier layer 108. In some embodiments, the thickness of the lower electrode layer 110 is greater than 75 angstroms, greater than 90 angstroms, greater than 100 angstroms, or some other thickness.

[0084] In some embodiments, the lower electrode layer 110 includes: ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; an alloy of any one of ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; a nitride of any one of ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; or some other suitable materials, and is deposited by CVD, PVD, ALD, or some other suitable process.

[0085] In some embodiments, the thickness of the barrier layer 108 is in the range of about 5 angstroms to about 140 angstroms, about 10 angstroms to about 100 angstroms, about 25 angstroms to about 75 angstroms, or some other suitable range. In some embodiments, the barrier layer 108 comprises tantalum, titanium, ruthenium, aluminum, cobalt, molybdenum, rhodium, tantalum nitride, titanium nitride, ruthenium nitride, aluminum nitride, cobalt nitride, molybdenum nitride, rhodium nitride, tungsten nitride, manganese nitride, nickel nitride, tin nitride, magnesium nitride, or some other suitable material, and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0086] In some embodiments, the thickness of the data storage layer 112 is in the range of about 10 angstroms to about 100 angstroms, about 10 angstroms to about 90 angstroms, about 10 angstroms to about 80 angstroms, or some other suitable range. In some embodiments, the data storage layer 112 comprises a high-k dielectric metal oxide, such as, for example, hafnium oxide, zirconium oxide, lanthanum oxide, gadolinium oxide, yttrium oxide, aluminum oxide, some other high-k dielectric material, or some other suitable material, and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0087] In some embodiments, the thickness of the capping layer 202 is in the range of about 25 angstroms to about 200 angstroms, about 50 angstroms to about 175 angstroms, about 50 angstroms to about 150 angstroms, or some other suitable range. In some embodiments, the capping layer 202 comprises titanium, hafnium, platinum, aluminum, tantalum, zirconium, nickel, iridium, or some other suitable material, and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0088] In some embodiments, the thickness of the upper electrode layer 114 is in the range of about 20 angstroms to about 200 angstroms, about 30 angstroms to about 170 angstroms, about 50 angstroms to about 150 angstroms, or some other suitable range. In some embodiments, the upper electrode layer 114 comprises: ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, titanium; an alloy of any one of ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; a nitride of any one of ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; or some other suitable material, and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0089] like Figure 19 As shown in cross-sectional view 1900, a hard mask layer 116 is deposited on the upper electrode layer 114, and the hard mask layer 116 is etched to form a separate hard mask structure. The hard mask structure is located directly above the conductors 104 and 704. In some embodiments, the hard mask layer 116 comprises silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, some metal nitride, or some other suitable material, and is deposited by CVD, PVD, and ALD processes, or some other suitable processes. In some embodiments, a masking layer (not shown) is formed over the hard mask layer, and the hard mask layer 116 is etched according to the masking layer. In some embodiments, the etching includes a dry etching process or some other suitable process.

[0090] Next, the upper electrode layer 114, cover layer 202, data storage layer 112, and lower electrode layer 110 are etched according to a patterned hard mask layer 116 (e.g., according to a separate hard mask structure retained after etching the hard mask layer 116) to form a layer stack 1902, 1904 over the conductors 104, 704. Etching stops at the barrier layer 108. In some embodiments, etching includes a plasma etching process or some other suitable process. Gases used during etching include oxygen, halogen gases (e.g., fluorine, chlorine, bromine, iodine), combinations thereof, or some other suitable gases. In some embodiments, etching includes an ashing process using oxygen plasma for cleaning after etching.

[0091] In some embodiments, the upper electrode layer 114 and / or the capping layer 202 may be oxidized during etching of the lower electrode layer 110. In some embodiments, the lower electrode layer 110 may be laterally recessed (e.g., undercut) during etching of the lower electrode layer 110, and atoms removed from the lower electrode layer 110 during etching may be deposited on and / or diffused into the data storage layer 112.

[0092] Oxidation of the upper electrode layer 114, oxidation of the capping layer 202, undercutting of the lower electrode layer 110, and / or deposition of the lower electrode material on the data storage layer 112 can be reduced by decreasing the oxygen concentration during etching of the lower electrode layer 110, decreasing the voltage used to generate plasma from oxygen, and / or reducing the duration of oxygen exposure to the lower electrode layer 110. For example, in some embodiments, the lower electrode layer 110 is exposed to electrode etching gas (e.g., oxygen-containing gas) for less time during etching of the lower electrode layer 110 than the barrier layer 108 is exposed to barrier etching gas (e.g., oxygen, halogen gas, combined gas, or some other suitable etching gas) during etching of the barrier layer 108. In some embodiments, the etching gas used during etching of the lower electrode layer 110 comprises oxygen and halogen, and the oxygen portion is reduced such that more than half (e.g., 50%) of the etching gas is halogen, and less than half of the etching gas is oxygen. In some embodiments, the oxygen portion of the etching gas is reduced such that more than three-quarters (e.g., 75%) of the etching gas is halogen and less than one-quarter (e.g., 25%) of the etching gas is oxygen. In some embodiments, the voltage applied during etching of the lower electrode layer 110 to generate the etching plasma is zero or some other suitable low voltage.

[0093] Furthermore, reducing the ashing time or skipping the ashing process entirely can reduce the oxidation of layers 114 and 202, reduce undercutting of the lower electrode layer 110, and reduce or prevent the deposition of lower electrode atoms on the data storage layer 112. Therefore, in some embodiments, the ashing process is skipped (e.g., the ashing time is zero). In some embodiments implementing a short ashing process, the voltage applied during the ashing of the lower electrode layer 110 is zero or some other suitable low voltage.

[0094] By reducing oxidation of the individual layers of the memory cell and by reducing the undercut of the lower electrode layer 110, the performance and / or reliability of the memory cell can be improved. For example, the effective area of ​​the memory cell 106 can be increased, the formation voltage (e.g., the voltage used to write the memory cell) can be reduced, the bit error rate can be reduced, the set / reset trigger count (e.g., the number of voltage pulses applied to set / reset the memory cell) can be reduced, the set / reset trigger count stability can be improved, the set / reset speed can be improved, the natural yield (e.g., the number of memory cells that function normally without repair) can be improved, the repair rate (e.g., the number of memory cells that function normally after repair), and / or the structural integrity of the memory cell 106 can be improved.

[0095] In some embodiments, atoms of the etching gas can diffuse into the exposed portion of the barrier layer 108 during etching. Therefore, in some embodiments, the exposed portion of the barrier layer 108 may further include oxygen, fluorine, chlorine, bromine, iodine, etc. In some embodiments, the exposed portion of the barrier layer 108 may have increased thickness due to etching gas diffusion.

[0096] In some embodiments, the etching of the upper electrode layer 114 and / or the etching of the cover layer 202 uses a low-oxygen or oxygen-free etching process to further reduce the oxidation of the upper electrode layer 114 and / or the cover layer 202.

[0097] like Figure 20 As shown in the cross-sectional view 2000, a spacer layer 118 is conformally deposited on the layer stack 1902, 1904 and the barrier layer 108. The spacer layer 118 covers the sidewalls of the hard mask layer 116, the sidewalls of the upper electrode layer 114, the sidewalls of the cover layer 202, the sidewalls of the data storage layer 112, the sidewalls of the lower electrode layer 110, and the upper surface of the barrier layer 108.

[0098] In some embodiments, spacer layer 118 comprises an oxygen-free dielectric material. For example, in some embodiments, spacer layer 118 comprises silicon nitride, silicon carbide, silicon carbonitride, or some other suitable material. In some embodiments, spacer layer 118 comprises a substantially low-oxygen dielectric material, wherein the atomic percentage of oxygen is less than 20%, less than 15%, less than 10%, or some other suitable value. For example, in some embodiments, spacer layer 118 comprises silicon oxynitride, silicon carbonitride, silicon carbonitride, or some other suitable material having a low atomic percentage of oxygen. Forming spacer layer 118 from an oxygen-free or low-oxygen dielectric material can help reduce oxidation of the layer on which spacer layer 118 is deposited.

[0099] like Figure 21 As shown in cross-sectional view 2100, spacer layer 118 is etched to remove spacer layer 118 from the upper surface of hard mask layer 116 and from a portion of barrier layer 108, thus forming spacer structures on the sidewalls of each of layer stacks 1902, 1904 by spacer layer 118. For example, a first spacer structure covers the sidewall of layer stack 1902, and a second spacer structure covers the sidewall of layer stack 1904.

[0100] In some embodiments, etching includes a dry etching process or some other suitable process. In some embodiments, etching is performed without forming a masking layer over the spacer layer 118 (e.g., etching is a blanket etching process). In some embodiments, etching may remove a small portion of the hard mask layer 116 and / or the barrier layer 108.

[0101] like Figure 22As shown in cross-sectional view 2200, a barrier layer 108 is etched according to the layer stack 1902, 1904 (e.g., according to hard mask layer 116) and spacer layer 118 to divide the barrier layer 108 into independent barrier structures corresponding to individual memory cells. For example, the etching of the layer stack 1902, 1904 and barrier layer 108 forms individual memory cells 106, 702.

[0102] In some embodiments, etching includes a dry etching process or some other suitable process. Etching stops at the diffusion barrier dielectric layer 502. For example, etching has a high selectivity for the barrier layer 108 compared to the diffusion barrier dielectric layer 502 (e.g., the barrier layer 108 has a substantially higher etch rate than the diffusion barrier dielectric layer 502). In some embodiments, etching may remove a small portion of the diffusion barrier dielectric layer 502. Because etching has a very small effect on the diffusion barrier dielectric layer 502, the thickness of the diffusion barrier dielectric layer 502 is not significantly affected, and therefore the diffusion barrier capability of the diffusion barrier dielectric layer 502 may not be significantly reduced.

[0103] The spacer layer 118 protects the lower electrode layer 110, data storage layer 112, cover layer 202, and upper electrode layer 114 during the etch stop layer 108. Therefore, oxidation of the lower electrode layer 110, cover layer 202, and / or upper electrode layer 114 can be reduced during the etch stop layer 108. This can further improve the performance and / or reliability of the memory cell.

[0104] like Figure 23 As shown in cross-sectional view 2300, a sealing layer 120 is conformally deposited over memory cells 106, 702 and diffusion barrier dielectric layer 502 to seal memory cells 106, 702. In some embodiments, the sealing layer 120 comprises silicon dioxide or some other suitable material formed using a CVD process with tetraethyl orthosilicate (TEOS) and oxygen. In some embodiments, an oxygen-containing gas is used in a cleaning process prior to the deposition of the sealing layer 120.

[0105] Spacer layer 118 protects lower electrode layer 110, data storage layer 112, cover layer 202, and upper electrode layer 114 during cleaning processes and deposition of sealing layer 120. Therefore, oxidation of lower electrode layer 110, cover layer 202, and / or upper electrode layer 114 can be further reduced. Consequently, the performance and / or reliability of the memory cell can be further improved.

[0106] like Figure 24As shown in cross-sectional view 2400, a dielectric layer 122 is deposited over the sealing layer 120. In some embodiments, the dielectric layer comprises a low-k dielectric material, an extremely low-k dielectric material (e.g., having a dielectric constant k of less than 2.5), or some other suitable material, and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0107] like Figure 25 As shown in cross-sectional view 2500, conductive interconnects coupled to the memory cells are formed above the memory cells in memory region 602. For example, conductive vias 124 and 706 coupled to the memory cells 106 and 702 are formed above them. Furthermore, in some embodiments, wires 410 coupled to the conductive vias 124 and 706 are formed above them. Additionally, conductive interconnects are formed in logic region 604. For example, a conductive via 610 coupled to a wire 608 is formed above a wire 608, and a wire 612 coupled to the conductive via 610 is formed above the conductive via 610.

[0108] In some embodiments, the conductive interconnect is formed by: etching dielectric layer 122, sealing layer 120, hard mask layer 116 (for conductive vias 124, 706) and diffusion barrier dielectric layer 502 (for conductive vias 610) using one or more etching processes to form an opening therein; and depositing one or more conductive materials (e.g., copper, aluminum, tungsten, titanium, tantalum, etc.) in the opening using one or more deposition processes.

[0109] Figures 26 to 30 Cross-sectional views 2600-3000 show some embodiments of a method for forming a memory cell 106 in which the lower electrode layer 110 is located between the spacer layer 118 and the barrier layer 108. Although the method is described... Figures 26 to 30 However, it should be understood that Figures 26 to 30 The structure disclosed in the document is not limited to this method, but can exist independently of the method.

[0110] like Figure 26 As shown in cross-sectional view 2600, after depositing layers 108, 110, 112, 202, and 114 and forming a separate hard mask structure by hard mask layer 116, the upper electrode layer 114, the capping layer 202, and the data storage layer 112 are etched according to the patterned hard mask layer 116 to form layer stacks 2602 and 2604. Etching stops at the lower electrode layer 110.

[0111] like Figure 27As shown in cross-sectional view 2700, spacer layer 118 is conformally deposited on layer stacks 2602, 2604 (e.g., on hard mask layer 116, upper electrode layer 114, capping layer 202, and data storage layer 112) and lower electrode layer 110. Spacer layer 118 covers the sidewalls of hard mask layer 116, upper electrode layer 114, capping layer 202, data storage layer 112, and upper surface of lower electrode layer 110.

[0112] like Figure 28 As shown in cross-sectional view 2800, spacer layer 118 is etched to remove spacer layer 118 from the upper surface of hard mask layer 116 and a portion of lower electrode layer 110, thus forming spacer structures on the sidewalls of layer stacks 2602, 2604 (e.g., on the sidewalls of data storage layer 112, cover layer 202 and upper electrode layer 114).

[0113] like Figure 29 As shown in cross-sectional view 2900, the lower electrode layer 110 and the barrier layer 108 are etched according to the hard mask layer 116 and the spacer layer 118 to separate the lower electrode layer 110 into individual lower electrodes and to separate the barrier layer 108 into individual barrier structures. The etching forms memory cells 106 and 702 by the layer stacks 2602 and 2604 and the etched layers 110 and 108.

[0114] The spacer layer 118 protects the sidewalls of the upper electrode layer 114, the capping layer 202, and the data storage layer 112 during the etching of the lower electrode layer 110. Therefore, oxidation of the protective layer can be reduced, and thus the performance and / or reliability of the memory cells can be improved.

[0115] like Figure 30 As shown in the cross-sectional view 3000, the sealing layer 120 is conformally deposited over the memory cells 106, 702 and the diffusion barrier dielectric layer 502 to seal the memory cells 106, 702.

[0116] The spacer layer 118 protects the sidewalls of the upper electrode layer 114, the cover layer 202, and the data storage layer 112 during the deposition of the sealing layer 120. Therefore, oxidation of the protective layer can be further reduced, and thus the performance and / or reliability of the memory cell can be further improved.

[0117] Figures 31 to 38 Cross-sectional views 3100-3800 illustrate some embodiments of a method for forming layers of memory cell 106 in which two spacer layers protect the memory cell 106. Although the method is described... Figures 31 to 38 However, it should be understood that Figures 31 to 38 The structure disclosed in the document is not limited to this method, but can exist independently of the method.

[0118] like Figure 31 As shown in cross-sectional view 3100, after deposition layers 108, 110, 112, 202, 114 and the formation of a separate hard mask structure by hard mask layer 116, the upper electrode layer 114 and the capping layer 202 are etched according to the patterned hard mask layer 116 to form layer stacks 3102, 3104. In some embodiments, etching stops at data storage layer 112. In some other embodiments, data storage layer 112 is etched, and etching stops at lower electrode layer 110 (see, for example...). Figure 10 ).

[0119] like Figure 32 As shown in cross-sectional view 3200, a first spacer layer 902 is conformally deposited on the layer stack 3102, 3104 (e.g., on the hard mask layer 116, the upper electrode layer 114, and the capping layer 202). The first spacer layer 902 covers the sidewalls of the hard mask layer 116, the sidewalls of the upper electrode layer 114, the sidewalls of the capping layer 202, and the upper surface of the data storage layer 112.

[0120] In some embodiments, the spacer layer 118 comprises a low-oxygen dielectric material or an oxygen-free dielectric material, and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0121] like Figure 33 As shown in cross-sectional view 3300, the first spacer layer 902 is etched to remove the first spacer layer 902 from the upper surface of the hard mask layer 116 and from a portion of the data storage layer 112, thus forming a first spacer structure on the sidewalls of the layer stack 3102, 3104 (e.g., on the sidewalls of the upper electrode layer 114 and the cover layer 202).

[0122] In some embodiments, etching includes a dry etching process or some other suitable process. In some embodiments, etching is performed without forming a masking layer over the spacer layer 118 (e.g., etching is a blanket etching process). In some embodiments, etching may remove a small portion of the hard mask layer 116 and / or the data storage layer 112.

[0123] Although Figures 31 to 33 The first spacer layer 902 is shown to be formed by depositing the first spacer layer on the upper electrode layer 114 and the cover layer 202 after etching the upper electrode layer 114 and the cover layer 202. However, in some other embodiments, the first spacer layer 902 is gradually formed by performing a cyclic deposition-etch process during etching the upper electrode layer 114 and etching the cover layer 202.

[0124] like Figure 34As shown in cross-sectional view 3400, the data storage layer 112, the lower electrode layer 110, and the barrier layer 108 are etched according to the hard mask layer 116 and the spacer layer 118 to separate the data storage layer 112 into independent data storage structures and to separate the lower electrode layer 110 into independent lower electrodes. The data storage structures and the lower electrodes are further formed into layer stacks 3102 and 3104.

[0125] The first spacer layer 902 protects the sidewalls of the upper electrode layer 114 and the cover layer 202 during the etching of the data storage layer 112 and the lower electrode layer 110. Therefore, oxidation of the protective layer can be reduced, and thus the performance and / or reliability of the memory cell can be improved.

[0126] like Figure 35 As shown in cross-sectional view 3500, a second spacer layer 118 is conformally deposited on the hard mask layer 116, the first spacer layer 902, the data storage layer 112, the lower electrode layer 110, and the barrier layer 108. The second spacer layer 118 covers the sidewalls of the first spacer layer 902, the sidewalls of the data storage layer 112, the sidewalls of the lower electrode layer 110, and the upper surface of the barrier layer 108.

[0127] In some embodiments, the second spacer layer 118 comprises a low-oxygen dielectric material or an oxygen-free dielectric material to reduce oxidation of the layer on which the second spacer layer 118 is deposited.

[0128] like Figure 36 As shown in the cross-sectional view 3600, the second spacer layer 118 is etched to remove the second spacer layer 118 from the upper surface of the hard mask layer 116 and from a portion of the barrier layer 108, thus forming a second spacer structure on the sidewalls of the first spacer layer 902, the sidewalls of the data storage layer 112, and the sidewalls of the lower electrode layer 110.

[0129] like Figure 37 As shown in cross-sectional view 3700, the barrier layer 108 is etched according to the hard mask layer 116 and the spacer layer 118 to separate the barrier layer 108 into individual barrier structures. The etching further forms memory cells 106, 702.

[0130] The second spacer layer 118 protects the sidewalls of the data storage layer 112 and the sidewalls of the lower electrode layer 110 during the etching barrier layer 108.

[0131] like Figure 38 As shown in the cross-sectional view 3800, the sealing layer 120 is conformally deposited over the memory cells 106, 702 and the diffusion barrier dielectric layer 502 to seal the memory cells 106, 702.

[0132] The second spacer layer 118 protects the sidewalls of the data storage layer 112 and the lower electrode layer 110 during the deposition of the sealing layer 120.

[0133] Figure 39 Flowcharts of some embodiments of a method 3900 for forming an integrated chip including memory cells are shown. The memory cells include spacer layers covering the sidewalls of an upper electrode layer, the sidewalls of a data storage layer, and the sidewalls of a lower electrode layer. While method 3900 is shown and described below as a series of steps or events, it should be understood that the shown order of such steps or events should not be construed as limiting. For example, some steps may occur in a different order and / or simultaneously with other steps or events in addition to those shown and / or described herein. Furthermore, not all steps shown may be necessary to implement one or more aspects or embodiments described herein. Additionally, one or more of the steps depicted herein may be performed in one or more separate steps and / or stages.

[0134] In block 3902, a barrier layer is deposited on the conductive interconnect, a lower electrode layer is deposited on the barrier layer, a data storage layer is deposited on the lower electrode layer, and an upper electrode layer is deposited on the data storage layer. The lower electrode layer is deposited to have a substantially large thickness to reduce undercut during subsequent etching of the lower electrode layer. Figure 18 A cross-sectional view 1800 is shown corresponding to some embodiments of block 3902.

[0135] In block 3904, an upper electrode layer, a data storage layer, and a lower electrode layer are etched to form a memory stack. Oxygen exposure during the etching of the lower electrode layer is reduced (e.g., oxygen concentration, oxygen exposure time, voltage applied during oxygen exposure, etc.) to reduce oxidation of the upper electrode layer and reduce undercut of the lower electrode layer. Furthermore, the post-etching ashing process time is reduced or eliminated, and the voltage applied during ashing is reduced or zero to further reduce oxidation of the upper electrode layer and further reduce undercut of the lower electrode layer. Figure 19 Cross-sectional view 1900 is shown for some embodiments corresponding to block 3904.

[0136] In block 3906, a spacer layer is formed covering the sidewalls of the memory stack. For example, the spacer layer is deposited on the sidewalls of the upper electrode layer, the sidewalls of the data storage layer, and the sidewalls of the lower electrode layer. Next, the spacer layer is etched to define the spacer layer. Figures 20 to 21 Cross-sectional views 2000-2100 are shown for some embodiments corresponding to block 3906.

[0137] In frame 3908, a barrier layer is etched to form a memory cell from the memory stack, spacer layer and barrier layer. Figure 22A cross-sectional view 2200 is shown corresponding to some embodiments of block 3908.

[0138] In box 3910, a sealing layer is deposited above the memory cell. The spacer layer protects the sidewalls of the upper electrode layer and the lower electrode layer from oxidation during the deposition of the sealing layer. Figure 23 A cross-sectional view 2300 corresponding to some embodiments of block 3910 is shown.

[0139] Therefore, embodiments of this disclosure relate to an integrated chip and a method of forming an integrated chip, the integrated chip including memory cells and one or more spacer layers located on the sidewalls of the memory cells to protect the memory cells during processing.

[0140] Therefore, in some embodiments, this disclosure relates to an integrated chip. The integrated chip includes a barrier layer comprising a first conductive material located above a semiconductor substrate. The integrated chip includes a lower electrode layer comprising a second conductive material different from the first conductive material located above the barrier layer. The integrated chip includes a dielectric layer located above the lower electrode layer. The integrated chip includes an upper electrode layer located above the dielectric layer. The integrated chip includes a sealing layer comprising a first dielectric material sealing the upper electrode layer, the dielectric layer, the lower electrode layer, and the barrier layer. The integrated chip includes a spacer layer comprising a second dielectric material different from the first dielectric material located on the upper surface of the barrier layer. The sealing layer is spaced apart from the sidewalls of the lower electrode layer, the dielectric layer, and the upper electrode layer by the spacer layer. In some embodiments, the spacer layer contacts the upper surface of the barrier layer, the sidewalls of the lower electrode layer, and the sidewalls of the dielectric layer. In some embodiments, the spacer layer is a first spacer layer. In some embodiments, the integrated chip further includes a second spacer layer located on the upper surface of the dielectric layer. In some embodiments, a second spacer layer covers the sidewalls of the upper electrode layer, and a first spacer layer covers the sidewalls of the lower electrode layer, the dielectric layer, and the second spacer layer. In some embodiments, the thickness of the lower electrode layer is greater than the thickness of the dielectric layer and greater than the thickness of the barrier layer. In some embodiments, the spacer layer is substantially oxygen-free. In some embodiments, the second dielectric material includes oxygen, the first dielectric material is silicon dioxide, and the atomic percentage of oxygen in the second dielectric material is less than the atomic percentage of oxygen in the silicon dioxide of the first dielectric material. In some embodiments, the sidewalls of the lower electrode layer, the dielectric layer, and the upper electrode layer are substantially aligned. In some embodiments, the sidewalls of the lower electrode layer are laterally offset from the sidewalls of the dielectric layer and the upper electrode layer by 1 to 50 angstroms. In some embodiments, the integrated chip further includes: a transistor located above a semiconductor substrate; a first conductive interconnect coupled to a first source / drain of the transistor; a capping layer located between the dielectric layer and the upper electrode layer; and a hard mask layer located above the upper electrode layer. The barrier layer is located on the upper surface of the first conductive interconnect. The capping layer includes a third conductive material. The upper electrode layer includes a fourth conductive material, different from the third conductive material. A sealing layer seals the cover layer and the hard mask layer. The sealing layer is spaced apart from the sidewalls of the cover layer and the hard mask layer by spacer layers.

[0141] In other embodiments, this disclosure relates to methods for forming an integrated chip. The method includes depositing a barrier layer comprising a first conductive material over a semiconductor substrate. The method includes depositing a lower electrode layer comprising a second conductive material different from the first conductive material over the barrier layer. The method includes depositing a data storage layer over the lower electrode layer. The method includes depositing an upper electrode layer over the data storage layer. The method includes etching the upper electrode layer, the data storage layer, and the lower electrode layer. The method includes depositing a spacer layer comprising a first dielectric material on the upper surface of the barrier layer, along the sidewalls of the lower electrode layer, along the sidewalls of the data storage layer, along the sidewalls of the upper electrode layer, and over the upper electrode layer. The method includes etching the spacer layer to remove the spacer layer from over the upper electrode layer. The method includes etching the barrier layer according to the spacer layer. The method includes depositing a sealing layer comprising a second dielectric material different from the first dielectric material over the upper electrode layer, along the sidewalls of the spacer layer, and along the sidewalls of the barrier layer. The spacer layer covers the sidewalls of the upper electrode layer, the data storage layer, and the lower electrode layer during the deposition of the sealing layer. In some embodiments, the duration for which the lower electrode layer is exposed to the first etching gas during etching is shorter than the duration for which the barrier layer is exposed to the second etching gas during etching the barrier layer. In some embodiments, the etching gas used during etching the lower electrode layer comprises oxygen and halogen, with halogen constituting more than half of the etching gas and oxygen constituting less than half. In some embodiments, after etching the lower electrode layer, the sidewalls of the upper electrode layer are oxidized, and the width of the oxidized region of the lower electrode layer is less than 100 angstroms. In some embodiments, after etching the lower electrode layer, the sidewalls of the lower electrode layer are laterally offset from the sidewalls of the data storage layer and the sidewalls of the upper electrode layer, and the offset is less than 50 angstroms. In some embodiments, tetraethyl orthosilicate (TEOS) and oxygen are used to deposit the sealing layer. In some embodiments, the method further includes forming a hard mask layer over the upper electrode layer. In some embodiments, the upper electrode layer, the data storage layer, and the lower electrode layer are etched according to the hard mask layer. In some embodiments, a spacer layer is deposited along the sidewalls of the hard mask layer and deposited above the upper surface of the hard mask layer. In some embodiments, the spacer layer is etched to remove the spacer layer from above the hard mask layer. In some embodiments, a barrier layer is etched based on the spacer layer and the hard mask layer. In some embodiments, a sealing layer is deposited above the upper surface of the hard mask layer. In some embodiments, the spacer layer is a first spacer layer. In some embodiments, the method further includes depositing a second spacer layer on the upper surface of the data storage layer, on the sidewalls of the upper electrode layer, and above the upper electrode layer. In some embodiments, the method further includes etching the second spacer layer to remove the spacer layer from above the upper electrode layer. In some embodiments, the data storage layer and the lower electrode layer are etched after the second spacer layer is etched.In some embodiments, a first spacer layer is deposited on top of a second spacer layer and on the sidewalls of a second spacer layer after etching the data storage layer and the lower electrode layer. In some embodiments, the central portion of the barrier layer includes a first conductive material, and the edge portion of the barrier layer includes the first conductive material and one or more of oxygen, fluorine, chlorine, bromine, and iodine after etching the lower electrode layer, and the spacer layer contacts the barrier layer at the edge portion of the barrier layer. In some embodiments, the edge portion of the barrier layer has a greater thickness than the central portion of the barrier layer. In some embodiments, after etching the lower electrode layer, a portion of the second conductive material is located on the sidewalls of the data storage layer.

[0142] In some other embodiments, this disclosure relates to a method for forming an integrated chip, the method including forming a barrier layer comprising a first conductive material over a semiconductor substrate. The method includes forming a lower electrode layer comprising a second conductive material different from the first conductive material over the barrier layer. The method includes forming a dielectric layer over the lower electrode layer. The method includes forming an upper electrode layer over the dielectric layer. The method includes forming a spacer layer comprising a first dielectric material on the upper surface of the barrier layer. The method includes sealing the upper electrode layer, dielectric layer, lower electrode layer, barrier layer, and spacer layer with a sealing layer comprising a second dielectric material different from the first dielectric material. The sealing layer is spaced apart from the sidewalls of the lower electrode layer, the dielectric layer, and the upper electrode layer by the spacer layer.

[0143] Some embodiments of this application provide an integrated chip, including: a barrier layer including a first conductive material located above a semiconductor substrate; a lower electrode layer including a second conductive material different from the first conductive material located above the barrier layer; a dielectric layer located above the lower electrode layer; an upper electrode layer located above the dielectric layer; a sealing layer including a first dielectric material sealing the upper electrode layer, the dielectric layer, the lower electrode layer, and the barrier layer; and a spacer layer including a second dielectric material different from the first dielectric material located on the upper surface of the barrier layer, wherein the sealing layer is spaced apart from the sidewalls of the lower electrode layer, the dielectric layer, and the upper electrode layer by the spacer layer.

[0144] In some embodiments, the spacer layer contacts the upper surface of the barrier layer, the sidewall of the lower electrode layer, and the sidewall of the dielectric layer. In some embodiments, the spacer layer is a first spacer layer, and the integrated chip further includes a second spacer layer located on the upper surface of the dielectric layer, wherein the second spacer layer covers the sidewall of the upper electrode layer, and wherein the first spacer layer covers the sidewall of the lower electrode layer, the sidewall of the dielectric layer, and the sidewall of the second spacer layer. In some embodiments, the thickness of the lower electrode layer is greater than the thickness of the dielectric layer and greater than the thickness of the barrier layer. In some embodiments, the spacer layer is substantially free of oxygen. In some embodiments, the second dielectric material includes oxygen, wherein the first dielectric material is silicon dioxide, and wherein the atomic percentage of oxygen in the second dielectric material is less than the atomic percentage of oxygen in the silicon dioxide of the first dielectric material. In some embodiments, the sidewalls of the lower electrode layer, the sidewall of the dielectric layer, and the sidewall of the upper electrode layer are substantially aligned. In some embodiments, the sidewalls of the lower electrode layer are laterally offset from the sidewalls of the dielectric layer and the upper electrode layer by 1 to 50 angstroms. In some embodiments, the integrated chip further includes: a transistor located above the semiconductor substrate; a first conductive interconnect coupled to a first source / drain of the transistor, wherein the barrier layer is located on the upper surface of the first conductive interconnect; a capping layer located between the dielectric layer and the upper electrode layer, wherein the capping layer comprises a third conductive material and the upper electrode layer comprises a fourth conductive material different from the third conductive material; and a hard mask layer located above the upper electrode layer, wherein the sealing layer further seals the capping layer and the hard mask layer, and wherein the sealing layer is spaced apart from the sidewalls of the capping layer and the sidewalls of the hard mask layer by the spacer layer.

[0145] Other embodiments of this application provide a method for forming an integrated chip, the method comprising: depositing a barrier layer comprising a first conductive material over a semiconductor substrate; depositing a lower electrode layer comprising a second conductive material different from the first conductive material over the barrier layer; depositing a data storage layer over the lower electrode layer; depositing an upper electrode layer over the data storage layer; etching the upper electrode layer, the data storage layer, and the lower electrode layer; depositing a spacer layer comprising a first dielectric material on the upper surface of the barrier layer, along the sidewalls of the lower electrode layer, along the sidewalls of the data storage layer, along the sidewalls of the upper electrode layer, and over the upper electrode layer; etching the spacer layer to remove the spacer layer from over the upper electrode layer; etching the barrier layer according to the spacer layer; and depositing a sealing layer comprising a second dielectric material different from the first dielectric material over the upper electrode layer, along the sidewalls of the spacer layer, and along the sidewalls of the barrier layer, wherein the spacer layer covers the sidewalls of the upper electrode layer, the sidewalls of the data storage layer, and the sidewalls of the lower electrode layer during the deposition of the sealing layer.

[0146] In some embodiments, the duration for which the lower electrode layer is exposed to a first etching gas during etching is shorter than the duration for which the barrier layer is exposed to a second etching gas during etching. In some embodiments, the etching gas used during etching the lower electrode layer comprises oxygen and halogen, wherein the halogen constitutes more than half of the etching gas and the oxygen constitutes less than half of the etching gas. In some embodiments, after etching the lower electrode layer, the sidewalls of the upper electrode layer are oxidized, wherein the width of the oxidized region of the lower electrode layer is less than 100 angstroms. In some embodiments, after etching the lower electrode layer, the sidewalls of the lower electrode layer are laterally offset from the sidewalls of the data storage layer and the sidewalls of the upper electrode layer, wherein the offset is less than 50 angstroms. In some embodiments, the method further includes: forming a hard mask layer over the upper electrode layer, wherein the upper electrode layer, the data storage layer, and the lower electrode layer are etched according to the hard mask layer, wherein the spacer layer is deposited along the sidewalls of the hard mask layer and deposited above the upper surface of the hard mask layer, wherein the spacer layer is etched to remove the spacer layer from above the hard mask layer, wherein the barrier layer is etched according to the spacer layer and the hard mask layer, and wherein the sealing layer is deposited above the upper surface of the hard mask layer. In some embodiments, the spacer layer is a first spacer layer, and the method further includes: depositing a second spacer layer on the upper surface of the data storage layer, on the sidewalls of the upper electrode layer, and over the upper electrode layer; and etching the second spacer layer to remove the spacer layer from above the upper electrode layer, wherein the data storage layer and the lower electrode layer are etched after the second spacer layer is etched, and wherein the first spacer layer is deposited above the second spacer layer and on the sidewalls of the second spacer layer after the data storage layer and the lower electrode layer are etched. In some embodiments, the central portion of the barrier layer includes the first conductive material, and the edge portion of the barrier layer, after etching the lower electrode layer, includes the first conductive material and one or more of oxygen, fluorine, chlorine, bromine, and iodine, wherein the spacer layer contacts the barrier layer at the edge portion. In some embodiments, the edge portion of the barrier layer has a greater thickness than the central portion of the barrier layer. In some embodiments, after etching the lower electrode layer, a portion of the second conductive material is located on the sidewall of the data storage layer.

[0147] Some embodiments of this application provide a method for forming an integrated chip, the method comprising: forming a barrier layer comprising a first conductive material over a semiconductor substrate; forming a lower electrode layer comprising a second conductive material different from the first conductive material over the barrier layer; forming a dielectric layer over the lower electrode layer; forming an upper electrode layer over the dielectric layer; forming a spacer layer comprising a first dielectric material on the upper surface of the barrier layer; and sealing the upper electrode layer, the dielectric layer, the lower electrode layer, the barrier layer, and the spacer layer with a sealing layer comprising a second dielectric material different from the first dielectric material, wherein the sealing layer is spaced apart from the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the upper electrode layer by the spacer layer.

[0148] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. An integrated chip, comprising: A barrier layer, comprising a first conductive material located above a semiconductor substrate; The lower electrode layer includes a second conductive material that is different from the first conductive material and is located above the barrier layer; A dielectric layer is located above the lower electrode layer; The upper electrode layer is located above the dielectric layer; The sealing layer includes a first dielectric material that seals the upper electrode layer, the dielectric layer, the lower electrode layer, and the barrier layer; as well as The spacer layer includes a second dielectric material different from the first dielectric material located on the upper surface of the barrier layer, wherein the sealing layer is spaced apart from the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the upper electrode layer by the spacer layer.

2. The integrated chip according to claim 1, wherein, The spacer layer contacts the upper surface of the barrier layer, the sidewall of the lower electrode layer, and the sidewall of the dielectric layer.

3. The integrated chip according to claim 1, wherein, The spacer layer is a first spacer layer, and the integrated chip further includes: A second spacer layer is located on the upper surface of the dielectric layer, wherein the second spacer layer covers the sidewall of the upper electrode layer, and wherein the first spacer layer covers the sidewall of the lower electrode layer, the sidewall of the dielectric layer, and the sidewall of the second spacer layer.

4. The integrated chip according to claim 1, wherein, The thickness of the lower electrode layer is greater than the thickness of the dielectric layer and also greater than the thickness of the barrier layer.

5. The integrated chip according to claim 1, wherein, The spacer layer is essentially oxygen-free.

6. The integrated chip according to claim 1, wherein, The second dielectric material includes oxygen, wherein the first dielectric material is silicon dioxide, and wherein the atomic percentage of oxygen in the second dielectric material is less than the atomic percentage of oxygen in the silicon dioxide of the first dielectric material.

7. The integrated chip according to claim 1, wherein, The sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the upper electrode layer are substantially aligned.

8. The integrated chip according to claim 1, wherein, The sidewall of the lower electrode layer is laterally offset from the sidewall of the dielectric layer and the sidewall of the upper electrode layer by 1 to 50 angstroms.

9. A method for forming an integrated chip, the method comprising: A barrier layer comprising a first conductive material is deposited over a semiconductor substrate; A lower electrode layer comprising a second conductive material different from the first conductive material is deposited above the barrier layer; A data storage layer is deposited above the lower electrode layer; A top electrode layer is deposited above the data storage layer; Etch the upper electrode layer, the data storage layer, and the lower electrode layer; A spacer layer comprising a first dielectric material is deposited on the upper surface of the barrier layer, along the sidewall of the lower electrode layer, along the sidewall of the data storage layer, along the sidewall of the upper electrode layer, and above the upper electrode layer; Etch the spacer layer to remove the spacer layer from above the upper electrode layer; The barrier layer is etched according to the spacer layer; and A sealing layer comprising a second dielectric material different from the first dielectric material is deposited above the upper electrode layer, along the sidewalls of the spacer layer and along the sidewalls of the barrier layer, wherein the spacer layer covers the sidewalls of the upper electrode layer, the sidewalls of the data storage layer and the sidewalls of the lower electrode layer during the deposition of the sealing layer.

10. A method for forming an integrated chip, the method comprising: A barrier layer comprising a first conductive material is formed above a semiconductor substrate; A lower electrode layer comprising a second conductive material different from the first conductive material is formed above the barrier layer; A dielectric layer is formed above the lower electrode layer; An upper electrode layer is formed above the dielectric layer; A spacer layer comprising a first dielectric material is formed on the upper surface of the barrier layer; and The upper electrode layer, the dielectric layer, the lower electrode layer, the barrier layer, and the spacer layer are sealed with a sealing layer comprising a second dielectric material different from the first dielectric material, wherein the sealing layer is spaced apart from the sidewalls of the lower electrode layer, the dielectric layer, and the upper electrode layer by the spacer layer.

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