Integrated circuit and method of manufacturing the same

Abstract

In some embodiments, an integrated circuit is provided. The integrated circuit includes transistors disposed along a semiconductor substrate, interconnect structures covering the transistors, and memory cells covering the transistors and coupled to the transistors through the interconnect structures. The interconnect structures include a plurality of wires disposed in a plurality of conductive interconnect layers, and a plurality of conductive vias. The memory cells include a plurality of resistance-varying elements coupled to each other through the interconnect structures and vertically disposed between a first conductive interconnect layer and a second conductive interconnect layer of the plurality of conductive interconnect layers, the second conductive interconnect layer covering and adjacent to the first conductive interconnect layer. Embodiments of the present invention also provide a method of manufacturing an integrated circuit.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of semiconductors, and more specifically, to integrated circuits and methods of manufacturing the same. Background Technology

[0002] Traditional p-bits typically use binary variables (e.g., 0 or 1) based on mathematical models (such as the Ising model) to solve problems, aiming to identify the optimal solution. However, many real-world problems require continuous variables (e.g., variables following a Gaussian distribution) rather than discrete binary values. To address this, Gaussian bits, which can represent continuous states, are sometimes used to solve practical problems. Gaussian bit circuits often suffer from large area requirements and complex metal wiring for multiple input and output signals. Therefore, improved Gaussian bit circuits that occupy less area and utilize simpler wiring structures are desirable to enhance scalability and integration. Summary of the Invention

[0003] An embodiment of the present invention provides an integrated circuit, comprising: a transistor disposed along a semiconductor substrate; an interconnect structure covering the transistor, wherein the interconnect structure includes a plurality of wires disposed in a plurality of conductive interconnect layers and a plurality of conductive vias; and a memory cell covering the transistor and coupled to the transistor through the interconnect structure, wherein the memory cell includes a plurality of resistance-varying elements coupled to each other through the interconnect structure and vertically disposed between a first conductive interconnect layer and a second conductive interconnect layer of the plurality of conductive interconnect layers, the second conductive interconnect layer covering and adjacent to the first conductive interconnect layer.

[0004] Another embodiment of the present invention provides an integrated circuit, comprising: a transistor disposed along a semiconductor substrate and including a first source / drain terminal, a second source / drain terminal, and a control terminal; an interconnect structure covering the transistor and including a plurality of wires disposed in a plurality of conductive interconnect layers, and a plurality of conductive vias; and a plurality of resistance-changing elements coupled to the transistor through the interconnect structure and vertically disposed between a first conductive interconnect layer and a second conductive interconnect layer in the plurality of conductive interconnect layers, the second conductive interconnect layer being located above and adjacent to the first conductive interconnect layer, wherein the plurality of resistance-changing elements are divided into a first element group and a second element group coupled in series, wherein the first element group includes a plurality of first resistance-changing elements coupled in parallel to each other, and wherein the second element group includes one or more second resistance-changing elements.

[0005] Another embodiment of the present invention provides a method for manufacturing an integrated circuit, comprising: forming a transistor along a first surface of a semiconductor substrate and including a first terminal; forming a first plurality of conductive interconnects above the first surface of the semiconductor substrate, wherein the first plurality of conductive interconnects includes a first wire electrically coupled to the first terminal of the transistor; forming a plurality of resistance-changing elements above the first plurality of conductive interconnects; and forming a second plurality of conductive interconnects above the plurality of resistance-changing elements, wherein the second plurality of conductive interconnects includes a second wire, wherein the plurality of resistance-changing elements are coupled between the first wire and the second wire in a series, parallel, or a combination of series and parallel connections. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1A This is a circuit diagram illustrating an exemplary Gaussian bit circuit having a transistor and multiple resistance-varying elements according to the first embodiment.

[0008] Figure 1B This is illustrated based on some embodiments. Figure 1A A cross-sectional view of a resistance-changing element in an exemplary Gaussian bit circuit.

[0009] Figure 1C According to the first embodiment, it can be described by Figure 1A The example Gaussian bit circuit outputs multiple states.

[0010] Figure 1D This is described according to the first embodiment. Figure 1A A cross-sectional view of an exemplary Gaussian bit circuit.

[0011] Figure 1E This is described according to the first embodiment. Figure 1D A layout view of an exemplary Gaussian bit circuit.

[0012] Figure 1F This is illustrated based on some embodiments and can be used for programming. Figure 1A A program circuit with multiple resistance-changing elements.

[0013] Figure 2A This is a circuit diagram illustrating another exemplary Gaussian bit circuit having a transistor and multiple resistance-varying elements according to the first embodiment.

[0014] Figure 2B This is described according to the first embodiment. Figure 2A A three-dimensional view of an exemplary Gaussian bit circuit.

[0015] Figure 2C This is described according to the first embodiment. Figure 2B A layout view of an exemplary Gaussian bit circuit.

[0016] Figure 3A This is a circuit diagram illustrating an exemplary Gaussian bit circuit having a transistor and multiple resistance-varying elements according to a second embodiment.

[0017] Figure 3B This is described according to the second embodiment. Figure 3A A cross-sectional view of an exemplary Gaussian bit circuit.

[0018] Figure 3C This is described according to the second embodiment. Figure 3B A layout view of an exemplary Gaussian bit circuit.

[0019] Figure 4A This is a circuit diagram illustrating another exemplary Gaussian bit circuit having a transistor and multiple resistance-varying elements according to the second embodiment.

[0020] Figure 4B This is described according to the second embodiment. Figure 4A A cross-sectional view of an exemplary Gaussian bit circuit.

[0021] Figure 4C This is described according to the second embodiment. Figure 4B A layout view of an exemplary Gaussian bit circuit.

[0022] Figure 5A This is a circuit diagram illustrating an exemplary Gaussian bit circuit having a transistor and multiple resistance-varying elements according to a third embodiment.

[0023] Figure 5B This is described according to the third embodiment. Figure 5A A cross-sectional view of an exemplary Gaussian bit circuit.

[0024] Figure 5C This is described according to the third embodiment. Figure 5B A layout view of an exemplary Gaussian bit circuit.

[0025] Figure 6A This is a circuit diagram illustrating another exemplary Gaussian bit circuit having a transistor and multiple resistance-varying elements according to the third embodiment.

[0026] Figure 6B This is described according to the third embodiment. Figure 6A A cross-sectional view of an exemplary Gaussian bit circuit.

[0027] Figure 6C This is described according to the third embodiment. Figure 6B A layout view of an exemplary Gaussian bit circuit.

[0028] Figure 7A This is a circuit diagram illustrating an exemplary Gaussian bit circuit having a transistor and multiple resistance-varying elements according to the fourth embodiment.

[0029] Figure 7B This is described according to the fourth embodiment. Figure 7A Cross-sectional view of a medium Gaussian bit circuit.

[0030] Figure 7C This is described according to the fourth embodiment. Figure 7B Layout view of a medium Gaussian bit circuit.

[0031] Figure 8A This is a circuit diagram illustrating a Gaussian bit circuit with a transistor and multiple resistance-varying elements according to the fourth embodiment.

[0032] Figure 8B This is described according to the fourth embodiment. Figure 8A Cross-sectional view of a medium Gaussian bit circuit.

[0033] Figure 8C This is described according to the fourth embodiment. Figure 8B Layout view of a medium Gaussian bit circuit.

[0034] Figures 9A to 9G These are a series of cross-sectional views of an intermediate semiconductor structure, illustrating its fabrication according to some embodiments. Figure 1A , Figure 1D and Figure 1E Some exemplary steps of a method for a Gaussian bit circuit having transistors and multiple resistance-varying elements.

[0035] Figure 10 This is based on some embodiments described for manufacturing. Figure 1A , Figure 1D and Figure 1E A flowchart of a method for using a Gaussian bit circuit with transistors and multiple resistance-varying elements. Detailed Implementation

[0036] This invention provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0037] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another (or other) element or component as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. In some embodiments, the terms “approximately” and / or “about” may be interpreted as meaning + / - 10% or + / - 5%, while in other embodiments, the terms “approximately” and / or “about” may be interpreted as meaning within the normal manufacturing tolerances of a given wafer fab manufacturing process.

[0038] Gaussian bit circuits are commonly used in computational paradigms based on randomness, probability, or statistical distributions. They can be used in applications such as stochastic computation, probabilistic inference engines, machine learning (ML) hardware accelerators, security and cryptography, and neuromorphic computation. A traditional Gaussian bit circuit typically consists of multiple unit cells, each containing one transistor (1T) and one magnetic tunnel junction (1MTJ), hence a "1T1MTJ" configuration. This type of Gaussian bit circuit can ideally represent 2... N There are 3 distinct states, where N is the total number of “1T1MTJ” unit cells. In the example, where N = 4, the Gaussian bits comprise four “1T1MTJ” unit cells and can ideally represent sixteen (2^36) units. 4 However, such Gaussian bit circuits may disadvantageously occupy a large area and may have complex metal wiring for input and output signals.

[0039] This disclosure relates to various designs, configurations, and implementations of Gaussian bit circuits. In some embodiments, a Gaussian bit circuit includes a first power node for receiving one of a supply voltage and a reference voltage, a second power node for receiving the other of the supply voltage and the reference voltage, an input node for receiving an input signal, an output node for providing an output signal, a transistor including a first terminal coupled to the output node, a second terminal coupled to the second power node, and a control terminal coupled to the input node, and a plurality of resistance-changing elements coupled between the first power node and the output node in parallel, series, or a combination of series and parallel. In some embodiments, the resistance-changing elements are magnetic tunnel junctions (MTJs). Therefore, Gaussian bit circuits occupy a smaller area and allow for simplified metal wiring for input and output signals, thereby advantageously enhancing integration efficiency and scalability.

[0040] Figure 1A This section describes a circuit diagram of an exemplary Gaussian bit circuit 100 having a transistor 110 and a plurality of resistance-changing elements 120 according to a first embodiment of the present disclosure. The exemplary Gaussian bit circuit 100 includes a first power node 102 for receiving one of a supply voltage (VDD) and a reference voltage (GND), a second power node 104 for receiving the other of the supply voltage (VDD) and the reference voltage (GND), an input node 106 for receiving an input signal (Vin), and an output node 108 for providing an output signal (Vm). In some embodiments, the first power node 102 is used to receive the supply voltage (VDD), and the second power node 104 is used to receive the reference voltage (GND) (e.g., ...). Figure 1A As shown), in other embodiments, the first power node 102 is used to receive the reference voltage (GND), and the second power node 104 is used to receive the supply voltage (VDD) (not shown).

[0041] In some embodiments, the exemplary Gaussian bit circuit 100 further includes a transistor 110 and a plurality of (Q) resistance variation elements 120 (e.g., 120(1) to 120(Q)) integrated with the transistor 110. In some embodiments, the transistor 110 includes a first terminal (e.g., a source terminal) 112 coupled to an output node 108, a second terminal (e.g., a drain terminal) 114 coupled to a second power node 104, and a control terminal (e.g., a gate terminal) 116 coupled to an input node 106. In some embodiments, the control terminal 116 may be implemented in different transistor architectures, such as a FinFET, a Gate All-Around (GAA) FET, or a Complementary FET (CFET). The control terminal 116 may include a gate dielectric layer comprising a high dielectric constant dielectric material (e.g., HfO2, k > 10) and a gate electrode comprising a work function metal (e.g., TiN, TaN, Ru, Mo, or W). In some embodiments, a plurality of (Q) resistance variation elements 120 (e.g., 120(1) to 120(Q), e.g., Q = 4) are coupled between the first power node 102 and the output node 108 in a combination of series and parallel configurations (e.g. Figure 1A As shown). In some embodiments, Figure 1A The plurality of (Q) resistance-changing elements 120 (e.g., 120(1) to 120(Q)) are plurality of magnetoresistive random access memory (MRAM) elements, each containing a magnetic tunnel junction (MTJ). In various embodiments, the plurality of (Q) resistance-changing elements 120 (e.g., 120(1) to 120(Q)) may each be or include a phase-change random access memory (PCRAM) element, a resistive random access memory (RRAM) element, a metal cation RRAM element, etc. In other embodiments, Figure 1A The multiple resistance-changing elements are selected from temperature-dependent resistors, light-dependent resistors, strain-dependent resistors, voltage-dependent resistors, humidity-dependent resistors, or piezoelectric resistors.

[0042] In some embodiments, a plurality of (Q) resistance-changing elements 120 (e.g., 120(1) to 120(Q)) are divided into a number (n) element groups 120G (120G(1) to 120G(n)), which are coupled in parallel between the first power node 102 and the output node 108, and each element group 120G (e.g., 120G(1)) includes a number (m) series-coupled resistance-changing elements 120 (e.g., 120(1) to 120(m)), so Q = n × m. This configuration of the Gaussian bit circuit 100 may be referred to as the “1T + (n × m)MTJ” configuration.

[0043] In some embodiments, in the “1T + (n × m)MTJ” configuration, the number (n) of element groups 120G is equal to the number (m) of resistance-changing elements 120 in each element group 120G, i.e., n = m. For example... Figure 1A As shown, n = m = 2, therefore Q = n × m = n × n = 2 × 2. For example... Figure 2A As shown, n = m = 3, therefore Q = n × m = n × n = 3 × 3. In some embodiments, the quantity n can be in the range of 2 to 10.

[0044] In other embodiments, in the “1T + (n×m)MTJ” configuration (not shown in the figure), the number (n) of element groups 120G is different from the number (m) of resistance-changing elements 120 (120(1) to 120(m)) in each element group 120G (e.g., 120G(1)), i.e., n ≠ m, n > 1, m > 1, therefore Q = n × m (e.g., 3×2, 4×2, 4×3, 5×2, 5×3, 5×4, 6×2, 6×3, 6×4, 6×5, etc.) (not shown in the figure). In some embodiments, the number n can be in the range of 2 to 10, and the number m can be in the range of 2 to 10.

[0045] In some embodiments, such as, for example Figure 1A As shown, the memory cell includes a plurality of resistance-varying elements 120 (e.g., 120(1) to 120(4)) coupled between a single input node 106 and a single output node 108. The memory cell is configured to have a number of discrete data states greater than the number of resistance-varying elements 120 among the plurality of resistance-varying elements 120 (e.g., four), and the number of resistance-varying elements is equal to or greater than two.

[0046] Figure 1B Description based on some embodiments Figure 1A A cross-sectional view of an exemplary MTJ 120 (e.g., 120(1)) of a plurality of (Q) MTJ 120s (e.g., 120(1) to 120(Q)) in an exemplary Gaussian bit circuit 100. In some embodiments, the MTJ 120 (e.g., 120(1)) includes a pinned magnetic layer 122, a free magnetization layer 124, and a tunneling barrier layer 126 perpendicularly separating the pinned magnetic layer 122 and the free magnetization layer 124. The magnetic orientation of the pinned magnetic layer 122 is static (i.e., fixed), while the magnetic orientation of the free magnetization layer 124 is switchable between a parallel configuration and an antiparallel configuration relative to the pinned magnetic layer 122. The parallel configuration provides a low-resistance state that digitally stores data as a first data state (e.g., logic "0"). The antiparallel configuration provides a high-resistance state that digitally stores data as a second data state (e.g., logic "1").

[0047] Figure 1C The description, based on some embodiments, can be derived from... Figure 1A The output (or output signal) Vm of the exemplary Gaussian bit circuit 100 represents multiple states. In some embodiments, Figure 1A Each resistance-changing element (e.g., 120(1)) of the resistance-changing element 120 is a magnetic tunnel junction (MTJ). Each MTJ 120 (e.g., 120(1) to 120(Q)) can be programmed to represent either logic "0" or logic "1". (See reference...) Figure 1B The resistance of the MTJ 120 (e.g., 120(1)) can be changed by manipulating the magnetization of its free magnetization layer 124, for example, by applying an external voltage pulse. By changing the magnetization orientation of the free magnetization layer 124, the MTJ 120 (e.g., 120(1)) can switch between a low resistance (parallel alignment) state (representing logic "0") and a high resistance (anti-parallel alignment) state (representing logic "1"). Figure 1A The MTJ 120 comprises a total of four MTJ120(1) to 120(4) arranged in a “1T + (2× 2)MTJ” configuration.

[0048] Reference Figure 1F Its description, according to some embodiments, can be used for programming. Figure 1A A programmable circuit 150 comprising multiple resistance-changing elements. The programmable circuit 150 includes a control circuit 170 and a voltage pulse circuit 180, the voltage pulse circuit 180 being coupled to the control circuit 170 and also coupled to… Figure 1A Each MTJ 120 (e.g., 120(1) to 120(4)). Control circuitry 170 is programmed to control voltage pulse circuitry 180 to selectively supply voltage pulses to Figure 1A The MTJ 120 can be set to either a low resistance state (representing logic "0") or a high resistance state (representing logic "1").

[0049] In the first embodiment, Figure 1AThe output signal Vm of the exemplary Gaussian bit circuit 100 has five voltage magnitudes. The output signal Vm has a first voltage magnitude when the four MTJs 120(1) to 120(4) are programmed to represent “0000”. The output signal Vm has a second voltage magnitude when the four MTJs 120(1) to 120(4) are programmed to represent any one of “1000”, “0100”, “0010”, and “0001”. The output signal Vm has a third voltage magnitude when the four MTJs 120(1) to 120(4) are programmed to represent any one of “1010”, “0110”, “1001”, and “0101”. The output signal Vm has a fourth voltage magnitude when the four MTJs 120(1) to 120(4) are programmed to represent any one of “1110”, “1011”, “1101”, and “0111”. When the four MTJs 120(1) to 120(4) are programmed to represent “1111”, the output signal Vm has a fifth voltage magnitude.

[0050] In the second embodiment, Figure 1A The output signal Vm of the exemplary Gaussian bit circuit 100 has six voltage magnitudes, including the first to fifth voltage magnitudes described in the first embodiment, and a sixth voltage magnitude. The output signal Vm has an additional sixth voltage magnitude when the four MTJs 120(1) to 120(4) are programmed to represent either "1100" or "0011".

[0051] Figure 1D Description based on the first embodiment Figure 1A A cross-sectional view of an exemplary Gaussian bit circuit 100. Figure 1E Description based on the first embodiment Figure 1D A layout view of an exemplary Gaussian bit circuit 100.

[0052] like Figure 1D As shown, in some embodiments, transistor 110 is formed along the front side 130f of semiconductor substrate 130, and conductive interconnect structure 160 is formed in dielectric layer 140 disposed above the front side 130f of semiconductor substrate 130. In some embodiments, conductive interconnect structure 160 includes a plurality of wires L (e.g., L1, L2, L3, L4, L5, L6, etc.) respectively disposed in a plurality of conductive interconnect layers M (e.g., M1, M2, M3, M4, M5, M6, etc.), and a plurality of conductive vias V for selectively connecting some of the plurality of wires L.

[0053] like Figure 1DAs shown, in some embodiments, the exemplary Gaussian bit circuit 100 further includes a first power node 102 for receiving one of the supply voltages (VDD), a second power node 104 for receiving a reference voltage (GND), an input node 106 for receiving an input signal (Vin), an output node 108 for providing an output signal (Vm), a transistor 110, and a plurality of (Q)MTJs 120 (e.g., four MTJs 120(1) to 120(4)) coupled to the transistor 110 via a conductive interconnect structure 160. In some embodiments, the transistor 110 includes a first terminal (e.g., a source terminal) 112 coupled to the output node 108 (e.g., via lines such as L1, L2, L3 and a plurality of vias V), a second terminal (e.g., a drain terminal) 114 coupled to the second power node 104 (e.g., via lines such as L1, L2 and vias), and a control terminal (e.g., a gate terminal) 116 coupled to the input node 106 (e.g., via L1 and vias V).

[0054] Reference Figure 1A and Figure 1D Four MTJs 120(1) to 120(4) are coupled between a first power node 102 and an output node 108 via a conductive interconnect structure 160 in a combination of parallel and series configurations. In some embodiments, the four MTJs 120 (e.g., 120(1) to 120(4)) are distinguished into two MTJ groups (or branches) 120G, such as a first MTJ group 120G(1) and a second MTJ group 120G(2), which are coupled in parallel via the conductive interconnect structure 160. The first MTJ group 120G(1) includes a first MTJ 120(1) and a second MTJ 120(2) coupled in series via the conductive interconnect structure 160, and the second MTJ group 120G(2) includes a third MTJ 120(3) and a fourth MTJ 120(4) coupled in series via the conductive interconnect structure 160. In some embodiments, the MTJ 120 (e.g., 120(1)) is vertically disposed in the back-end process (BEOL) above the front side 130f of the semiconductor substrate 130, and is vertically disposed between the bottom electrode (e.g., wire L4 in conductive layer M4) and the top electrode (e.g., wire L5 in conductive layer M5). In some embodiments, the MTJ 120 (e.g., 120(1) to 120(Q)) is disposed in a one-dimensional array, while in other embodiments, the MTJ 120 (e.g., 120(1) to 120(Q)) is disposed in a two-dimensional array.

[0055] In some embodiments, such as Figure 1D and Figure 1EAs shown, all (Q)MTJ 120s (e.g., 120(1) to 120(Q)) are coplanar. For example, all MTJ 120s (e.g., 120(1) to 120(Q)) are located between the i-th conductive layer (Mi) (e.g., but not limited to the fourth conductive layer (M4)) and the (i+1)-th conductive layer (M(i+1)) (e.g., but not limited to the fifth metal layer (M5)), where i ≥ 1. In other embodiments, not shown, the MTJ 120s (e.g., 120(1) to 120(Q)) are alternatively non-coplanar. For example, some of the MTJ 120s (e.g., 120(1) to 120(Q)) may be located, for example, between the fourth metal layer (M4) and the fifth metal layer (M5), and others of the MTJ 120s (e.g., 120(1) to 120(Q)) may be located, for example, between the second metal layer (M2) and the third metal layer (M3).

[0056] In some embodiments, such as Figure 1D and Figure 1E As shown, wires L (e.g., L4 and L5) for connecting MTJ 120 (e.g., 120(1) to 120(Q)) together are formed in two conductive layers M (e.g., M4 and M5), wire L (e.g., L6) for transmitting supply voltage (VDD) is formed in conductive layer (e.g., M6), wire L (e.g., L2) for transmitting reference voltage (GND) is formed in conductive layer (e.g., M2), wire L (e.g., L1) for transmitting input signal (Vin) is formed in conductive layer (e.g., M1), and wire L (e.g., L3) for transmitting output signal (Vm) is formed in conductive layer (e.g., M3).

[0057] Since it mainly requires one transistor 110, one input node 106 and one output node 108, the Gaussian bit circuit 100 occupies a small area and has simplified metal wiring for the input signal (Vin) and the output signal (Vm), thereby advantageously enhancing integration efficiency and scalability.

[0058] Figure 2A A circuit diagram illustrating another exemplary Gaussian bit circuit 200 having a transistor 110 and a plurality of resistance changing elements 120 according to the first embodiment is provided. Figure 2B Description based on the first embodiment Figure 2A A three-dimensional (3D) view of an exemplary Gaussian bit circuit 200. Figure 2C Description based on the first embodiment Figure 2B A layout view of an exemplary Gaussian bit circuit 200. Similar to... Figure 1A Gaussian bit circuit 100 in the middle, Figure 2A The Gaussian bit circuit 200 in the middle has a configuration of “1T + (n×n)MTJ”, where n = 3.

[0059] like Figure 2A , Figure 2B and Figure 2C As shown, the exemplary Gaussian bit circuit 200 includes a first power node 102 for receiving one of a supply voltage (VDD) and a reference voltage (GND), a second power node 104 for receiving the other of the supply voltage (VDD) and the reference voltage (GND), an input node 106 for receiving an input signal (Vin), and an output node 108 for providing an output signal (Vm), a transistor 110, and a plurality of (Q) resistance-changing elements 120 (e.g., 120(1) to 120(9)) coupled to the transistor 110. In some embodiments, the transistor 110 includes a first terminal (e.g., a source terminal) 112 coupled to the output node 108, a second terminal (e.g., a drain terminal) 114 coupled to the second power node 104, and a control terminal (e.g., a gate terminal) 116 coupled to the input node 106. In some embodiments, the plurality of (Q) resistance-changing elements 120 (e.g., 120(1) to 120(9)) are a plurality of magnetic tunnel junctions (MTJs).

[0060] Reference Figure 2A and Figure 2B Nine MTJs 120(1) to 120(9) are coupled between a first power node 102 and an output node 108 via a conductive interconnect structure 160 in a combination of parallel and series configurations. In some embodiments, the nine MTJs 120 (e.g., 120(1) to 120(9)) are divided into three MTJ groups (or branches) 120G, such as a first MTJ group 120G(1), a second MTJ group 120G(2), and a third MTJ group 120G(3), which are coupled in parallel via the conductive interconnect structure 160. The first MTJ group 120G(1) includes a first MTJ 120(1), a second MTJ 120(2), and a third MTJ 120(3) coupled in series via the conductive interconnect structure 160. The second MTJ group 120G(2) includes a fourth MTJ 120(4), a fifth MTJ 120(5), and a sixth MTJ 120(6) coupled in series via the conductive interconnect structure 160. The third MTJ group 120G (3) includes a seventh MTJ 120 (7), an eighth MTJ 120 (8), and a ninth MTJ 120 (9) coupled in series via a conductive interconnect structure 160. Although Figure 1A Show Q = 2 × 2 (n = 2) and Figure 2A The expression Q = 3 × 3 (n = 3), where n is not limited to 2 or 3. In some embodiments, Q = n × n, and n can be any integer greater than 1, such as n = 2, 3, 4, 5, 6, 7, 8, 9, or 10.

[0061] Figure 3AA circuit diagram illustrating an exemplary Gaussian bit circuit 300 having a transistor 110 and a plurality of resistance-changing elements 120 according to the second embodiment is provided. Figure 3B Description based on the second embodiment Figure 3A A cross-sectional view of an exemplary Gaussian bit circuit 300. Figure 3C Description based on the second embodiment Figure 3B A layout view of an exemplary Gaussian bit circuit 300.

[0062] like Figure 3A The implementation method in the second embodiment shown is similar to that in the first embodiment (e.g., as shown in the first embodiment). Figure 1A and 2A As shown), but with some differences. In the first embodiment, the Gaussian bit circuit 100 includes transistor 110 and a plurality of (Q)MTJs 120 (e.g., 120(1) to 120(Q)) in a configuration of “1T + (n×m)MTJ”, where Q = n×m, n = m (e.g., in Figure 1A (m), or n ≠ m (not shown in the figure). In the second embodiment, for example, in Figure 3A In the Gaussian bit circuit 300, transistor 110 and multiple (Q)MTJs 120 (e.g., 120(1) - 120(Q)) in different configurations “1T + (n + m)MTJs”, where Q = n + m, n ≥ 1, m ≥ 1, and n ≠ m. For example, in a second embodiment, Q can be 2 + 1, 2 + 3, 2 + 4, 3 + 1, 3 + 2, 3 + 4, 4 + 1, 4 + 2, 4 + 3, etc.

[0063] In the second embodiment, a plurality of (Q) MTJ 120s (e.g., 120(1) to 120(Q)) are divided into a first element group 120G(1) and a second element group 120G(2). The first element group 120G(1) includes a first number (n) of MTJ 120s (e.g., 120(1) to 120(n)). The second element group 120G(2) includes a second number (m) of MTJ 120s (e.g., 120(n+1) to 120(Q)). The MTJ 120(1) to 120(n) of the first element group 120G(1) are coupled between the first power node 102 and the intermediate node 152, and are coupled in parallel to each other when n ≥ 2 (e.g., ...). Figure 3A and Figure 4A As shown). The MTJ 120(n+1) to 120(Q) of the second element group 120G(2) are coupled between the intermediate node 152 and the output node Vm, and are coupled in parallel to each other when m ≥ 2 (as shown). Figure 4A (As shown).

[0064] like Figure 3AAs shown, in some embodiments, the Gaussian bit circuit 300 is configured as “1T + (2 + 1) MTJ”. The three MTJs 120(1) to 120(3) are distinguished as a first element group 120G(1) and a second element group 120G(2). The first element group 120G(1) includes the first MTJ 120(1) and the second MTJ 120(2), which are coupled in parallel between each other between the first power node 102 (for VDD) and the intermediate node 152. The second element group 120G(2) includes the third MTJ 120(3), which is coupled between the intermediate node 152 and the output node 108 (for providing Vm).

[0065] Figure 4A A circuit diagram illustrating another exemplary Gaussian bit circuit 400 having a transistor 110 and a plurality of resistance changing elements 120 according to the second embodiment is provided. Figure 4B Description based on the second embodiment Figure 4A A cross-sectional view of an exemplary Gaussian bit circuit 400. Figure 4C Description based on the second embodiment Figure 4B A layout view of an exemplary Gaussian bit circuit 400.

[0066] like Figure 4A As shown, in some embodiments, the Gaussian bit circuit 400 is configured as “1T + (3 + 2) MTJs”. The five MTJs 120(1) to 120(5) are divided into a first element group 120G(1) and a second element group 120G(2). The first element group 120G(1) includes a first MTJ 120(1), a second MTJ 120(2) and a third MTJ 120(3), which are coupled in parallel to each other between a first power node 102 (for VDD) and an intermediate node 152. The second element group 120G(2) includes a fourth MTJ 120(4) and a fifth MTJ 120(5), which are coupled in parallel to each other between an intermediate node 152 and an output node 108 (for providing Vm).

[0067] Figure 5A A circuit diagram illustrating an exemplary Gaussian bit circuit 500 having a transistor 110 and a plurality of resistance-changing elements 120 according to a third embodiment is provided. Figure 5B Description based on the third embodiment Figure 5A A cross-sectional view of an exemplary Gaussian bit circuit 500. Figure 5C Description based on the third embodiment Figure 5B A layout view of an exemplary Gaussian bit circuit 500.

[0068] In some embodiments, the Gaussian bit circuit 500 includes a first power node 102 for receiving one of the supply voltages (VDD), a second power node 104 for receiving a reference voltage (GND), an input node 106 for receiving an input signal (Vin), an output node 108 for providing an output signal (Vm), a transistor 110 including a first terminal 112 coupled to the output node 108, a second terminal 114 coupled to the second power node 104, and a control terminal 116 coupled to the input node 106, and a plurality of (Q)MTJs 120(1) to 120(Q) coupled in series between the first power node 102 and the output node 108. Figure 5A As shown, in some embodiments, Q = 2, that is, the first MTJ 120 (1) and the second MTJ 120 (2) are coupled in series between the first power node 102 and the output node 108. Figure 5A The exemplary Gaussian bit circuit 500 has at least three states. That is, when transistor 110 is turned on, the output (or output signal) Vm has at least three voltage magnitudes.

[0069] like Figure 5B and Figure 5C As shown, in some embodiments, input node 106 and output node 108 are disposed in a conductive layer above transistor 110 and below MTJ 120(1) and 120(2), and output node 108 is disposed in a conductive layer above input node 106. In some embodiments, MTJ 120(1) and 120(2) are as follows Figure 5B The configuration shown is coplanar, while in other embodiments, MTJ 120(1) and 120(2) are not coplanar (not shown).

[0070] Figure 6A A circuit diagram illustrating another exemplary Gaussian bit circuit 600 having a transistor and multiple resistance-varying elements according to the third embodiment is provided. Figure 6B Description based on the third embodiment Figure 6A A cross-sectional view of an exemplary Gaussian bit circuit 600. Figure 6C Description based on the third embodiment Figure 6B A layout view of an exemplary Gaussian bit circuit 600. Figure 6A The exemplary Gaussian bit circuit 600 is similar to Figure 5A The exemplary Gaussian bit circuit 500, in addition to the exemplary Gaussian bit circuit 600, includes three MTJs 120(1), 120(2), and 120(3) series coupled between the first power supply node 102 and the output node 108. Figure 6B and Figure 6CAs shown, in some embodiments, input node 106 and output node 108 are disposed in a conductive layer above transistor 110 and below MTJ 120 (e.g., 120(1) to 120(3)), and output node 108 is disposed in a conductive layer above input node 106.

[0071] Although Figure 5A The number of MTJ 120s connected in series between the first power node 102 and the output node 108 is two, and Figure 6A The number of MTJ 120s series-coupled between the first power node 102 and the output node 108 is shown to be three, but according to the third embodiment, the number of MTJ 120s series-coupled between the first power node 102 and the output node 108 can be any integer greater than two. In some embodiments, the number of MTJ 120s series-coupled between the first power node 102 and the output node 108 is in the range of 2 to 10.

[0072] Figure 7A A circuit diagram illustrating an exemplary Gaussian bit circuit 700 having a transistor 110 and a plurality of resistance-changing elements 120 according to the fourth embodiment is provided. Figure 7B Description based on the fourth embodiment Figure 7A A cross-sectional view of an exemplary Gaussian bit circuit 700. Figure 7C Description based on the fourth embodiment Figure 7B A layout view of an exemplary Gaussian bit circuit 700.

[0073] In some embodiments, the exemplary Gaussian bit circuit 700 includes a first power node 102 for receiving one of the supply voltages (VDD), a second power node 104 for receiving a reference voltage (GND), an input node 106 for receiving an input signal (Vin), an output node 108 for providing an output signal (Vm), a transistor 110 including a first terminal 112 coupled to the output node 108, a second terminal 114 coupled to the second power node 104, and a control terminal 116 coupled to the input node 106, and a plurality of (Q)MTJs 120 (120(1) to 120(Q)) coupled in parallel between the first power node 102 and the output node 108. Figure 7A As shown, in some embodiments, Q = 2, that is, the first MTJ 120 (1) and the second MTJ 120 (2) are coupled in parallel between the first power node 102 and the output node 108.

[0074] Figure 8A A circuit diagram illustrating another exemplary Gaussian bit circuit 800 having a transistor and multiple resistance-changing elements according to the fourth embodiment is provided. Figure 8B Description based on the fourth embodiment Figure 8AA cross-sectional view of an exemplary Gaussian bit circuit 800. Figure 8C Description based on the fourth embodiment Figure 8B A layout view of an exemplary Gaussian bit circuit 800. Figure 8A The exemplary Gaussian bit circuit 800 is similar to Figure 7A The exemplary Gaussian bit circuit 700, in addition to the exemplary Gaussian bit circuit 800, includes three MTJs 120(1), 120(2), and 120(3) coupled in parallel between the first power supply node 102 and the output node 108. Figure 8B and Figure 8C As shown, in some embodiments, input node 106 and output node 108 are configured in a conductive layer above transistor 110 and below MTJ 120 (e.g., 120(1) to 120(3)), and output node 108 is configured in a conductive layer above input node 106.

[0075] Although Figure 7A The number of MTJ 120s connected in parallel between the first power node 102 and the output node 108 is two, and Figure 8A The number of MTJ 120s parallelly coupled between the first power node 102 and the output node 108 is shown to be three, but according to a third embodiment, the number of MTJ 120s parallelly coupled between the first power node 102 and the output node 108 can be any integer greater than one. In some embodiments, the number of MTJ 120s parallelly coupled between the first power node 102 and the output node 108 is in the range of 2 to 10.

[0076] Figures 9A to 9G These are a series of cross-sectional views of the intermediate semiconductor structure, illustrating its fabrication according to some embodiments. Figure 1A , Figure 1D and Figure 1E Some exemplary steps of a method for an exemplary Gaussian bit circuit 100 having transistors and multiple resistance-changing elements. Although Figures 9A to 9G It's about the method description, but it should be understood that... Figures 9A to 9G The structures revealed are not limited to this method, but can exist independently of the method.

[0077] Reference Figure 1A , Figure 1D and Figure 1EAn exemplary Gaussian bit circuit 100 includes a first power node 102 for receiving a supply voltage (VDD), a second power node 104 for receiving a reference voltage (GND), an input node 106 for receiving an input signal (Vin), an output node 108 for providing an output signal (Vm), a transistor 110 including a first terminal 112 coupled to the output node 108, a second terminal 114 coupled to the second power node 104, and a control terminal 116 coupled to the input node 106, and a plurality (e.g., four) MTJ 120s (e.g., 120(1) to 120(4)) coupled in series and parallel combinations between the first power node 102 and the output node 108. MTJ 120(1) and 120(2) are coupled in series to form a first element group 120G(1), MTJ 120(3) and 120(4) are coupled in series to form a second element group 120G(2), and the first element group 120G(1) and the second element group 120G(2) are coupled in parallel.

[0078] like Figure 9A As shown in cross-sectional view 900A, in some embodiments, a transistor 110 including a first source / drain terminal 112, a second source / drain terminal 114, and a gate terminal 116 is formed along the front side 130f of the semiconductor substrate 130.

[0079] like Figure 9B As shown in cross-sectional view 900B, in some embodiments, a dielectric layer 140 is formed over the front side 130f of the semiconductor substrate 130, and a conductive interconnect structure 160 is formed in the dielectric layer 140. In some embodiments, the conductive interconnect structure 160 includes a plurality of wires L (e.g., L1 to L6) respectively disposed in a plurality of conductive interconnect layers (e.g., M1 to M6), and a plurality of conductive vias V selectively coupled to some of the plurality of wires L.

[0080] In some embodiments, an input node 106 configured to receive an input signal (Vin) is formed in a first conductive layer (e.g., M1) of a plurality of conductive layers M (e.g., M1 to M6), and is coupled to a control terminal 116 of a transistor 110 via at least a portion of a conductive interconnect structure 160. In some embodiments, a second power node 104 is formed in a second conductive layer (e.g., M2) of a plurality of conductive layers M (e.g., M1 to M6), and is coupled to a second terminal 114 of a transistor 110 via at least a portion of a conductive interconnect structure 160. In some embodiments, an output node 108 configured to provide an output signal (Vm) is formed in a third conductive layer (e.g., M3) of a plurality of conductive layers M (e.g., M1 to M6).

[0081] like Figure 9CAs shown in cross-sectional view 900C, in some embodiments, a pinned magnetic layer 122 is formed above the top surface of the dielectric layer 140, a tunneling barrier layer 126 is formed above the pinned magnetic layer 122, and a free magnetization layer 124 is formed above the pinned magnetic layer 122 by, for example, a deposition process (e.g., CVD, PVD, etc.). The material of the pinned magnetic layer 122 has a fixed magnetization direction. The material of the free magnetization layer 124 has a switchable magnetization direction. The material of the tunneling barrier layer 126 vertically separates the pinned magnetic layer 122 and the free magnetization layer 124. In some embodiments, the material of the pinned magnetic layer 122 includes cobalt iron boron (CoFeB) or cobalt iron (CoFe). In some embodiments, the material of the free magnetization layer 124 includes CoFeB or a nickel iron (NiFe) alloy. In some embodiments, the material of the tunneling barrier layer 126 includes magnesium oxide (MgO) or aluminum oxide (Al2O3).

[0082] like Figure 9D As shown in cross-sectional view 900D, in some embodiments, openings (or grooves) 902 are formed by employing, for example, a photolithography process followed by an etching process, perpendicularly passing through the free magnetization layer 124, the tunneling barrier layer 126, and the pinned magnetic layer 122 in some areas, while retaining the free magnetization layer 124, the tunneling barrier layer 126, and the pinned magnetic layer 122 in other areas. Thus, a plurality of MTJs 120 (e.g., 120(1) to 120(4)) are formed, each MTJ 120 (e.g., 120(4)) including the pinned magnetic layer 122, the free magnetization layer 124, and a tunneling barrier layer 126 perpendicularly located between the pinned magnetic layer 122 and the free magnetization layer 124 to separate them from each other.

[0083] like Figure 9E As shown in cross-sectional view 900E, in some embodiments, an additional layer of dielectric layer 140 is formed by employing, for example, deposition processes (e.g., CVD, PVD, etc.) to fill opening 902 (in Figure 9D (middle) and cover the top surface of MTJ 120 (e.g. 120(1) to 120(4)).

[0084] like Figure 9F As shown in cross-sectional view 900F, in some embodiments, a plurality of vias V (e.g., V6) are formed by employing, for example, a photolithography process followed by an etching process and a deposition process (e.g., CVD, PVD, etc.). In some embodiments, some of the vias V6 are coupled to the free magnetization layer 124 of MTJ 120 (e.g., 120(1) to 120(4)), and other vias V6 are coupled to some of the conductors L (e.g., L4) of the conductive interconnect structure 160.

[0085] like Figure 9GAs shown in the cross-sectional view 900G, in some embodiments, an additional dielectric layer 140 is formed over via V6 and the existing dielectric layer 140, and additional conductors (e.g., conductor L5 in M5 and conductor L6 in M6) and additional conductive vias (e.g., V7) of the conductive interconnect structure 160 are formed within the additional dielectric layer 140 by employing processes such as photolithography, etching, and deposition (e.g., CVD, PVD, etc.). In some embodiments, conductor L6 in M6 is formed to serve as a first power node 102 for receiving a supply voltage (VDD). MTJ 120(1) and 120(2) are coupled in series to form a first element group 120G(1), MTJ 120(3) and 120(4) are coupled in series to form a second element group 120G(2), and the first element group 120G(1) and the second element group 120G(2) are coupled in parallel.

[0086] In this manner, an exemplary Gaussian bit circuit 100, including multiple MTJ 120s and primarily consisting of a transistor 110, an input node 106, and an output node 108, is described, for example... Figure 1D The configuration shown occupies a small area and has simplified metal wire routing for input and output nodes, thereby advantageously enhancing integration efficiency and scalability.

[0087] Figure 10 Description of some embodiments for manufacturing such as Figure 1A , 1D The flowchart of method 1000, shown in Figure 1E, illustrates an exemplary Gaussian bit circuit 100 having transistor 110 and multiple resistance-changing elements 120. While method 1000 is illustrated and described herein as a series of actions or events, it should be understood that the order of such actions or events should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those illustrated and / or described herein. Furthermore, not all illustrated actions may be required to implement one or more aspects or embodiments described herein. Additionally, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0088] like Figure 1A and Figure 1DAs shown, the exemplary Gaussian bit circuit 100 includes a first power node 102 for receiving a supply voltage (VDD), a second power node 104 for receiving a reference voltage (GND), an input node 106 for receiving an input signal (Vin), an output node 108 for providing an output signal (Vm), a transistor 110 including a first terminal 112 coupled to the output node 108, a second terminal 114 coupled to the second power node 104, and a control terminal 116 coupled to the input node 106, and a plurality of (Q) MTJ120s (120(1) to 120(Q)) coupled in series and parallel combinations between the first power node 102 and the output node 108 (e.g. Figure 1A (Q = 4).

[0089] For example Figure 1D As shown, a conductive interconnect structure 160 is formed in a dielectric layer 140 and includes a plurality of conductors L (e.g., L1 to L6, etc.) respectively disposed in a plurality of conductive interconnect layers (e.g., M1 to M6, etc.), and a plurality of conductive vias V selectively coupled to the plurality of conductors L for selectively connecting elements and nodes. In some embodiments, the conductive interconnect structure 160 may be made of a conductive material, such as aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), and copper (Cu). The interconnect structure 160 may further include one or more titanium (Ti) or tantalum (Ta) based liner or barrier layer, cobalt (Co) capping layer, or cobalt-based barrier layer.

[0090] In action 1002, such as Figure 9A and Figure 10 As shown, in some embodiments, a transistor 110 including a first source / drain terminal 112, a second source / drain terminal 114, and a gate terminal 116 is formed along the front side 130f of a semiconductor substrate 130 (see Figure 130). Figure 10 and Figure 1D In some embodiments, such as Figure 9B As shown, a dielectric layer 140 is formed above the front side 130f of the semiconductor substrate 130, and a plurality of conductive vias V are formed in the dielectric layer 140.

[0091] In some embodiments, the semiconductor substrate 130 may be any type of semiconductor substrate (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer, and any other type of semiconductor and / or epitaxial layer associated therewith. In some embodiments, dielectric layer 140 may include low-k materials, such as silicon dioxide (SiO2) with k = 3.9, and other low-k materials with k values ​​less than that of SiO2 (3.9), such as fluorine-doped silicon dioxide (SiOF) (k about 3.0 to 4.0), carbon-doped silicon dioxide (SiCOH), phosphosilicate glass (PSG), organosilicon glass (OSG) (k about 2.5 to 3.0), porous silicon dioxide (k about 1.3 to 2.5), porous organosilicon glass (k about 2.5 to 3.0), polymeric materials (such as polyimide, parylene, PTFE, k about 2.0 to 3.1), air gaps (k about 1.0), borosilicate glass (BPSG), borosilicate glass (BSG), fluorosilicate glass (FSG), undoped silicate glass (USG), and / or the like.

[0092] In action 1004, such as Figure 9B and Figure 10 As shown, in some embodiments, the input node 106 configured to receive the input signal (Vin) is formed in the first conductive layer (e.g., M1) of a plurality of conductive layers (e.g., M1 to M6) (see Figure 1). Figure 10 and Figure 1D Input node 106 is coupled to control terminal 116 via at least a portion of conductive interconnect structure 160.

[0093] In action 1006, such as Figure 9B and Figure 10 As shown, in some embodiments, one of the first power node 102 and the second power node 104 is formed in a second conductive layer (e.g., M2) of a plurality of conductive layers (e.g., M1 to M6) (see reference). Figure 10 and Figure 1D In some embodiments, a second conductive layer (e.g., M2) is formed over a first conductive layer (e.g., M1). In some embodiments, a second power node 104 is formed in a second conductive layer (e.g., M2) of a plurality of conductive layers (e.g., M1 to M6), and is coupled to a second terminal 114 (in) via at least a portion of a conductive interconnect structure 160. Figure 1D middle).

[0094] In action 1008, such as Figure 9B and Figure 10 As shown, in some embodiments, the output node 108 configured to provide an output signal (Vm) is formed in a third conductive layer (e.g., M3) of a plurality of conductive layers (e.g., M1 to M6) (see Figure 1). Figure 10 and Figure 1D In some embodiments, a third conductive layer (e.g., M3) is formed over a second conductive layer (e.g., M2).

[0095] In action 1010, such as Figures 9C to 9E and Figure 10 As shown, in some embodiments, a plurality of (Q)MTJ 120s (e.g., 120(1) to 120(Q)) are formed between a fourth conductive layer (e.g., M4) and a fifth conductive layer (e.g., M5) of a plurality of conductive layers (e.g., M1 to M6). In some embodiments, the fourth conductive layer (e.g., M4) is formed over a third conductive layer (e.g., M3), and the fifth conductive layer (e.g., M5) is formed over the fourth conductive layer (e.g., M4).

[0096] In some embodiments, a plurality of (Q)MTJ 120s (e.g., 120(1) to 120(Q)) are divided into a number (n) element groups 120G (e.g., 120G(1) to 120G(n)) which are coupled in parallel between the first power node 102 and the output node 108, and each element group 120G (e.g., 120G(1)) includes a number (m) series-coupled resistance-changing elements 120 (e.g., 120(1) to 120(m)), so Q = n × m. In some embodiments, as Figure 9G As shown, n = m = 2, and this configuration can be called the “1T + (n × n)MTJ” configuration.

[0097] like Figure 9G As shown, the four MTJ 120(1) to 120(4) are divided into two component groups 120G(1) and 120G(2), which are coupled in parallel between the first power node 102 and the output node 108 through at least a portion of the conductive interconnect structure 160. Component group 120G(1) includes MTJ 120(1) and MTJ 120(2) coupled in series through at least a portion of the conductive interconnect structure 160, and component group 120G(2) includes MTJ 120(3) and MTJ 120(4) coupled in series through at least a portion of the conductive interconnect structure 160.

[0098] In action 1012, such as Figure 9G and Figure 10 As shown, in some embodiments, another of the first power node 102 and the second power node 104 is formed in a sixth conductive layer (e.g., M6) of a plurality of conductive layers (e.g., M1 to M6) (see example). Figure 10 and Figure 1DIn some embodiments, a sixth conductive layer (e.g., M6) is formed over a fifth conductive layer (e.g., M5). In some embodiments, a first power node 102 is formed in the sixth conductive layer (e.g., M6) of a plurality of conductive layers (e.g., M1 to M6) (see, for example...). Figure 1D ).

[0099] Thus, forming, for example Figure 1D The Gaussian bit circuit 100 in the circuit mainly requires one transistor 110, one input node 106 and one output node 108, thus occupying a small area and having simplified metal wiring for input and output signals, thereby advantageously enhancing integration efficiency and scalability.

[0100] Therefore, in some embodiments, an integrated circuit is provided. The integrated circuit includes a first power node for receiving one of a supply voltage and a reference voltage; a second power node for receiving the other of the supply voltage and the reference voltage; an input node for receiving an input signal; an output node for providing an output signal; a transistor including a first terminal coupled to the output node, a second terminal coupled to the second power node, and a control terminal coupled to the input node; and a memory cell including a plurality of resistance-changing elements coupled between the first power node and the output node. The memory cell is configured to have a number of discrete data states greater than the number of resistance-changing elements among the plurality of resistance-changing elements. In some embodiments, the plurality of resistance-changing elements are coupled in parallel between the first power node and the output node. In some embodiments, the plurality of resistance-changing elements are coupled in series between the first power node and the output node. In some embodiments, each of the plurality of resistance-changing elements includes a magnetic tunnel junction (MTJ). In some embodiments, each of the plurality of resistance-changing elements is configured to have a low-resistance state (LRS) and a high-resistance state (HRS). In some embodiments, the memory cell is configured to have a first data state when each of the plurality of resistance-changing elements is in LRS; the memory cell is configured to have a second data state when a single resistance-changing element of the plurality of resistance-changing elements is in HRS and the remaining resistance-changing elements of the plurality of resistance-changing elements are each in LRS; and the memory cell is configured to have a third data state when each of the plurality of resistance-changing elements is in HRS. In some embodiments, the plurality of resistance-changing elements are distinguished and configured as a plurality of element groups coupled in parallel between a first power node and an output node, and each element group contains a plurality of resistance-changing elements coupled in series. In some embodiments, the number of element groups is equal to the number of resistance-changing elements in each element group. In some embodiments, the number of element groups is different from the number of resistance-changing elements in each element group. In some embodiments, the integrated circuit further includes a semiconductor substrate having a first surface, wherein transistors are disposed along the first surface of the semiconductor substrate; and a dielectric structure above the semiconductor substrate, wherein the plurality of resistance-changing elements are disposed in the dielectric structure and cover the transistors. In some embodiments, the integrated circuit further includes a conductive interconnect structure in the dielectric structure, the conductive interconnect structure including a plurality of conductive interconnect layers stacked perpendicularly to each other, and the plurality of resistance-changing elements are coplanar and perpendicularly spaced between two adjacent conductive interconnect layers in the plurality of conductive interconnect layers.

[0101] In other embodiments, an integrated circuit is provided. The integrated circuit includes a first power node for receiving one of a supply voltage and a reference voltage; a second power node for receiving the other of the supply voltage and the reference voltage; an input node for receiving an input signal; an output node for providing an output signal; a transistor including a first terminal coupled to the output node, a second terminal coupled to the second power node, and a control terminal coupled to the input node; and a plurality of resistance-changing elements coupled between the first power node and the output node, wherein the plurality of resistance-changing elements are divided into a first element group and a second element group coupled in series, wherein the first element group includes a plurality of first resistance-changing elements coupled in parallel with each other, and wherein the second element group includes one or more second resistance-changing elements. In some embodiments, the first element group is coupled between the first power node and an intermediate node, and the second element group is coupled between the intermediate node and the output node. In some embodiments, the second element group includes a plurality of second resistance-changing elements coupled in parallel. In some embodiments, the number of first resistance-changing elements is greater than the number of second resistance-changing elements. In some embodiments, the input node and the output node are configured above the transistor and below the plurality of resistance-changing elements, and the output node is configured above the input node.

[0102] In other embodiments, a method of manufacturing an integrated circuit is provided. The method includes forming a transistor along a first surface of a semiconductor substrate and including a first terminal; forming a first plurality of conductive interconnects above the first surface of the semiconductor substrate, wherein the first plurality of conductive interconnects includes a first wire electrically coupled to the first terminal of the transistor; forming a plurality of resistance-changing elements above the first plurality of conductive interconnects; and forming a second plurality of conductive interconnects above the plurality of resistance-changing elements. The second plurality of conductive interconnects includes a second wire. The plurality of resistance-changing elements are coupled between the first wire and the second wire in a series, parallel, or a combination of series and parallel connections. In some embodiments, the bottom surfaces of the plurality of resistance-changing elements are aligned with each other. In some embodiments, the first wire is an output node or coupled to an output node, and the second wire is a first power node or coupled to a first power node, the first plurality of conductive interconnects further including a third wire electrically coupled to a second terminal of the transistor, the third wire being a second power node or coupled to a second power node, the first power node being configured to receive one of a supply voltage and a reference voltage, and the second power node being configured to receive the other of the supply voltage and the reference voltage. In some embodiments, the plurality of resistance-changing elements includes a first element group and a second element group coupled in parallel, each of the first element group and the second element group including at least two resistance-changing elements coupled in series.

[0103] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit, comprising: Transistors, arranged along a semiconductor substrate; An interconnect structure covering the transistor, wherein the interconnect structure includes a plurality of wires respectively disposed in a plurality of conductive interconnect layers, and a plurality of conductive vias; as well as A memory cell covers the transistor and is coupled to the transistor through the interconnect structure, wherein the memory cell includes a plurality of resistance-varying elements coupled to each other through the interconnect structure and vertically disposed between a first conductive interconnect layer and a second conductive interconnect layer of a plurality of conductive interconnect layers, the second conductive interconnect layer covering and adjacent to the first conductive interconnect layer.

2. The integrated circuit according to claim 1, wherein the top surfaces of the plurality of resistance-changing elements are coplanar.

3. The integrated circuit of claim 1, wherein the plurality of resistance changing elements are distinguished and configured into a plurality of element groups, the plurality of element groups being coupled in parallel, and each element group comprising a plurality of the plurality of resistance changing elements coupled in series.

4. An integrated circuit, comprising: A transistor, disposed along a semiconductor substrate, includes a first source / drain terminal, a second source / drain terminal, and a control terminal; An interconnect structure covering the transistor includes multiple wires respectively disposed in multiple conductive interconnect layers, and multiple conductive vias; as well as Multiple resistance-changing elements are coupled to the transistor through the interconnect structure and vertically arranged between a first conductive interconnect layer and a second conductive interconnect layer in the multiple conductive interconnect layers. The second conductive interconnect layer is located above and adjacent to the first conductive interconnect layer. The multiple resistance-changing elements are divided into a first element group and a second element group that are coupled in series. The first element group includes multiple first resistance-changing elements coupled in parallel with each other, and the second element group includes one or more second resistance-changing elements.

5. The integrated circuit of claim 4, wherein the second element group comprises a plurality of parallel-coupled second resistance changing elements.

6. The integrated circuit according to claim 5, wherein the number of the first resistance changing elements is greater than the number of the second resistance changing elements.

7. A method for manufacturing an integrated circuit, comprising: A transistor is formed along a first surface of a semiconductor substrate and includes a first terminal; A first plurality of conductive interconnects are formed above the first surface of the semiconductor substrate, wherein the first plurality of conductive interconnects includes a first wire electrically coupled to the first terminal of the transistor; A plurality of resistance-changing elements are formed above the first plurality of conductive interconnects; as well as A second plurality of conductive interconnects are formed above the plurality of resistance-changing elements, wherein the second plurality of conductive interconnects includes a second wire. The plurality of resistance-changing elements are coupled between the first conductor and the second conductor in a series, parallel, or a combination of series and parallel connections.

8. The method of claim 7, wherein the bottom surfaces of the plurality of resistance-changing elements are aligned with each other.

9. The method of claim 7, wherein the first conductor is or coupled to an output node, and the second conductor is or coupled to a first power node, wherein the first plurality of conductive interconnects further comprises a third conductor electrically coupled to a second terminal of the transistor, wherein the third conductor is or coupled to a second power node, wherein the first power node is configured to receive one of a supply voltage and a reference voltage, and wherein the second power node is configured to receive the other of the supply voltage and the reference voltage.

10. The method of claim 7, wherein the plurality of resistance changing elements comprises a first element group and a second element group coupled in parallel, wherein each of the first element group and the second element group comprises at least two resistance changing elements coupled in series.

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