Phase change memory cells including resistive elements connected in parallel

Abstract

This disclosure relates to a phase change memory (PCM) cell including resistive elements connected in parallel. An apparatus includes a PCM cell comprising at least one first resistive element and a second resistive element electrically connected in parallel between conductive contacts. The first resistive element has a resistance having a first value at a first temperature below its crystallization temperature and a second value less than or equal to its first value at a second temperature above its melting temperature. The second resistive element has a resistance having a first value greater than the first value of the first resistive element at the first temperature and a second value less than the second value of the first resistive element at the second temperature.

Description

background Invention Field

[0001] This description generally relates to integrated circuits that include phase-change memory (PCM) cells.

[0002] Description of related technologies

[0003] A phase-change memory cell is a type of non-volatile memory that can be thought of as a variable-resistive electric dipole in which binary information is stored. Conventionally, such a memory cell includes an active portion formed of a phase-change material and is positioned between two electrodes.

[0004] When the active material is in a crystalline phase, its resistivity is low, allowing it to encode the SET state (typically logic state 1), while in the amorphous phase, its resistivity is high, allowing it to encode the RESET state (logic state 0).

[0005] The phase transition temperature is achieved by heating the resistive element of the memory cell using the Joule effect. This resistive element corresponds to a heating resistor (heater) that has both thermal and electrical contact with the active portion of the memory cell.

[0006] However, it would be beneficial to improve the performance of such memory cells, especially within the matrix of the same memory cells. Summary of the Invention

[0007] According to one aspect of this disclosure, a phase change memory cell is provided, the phase change memory cell including an active portion of a phase change material having a crystallization temperature and a melting temperature. The memory cell includes:

[0008] First conductive contact;

[0009] At least one first resistive element and at least one second resistive element are electrically connected and coupled to the first conductive contact in parallel.

[0010] The first resistive element has a resistance having: a first value at a first temperature below the crystallization temperature, and a second value less than or equal to its first value at a second temperature above the melting temperature.

[0011] The second resistive element has a resistance having: a first value greater than a first value of the first resistive element at a first temperature, and a second value less than a second value of the first resistive element at a second temperature;

[0012] The active portion is coupled to the first and second resistive elements;

[0013] The second conductive contact is coupled to the active part.

[0014] According to one embodiment, the first resistive element and the second resistive element each include a first portion extending from a first conductive contact to an active portion, the first portion of the first resistive element being spaced apart from the first portion of the second resistive element by a first spacer made of an electrically insulating material.

[0015] According to one embodiment, the first resistive element and the second resistive element each include a second portion extending from the first portion and positioned in contact with the first conductive contact, and the first spacer covers the second portion of the first resistive element.

[0016] According to one embodiment, the memory cell includes a second spacer that extends along the surface of a first portion of a second resistive element opposite to a first spacer and covers a second portion of the second resistive element.

[0017] According to one embodiment, the first resistive element and the second resistive element have the same or different thicknesses.

[0018] According to one embodiment, at a first temperature, the first value of the resistance of the second resistive element is at least twice the first value of the resistance of the first resistive element.

[0019] According to one embodiment, the first resistive element and / or the second resistive element are made of a material based on titanium silicon and / or tungsten nitride.

[0020] According to one embodiment, the active portion is made of a chalcogenide, preferably a ternary chalcogenide compound.

[0021] According to another aspect, an integrated circuit is provided, which includes a matrix of the same memory cells according to any of the foregoing features.

[0022] According to another aspect, a method for manufacturing at least one memory cell according to any of the foregoing features is provided, the method comprising the following steps:

[0023] Fabricate a first insulating layer and extend through the first insulating layer to open out onto the upper face;

[0024] Fabricate a second insulating layer covering the first insulating layer and the first conductive contact;

[0025] Make at least one opening that extends through the second insulating layer and onto the first conductive contact;

[0026] A first thin conductive layer is deposited onto the side flanks of the opening, and local etching is performed to obtain a first resistive element;

[0027] A thin insulating layer is deposited onto the side flanks of the first resistive element, and local etching is performed to obtain the first spacer;

[0028] A second thin conductive layer is deposited onto the side flanks of the first spacer, and local etching is performed to obtain a second resistive element;

[0029] Create the active component;

[0030] Fabricate a second conductive contact.

[0031] According to one embodiment, the first thin conductive layer is deposited by chemical vapor deposition.

[0032] According to one embodiment, the second thin conductive layer is deposited by atomic layer deposition.

[0033] According to one embodiment, the first thin conductive layer and / or the second thin conductive layer are made of a material based on titanium silicon and / or tungsten nitride.

[0034] According to one embodiment, the manufacturing method includes a step of filling an opening, which is performed before and after a step of forming a continuous layer of phase change material, in which the filling of the opening occurs.

[0035] According to another aspect, a method for manufacturing an integrated circuit is provided, the method comprising simultaneously fabricating a matrix of identical memory cells by means of the method according to any of the foregoing features.

[0036] In one embodiment, a method includes depositing a first insulating layer on a first conductive contact of a memory cell, exposing the first conductive contact by forming a trench in the insulating layer, depositing a first resistive element of the memory cell in the trench on a top surface of the first conductive contact, and depositing a second resistive element of the memory cell adjacent to the first resistive element in the trench on the top surface of the first conductive contact. The method includes filling the trench with a first insulating material, depositing a phase change material layer of the memory cell on the top surface of the resistive element, on the top surface of the second resistive element, and on the top surface of the first insulating material, and depositing the second conductive contact on the phase change material layer. Attached Figure Description

[0037] Other advantages and features of this disclosure will become clear from a review of the detailed description of the non-limiting embodiments and implementations, as well as from the accompanying drawings, in which:

[0038] Figure 1A This is a schematic and partial cross-sectional view of an integrated circuit including a memory cell according to one embodiment;

[0039] Figure 1BThe illustration shows an example of the equivalent resistance associated with two resistive elements of a memory cell according to one embodiment, as a function of temperature; and

[0040] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E and Figure 2F The illustration shows different steps in a method for manufacturing an integrated circuit including a memory cell according to one embodiment. Detailed Implementation

[0041] In the accompanying drawings and the following description, the same reference numerals denote the same or similar elements. Furthermore, different elements are not shown to scale to facilitate clarity of the drawings. Moreover, different embodiments and alternatives are not mutually exclusive and can be combined together.

[0042] Unless otherwise indicated, the terms “substantially,” “approximately,” and “about” mean the nearest 10%, and preferably the nearest 5%. Furthermore, the terms “between… and…” and their equivalents mean including the boundary, unless otherwise indicated.

[0043] Figure 1A This is a schematic and partial cross-sectional view of an integrated circuit 1 that includes at least one phase-change memory cell 10 according to one embodiment, and herein includes a matrix of the same memory cells.

[0044] Here and throughout the remainder of this description, a three-dimensional direct reference frame XYZ is defined, wherein the plane XY is parallel to the main plane of the integrated circuit, and wherein the axis Z is oriented along its thickness. Furthermore, the terms "lower" and "upper" are understood to refer to incremental positioning relative to the direction +Z.

[0045] Generally, each memory cell 10 includes at least one lower conductive contact 11, at least two resistive elements H1 and H2 electrically connected in parallel, an active portion 12 of phase change material, and an upper conductive contact 24.

[0046] Therefore, resistive elements H1 and H2 are electrically coupled to the lower conductive contact 11 on one hand and to the upper conductive contact 24 on the other. Each resistive element may therefore include a longitudinal portion extending from the lower end electrically coupled to the lower conductive contact 11 to the upper end electrically coupled to the upper conductive contact 24. Thus, the longitudinal portions of resistive elements H1 and H2 are electrically insulated from each other.

[0047] Recall that during use, three operations can be performed: a read operation (READ), in which the resistance of memory cell 10 is determined to know its SET or RESET state; a write programming step (SET state); and an erase programming step (RESET state).

[0048] A read operation involves determining the resistance of a memory cell, for example, by applying a voltage and measuring the current flowing through the memory cell. If the current is maximum, this corresponds to an active portion whose material is a crystalline phase and therefore has low resistance: the state of the memory cell typically corresponds to the SET state (logic state 1). On the other hand, if the current is minimum, the active portion's material is an amorphous phase and therefore has high resistance: the memory cell has a RESET state (logic state 0). This read operation is performed below the crystallization temperature T of the phase change material. c Temperature T of the memory cell READ It is designed to operate at ambient temperatures (i.e., typically between -40°C and +165°C when the product is in use).

[0049] The write-program operation (SET) corresponds to the crystallization of the material in the active portion. Here, the memory cell can be subjected to an electrical pulse, the properties of which (intensity, duration, fall time, etc.) are selected to cause the temperature of the active portion to reach at least equal to the crystallization temperature T. c The value T SET The material in the active portion then changes from an amorphous phase to a crystalline phase, and the memory cell then has a SET state.

[0050] The RESET erase / programming operation corresponds to the amorphization of the material in the active portion. Here, the memory cell can be subjected to an electrical pulse, the properties of which (intensity, duration, fall time, etc.) are selected to cause the temperature of the active portion to reach a level greater than the melting temperature T. f T RESET Value: T RESET >T f The material in the active portion changes from a crystalline phase to an amorphous phase, and the memory cell then has a RESET state.

[0051] Let's go back Figure 1A In this example, integrated circuit 1 includes a lower insulating layer 21 made of an electrically insulating material such as silicon oxide. This layer 21 may be located on a passivation layer (not shown) made of an electrically insulating material such as silicon nitride.

[0052] It should be noted that integrated circuit 1 typically includes a FEOL (front-end) structure, with a lower insulating layer 21 located on the FEOL structure and memory cells 10 electrically coupled to the FEOL structure. The FEOL structure includes electronic components, such as field-effect transistors, specifically for controlling the memory cells. For clarity, it is not shown. A BEOL (back-end) structure may also exist under or within the lower insulating layer 21.

[0053] A lower conductive contact 11, made of at least one conductive material (preferably a metallic material such as copper, tungsten, etc.), extends vertically through the lower insulating layer 21. In this embodiment, each memory cell 10 includes a conductive contact 11. These conductive contacts 11 have a through-silicon via (TSV) shape.

[0054] An intermediate insulating layer 22, made of at least one electrically insulating material (such as silicon oxide and / or nitride), covers the lower insulating layer 21 and surrounds the resistive elements H1 and H2 in the plane XY. It is formed by different insulating portions (spacers, etc.) described later.

[0055] Each memory cell 10 includes at least two resistive elements H1, H2 that are electrically connected in parallel and electrically coupled to the lower conductive contact 11 and the active portion 12. In this embodiment, it includes two resistive elements, but it may include more resistive elements.

[0056] Each resistive element H1, H2 forms a heating element (heater) configured to enable programming of the logic state through a phase change in the material of the active portion 12. Therefore, it is made of a conductive material and has a resistance R value that depends on the temperature of the memory cell 10 in use.

[0057] The resistance R of a resistive element is usually expressed as a function of the resistivity ρ of its material and its dimensions L, l, e: R = ρ×L / (e×l), where L is its height, l is its width, and e is its thickness.

[0058] According to one embodiment, each resistive element H1, H2 has a so-called "wall" structure and includes at least one vertical portion H1.2, H2.2, which has a height L along axis Z, a thickness e along axis X, and a width l along axis Y. The height L and width l of each resistive element H1, H2 can be the same. The thicknesses e1 and e2 can be the same or different, as explained below.

[0059] Each resistive element H1, H2 may also include a lower portion H1.1, H2.1 extending from the lower end of the vertical portions H1.2, H2.2 in the plane XY and in contact with the lower conductive contact 11. The vertical portions H1.1, H2.1 and the lower portions H1.2, H2.2 are arranged in an L-shape here. Other arrangements may be considered.

[0060] The resistance R1 of the first resistive element H1 has the following characteristics: below the crystallization temperature T c The first value R1 at the first temperature TREAD The first temperature, such as the reading temperature T, READ ; and above the melting temperature T f The second value R1 at the second temperature TRESET The second temperature, such as the temperature T used for programming the RESET state, is... RESET .

[0061] Similarly, the resistance R2 of the second resistive element H2 specifically has the following characteristics: at a first temperature (reading temperature T) READ The first value R2 under ) TREAD ; and at the second temperature (the temperature T used for programming the RESET state) RESET The second value R2 under ) TRESET .

[0062] Resistive elements H1 and H2 are made of materials that have the following properties in terms of resistivity and dimensionality:

[0063] At the first temperature (read temperature T) READ Under these conditions, the value R1 TREAD Less than value R2 TREAD R1 TREAD <R2 TREAD This causes the current to mainly flow through the first resistive element H1;

[0064] At the second temperature (RESET programming T) RESET At temperature), R2 TRESET Value lower than R1 TRESET Value: R2 TRESET <R1 TRESET This causes the current to flow mainly through the second resistive element H2.

[0065] For example, in the case of germanium-antimony-tellurium type (GeSbTe, also known as GST) phase change materials, the crystallization temperature T c It can be approximately 300°C, and the melting temperature T f It can be around 650°C. These values ​​depend specifically on the germanium and antimony content. READ Temperature can be higher than T c25°C, 50°C, or more below. This can be the product's operating temperature, which can be, for example, between approximately -40°C and +165°C. Temperature T RESET Can be compared to T f 25°C, 50°C or more higher, and at temperature T f At approximately 650°C, it can be equal to 700°C, 750°C, or even 800°C.

[0066] The first resistive element H1 can have a resistivity ρ1 that varies with temperature, and this resistivity ρ1 can be maintained at temperature T. READ (e.g., 25°C) and T RESET (For example, 750°C) is constant, or it can be slightly reduced, for example, by up to 30%, or even 20%, or even 10%.

[0067] As an example, the value of resistivity ρ1 is ρ1 TREAD It can be between 0.5 mΩ·cm and 1 mΩ·cm, and the value ρ1 TRESET They can be essentially equal or slightly lower. Therefore, the value ρ1 TREAD It can be equal to approximately 1 mΩ·cm, and the value ρ1 TRESET It can be between 0.8 mΩ·cm and 1 mΩ·cm, or even between 0.9 mΩ·cm and 1 mΩ·cm.

[0068] The second resistive element H2 can have a resistivity ρ2 that varies with temperature, and this resistivity ρ2 at temperature T READ With T RESET The reduction is even greater, for example, by half an order of magnitude or even an order of magnitude. Furthermore, as mentioned earlier, the value R2... TREAD Greater than R1 TREAD For example, it can be 2 times, 5 times, or even 10 times larger, while the value R2 TRESET Less than R1 TRESET .

[0069] As an example, the value of resistivity ρ2 is ρ2 TREAD It can be between 5 mΩ·cm and 10 mΩ·cm, and the value ρ2 TRESET It can be between 0.5 mΩ·cm and 1 mΩ·cm. Therefore, the value ρ2 TREAD It can be equal to approximately 5 mΩ·cm (compared to the value of 1 mΩ·cm ρ1) TREAD (high), and the value ρ2 TRESET It can be equal to 0.8 mΩ·cm (compared to the value of 1 mΩ·cm ρ2) TREAD Low).

[0070] Resistive elements H1 and / or H2 can be made based on titanium silicon nitride (TiSiN), tungsten, etc. Differences in electrical behavior with temperature may originate from the chemical composition of the material, its structural properties (e.g., porosity), etc.

[0071] Therefore, the resistive element H1 can be TiSiN fabricated by chemical vapor deposition (CVD). As an example, CVD deposition can be performed between approximately 390°C and 420°C, at a pressure of approximately 5 Torr, and using the precursor tetrakis(dimethylamido)titanium (TDMAT). The change in resistivity as a function of temperature can be adjusted by regulating the densification of the material, particularly via the power used during CVD deposition.

[0072] Furthermore, the resistive element H2 can be TiSiN produced by atomic layer deposition (ALD). As an example, ALD deposition can be performed between approximately 400°C and 450°C at a pressure of approximately 30 Torr. The change in resistivity as a function of temperature can be adjusted by regulating the flow rate of silane SiH4 used after each deposition cycle.

[0073] Figure 1B The diagram illustrates the relationship between... Figure 1A An example of the change in equivalent resistance Req of two resistive elements H1 and H2 connected in parallel in a memory cell 10, similar to the memory cell in the example.

[0074] In this example, we consider the active portion as being determined by its crystallization temperature T. c Equal to approximately 300°C and melting temperature T f It is made of GST material at approximately 650°C. The temperature here is T. READ The ambient temperature is 25°C, and the temperature T RESET It is approximately equal to 750°C.

[0075] Furthermore, the temperature process of resistor Req was compared with variations in the proportion of thickness in the two resistive elements. In other words, the total thickness emax = e1 + e2 is considered, and the proportion of each thickness in the total thickness is varied as follows: (e1; e2) = (100%; 0%); (75%; 25%); (50%; 50%); (25%; 75%); and (0%; 100%).

[0076] When (e1; e2) = (100%; 0%), the resistor Req corresponds to the resistor R1 of resistor H1, where the resistor R1 of resistor H1 is at a value of R1 TREAD It is basically equal to R1TREAD The value of R1 TRESET The values ​​vary between these values. The resistive element H1 has a thickness e1 equal to emax.

[0077] In the relative case (e1; e2) = (0%; 100%), the resistor Req corresponds to the resistance R2 of the resistive element H2, where the resistance R2 of the resistive element H2 is at a value of R2 TREAD With R2 much lower TREAD The value of R2 TRESET The values ​​vary between these values. The resistive element H2 has a thickness e2 equal to emax.

[0078] Below T c Temperature (e.g., temperature T) READ Under these conditions, resistor R1 TREAD Below R2 TREAD And above T f Temperature (e.g., temperature T) RESET At point R2 TRESET Below R1 TRESET .

[0079] With (e1;e2) = (75%;25%), (50%;50%), and (25%;75%), the resistor Req varies with temperature between two curves R1 and R2. The thickness distribution between e1 and e2 allows for specific adjustment of the current distribution through each resistive element H1, H2 during read operations, write programming, and erase programming operations.

[0080] In any case, during the read operation, i.e. at temperature T READ At this temperature, the current mainly flows through the resistive element H1 (i.e., more than 50% of the current flows through H1), while during the erase programming operation, i.e., at temperature T... RESET In this case, the current mainly flows through the resistive element H2 (i.e., more than 50% of the current flows through H2).

[0081] Let's go back Figure 1A Each resistive element H1, H2 extends through the intermediate insulating layer 22 at a height L. The vertical portions H1.2, H2.2 may extend parallel to the vertical axis Z as illustrated herein, or may extend at an angle as illustrated in reference EP 3,890,024 A1.

[0082] According to one embodiment, the lower portions H1.1 and H2.1 of the resistive elements H1 and H2 of the same memory cell 10 can contact each other. They are in electrical contact with the same conductive contact 11. On the other hand, the vertical portions H1.2 and H2.2 do not contact each other and are spaced apart by a first spacer 22.1. The first spacer 22.1 is a portion of the intermediate insulating layer 22 that extends vertically along axis Z and is located between the vertical portions H1.2 and H2.2 of the resistive elements H1 and H2 of the same memory cell 10. They cover the lower portion H1.1 of the resistive element H1. They can be made of silicon nitride.

[0083] In this embodiment, the intermediate insulating layer 22 includes additional portions forming the second spacer 22.2. These extend vertically along axis Z and are positioned opposite the first spacer 22.1, abutting against the vertical portion H2.2 of the resistive element H2. They cover the lower portion H2.1 of the resistive element H2. They may be made of silicon nitride.

[0084] The intermediate insulating layer 22 may include a third spacer 22.3 that extends vertically along axis Z and is positioned opposite the resistive element H2 against the side flank of the second spacer 22.2. They may be made of silicon nitride.

[0085] The intermediate insulating layer 22 includes an interlayer portion 22.4 located between each resistive element H1, which may be made of, for example, silicon nitride. The intermediate insulating layer 22 may also include an interlayer portion 22.5 located between each resistive element H2 and here between third spacers 22.3 facing each other in the plane XY. It may be made of, for example, silicon oxide.

[0086] Each memory cell 10 includes an active portion 12 made of a phase change material. The active portion 12 is electrically and thermally coupled to two resistive elements H1 and H2. The phase change material can be a chalcogenide, such as a ternary chalcogenide, like germanium-antimony-tellurium (GST). As previously mentioned, the contents of germanium and antimony are selected to obtain the desired crystallization temperature T. c and melting temperature T f The value of , the desired crystallization temperature T c and melting temperature T f The values ​​can be approximately 300°C and approximately 650°C, respectively.

[0087] In this embodiment, the active portion 12 is a dome-shaped region of the same continuous layer 23 of the phase change material, which extends on and in contact with the intermediate insulating layer 22 and the resistive elements H1 and H2.

[0088] Finally, each memory cell 10 includes an upper conductive contact made of a conductive material. These contacts may here be regions of the same conductive layer 24 that continuously cover the phase transition continuity layer 23. The conductive layer 24 may be made of one or more metallic materials, such as tungsten, TiN, etc.

[0089] It should be noted that the memory cells 10 are typically arranged as a matrix of rows and columns, such that each memory cell is located at the intersection of the row (bit line) and column (word line). They can be controlled by MOS or bipolar selection transistors.

[0090] Of course, other memory cell architectures are also possible regarding the shape of conductive contacts, resistive elements, and active parts.

[0091] The memory cell 10 and the memory cell matrix of the integrated circuit 1 here therefore have improved performance during read operations and during RESET programming operations.

[0092] In fact, memory cell 10 includes two resistive elements H1, H2 (or even more) connected in parallel. The resistance of these two resistive elements causes current to flow primarily through resistive element H1 (minimum resistance R1) during read operations. TREAD However, during the RESET operation in programming, the resistor element H2 (the lowest resistance R2) is used. TRESET This allows the different properties of these resistive elements H1 and H2 to be utilized during these operations.

[0093] Therefore, the inventors have discovered that materials for resistive elements that may be used as memory cells can have electrical behaviors that differ with temperature, for example, in terms of resistivity and robustness.

[0094] Robustness here refers to the spatial reproducibility of electrical properties. Therefore, it is expected that identical resistive elements in different, identical memory cells of an integrated circuit will generate the same amount of heat when subjected to electrical signals of the same strength.

[0095] In addition, the resistive element H1 at temperature T READ The following component possesses more interesting electrical properties than resistive element H2: in particular, it has a lower resistivity (and therefore a lower resistance). Furthermore, the fact that current primarily flows through resistive element H1 during read operations particularly allows for limiting the performance degradation of the memory cell when it is in the SET state. In fact, during reading from the SET state, a high current is expected to be measured due to the low resistance of the active portion. Therefore, a decrease in current due to the high resistance of the resistive element is undesirable.

[0096] On the other hand, the resistive element H2 at temperature T RESET The resistor H2 exhibits more interesting electrical properties than the resistor H1, such as in terms of robustness. Furthermore, the fact that current primarily flows through the resistor H2 during the RESET programming operation allows for improvements in the performance of memory cells, and also in the performance of integrated circuits comprising matrices of the same memory cells.

[0097] Figures 2A to 2F The illustration shows different steps of a method for manufacturing an integrated circuit 1 that includes memory cells 10 according to one embodiment, and herein a matrix of the same memory cells.

[0098] refer to Figure 2A A lower insulating layer 21 is fabricated on the FEOL structure (not shown), which is made of, for example, SiO2. The FEOL (front-end process) structure contains electronic components such as field-effect transistors.

[0099] The lower conductive contacts 11 extend vertically through the lower insulating layer 21. They are made of a conductive material, such as one or more metals, such as tungsten.

[0100] A first insulating layer 25, for example made of silicon nitride, is deposited to cover the lower insulating layer 21 and the conductive contact 11. Its thickness substantially corresponds to the height of the resistive element. A second insulating layer 26, for example made of silicon oxide, is deposited on the first insulating layer 25.

[0101] refer to Figure 2B The opening 27 is made to pass through the second insulating layer 26 and then through the first insulating layer 25 to extend onto the lower insulating layer 21 and free up the upper surface of each conductive contact 11.

[0102] Then, a first thin conductive layer 28 is conformally deposited to continuously cover the top of the second insulating layer 26, the sidewalls of the second insulating layer 26 and the first insulating layer 25, and the free surfaces of the conductive contact 11 and the lower insulating layer 21. This first thin conductive layer 28 is to form the first resistive element H1. In this example, it is made of TiSiN deposited by CVD. The thickness on the sidewalls corresponds to the thickness e1 of the structure that will become the resistive element H1.

[0103] Then, a first thin passivation layer 29 is conformally deposited to continuously cover the first thin conductive layer 28. This layer forms the first spacer 22.1. Its thickness along the side flanks will define the spacing between resistive elements H1 and H2 in the XY plane.

[0104] refer to Figure 2C The first spacer 22.1 and the resistive element H1 are fabricated.

[0105] A thin passivation layer 29 is partially etched in the opening 27 and on the second insulating layer 26 to form a spacer 22.1 extending vertically along the thin conductive layer 28 at the edge of the opening 27.

[0106] Subsequently, chemical wet etching or reactive plasma etching is performed to remove material from the thin conductive layer 28 that is not protected by spacer 22.1. This yields the reactive element H1 in the L-shaped "wall" structure. The lower portion H1.1 of the reactive element H1 contacts the conductive contact 11, and the vertical portion H1.2 extends vertically along portion 22.4.

[0107] Therefore, the upper part of the second insulating layer 26 is made free. Resistive elements H1 are obtained from the thin conductive layer 28, each of which has a lower portion H1.1 and a vertical portion H1.2 that contacts the conductive contact 11. Only a portion 22.1 covering the lower portion H1.1 and extending vertically along the vertical portion H1.2 is retained from the thin passivation layer 29. These portions 22.1 form the first spacer.

[0108] refer to Figure 2D , repeating similar Figure 2B and Figure 2C Those steps are used to make the second spacer 22.2 and the resistive element H2.

[0109] To this end, a second continuous thin conductive layer 30 is conformally deposited to continuously cover the top of the second insulating layer 26 and the vertical flanks of the spacer 22.1, and finally covers the free surfaces of the lower conductive contact 11 and the lower insulating layer 21. This second thin conductive layer 30 is to form the resistive element H2. In this example, it is made of TiSiN deposited by ALD. The thickness on the flanks corresponds to the thickness e2 of the structure that will become the resistive element H2.

[0110] A second thin passivation layer 31 is deposited conformally to continuously cover the second thin conductive layer 30. This layer is to form the second spacer 22.2.

[0111] refer to Figure 2E The second spacer 22.2 and the resistive element H2 are then fabricated.

[0112] A passivation layer 31 is partially etched in the opening 27 and on the second insulating layer 26 to form a second spacer 22.2 that extends vertically along the thin conductive layer 30 at the edge of the opening 27.

[0113] Subsequently, chemical wet etching or reactive plasma etching is performed to remove material from the thin conductive layer 30 that is not protected by spacer 22.2. This yields the reactive element H2 in the L-shaped "wall" structure. The lower portion H2.1 of the reactive element H2 contacts the conductive contact 11, and the vertical portion H2.2 extends vertically along spacer 22.1.

[0114] Therefore, the top of the second insulating layer 26 is again made free. Resistive elements H2 are obtained from the second thin conductive layer 30, each of which is formed by a lower portion H2.1 that contacts the conductive contact 11 and a vertical portion H2.2 that extends vertically against the first spacer 22.1. Only the portion 22.2 covering the lower portion H2.1 and extending vertically along the vertical portion H2.1 is retained from the second thin passivation layer 31. These portions 22.2 form the second spacer.

[0115] refer to Figure 2F The fabrication of memory cell 10 is completed. To this end, a filler layer is deposited to fill the openings, followed by chemical mechanical planarization to remove excess filler material, thereby obtaining portion 22.5, and to remove the second insulating layer 26 and reduce the heights of resistive elements H1 and H2 and spacers 22.1 and 22.2. This results in a planar continuous surface.

[0116] Next, a layer 23 made of phase change material is deposited to continuously cover the intermediate lower layer 22. Region 12 makes electrical and thermal contact with resistive elements H1 and H2, forming the active portion of the memory cell. Finally, a conductive layer 24 is deposited to cover the phase change layer.

[0117] Therefore, an integrated circuit 1 comprising a matrix of identical memory cells is obtained, each memory cell 10 including at least two resistive elements H1, H2 connected in parallel, the resistance of which has the aforementioned characteristics. Thus, a memory cell exhibiting improved performance, particularly during read operations in the SET state and also during RESET programming operations, is obtained.

[0118] The embodiments have just been described. Various alternatives and modifications will arise for those skilled in the art.

[0119] In one embodiment, the memory cell (10) includes a crystallization temperature (Tc). c ) and melting temperature (T) fThe active portion (12) of the phase change material is summarized as including: a first conductive contact (11); at least one first resistive element (H1) and a second resistive element (H2) electrically connected and coupled to the first conductive contact (11) in parallel, the first resistive element (H1) having a resistance (R1) that has the following properties: below the crystallization temperature (T c The first temperature (T) READ The first value under (R1) TREAD ), and less than or equal to its first value (R1) TREAD ) at temperatures greater than the melting temperature (T) f The second temperature (T) RESET The second value (R1) under ) TRESET The second resistive element (H2) has a resistance (R2) that is greater than a first value (R1) of the first resistive element (H1). TREAD ) at the first temperature (T) READ The first value under (R2) TREAD ), and a second value (R1) lower than the first resistive element (H1). TRESET ) at the second temperature (T RESET The second value (R2) under ) TRESET ); active portion (12), coupled to first resistive element (H1) and second resistive element (H2); and second conductive contact (24), coupled to active portion (12).

[0120] The first resistive element (H1) and the second resistive element (H2) each include a first portion (H1.2, H2.2) extending from the first conductive contact (11) to the active portion (12), the first portion (H1.2) of the first resistive element (H1) being spaced apart from the first portion (H2.2) of the second resistive element (H2) by a first spacer (22.1) made of an electrically insulating material.

[0121] The first resistive element (H1) and the second resistive element (H2) each include a second portion (H1.1, H2.1) extending from the first portion (H1.2, H2.2) and positioned in contact with the first conductive contact (11), and a first spacer (22.1) covers the second portion (H1.1) of the first resistive element (H1).

[0122] The memory cell (10) includes a second spacer (22.2) which extends along the surface of a first portion (H2.2) of a second resistive element (H2) opposite to a first spacer (22.1) and covers a second portion (H2.1) of the second resistive element (H2).

[0123] The first resistive element (H1) and the second resistive element (H2) have the same or different thicknesses.

[0124] At the first temperature (T) READ Under these conditions, the first value of the resistance (R2) of the second resistive element (H2) is... TREAD ) is the first value of the resistance (R1) of the first resistive element (H1). TREAD It is at least twice the size.

[0125] The first resistive element (H1) and / or the second resistive element (H2) are made of materials based on titanium silicon and / or tungsten nitride.

[0126] The active part (12) is made of chalcogenides, preferably of ternary chalcogenides.

[0127] In one embodiment, the integrated circuit (1) includes an array of identical memory cells (10).

[0128] A method for manufacturing at least one memory cell (10) according to any one of claims 1 to 8 is summarized as comprising the following steps: fabricating a first insulating layer (21) and at least one first conductive contact (11) extending through the first insulating layer (21) onto the first conductive contact (11); fabricating a second insulating layer (25) covering the first insulating layer (21) and the first conductive contact (11); fabricating at least one opening (27) extending through the second insulating layer (25) onto the first conductive contact (11); depositing a first thin conductive layer (28) onto the sidewalls of the opening (27) and partially etching to obtain a first resistive element (H1); depositing a thin insulating layer (29) onto the sidewalls of the first resistive element (H1) and partially etching to obtain a first spacer (22.1); depositing a second thin conductive layer (30) onto the sidewalls of the first spacer (22.1) and partially etching to obtain a second resistive element (H2); fabricating an active portion (12); and fabricating a second conductive contact (24).

[0129] The first thin conductive layer (28) is deposited by chemical vapor deposition.

[0130] The second thin conductive layer (30) is deposited by atomic layer deposition.

[0131] The first thin conductive layer (28) and / or the second thin conductive layer (30) are made of materials based on titanium silicon and / or tungsten nitride.

[0132] The manufacturing method includes a step of filling an opening (27), which is performed before and after the step of making the active portion (12) and followed by the step of making a continuous layer (23) of phase change material.

[0133] A method for manufacturing an integrated circuit (1) is summarized as including simultaneously fabricating an array of identical memory cells (10) by the method described above.

[0134] In view of the above detailed description, these and other changes may be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed as including all possible embodiments and the full scope of any equivalents to which these claims are given. Therefore, the claims are not limited by the disclosure.

Claims

1. A memory cell comprising an active portion of a phase change material having a crystallization temperature and a melting temperature, the memory cell comprising: First conductive contact; At least one first resistive element and one second resistive element are electrically connected and coupled to the first conductive contact in parallel. The first resistive element has resistance, which has the following properties: The first value at a first temperature below the crystallization temperature, and A second value less than or equal to its first value at a second temperature greater than the melting temperature. The second resistive element has resistance, which has the following properties: A first value greater than the first value of the first resistive element at a first temperature, and A second value at a second temperature that is lower than the second value of the first resistive element; The active portion is coupled to the first resistive element and the second resistive element; as well as The second conductive contact is coupled to the active portion.

2. The memory cell of claim 1, wherein the first resistive element and the second resistive element each include a first portion extending from the first conductive contact to the active portion, the first portion of the first resistive element being spaced apart from the first portion of the second resistive element by a first spacer made of an electrically insulating material.

3. The memory cell of claim 2, wherein the first resistive element and the second resistive element each include a second portion extending from the first portion and positioned in contact with the first conductive contact, and the first spacer covers the second portion of the first resistive element.

4. The memory cell of claim 3 further includes a second spacer, which extends along the surface of a first portion of the second resistive element opposite to the first spacer and covers a second portion of the second resistive element.

5. The memory cell according to claim 1, wherein the first resistive element and the second resistive element have the same or different thicknesses.

6. The memory cell according to claim 1, wherein, At the first temperature, the first value of the resistance of the second resistive element is at least twice the first value of the resistance of the first resistive element.

7. The memory cell of claim 1, wherein the first resistive element and / or the second resistive element are made of a material based on titanium silicon and / or tungsten nitride.

8. The memory cell according to claim 1, wherein the active portion is made of a chalcogenide, preferably a ternary chalcogenide.

9. A method for manufacturing at least one memory cell, the method comprising: A first insulating layer is fabricated and at least one first conductive contact is extended through the first insulating layer onto it; Fabricate a second insulating layer covering the first insulating layer and the first conductive contact; Make at least one opening that extends through the second insulating layer and onto the first conductive contact; A first thin conductive layer is deposited onto the side flanks of the opening, and local etching is performed to obtain a first resistive element; A thin insulating layer is deposited onto the side flanks of the first resistive element, and local etching is performed to obtain the first spacer; A second thin conductive layer is deposited onto the side flanks of the first spacer, and local etching is performed to obtain a second resistive element; An active portion of a phase change material having a crystallization temperature and a melting temperature is fabricated, and the active portion is coupled to a first resistive element and a second resistive element. as well as A second conductive contact is fabricated and coupled to the active portion.

10. The manufacturing method according to claim 9, wherein the first thin conductive layer is deposited by chemical vapor deposition.

11. The manufacturing method according to claim 9, wherein the second thin conductive layer is deposited by atomic layer deposition.

12. The manufacturing method according to claim 9, wherein the first thin conductive layer and / or the second thin conductive layer are made of a material based on titanium silicon and / or tungsten nitride.

13. The manufacturing method according to claim 9 further includes a step of filling the opening, wherein the step of filling the opening is performed before the step of making the active portion and is followed by the step of making a continuous layer of the phase change material.

14. A method comprising: A first insulating layer is deposited on the first conductive contact of the memory cell; The first conductive contact is exposed by forming a trench in the insulating layer; A first resistive element of the memory cell is deposited in the trench on the top surface of the first conductive contact. A second resistive element of the memory cell is deposited adjacent to the first resistive element in the trench on the top surface of the first conductive contact. The trench is filled with a first insulating material; A phase change material layer of the memory cell is deposited on the top surface of the resistive element, on the top surface of the second resistive element, and on the top surface of the first insulating material. as well as A second conductive contact is deposited on the phase change material layer.

15. The method of claim 14, wherein the first resistive element and the second resistive element each have an L-shape.

16. The method of claim 15, wherein the lower portion of the first resistive element is in contact with the lower portion of the second resistive element.

17. The method of claim 16, further comprising: A portion of the top surface of the first conductive contact is exposed by patterning the first resistive element; as well as After patterning the first resistive element, a second resistive element is deposited on the portion of the top surface of the first conductive contact.

18. The method of claim 15, wherein the second insulating material is positioned between the upper portion of the first resistive element and the upper portion of the second resistive element.

19. The method of claim 18, wherein the second conductive contact is on the top surface of the second insulating material.

20. The method of claim 14, wherein the phase change material layer is positioned on a first resistive element and a second resistive element of a plurality of memory cells.

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