High bandwidth memory and semiconductor package

Abstract

This invention discloses a high-bandwidth memory and semiconductor package, wherein the high-bandwidth memory (HBM) includes a logic chip and a dynamic random access memory (DRAM) stack. The DRAM stack includes multiple HBM DRAM chips and multiple through-silicon via (TSV) stacks. The HBM DRAM chips are vertically stacked on the logic chip. The TSV stacks are configured to electrically connect the HBM DRAM chips to the logic chip via multiple solder balls formed by TSV solder ball regions defined on the logic chip, wherein the TSV solder ball regions are along a horizontal direction defined by the layout orientation of the logic chip.

Description

Technical Field

[0001] This invention relates to integrated circuit (IC) design, and more particularly to a high bandwidth memory (HBM) with a rotating dynamic random access memory (DRAM) stack on a logic die and related semiconductor packaging. Background Technology

[0002] HBM systems are typically used in application-specific integrated circuit (ASIC) chip designs that employ special-purpose processors such as artificial intelligence (AI) accelerators, graphics processing units (GPUs), central processing units (CPUs), or other datacenter processors. HBMs employ a three-dimensional (3D) stacking method, vertically stacking multiple HBM DRAM chips on a logic chip (also known as the base die) and electrically connecting the HBM DRAM chips to the logic chip using through-silicon vias (TSVs). In traditional HBM designs, the TSV stack is formed at the center of the DRAM stack, requiring a vertical TSV solder ball region on the logic chip. This makes implementation challenging because the TSV stack consists of metal pillars. Since each TSV requires a keep-out zone (KOZ), signals are blocked when routing from one side of the vertical TSV solder ball region, unable to pass through the TSV solder ball region to reach the other side. Summary of the Invention

[0003] One of the objectives of this invention is to provide a high-bandwidth memory (HBM) (e.g., a custom high-bandwidth memory (cHBM)) having a rotating dynamic random access memory stack on a logic chip (e.g., a custom logic chip) and an associated semiconductor package.

[0004] According to a first aspect of the invention, an exemplary high-bandwidth memory (HBM) includes a logic chip and a dynamic random access memory (DRAM) stack. The DRAM stack includes a plurality of HBM DRAM chips and a plurality of through-silicon via (TSV) stacks. The HBM DRAM chips are vertically stacked on the logic chip. The TSV stack is configured to electrically connect the HBM DRAM chips to the logic chip via a plurality of solder balls formed by TSV solder ball regions defined on the logic chip, wherein the TSV solder ball regions are along a horizontal direction defined by the layout orientation of the logic chip.

[0005] According to a second aspect of the invention, an exemplary semiconductor package includes a computing chip and a high-bandwidth memory (HBM). The HBM includes a logic chip and a dynamic random-access memory (DRAM) stack. The DRAM stack includes a plurality of HBM DRAM chips and a plurality of through-silicon via (TSV) stacks. The HBM DRAM chips are vertically stacked on the logic chip. The TSV stack is configured to electrically connect the HBM DRAM chips to the logic chip via a plurality of solder balls formed by TSV solder ball regions defined on the logic chip. The TSV solder ball regions are along a direction perpendicular to a first side of the logic chip, the first side being adjacent to the computing chip.

[0006] These and other objectives of the present invention will undoubtedly become apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments and the figures and drawings. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the structure of a semiconductor package according to an embodiment of the present invention.

[0008] Figure 2 This diagram illustrates the vertical TSV solder ball region on a traditional logic chip and the horizontal TSV solder ball region on a logic chip proposed in this invention.

[0009] Figure 3 for Figure 1 The diagram shows a top view of the logic chip.

[0010] Figure 4 This is a schematic diagram of the signal routing design at the top and bottom of the TSV solder ball area according to an embodiment of the present invention.

[0011] The reference numerals in the attached figures are explained as follows: 100: Semiconductor Packaging 101: Packaging substrate 102: Computing chip 104: HBM 106: Intermediary Layer 108, 108': Logic chip 110: HBM DRAM chip 111: DRAM Stack 112: TSV Stack 113, 115: Logic circuits 114, 116: PHY circuit 118: Welding ball 202: Vertical TSV solder ball area 204: Horizontal TSV solder ball area 302: One side of the logic chip 304: Top side of the horizontal TSV solder ball area 306: Bottom side of the horizontal TSV solder ball area 308: Left side of the horizontal TSV solder ball area 310: Right side of the horizontal TSV solder ball area 312_1, 312_2, 312_3, 312_N: TSV stack groups Detailed Implementation

[0012] Certain terms are used in the following description and claims to refer to specific components. As those skilled in the art will understand, electronic device manufacturers may use different names to refer to the same component. This document is not intended to distinguish between components with different names but the same function. In the following description and claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as "including but not limited to...". Furthermore, the term "coupled" is intended to indicate an indirect or direct electrical connection. Thus, if one device is coupled to another device, the connection can be a direct electrical connection or an indirect electrical connection through other devices and connections.

[0013] Figure 1 This is a schematic diagram of a semiconductor package structure according to an embodiment of the present invention. The semiconductor package 100 can be an ASIC chip. Figure 1As shown, the semiconductor package 100 includes a package substrate 101, a compute die 102, a high bandwidth memory (HBM) 104, and an interposer 106. Both the compute die 102 and the HBM 104 are mounted on and connected to the interposer 105. In this embodiment, the compute die 102 and the HBM 104 are placed side-by-side on the interposer 105. The HBM 104 is implemented using a three-dimensional stacking method by vertically stacking multiple HBM DRAM chips 110 on a logic chip (also referred to as the bottom chip) 108. Specifically, the HBM 104 has a DRAM stack 111 on the logic chip 108 (which includes vertically stacked HBM DRAM chips 110). The DRAM stack 111 also includes multiple TSV stacks 112, each TSV stack forming a TSV in all HBM DRAM chips 110 except for the top HBM DRAM chip. TSV stack 112 is used to electrically connect HBM DRAM chip 110 to logic chip 108. Logic chip 108 is the basic non-memory layer at the bottom of the 3D memory stack and provides an interface to computing chips (such as GPU / CPU / SoC chips) 102. For example, logic chip 108 has a physical layer (PHY) circuit (labeled "PHY" in the figure) 114, which is electrically connected to the PHY circuit (labeled "PHY" in the figure) 116 on computing chip 102. PHY circuits 114 / 116 include multiple physical channels, each of which is divided into multiple pseudochannels. For example, for a 3D memory stack of HBM 104, a 64-bit physical channel can be divided into two 32-bit pseudochannels.

[0014] If the DRAM stack 111, manufactured and supplied by the DRAM supplier, is not rotated 90 degrees before being mounted to the legacy logic chip 108' via multiple solder balls (e.g., micro-solder balls), then as Figure 2 As shown in sub-figure (A), a vertical TSV solder ball region 202 is defined on the conventional logic chip 108'. Since the vertical TSV solder ball region 202 extends along a vertical direction defined by the layout direction of the conventional logic chip 108', and the KOZ requirement of the TSV needs to be met, signal routing from one side A of the vertical TSV solder ball region 202 is blocked and cannot pass through the vertical TSV solder ball region 202 to reach the other side B. Such a vertical TSV solder ball region makes it difficult to add additional logic circuitry (i.e., more logic functions) on the logic chip (the underlying chip) to implement a custom high-bandwidth memory (also known as cHBM) for the custom logic chip.

[0015] In this embodiment, the DRAM stack 111, manufactured and supplied by the DRAM supplier, is rotated 90 degrees before being mounted onto the logic chip 108 via multiple solder balls 118 (e.g., micro-solder balls), each solder ball 118 being connected to one of multiple TSV stacks 112. By rotating the DRAM stack 90 degrees relative to the logic chip, the positions of the TSV stacks 112 change, allowing a horizontal TSV solder ball region 204 to be defined on the logic chip 108, such as... Figure 2 As shown in sub-figure (B), solder balls 118 are formed on a horizontal TSV solder ball region 204, which extends along a horizontal direction defined by the layout orientation of the logic chip 108. Rotating the DRAM stack 111 by 90 degrees does not cause wiring problems. Such a horizontal TSV solder ball region facilitates the addition of additional logic circuitry (i.e., more logic functions) on the logic chip to implement custom logic chips for custom high-bandwidth memories. For example, in addition to the basic functions of a typical logic chip, the logic chip 108 of HBM 104 (i.e., the custom logic chip of cHBM) can also include additional logic functions, including direct access (DA), programmable memory built-in self-test (PMBIST), memory controller (MC), etc. About Figure 1 In the illustrated embodiment, logic chip 108 may include two logic circuits 113 and 115, wherein logic circuit 113 (labeled "MC") handles MC functions, and logic circuit 115 (labeled "DA / PMBIST") handles DA / PMBIST functions. A system-technology co-optimization (STCO) approach can be used to assemble multiple asynchronously designed chips into a single semiconductor package 100. For example, the chip shoreline can be changed from 11 mm to 14 mm.

[0016] It is important to note that Figure 1 The packaging structure shown is for illustrative purposes only and is not intended to limit the invention. In practical applications, the present invention does not limit the packaging technology used for assembling and packaging the computing chip 102 and HBM 104. Furthermore, the number of computing chips and the number of HBMs can be adjusted according to actual application requirements. In some embodiments of the present invention, the semiconductor package 100 may be an ASIC chip having multiple computing chips 102 and / or multiple HBMs 104. In short, any semiconductor package having a 90-degree rotated DRAM stack and mounted on a logic chip (bottom chip) with horizontal TSV solder ball areas falls within the scope of the present invention.

[0017] Figure 3 yes Figure 1 The diagram shows a top view of the logic chip 108. A horizontal TSV solder ball region 204 extends along a horizontal direction defined by the layout orientation of the logic chip 108. Since the HBM 104 and the compute chip 102 are placed side-by-side on the interposer 106, the logic chip 108 has one side 302 (e.g., the right side or east side) adjacent to the compute chip 102. The horizontal TSV solder ball region 204 is a rectangular region. Figure 3 As shown, the horizontal TSV solder ball region 204 has a top side 304 and a bottom side 306, both perpendicular to one side 302 of the logic chip adjacent to the computing chip 102, and a left side 308 and a right side 310, both parallel to one side 302 of the logic chip adjacent to the computing chip 102. The horizontal TSV solder ball region 204 is along a direction perpendicular to one side 302 of the logic chip adjacent to the computing chip 102. In this embodiment, logic circuits 113 and 115 are both electrically connected to the TSV stack 112 via solder balls (e.g., micro solder balls) formed on the horizontal TSV solder ball region 204. Logic circuit 115 (e.g., DA / PMBIST circuit) is located on the left side of the horizontal TSV solder ball region 204. Logic circuit 113 (e.g., MC circuit) is located on the right side of the horizontal TSV solder ball region 204.

[0018] Since the horizontal TSV solder ball region 204 is a horizontal TSV solder ball region, the signal traces of logic circuit 113 can be routed to the top and bottom sides of the horizontal TSV solder ball region 204, and the signal traces of logic circuit 115 can also be routed to the top and bottom sides of the horizontal TSV solder ball region 204. In this embodiment, the TSV stack 112 is classified into multiple TSV stack groups 312_1 to 302_N ( These correspond to different channels of HBM 104. For example, TSV stack group 312_1 corresponds to channel CH0, TSV stack group 312_2 corresponds to channel CH1, TSV stack group 312_3 corresponds to channel CH2, and so on. In some embodiments of the present invention, logic circuits 113 and 115 are electrically connected to TSV stack groups 312_1 to 312_N from the top side of the horizontal TSV solder ball region 204 in an interleaved manner, and logic circuits 113 and 115 are electrically connected to TSV stack groups 312_1 to 312_N from the bottom side of the horizontal TSV solder ball region 204 in an interleaved manner. For example, logic circuit 115 is electrically connected to the first channel of HBM 104 from the top side of the horizontal TSV solder ball region 204, and logic circuit 113 is electrically connected to the first channel of HBM 104 from the bottom side of the TSV solder ball region; logic circuit 115 is electrically connected to the second channel of HBM 104 from the bottom side of the horizontal TSV solder ball region 204, and logic circuit 113 is electrically connected to the second channel of HBM 104 from the top side of the horizontal TSV solder ball region 204. The first channel and the second channel can be adjacent channels of HBM 104.

[0019] Figure 4 This is a schematic diagram of the signal routing design at the top and bottom of the TSV solder ball area according to an embodiment of the present invention. Assuming logic circuit 115 is a memory test circuit (e.g., a DA / PMBIST circuit), logic circuit 113 is a memory controller circuit, and TSV stack 112 is classified into 16 TSV stack groups 312_1 to 302_N (N=16), corresponding to the 16 channels CH0 to CH15 of HBM 104 respectively. Figure 4As shown, the test signal traces are DA / PMBIST. <0> DA / PMBIST <2> , ..., DA / PMBIST <14> and memory access signal routing DFI2TSV <1> ..., DFI2TSV <15> The memory access signal traces DFI2TSV are arranged alternately on the top side of the horizontal TSV solder ball area 204. <0> DFI2TSV <2> ..., DFI2TSV <14> And test signal routing DA / PMBIST <1> , ..., DA / PMBIST <15> They are arranged alternately on the bottom side of the horizontal TSV solder ball area 204. Therefore, the memory test circuit can be routed via the test signal traces DA / PMBIST. <0> Testing the HBM channel CH0 from the top side of the horizontal TSV solder ball area 204, the memory controller circuit can be accessed via the memory access signal trace DFI2TSV. <0> HBM channel CH0 is accessed (read / write) from the bottom side of the horizontal TSV solder ball area 204; the memory test circuit can be accessed via the test signal trace DA / PMBIST. <1> Testing HBM channel CH1 from the bottom side of horizontal TSV solder ball area 204 allows the memory controller circuitry to access the memory access signal trace DFI2TSV. <1> HBM channel CH1 is accessed (read / write) from the top side of the horizontal TSV solder ball area 204; the memory test circuit can be accessed via the test signal trace DA / PMBIST. <2> Testing of HBM channel CH2 from the top side of horizontal TSV solder ball area 204 allows the memory controller circuitry to access the memory access signal trace DFI2TSV. <2> HBM channel CH2 is accessed (read / write) from the bottom side of the horizontal TSV solder ball area 204; the memory test circuit can be accessed via the test signal trace DA / PMBIST. <14> Testing of HBM channel CH14 from the top side of horizontal TSV solder ball area 204 allows the memory controller circuitry to access the memory access signal trace DFI2TSV. <14> HBM channel CH14 is accessed (read / write) from the bottom side of the horizontal TSV solder ball area 204; the memory test circuit can be accessed via the test signal trace DA / PMBIST. <15> Testing of HBM channel CH15 from the bottom side of horizontal TSV solder ball area 204 allows the memory controller circuitry to access the memory access signal trace DFI2TSV. <15> Access (read / write) HBM channel CH15 from the bottom side of the horizontal TSV solder ball area 204.

[0020] The foregoing has outlined the features of several embodiments, enabling those skilled in the art to fully understand various aspects of the invention. Those skilled in the art should recognize that the invention provides a basis for designing or modifying other processes and structures to achieve substantially the same functionality and / or substantially the same results as the embodiments described above. Furthermore, such equivalent configurations do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made without departing from that spirit and scope.

Claims

1. A high-bandwidth memory (HBM), characterized in that, include: Logic chip; as well as The dynamic random access memory (DRAM) stack includes: Multiple HBM DRAM chips are vertically stacked on this logic chip; as well as Multiple through-silicon via (TSV) stacks are used to electrically connect multiple HBM DRAM chips to the logic chip via multiple solder balls formed by TSV solder ball regions defined on the logic chip, wherein the TSV solder ball regions are along a horizontal direction defined by the layout direction of the logic chip.

2. The HBM as described in claim 1, characterized in that, The logic chip includes a first logic circuit and a second logic circuit, both of which are electrically connected to the plurality of TSV stacks. The first logic circuit is located on the left side of the TSV solder ball area, and the second logic circuit is located on the right side of the TSV solder ball area.

3. The HBM as described in claim 2, characterized in that, One of the first logic circuit and the second logic circuit is a memory controller circuit.

4. The HBM as described in claim 2, characterized in that, One of the first logic circuit and the second logic circuit is a memory test circuit.

5. The HBM as described in claim 2, characterized in that, The multiple TSV stacks are classified into multiple TSV stack groups, each corresponding to a multiple channel of the HBM; the first logic circuit is electrically connected to the first channel of the HBM from the top of the TSV solder ball region, and the second logic circuit is electrically connected to the first channel of the HBM from the bottom of the TSV solder ball region; and the first logic circuit is electrically connected to the second channel of the HBM from the bottom of the TSV solder ball region, and the second logic circuit is electrically connected to the second channel of the HBM from the top of the TSV solder ball region.

6. The HBM as described in claim 5, characterized in that, The first channel and the second channel are adjacent channels of the HBM.

7. The HBM as described in claim 1, characterized in that, The HBM is a custom high-bandwidth memory, and the logic chip is a custom logic chip.

8. A semiconductor package, characterized in that, include: Computing chip; as well as HBM, including: Logic chips; and The DRAM stack includes: Multiple HBM DRAM chips are vertically stacked on this logic chip; and Multiple TSV stacks are used to electrically connect multiple HBM DRAM chips to the logic chip through multiple solder balls formed by TSV solder ball regions defined on the logic chip; The first side of the logic chip is adjacent to the computing chip, and the TSV solder ball area extends along a direction perpendicular to the first side of the logic chip.

9. The semiconductor package as described in claim 8, characterized in that, The logic chip includes a first logic circuit and a second logic circuit, both of which are electrically connected to the plurality of TSV stacks. The first logic circuit is located on a first side of the TSV solder ball region, and the second logic circuit is located on a second side of the TSV solder ball region. Both the first and second sides are parallel to the first side of the logic chip.

10. The semiconductor package as claimed in claim 9, characterized in that, One of the first logic circuit and the second logic circuit is a memory controller circuit.

11. The semiconductor package as described in claim 9, characterized in that, One of the first logic circuit and the second logic circuit is a memory test circuit.

12. The semiconductor package as described in claim 9, characterized in that, The multiple TSV stacks are classified into multiple TSV stack groups, each corresponding to a multiple channel of the HBM; the first logic circuit is electrically connected to the first channel of the HBM from the third side of the TSV solder ball region, and the second logic circuit is electrically connected to the first channel of the HBM from the fourth side of the TSV solder ball region; the first logic circuit is electrically connected to the second channel of the HBM from the fourth side of the TSV solder ball region, and the second logic circuit is electrically connected to the second channel of the HBM from the third side of the TSV solder ball region, and both the third side and the fourth side are perpendicular to the first side of the logic chip.

13. The semiconductor package as described in claim 12, characterized in that, The first channel and the second channel are adjacent channels of the HBM.

14. The semiconductor package as claimed in claim 8, characterized in that, The HBM is a custom high-bandwidth memory, and the logic chip is a custom logic chip.

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