A three-dimensional memory package assembly with heat flow adaptive barrier interface and method of construction thereof

Abstract

This invention discloses a three-dimensional memory packaging component with a heat flux adaptive barrier interface and its configuration method, belonging to the field of semiconductor packaging technology. The packaging component includes a packaging substrate, a main control chip, an insulating adhesive layer, a silicon-based isolation pad, a memory chip stack layer, and a molding compound. The silicon-based isolation pad has a shallow groove on the side facing the main control chip. The opening boundary of the shallow groove is formed as an irregular, smooth, closed curve adapted to the heat flux density distribution of the high-heat area on the back of the main control chip, and its orthographic projection covers the high-heat area. The shallow groove adopts a continuously transitioning non-linear gradient slope to reduce thermal stress concentration between the adhesive layer and the silicon-based isolation pad. This solution can balance local hot spot isolation, overall heat dissipation, packaging structure stability, and memory chip data retention reliability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically, it relates to a three-dimensional storage packaging component with a thermal flow adaptive barrier interface and its configuration method. Background Technology

[0002] As enterprise-grade solid-state drives, high-density non-volatile memory, and edge computing devices evolve towards miniaturization and high capacity, three-dimensional storage packaging structures that integrate the main control chip and multi-layer storage chips within a single package are becoming increasingly common. Existing three-dimensional storage packages typically include a packaging substrate, a main control chip mounted on the substrate, an isolation pad on the back of the main control chip, and multi-layer storage chips mounted on the isolation pad. This stacked structure shortens the interconnect paths between chips, reduces package size, and increases storage capacity density. However, during high-load operations such as data processing, garbage collection, wear leveling, and read / write scheduling, the logic operation areas within the main control chip are prone to high localized heat flux density. Simultaneously, the non-volatile storage chips located above the main control chip are highly temperature-sensitive; excessively high temperatures can affect their charge retention characteristics, read / write reliability, and lifespan.

[0003] In existing technologies, to improve the overall heat dissipation capacity of packaged components, a thin thermally conductive adhesive layer is typically placed between the main control chip and the isolation pad, or an adhesive material with high thermal conductivity is used to reduce the vertical thermal resistance between the main control chip and the isolation pad. However, in a package structure where the main control chip and memory chips are stacked vertically, the heat generated by the high-heat-generating area of ​​the main control chip may be directly transferred to the upper memory chip stack layer via the low thermal resistance path, causing localized temperature rise in the underlying memory chip adjacent to the main control chip, thereby increasing the risk of data retention failure and decreased thermal reliability. Furthermore, simply increasing the thickness of the adhesive layer or forming regular grooves on the isolation pad to improve localized thermal resistance can easily introduce new problems. On the one hand, regularly shaped grooves are often difficult to match with the irregular heat flow distribution in the actual high-heat areas of the main control chip, which may result in insufficient coverage of hot spots or excessive coverage of low-heat areas, thus hindering normal heat dissipation. On the other hand, there are significant differences in elastic modulus and thermal expansion coefficient between the isolation pad and the adhesive layer. Grooves with right-angled sidewalls or sharp edges are prone to stress concentration during reflow soldering and temperature cycling, which can lead to problems such as adhesive layer delamination, silicon-based isolation pad cracking, or package warping exceeding tolerance.

[0004] Therefore, how to construct a local thermal resistance isolation area based on the actual heat flow distribution of the main control chip, while suppressing the vertical transfer of heat from the high-heat area to the memory chip above, while retaining an effective heat dissipation path for the low-heat area, and taking into account the anti-warping capability, interface bonding reliability and manufacturing feasibility of the packaged components, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The present invention aims to at least solve the problems in the prior art where heat from the local high-heat area of ​​the main control chip is easily transferred vertically to the upper memory chip stack layer, regular heat-resistant structures are difficult to adapt to the actual heat flow distribution, and locally thickened adhesive layers can easily cause thermal stress concentration and package warping.

[0006] This invention employs the following technical solution: a three-dimensional memory packaging assembly with a heat flux adaptive barrier interface, comprising a packaging substrate, a main control chip, an insulating adhesive layer, a silicon-based isolation pad, a memory chip stack layer, and a molding compound; the main control chip is disposed on the main surface of the packaging substrate via flip-chip bonding; the silicon-based isolation pad is disposed on the back side of the main control chip, having a first surface for supporting the memory chip stack layer and a second surface facing the main control chip; the second surface has a shallow groove, the opening boundary of the shallow groove on the second surface being an irregular smooth closed curve adapted to the heat flux density distribution on the back side of the main control chip, and the orthogonal projection of the shallow groove on the main control chip covers the main control chip. The chip has a high-heat area; the insulating adhesive layer is disposed between the main control chip and the silicon-based isolation pad, and fills the shallow groove, so as to form a thick adhesive layer area at the position corresponding to the high-heat area and a thin adhesive layer area at the position outside the shallow groove; the inner wall of the shallow groove is a non-linear gradient slope that continuously transitions from the bottom of the groove to the edge of the opening; the memory chip stack layer is disposed on the first surface and electrically connected to the packaging substrate; wherein, the thick adhesive layer area and the thin adhesive layer area constitute a heat flow adaptive barrier interface, so that the heat of the high-heat area diffuses laterally to its edge area through the main control chip, and enters the silicon-based isolation pad through the thin adhesive layer area and is then conducted to the periphery of the silicon-based isolation pad.

[0007] Preferably, the thermal conductivity of the insulating patch adhesive layer is less than 1.5 W / (m·K), the silicon-based insulating pad is a monocrystalline silicon pad, and the thermal conductivity of the silicon-based insulating pad is greater than 130 W / (m·K).

[0008] Preferably, the irregular smooth closed curve is formed by offsetting the critical heat flux density contour line on the back of the main control chip outward along the normal direction by a preset assembly compensation distance, wherein the preset assembly compensation distance is 30μm to 50μm.

[0009] Preferably, the total thickness of the silicon-based insulating pad is 80 μm to 120 μm, the maximum depth of the shallow groove is 15% to 22% of the total thickness of the silicon-based insulating pad, and the thickness of the silicon material retained above the shallow groove is 78% to 85% of the total thickness of the silicon-based insulating pad.

[0010] Preferably, the thickness of the thin adhesive layer region is 5 μm to 10 μm, and the thickness of the thick adhesive layer region is 20 μm to 32 μm.

[0011] Preferably, the nonlinear gradient slope is tangent to the bottom plane of the shallow groove at the bottom of the groove and tangent to the second surface at the opening edge of the shallow groove; the bottom of the shallow groove and the nonlinear gradient slope are connected by a first arc surface, and the nonlinear gradient slope and the second surface are connected by a second arc surface, wherein the radii of curvature of the first arc surface and the second arc surface are both greater than 5μm.

[0012] Preferably, the memory chip stack layer comprises multiple layers of non-volatile memory dies stacked in a staggered manner; each of the non-volatile memory dies is fixed to the first surface of the silicon-based isolation pad by an insulating adhesive film and electrically connected to the packaging substrate by metal leads; the molding compound covers the packaging substrate, the main control chip, the insulating patch adhesive layer, the silicon-based isolation pad, and the memory chip stack layer.

[0013] A configuration method for a three-dimensional memory packaging component with a heat flux adaptive barrier interface includes: acquiring the layout power consumption distribution of a main control chip, the material thermal parameters of the main control chip, the material thermal parameters of a silicon-based isolation pad, and the assembly positioning tolerance between the main control chip and the silicon-based isolation pad; establishing a steady-state heat conduction model of the main control chip based on the layout power consumption distribution and material thermal parameters, and solving for the heat flux density distribution on the back side of the main control chip; determining a critical heat flux density threshold corresponding to the safe temperature of the memory chip, and extracting a closed contour line where the heat flux density on the back side of the main control chip is equal to the critical heat flux density threshold; and, based on the assembly positioning tolerance, configuring the... The closed isotropic trajectory line is used for outward expansion compensation to obtain the opening profile of the shallow groove; a two-phase mechanical coupling model of silicon-based isolation pad and insulating patch adhesive layer is established, and the nonlinear gradient slope and maximum depth of the shallow groove are determined under the constraint of groove volume; according to the opening profile, nonlinear gradient slope and maximum depth, a shallow groove is formed on the second surface of silicon-based isolation pad; the insulating patch adhesive layer is placed on the back of the main control chip, so that the insulating patch adhesive layer fills the shallow groove and is cured to form a thick adhesive layer area corresponding to the high heat generation area of ​​the main control chip and a thin adhesive layer area corresponding to the edge area of ​​the main control chip; and a memory chip stack layer is formed on the first surface of silicon-based isolation pad and encapsulation is completed.

[0014] Preferably, determining the nonlinear gradient slope and maximum depth of the shallow groove includes: under simulated reflow soldering temperature load, obtaining the outer corner vertex of the packaging substrate, the edge junction point of the main control chip and the silicon-based isolation pad, and the deformation control node at the highest corner of the memory chip stack layer; determining the maximum depth of the shallow groove with the constraint that the vertical displacement of the deformation control node does not exceed a preset warping threshold; wherein, the preset warping threshold is 75μm.

[0015] Preferably, forming the shallow groove includes: converting the opening profile into photomask data; forming a photoresist pattern corresponding to the photomask data on the second surface of the silicon-based isolation pad; and forming a shallow groove with the irregular smooth closed curve and nonlinear gradient slope in the silicon-based isolation pad by using reactive ion etching, wet etching, grayscale photolithography combined with dry etching, or multi-pass progressive photolithography combined with isotropic etching process.

[0016] Compared to existing technologies, this invention offers at least the following advantages: By creating a shallow groove on the side of the silicon-based isolation pad facing the main control chip, and using the insulating adhesive layer filling the shallow groove to form a thick adhesive layer region, the vertical thermal resistance between the high-heat area of ​​the main control chip and the silicon-based isolation pad can be increased. This reduces the possibility of localized high heat flow being directly transferred to the upper memory chip stack layer, thereby reducing the risk of localized overheating of the underlying memory chip. The opening boundary of the shallow groove is determined based on the heat flux density distribution on the back of the main control chip, allowing the thick adhesive layer region to adapt to the high-heat area. Simultaneously, a thin adhesive layer region is retained in the low-heat edge region, allowing heat from the high-heat area to diffuse laterally within the main control chip and then enter the silicon-based isolation pad through the thin adhesive layer region and be conducted to the periphery. Thus, while suppressing vertical heat transfer from hot spots, the overall heat dissipation path is prevented from being completely blocked. By determining the shallow groove opening profile based on the isotropic trajectory of critical heat flux density and combining it with assembly positioning tolerances for outward expansion compensation, the thick adhesive layer area formed by filling the shallow groove can stably cover the high-heat-generating area of ​​the main control chip under actual mounting conditions, reducing the risk of hot spots not being effectively heat-resistant due to chip mounting deviations. The shallow groove adopts a non-linear gradient slope that continuously transitions from the groove bottom to the opening edge, and a smooth connection structure is set at the groove bottom and the opening edge. This avoids stress concentration at the interface between the silicon-based isolation pad and the insulating patch adhesive layer, as is common with traditional right-angle grooves, thereby reducing the risk of adhesive layer delamination, silicon microcracks, and package structure failure under thermal loads such as reflow soldering and temperature cycling. By determining the shallow groove depth based on the vertical warpage of the packaged component under thermal loads, the groove depth can provide the local thermal resistance increment required to form the thick adhesive layer area while retaining a sufficiently thick silicon-based isolation pad carrier layer, thus balancing local thermal resistance requirements, bonding capacity, and package coplanarity requirements. This invention synergistically configures heat flow distribution, assembly tolerance, material thermal expansion mismatch, interface geometry, and package warpage control, which can improve the thermal management performance, mechanical structure stability, and data retention reliability of three-dimensional storage packaging components without significantly increasing the package volume. Attached Figure Description

[0017] Figure 1 This is a front longitudinal section structural diagram of a three-dimensional storage packaging component with a heat flow adaptive barrier interface provided in an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram showing the alignment relationship between the irregular shallow groove on the bottom surface of the silicon-based isolation pad and the high-heat area of ​​the main control chip, as provided in an embodiment of the present invention.

[0019] Figure 3 This is a side view of a three-dimensional storage packaging component with a heat flow adaptive barrier interface provided in an embodiment of the present invention.

[0020] Figure 4 for Figure 3 The enlarged structural diagram at point B shows the structural relationship between the nonlinear gradient slope of the shallow groove, the thick adhesive layer region, and the thin adhesive layer region.

[0021] In the diagram, 100-packaging substrate; 101-external solder ball; 200-main control chip; 201-flip-chip metal bump; 202-high heat generation area; 300-silicon-based insulating pad; 301-shallow groove; 302-shallow groove opening boundary; 400-insulating patch adhesive layer; 401-thick adhesive layer area; 402-thin adhesive layer area; 500-memory chip stack layer; 600-metal lead; 700-molding compound. Detailed Implementation

[0022] To make the technical solution, structural relationships, and configuration process of the present invention clearer, the present invention will be further described below in conjunction with the accompanying drawings. It should be understood that the following embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the present invention; any equivalent substitutions or modifications made by those skilled in the art to materials, dimensions, process parameters, and structural forms without departing from the concept of the present invention should fall within the scope of protection of the present invention.

[0023] like Figures 1 to 4As shown, this invention provides a three-dimensional memory packaging assembly with a heat flow adaptive barrier interface, including a packaging substrate 100, a main control chip 200, an insulating adhesive layer 400, a silicon-based insulating pad 300, a memory chip stack layer 500, metal leads 600, and molding compound 700. The packaging substrate 100 supports the main control chip 200 and the memory chip stack layer 500, and provides corresponding electrical interconnection paths. The packaging substrate 100 can be an organic resin packaging substrate, a BT resin substrate, an ABF carrier board, or other multilayer interconnection substrates suitable for semiconductor packaging. The bottom of the packaging substrate 100 has multiple external solder balls 101 for electrically connecting the packaging assembly to an external printed circuit board. The main control chip 200 is disposed on the main surface of the packaging substrate 100. Specifically, the active surface of the main control chip 200 faces the packaging substrate 100. The main control chip 200 is connected to corresponding pads on the packaging substrate 100 via multiple flip-chip bonding metal bumps 201 to achieve mechanical fixation and electrical interconnection between the main control chip 200 and the packaging substrate 100. The side of the main control chip 200 facing away from the packaging substrate 100 is called the back side, and a silicon-based isolation pad 300 is disposed above this back side. The main control chip 200 has a high-heat area 202 under rated operating conditions. The high-heat area 202 may correspond to the area in the main control chip 200 where functional modules performing data processing, error checking, garbage collection, wear leveling, read / write scheduling, high-speed interface control, or other high-load computing tasks are located. The high-heat area 202 does not necessarily need to be located at the geometric center of the main control chip 200; its shape and position can be determined according to the actual layout power consumption distribution of the main control chip 200. The silicon-based isolation pad 300 has a first surface and a second surface disposed opposite to each other. The first surface is used to support the memory chip stack layer 500, and the second surface faces the main control chip 200. The silicon-based isolation pad 300 can be formed of single-crystal silicon material or other semiconductor materials with high in-plane thermal conductivity and sufficient mechanical strength. In one embodiment, the thermal conductivity of the silicon-based isolation pad 300 is greater than 130 W / (m·K), for example, it can be from 130 W / (m·K) to 170 W / (m·K). The second surface of the silicon-based isolation pad 300 has a shallow groove 301, and the opening boundary of the shallow groove 301 is a shallow groove opening boundary 302. The shallow groove opening boundary 302 is an irregular smooth closed curve, and the orthogonal projection of the shallow groove 301 on the main control chip 200 covers the high-heat area 202. In other words, the shallow groove 301 does not necessarily have to adopt a rectangular, circular, elliptical or other regular geometric shape, and its opening profile can be determined according to the actual heat flux density distribution on the back side of the main control chip 200. An insulating adhesive layer 400 is disposed between the main control chip 200 and the silicon-based insulating pad 300. The insulating adhesive layer 400 fills the shallow groove 301 and forms a thick adhesive layer area 401 at the position corresponding to the high heat generation area 202; a thin adhesive layer area 402 is formed at the position outside the shallow groove 301.The insulating patch adhesive layer 400 can be a modified epoxy resin adhesive, polyimide adhesive, epoxy-siloxane composite adhesive, or other low thermal conductivity polymer materials with insulating and adhesive properties.

[0024] In one embodiment, the thermal conductivity of the insulating patch adhesive layer 400 is less than 1.5 W / (m·K), preferably from 0.3 W / (m·K) to 1.0 W / (m·K). After the insulating patch adhesive layer 400 is cured, the thickness of the thick adhesive layer region 401 is greater than the thickness of the thin adhesive layer region 402, thereby giving the vertical heat transfer path above the high-heat-generating region 202 a higher thermal resistance, while retaining a relatively low thermal resistance heat conduction path above the edge region of the main control chip 200. The memory chip stack layer 500 is disposed on the first surface of the silicon-based isolation pad 300. The memory chip stack layer 500 may include a plurality of non-volatile memory dies stacked in a staggered manner, with adjacent memory dies fixed together by an insulating adhesive film, chip mounting adhesive, or other insulating adhesive materials. The memory chip stack layer 500 is electrically connected to the bonding pads on the packaging substrate 100 via metal leads 600. The molding compound 700 encapsulates the packaging substrate 100, the main control chip 200, the insulating adhesive layer 400, the silicon-based isolation pad 300, the memory chip stack layer 500, and the metal leads 600 to form a complete package.

[0025] Thermal barrier structure: such as Figure 1 and Figure 3 As shown, the main control chip 200, insulating adhesive layer 400, silicon-based insulating pad 300, and memory chip stack layer 500 are sequentially arranged along the thickness direction of the packaging substrate 100. Directly above the high-heat region 202, the insulating adhesive layer 400 fills the shallow groove 301, forming a thick adhesive layer region 401; above the edge region of the main control chip 200 outside the high-heat region 202, the insulating adhesive layer 400 forms a thin adhesive layer region 402. Let the thickness of the thin adhesive layer region 402 be... The thickness of the thick adhesive layer region 401 is The maximum depth of the shallow groove 301 is Then, at the deepest point of the shallow groove 301, the three conditions are satisfied: .in, , and The units are all in μm. For thermal conductivity... Thickness is The effective heat transfer area is The one-dimensional thermal resistance along the thickness direction of a uniform material layer can be estimated by the following formula: In the formula: Thermal resistance, measured in K / W; The thickness of the heat conduction path is expressed in meters (m). The thermal conductivity of the material is expressed in W / (m·K). The effective heat transfer area is expressed in meters (m²). When the thick adhesive layer region 401 and the thin adhesive layer region 402 use the same insulating adhesive material and have the same area, their thermal resistance ratio is: Therefore, when At this time, the vertical thermal resistance of the thick adhesive layer region 401 is greater than that of the thin adhesive layer region 402. When the heat generated by the high-heat area 202 of the main control chip 200 diffuses upward, it is blocked by the thick adhesive layer region 401; some heat diffuses in the in-plane direction within the main control chip 200 to the edge region, and can then enter the silicon-based isolation pad 300 through the thin adhesive layer region 402, and be conducted to its periphery by utilizing the higher in-plane thermal conductivity of the silicon-based isolation pad 300. Thus, the thick adhesive layer region 401 and the thin adhesive layer region 402 constitute a regionally differentiated thermal resistance interface: the thick adhesive layer region 401 mainly inhibits the local heat transfer of the high-heat area 202 to the memory chip stack layer 500 in the vertical direction, while the thin adhesive layer region 402 retains the heat dissipation path from the edge region of the main control chip 200 to the silicon-based isolation pad 300.

[0026] Shallow groove configuration: such as Figure 2 As shown, the shallow recess opening boundary 302 is adapted to the high-heat area 202 of the main control chip 200. Specifically, the layout power consumption distribution, material thermal parameters, package boundary conditions, and assembly positioning tolerances of the main control chip 200 can be obtained in advance, and a steady-state heat conduction model of the main control chip 200 can be established. The steady-state heat conduction model satisfies: In the formula: For gradient operators; The thermal conductivity of the material at the corresponding location; For temperature field; The heat source power density is expressed in W / m³. After obtaining the temperature field, the heat flux density vector on the back of the main control chip 200 can be expressed as: In the formula: This is a heat flux density vector, with units of W / m. The thermal conductivity of the main control chip is 200. The temperature gradient on the back of the main control chip 200 is used. A critical heat flux density threshold is set based on the acceptable temperature or temperature rise conditions of the memory chip stack layer 500. The set of points on the back of the main control chip 200 that satisfy the following formula can form the contour line of the critical heat flux density. : In the formula, and The coordinates are shown on the back of the main control chip 200. Considering potential lateral assembly deviations during the pressing of the main control chip 200 and the silicon-based isolation pad 300, the contour lines of the critical heat flux density can be represented. Outward offset compensation distance along the normal direction The shallow groove opening boundary 302 is obtained: In the formula: The shallow groove opening boundary is 302; This is the geometric offset calculation along the curve normal direction; To compensate for the assembly distance.

[0027] In one embodiment, the assembly compensation distance The depth can range from 30μm to 50μm, for example, 40μm. Through this compensation design, even if there is a lateral positional deviation within a predetermined range between the main control chip 200 and the silicon-based insulating pad 300 during the lamination process, the thick adhesive layer region 401 can still cover the high-heat area 202. The inner wall of the shallow groove 301 adopts a non-linear gradient slope that continuously transitions from the bottom of the groove to the shallow groove opening boundary 302. This slope smoothly connects to the bottom plane of the groove at the bottom position and smoothly connects to the second surface of the silicon-based insulating pad 300 at the shallow groove opening boundary 302. This avoids significant stress concentration at the bonding position between the silicon material and the insulating patch adhesive layer 400 in conventional right-angle grooves. The maximum depth of the shallow groove 301... Total thickness of silicon-based insulating pad 300 satisfy: Accordingly, the thickness of the silicon material retained above the shallow groove 301 The proportion of the total thickness of the 300mm silicon-based insulating pad is: The aforementioned depth range provides sufficient local thermal resistance increment for the thick adhesive layer region 401, while also allowing the silicon-based insulating pad 300 to retain the structural strength required to support the bonding operations of the memory chip stack layer 500 and the metal leads 600.

[0028] Encapsulation component examples In this embodiment, the packaging substrate 100 is a high-density interconnect resin substrate, and the main control chip 200 has an external dimension of 10.0mm × 10.0mm and a thickness of 150μm. The main control chip 200 is connected to the packaging substrate 100 via flip-chip bonding metal bumps 201; the external solder balls 101 on the bottom of the packaging substrate 100 are used to connect to an external circuit board. The silicon-based isolation pad 300 is a single-crystal silicon pad with a total thickness of [missing information]. The diameter is 100 μm, and the thermal conductivity is 150 W / (m·K). The maximum depth of the shallow groove 301 on the second surface of the silicon-based insulating pad 300 is... If it is 18μm, then: At this point, the thickness of the silicon material remaining above the shallow groove 301 is: The proportion of residual silicon material thickness to the total thickness of the 300mm silicon-based insulating pad is: This proportion falls within the range of 78% to 85%. The insulating patch adhesive layer 400 uses a modified epoxy resin adhesive with a thermal conductivity of 0.5 W / (m·K). The thickness of the thin adhesive layer region 402... The maximum depth of the shallow groove 301 is 6μm. The thickness is 18 μm, therefore, the maximum thickness of the thick adhesive layer region 401 is... for: Under the same effective heat transfer area, the vertical thermal resistance ratio of the thick adhesive layer region 401 to the thin adhesive layer region 402 is: That is, the vertical thermal resistance of the thick adhesive layer region 401 is approximately four times that of the corresponding vertical thermal resistance of the thin adhesive layer region 402. In this embodiment, the shallow groove opening boundary 302 is determined based on the equivalent trajectory of the critical heat flux density on the back of the main control chip 200. Let the critical heat flux density threshold be... The threshold is 0.38 W / mm, and a 40 μm normal bias is applied around the closed isopleth trajectory formed by this threshold to form the shallow groove opening boundary 302. The maximum tangent angle of the slope of the shallow groove 301 can be 35°, and the slope transitions continuously from the bottom of the groove to the shallow groove opening boundary 302. The memory chip stack layer 500 includes eight layers of non-volatile memory dies stacked in a staggered, stepped manner. Each memory die is fixed to the first surface of the silicon-based isolation pad 300 by an insulating adhesive material and electrically connected to the packaging substrate 100 by a metal lead 600. The molding compound 700 is an epoxy resin molding compound that encapsulates the packaging substrate 100, the main control chip 200, the insulating patch adhesive layer 400, the silicon-based isolation pad 300, the memory chip stack layer 500, and the metal lead 600.

[0029] Configuration Method Implementation Examples The aforementioned three-dimensional storage packaging component can be formed according to the following method. Step S101: Obtain the layout power consumption distribution of the main control chip 200, the thermal conductivity of the main control chip 200, the thermal conductivity of the silicon-based isolation pad 300, the thermal conductivity of the insulating adhesive layer 400, the safe temperature conditions of the storage chip stack layer 500, and the assembly positioning tolerance between the main control chip 200 and the silicon-based isolation pad 300. Step S102: Establish a steady-state heat conduction model based on the layout power consumption distribution of the main control chip 200, and solve for the temperature field and heat flux density vector on the back of the main control chip 200. Step S103: Determine the critical heat flux density threshold based on the safe operating temperature of the memory chip stack layer 500. Extraction satisfies: The closed contour line Step S104: Based on the assembly positioning tolerance, draw the closed contour line. Outward offset compensation distance Step S105: Photolithography and etching are performed on the second surface of the silicon-based insulating pad 300 to form the shallow groove 301. During processing, reactive ion etching, wet etching, grayscale photolithography combined with dry etching, or multi-pass progressive photolithography combined with isotropic etching can be used to create a continuously transitioning nonlinear gradient slope in the shallow groove 301. Step S106: The maximum depth of the shallow groove 301 is determined based on the thermomechanical simulation results of the packaged component. Under reflow soldering temperature load, the outer corner of the packaging substrate 100, the edge junction of the main control chip 200 and the silicon-based isolation pad 300, and the top corner of the memory chip stack layer 500 are selected as deformation control nodes. Let the first... The vertical displacement of each deformation control node is The average vertical displacement of all deformation control nodes is The maximum warpage can then be expressed as: In the formula: This represents the maximum warpage. This is the set of deformation control nodes; For the first Vertical displacement of each deformation control node; This represents the average vertical displacement of each deformation control node. The maximum depth of the shallow groove 301 is controlled by... To satisfy simultaneously: .as well as: Step S107: Apply an insulating adhesive layer 400 to the back of the main control chip 200, and press the main control chip 200 onto the silicon-based isolation pad 300. During the pressing process, the insulating adhesive layer 400 fills the shallow groove 301, forming a thick adhesive layer area 401; the insulating adhesive layer 400 outside the shallow groove 301 forms a thin adhesive layer area 402. The insulating adhesive layer 400 is then cured. Step S108: Form a memory chip stack layer 500 on the first surface of the silicon-based isolation pad 300; electrically connect the memory chip stack layer 500 to the packaging substrate 100 via metal leads 600; finally, complete the molding process using molding compound 700, and form external solder balls 101 on the bottom of the packaging substrate 100. Through the above structure and configuration method, a thick adhesive layer region 401 with local high thermal resistance is formed above the high heat generation area 202 of the main control chip 200, while a thin adhesive layer region 402 is retained at the edge of the main control chip 200. This allows heat to form a heat transfer path of "vertical isolation of the high heat generation area, introduction of the edge area into the pad, and peripheral conduction of the silicon-based isolation pad", thereby reducing the risk of local overheating of the memory chip stack layer 500, especially the bottom memory die close to the main control chip 200.

[0030] Application Example 1: Intelligent Connected Vehicle Autonomous Driving Main Control and Environmental Data Recording and Storage Component The three-dimensional storage packaging component of this embodiment is applied to the core data storage module of the vehicle-mounted autonomous driving domain controller. This module can be located in the area between the engine compartment and the passenger compartment and is suitable for operation within an ambient temperature range of -40°C to 105°C. The main control chip 200 is used for real-time processing of multi-camera image data, LiDAR point cloud data, and vehicle control data; the storage chip stack layer 500 includes eight layers of non-volatile storage dies stacked in a staggered, ladder-like manner.

[0031] The silicon-based insulating pad 300 is a monocrystalline silicon pad with a total thickness H of 100 μm. The maximum depth D of the shallow groove 301 is 18 μm, accounting for 18% of the total thickness. The silicon material thickness retained above the shallow groove 301 is 82 μm. The thickness T1 of the thin adhesive layer region 402 is 6 μm, and the thickness T2 of the thick adhesive layer region 401 at the deepest point of the shallow groove 301 is 24 μm. The maximum tangent angle of the nonlinear gradient slope of the shallow groove 301 is 35°, and the radius of the transition arc between the groove bottom and the gradient slope is 8 μm.

[0032] The high-heat area 202 of the main control chip 200 may correspond to the area where the central processing core, image processing unit, or high-speed data exchange unit is located. The shallow groove opening boundary 302 is determined based on the isopleth trajectory line of the critical heat flux density corresponding to the high-heat area 202, and may be formed by offsetting outward by 40μm along the normal direction of the isopleth trajectory line to cover the high-heat area 202 within the assembly positioning error range.

[0033] Since the thickness of the thick adhesive layer region 401 is four times that of the thin adhesive layer region 402, under the condition of using the same insulating adhesive material and having a comparable effective heat transfer area, the vertical thermal resistance of the thick adhesive layer region 401 increases accordingly, thereby suppressing the direct transfer of heat from the high-heat region 202 to the memory chip stack layer 500. Heat can diffuse towards the edge region along the in-plane direction of the main control chip 200, and enter the silicon-based isolation pad 300 via the thin adhesive layer region 402, and then be conducted to the periphery via the silicon-based isolation pad 300. The retained 82μm silicon material layer also provides structural support for the mounting of the eight-layer memory chips and the bonding of the metal leads 600. During thermal cycling and mechanical reliability verification, the 35° continuous gradient slope and 8μm arc transition structure help reduce the risk of shear stress concentration at the interface between the silicon-based isolation pad 300 and the insulating adhesive layer 400.

[0034] Application Example 2: High-Density Enterprise-Grade Solid-State Storage Components for Cloud Computing Data Centers This embodiment applies to a high-speed solid-state storage accelerator card for data center rack servers. The main control chip 200 operates continuously under conditions of continuous random read / write, garbage collection, error correction calculation, and high-speed interface communication. The storage chip stack layer 500 includes sixteen layers of non-volatile storage dies to increase storage capacity density within a limited package thickness.

[0035] The total thickness H of the silicon-based insulating pad 300 is 120 μm, and the maximum depth D of the shallow groove 301 is 24 μm, accounting for 20% of the total thickness; the thickness of the silicon material retained above the shallow groove 301 is 96 μm. The thickness T1 of the thin adhesive layer region 402 is 8 μm, and the maximum thickness T2 of the thick adhesive layer region 401 is 32 μm. The maximum tangent angle of the nonlinear gradient slope of the shallow groove 301 is 42°, and smooth transition arcs with a radius of curvature of 6 μm are respectively set at the bottom of the groove and the edge of the opening.

[0036] In this embodiment, the 32μm thick adhesive layer region 401 forms a relatively high local vertical thermal resistance above the high-heat-generating area 202 of the main control chip 200, causing heat in this region to preferentially diffuse to the peripheral area of ​​the main control chip 200. The peripheral 8μm thin adhesive layer region 402 forms a relatively low thermal resistance heat conduction channel, allowing the heat diffused laterally to be introduced into the silicon-based insulating pad 300 and further conducted to the heat dissipation structure around the component.

[0037] Furthermore, the depth of the shallow groove 301 is controlled at 20% of the total thickness of the silicon-based insulating pad 300, which allows for the formation of a thicker adhesive layer 401 while retaining a 96μm silicon material carrier layer to meet the structural support requirements of sixteen-layer memory chip stacking, wire bonding, and subsequent molding processes. The continuous gradient slope and the rounded transition structure at both ends can mitigate local stress concentration caused by thermal expansion mismatch between different materials under reflow soldering temperature loads and long-term high-temperature operation conditions, thereby reducing the risk of interface delamination and microcrack formation.

[0038] Application Example 3: Storage Unit for Edge Computing Controllers in Industrial Automation and Robotics This embodiment applies to an embedded motion control board inside the joint of an industrial robot in a smart manufacturing production line. In this application scenario, in addition to being subjected to periodic thermal pulses caused by motor drive, the main control chip 200 may also be subjected to high-frequency vibrations and impact loads caused by the movement of stamping equipment or robotic arms.

[0039] The total thickness H of the silicon-based insulating pad 300 is 90 μm, and the maximum depth D of the shallow groove 301 is 15 μm, accounting for 16.7% of the total thickness; the thickness of the silicon material retained above the shallow groove 301 is 75 μm. The thickness T1 of the thin adhesive layer region 402 is 5 μm, and the maximum thickness T2 of the thick adhesive layer region 401 is 20 μm. The maximum tangent angle of the nonlinear gradient slope of the shallow groove 301 is 30°, and the radius of the transition arc is 10 μm.

[0040] For asymmetrically distributed heat-generating units in industrial multi-core processors, a critical heat flux density contour line can be obtained based on the heat flux density distribution on the back of the main control chip 200. This contour line is then offset outward by 40 μm along the normal direction to form a shallow groove opening boundary 302. Thus, the two-dimensional contour of the shallow groove 301 can cover all major pulsed heat-generating points, while retaining a necessary area of ​​thin adhesive layer region 402 in the low-heat-generating edge region.

[0041] The 30° gradual slope and 10μm circular arc transition structure create a continuous contact interface between the insulating patch adhesive layer 400 and the silicon-based insulating gasket 300, which helps to disperse the interfacial shear stress generated by vibration loads and temperature cycling loads. The 75μm residual silicon material layer can reduce the decrease in the flexural stiffness of the gasket caused by local grooving, and improve the structural stability of the module under vibration and impact conditions.

[0042] Application Example 4: High-speed data buffer storage component for outdoor radio frequency unit of communication base station This embodiment applies to a high-speed data buffer storage component in an outdoor radio frequency transceiver unit of a communication tower. This component can operate within a sealed metal enclosure and is suitable for withstanding the transient high load conditions of the main control chip caused by sudden large data traffic, typically ranging from 70°C to 85°C, under relatively high ambient temperatures.

[0043] The total thickness H of the silicon-based insulating pad 300 is 100 μm, and the maximum depth D of the shallow groove 301 is 20 μm, accounting for 20% of the total thickness; the thickness of the silicon material retained above the shallow groove 301 is 80 μm. The thickness T1 of the thin adhesive layer region 402 is 7 μm, and the maximum thickness T2 of the thick adhesive layer region 401 is 27 μm. The maximum tangent angle of the nonlinear gradient slope of the shallow groove 301 is 38°, and the radius of the transition arc is 7 μm.

[0044] At higher ambient temperatures, the 27μm thick adhesive layer region 401 can increase the local vertical thermal resistance between the high-heat region 202 of the main control chip 200 and the silicon-based isolation pad 300, thereby reducing the tendency for heat to be directly concentrated and transferred to the underlying memory chip above. Heat from the edge region of the main control chip 200 can then enter the silicon-based isolation pad 300 through the 7μm thin adhesive layer region 402 and be released to the outside of the component in conjunction with the external metal heat dissipation structure.

[0045] The shallow groove 301 has a maximum depth of 20μm, which ensures the formation of a thermally differentiated interface while controlling the local adhesive filling volume. Combined with a 38° continuous gradient slope and a 7μm arc transition structure, it can reduce stress concentration caused by adhesive layer volume changes under high temperature and high humidity storage, moisture-absorbing reflow soldering, and thermal cycling conditions, thereby reducing the risk of interface peeling inside the molded body.

[0046] Application Example 5: Rail Transit Vehicle Signal Safety Computer and Black Box Storage Module This embodiment applies to a disaster recovery storage module in a rail transit vehicle operation monitoring system, such as a non-volatile storage unit for a train operation recording device or a signal safety computer. This module can withstand low-frequency mechanical vibrations transmitted through wheel-rail contact, intermittent temperature changes within the electrical cabinet, and thermal loads generated during continuous operation.

[0047] The total thickness H of the silicon-based insulating pad 300 is 110 μm, and the maximum depth D of the shallow groove 301 is 21 μm, accounting for 19.1% of the total thickness; the thickness of the silicon material retained above the shallow groove 301 is 89 μm. The thickness T1 of the thin adhesive layer region 402 is 6 μm, and the maximum thickness T2 of the thick adhesive layer region 401 is 27 μm. The maximum tangent angle of the nonlinear gradient slope of the shallow groove 301 is 36°, and the radius of the transition arc is 9 μm.

[0048] In this embodiment, the shallow groove opening boundary 302 is determined based on the equivalent heat flux density trajectory corresponding to the high-heat area 202 of the main control chip 200. This allows the thick adhesive layer region 401 to form local thermal resistance isolation for the high-heat area 202, while ensuring effective thermal conductivity between the edge region of the main control chip 200 and the silicon-based insulating pad 300 through the thin adhesive layer region 402. This reduces the possibility of repeated thermal stress on adjacent memory chips caused by local hot spots of the main control chip 200 during long-term operation.

[0049] A 36° non-linear gradient slope and a 9μm circular arc transition structure are used to maintain a continuous transition at the interface between the silicon-based insulating pad 300 and the insulating patch adhesive layer 400, reducing local shear stress concentration caused by long-term low-frequency vibration, temperature fluctuations, and material thermal expansion mismatch. A 19.1% groove depth ratio retains an 89μm silicon material layer while forming the thick adhesive layer region 401, which helps control warpage during the curing, reflow soldering, and long-term service of the packaged components, and maintains the connection reliability of the memory chip stack layer 500 and the metal leads 600.

Claims

1. A three-dimensional storage encapsulation component with a heat flux adaptive barrier interface, characterized in that, The package includes a packaging substrate, a main control chip, an insulating adhesive layer, a silicon-based insulating pad, a memory chip stack, and a molding compound. The main control chip is flip-chip bonded to the main surface of the packaging substrate. The silicon-based insulating pad is disposed on the back side of the main control chip, having a first surface for supporting the memory chip stack and a second surface facing the main control chip. The second surface has a shallow groove, the opening boundary of which is an irregular smooth closed curve adapted to the heat flux density distribution on the back side of the main control chip, and the orthogonal projection of the shallow groove onto the main control chip covers the high-heat-generating area of ​​the main control chip. The insulating adhesive layer is... A shallow groove is filled between the main control chip and the silicon-based isolation pad to form a thick adhesive layer area at the location corresponding to the high-heat area and a thin adhesive layer area outside the shallow groove; the inner wall of the shallow groove is a non-linear gradient slope that continuously transitions from the bottom of the groove to the edge of the opening; the memory chip stack layer is disposed on the first surface and electrically connected to the packaging substrate; wherein, the thick adhesive layer area and the thin adhesive layer area constitute a heat flow adaptive barrier interface, so that the heat of the high-heat area diffuses laterally to its edge area through the main control chip, and enters the silicon-based isolation pad through the thin adhesive layer area and is then conducted to the periphery of the silicon-based isolation pad.

2. The three-dimensional storage encapsulation component with a heat flow adaptive barrier interface according to claim 1, characterized in that, The thermal conductivity of the insulating patch adhesive layer is less than 1.5 W / (m·K), the silicon-based insulating pad is a monocrystalline silicon pad, and the thermal conductivity of the silicon-based insulating pad is greater than 130 W / (m·K).

3. The three-dimensional storage encapsulation component with a heat flow adaptive barrier interface according to claim 1, characterized in that, The irregular smooth closed curve is formed by offsetting the critical heat flux density contour line on the back of the main control chip outward along the normal direction by a preset assembly compensation distance, which is 30μm to 50μm.

4. The three-dimensional storage encapsulation component with a heat flow adaptive barrier interface according to claim 1, characterized in that, The total thickness of the silicon-based insulating pad is 80 μm to 120 μm, the maximum depth of the shallow groove is 15% to 22% of the total thickness of the silicon-based insulating pad, and the thickness of the silicon material retained above the shallow groove is 78% to 85% of the total thickness of the silicon-based insulating pad.

5. The three-dimensional storage encapsulation component with a thermally adaptive barrier interface according to claim 1 or 4, characterized in that, The thickness of the thin adhesive layer region is 5 μm to 10 μm, and the thickness of the thick adhesive layer region is 20 μm to 32 μm.

6. The three-dimensional storage encapsulation component with a heat flow adaptive barrier interface according to claim 1, characterized in that, The nonlinear gradient slope is tangent to the bottom plane of the shallow groove at the bottom of the groove and tangent to the second surface at the opening edge of the shallow groove; the bottom of the shallow groove and the nonlinear gradient slope are connected by a first arc surface, and the nonlinear gradient slope and the second surface are connected by a second arc surface, wherein the radii of curvature of the first arc surface and the second arc surface are both greater than 5μm.

7. The three-dimensional storage encapsulation component with a heat flow adaptive barrier interface according to claim 1, characterized in that, The memory chip stack layer includes multiple non-volatile memory dies stacked in a staggered, stepped manner; each of the non-volatile memory dies is fixed to the first surface of the silicon-based isolation pad by an insulating adhesive film and electrically connected to the packaging substrate by metal leads; The molding compound covers the packaging substrate, main control chip, insulating patch adhesive layer, silicon-based isolation pad, and memory chip stack layer.

8. A configuration method for a three-dimensional storage packaging component with a thermally adaptive barrier interface, characterized in that, include: The process involves obtaining the layout power consumption distribution of the main control chip, the material thermal parameters of the main control chip, the material thermal parameters of the silicon-based isolation pad, and the assembly positioning tolerance between the main control chip and the silicon-based isolation pad. Based on the layout power consumption distribution and material thermal parameters, a steady-state heat conduction model of the main control chip is established, and the heat flux density distribution on the back of the main control chip is solved. A critical heat flux density threshold corresponding to the safe temperature of the memory chip is determined, and a closed isopleth trajectory line where the heat flux density on the back of the main control chip equals the critical heat flux density threshold is extracted. Based on the assembly positioning tolerance, the closed isopleth trajectory line is expanded and compensated to obtain the opening profile of the shallow groove. A two-phase mechanical coupling model of the silicon-based isolation pad and the insulating patch adhesive layer is established, and the nonlinear gradient slope and maximum depth of the shallow groove are determined under the groove volume constraint. Based on the opening profile, the nonlinear gradient slope, and the maximum depth, a shallow groove is formed on the second surface of the silicon-based isolation pad. An insulating adhesive layer is placed on the back of the main control chip, filling the shallow groove and curing it to form a thick adhesive layer area corresponding to the high heat generation area of ​​the main control chip and a thin adhesive layer area corresponding to the edge area of ​​the main control chip. And a memory chip stack layer is formed on the first surface of the silicon-based isolation pad, and then encapsulation is completed.

9. The configuration method of the three-dimensional storage packaging component with a thermally adaptive barrier interface according to claim 8, characterized in that, The determination of the nonlinear gradient slope and maximum depth of the shallow groove includes: under simulated reflow soldering temperature load, obtaining the outer corner vertex of the packaging substrate, the edge junction point of the main control chip and the silicon-based isolation pad, and the deformation control node at the highest corner of the memory chip stack layer; and determining the maximum depth of the shallow groove with the vertical displacement of the deformation control node not exceeding a preset warping threshold as a constraint; wherein the preset warping threshold is 75μm.

10. The configuration method of the three-dimensional storage packaging component with a thermally adaptive barrier interface according to claim 8, characterized in that, Forming the shallow groove includes: converting the opening profile into photomask data; forming a photoresist pattern corresponding to the photomask data on the second surface of the silicon-based isolation pad; and forming a shallow groove with an irregular smooth closed curve and a nonlinear gradient slope in the silicon-based isolation pad by using reactive ion etching, wet etching, grayscale photolithography combined with dry etching, or multi-pass progressive photolithography combined with isotropic etching processes.

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