PIP capacitor structure based on nord flash process and method of manufacturing the same

Abstract

This invention provides a PIP capacitor structure based on NORD flash memory technology and its manufacturing method. The structure includes: a substrate and an isolation structure; a first conductive structure located on the isolation structure and defining a trench region; an insulating dielectric component located on the trench sidewall; and a second conductive structure filling the trench. The manufacturing method includes: forming the isolation structure in the substrate; forming a stack on the isolation structure; patterning the stack to form a trench; forming an insulating dielectric component on the trench sidewall; and filling the trench with a second conductive material. This invention utilizes the self-alignment characteristics of the NORD process, eliminating the need for an additional photomask, thus reducing manufacturing costs. Furthermore, the isolation structure effectively reduces parasitic capacitance to the substrate, resulting in high density and high reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a PIP capacitor structure based on NORD flash memory technology and its manufacturing method. Background Technology

[0002] In mixed-signal circuit design, polysilicon-insulator-polysilicon (PIP) capacitors are widely used in analog circuit modules, such as filters and analog-to-digital converters (ADCs), due to their advantages such as good linearity and low voltage coefficient. Traditional PIP capacitors typically consist of two polysilicon plates sandwiched between them and a dielectric layer.

[0003] However, existing PIP capacitor structures and their manufacturing processes have the following significant drawbacks in practical applications, limiting their use in advanced process nodes and low-cost chip designs:

[0004] First, there's the issue of photomask layers and manufacturing costs. Traditional PIP capacitor structures typically require a two-layer polysilicon process, with each polysilicon layer needing its own photomask and etching steps to define the pattern. To form specific electrode structures or interconnects, additional masks are often needed, directly leading to increased manufacturing costs and longer production cycles.

[0005] Secondly, there is the issue of parasitic capacitance. Conventional PIP capacitors typically employ a large-area planar stacked structure, with the lower electrode (Poly I) directly resting on the field oxide or shallow trench isolation layer. This close proximity to the semiconductor substrate and the large area directly opposite it contributes to the parasitic capacitance. When the capacitor area is large, the parasitic capacitance of the lower electrode to the substrate becomes very significant; according to measured data, this parasitic capacitance can typically account for 10% to 20% of the total capacitance. Excessive parasitic capacitance can introduce substrate noise into the capacitor or leak signals to the substrate, severely affecting the circuit's frequency response characteristics and signal accuracy.

[0006] In view of the above problems, the industry urgently needs a capacitor structure that can reduce manufacturing costs, eliminate the need for additional photomasks, and effectively reduce parasitic capacitance to the substrate, especially a solution that is fully compatible with existing NORD Flash (self-aligned gate flash memory) manufacturing processes. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a PIP capacitor structure based on NORD flash memory technology and its manufacturing method, so as to solve the technical problems of increased cost due to the need for additional photomasks in the manufacturing of existing PIP capacitors, and the large parasitic capacitance between the lower electrode and the substrate.

[0008] To achieve the above and other related objectives, the present invention provides a PIP capacitor structure based on NORD flash memory technology, comprising:

[0009] Substrate;

[0010] An isolation structure is located within the substrate;

[0011] A first conductive structure is located on the isolation structure. The first conductive structure includes two spaced-apart portions, with a trench region defined between the two portions.

[0012] An insulating dielectric assembly is located on the sidewall surface of the trench region;

[0013] A second conductive structure is filled in the trench area and isolated from the first conductive structure by the insulating dielectric component;

[0014] The first conductive structure, the insulating dielectric component, and the second conductive structure constitute the PIP capacitor structure; the first conductive structure serves as the first electrode of the PIP capacitor structure, the second conductive structure serves as the second electrode of the PIP capacitor structure, and the insulating dielectric component serves as the capacitor dielectric of the PIP capacitor structure.

[0015] Preferably, an insulating layer is further disposed below the first conductive structure, and the first conductive structure and the insulating layer together form a stepped structure; the bottom of the second conductive structure extends to below the top surface of the isolation structure; the insulating dielectric assembly covers the sidewalls of the first conductive structure, the sidewalls of the insulating layer, and the groove surface of the isolation structure formed by the extension of the second conductive structure.

[0016] Preferably, the insulating dielectric assembly is a multilayer composite structure, comprising: a protective sidewall attached to the sidewall of the first conductive structure; a dielectric spacer attached to the side of the protective sidewall opposite to the first conductive structure; and a tunneling dielectric layer located between the dielectric spacer layer and the second conductive structure.

[0017] Preferably, the capacitor unit, which is composed of the first conductive structure, the insulating dielectric component and the second conductive structure, is arranged in a direction perpendicular to the surface of the substrate, and the capacitor unit is electrically isolated from the substrate through the isolation structure at the bottom.

[0018] Preferably, the material of the first conductive structure includes control gate polysilicon, and the material of the second conductive structure includes word line polysilicon.

[0019] Preferably, the isolation structure is a shallow trench isolation structure.

[0020] Preferably, the insulating stack comprises a silicon oxide-silicon nitride-silicon oxide stack.

[0021] This invention also provides a method for manufacturing a PIP capacitor structure based on NORD flash memory technology, comprising:

[0022] Step 1: Provide a substrate and form an isolation structure in the substrate;

[0023] Step 2: Form a stacked structure on the isolation structure, the stacked structure including an insulating layer and a first conductive material layer stacked sequentially from bottom to top;

[0024] Step 3: Pattern the stacked structure to form a first conductive structure and an insulating layer pattern below it, and form trenches between the first conductive structures to expose the insulating structure.

[0025] Step 4: Form an insulating dielectric assembly on the sidewall surface of the trench;

[0026] Step 5: Fill the trench with a second conductive material to form a second conductive structure;

[0027] The first conductive structure, the insulating dielectric component, and the second conductive structure together constitute the PIP capacitor structure.

[0028] Preferably, in step two, the stacked structure further includes a hard mask layer located above the first conductive material layer; in step three, the patterning process of the stacked structure includes: forming an opening in the hard mask layer; forming a first sidewall on the sidewall of the opening; and etching the first conductive material layer using the first sidewall as a mask to define the upper width of the trench.

[0029] Preferably, in step three, after patterning the stacked structure, the exposed isolation structure is further over-etched so that the bottom of the trench extends below the top surface of the isolation structure.

[0030] Preferably, in step four, forming the insulating dielectric assembly includes: sequentially forming a second sidewall and a third sidewall on the sidewall of the trench; using the third sidewall as a mask, etching the exposed isolation structure to form a groove located inside the isolation structure; and forming a tunneling dielectric layer covering the surface of the third sidewall and the groove.

[0031] Preferably, in step five, filling the second conductive material includes: depositing polycrystalline silicon material to fill the trench, and planarizing the polycrystalline silicon material by a chemical mechanical polishing process until the mask layer structure covering the first conductive structure is exposed.

[0032] Preferably, the method further includes step six: removing the hard mask layer, retaining the first sidewall, and using the second conductive structure, the first sidewall, and the insulating dielectric assembly as a mask, etching the first conductive structure to pattern the first conductive structure into independent capacitor plates.

[0033] Preferably, the manufacturing steps of the PIP capacitor structure are performed simultaneously with the manufacturing steps of the NORD flash memory cell on the substrate; wherein, the first conductive structure and the control gate of the NORD flash memory cell are formed simultaneously from the same first conductive material layer, and the second conductive structure and the word line of the NORD flash memory cell are formed simultaneously from the same second conductive material layer.

[0034] As described above, the PIP capacitor structure and its manufacturing method based on NORD flash memory technology of the present invention have the following beneficial effects:

[0035] This invention offers significant advantages at the photomask level. Only trenches need to be defined in the control gate layer of the NORD manufacturing process; subsequent structures are formed using self-aligned processes, eliminating the need for additional photomasks and thus reducing manufacturing costs. Secondly, based on the BulkSTI isolation structure and vertically arranged electrode design, the PIP capacitors are effectively isolated from the substrate, significantly reducing parasitic capacitance to the substrate. This structure has a large process window, maintaining stable capacitance density even under critical dimension misalignment, and its breakdown voltage remains consistently above 20V, demonstrating excellent withstand voltage and reliability. Finally, because this structure is fully compatible with existing NORD Flash processes, it facilitates the integration of high-density PIP capacitors in mixed-signal circuit designs. Attached Figure Description

[0036] Figure 1 The diagram shows the manufacturing process of the PIP capacitor structure based on NORD flash memory technology according to the present invention.

[0037] Figure 2 The diagram shown is a cross-sectional view of the isolation structure formed in the manufacturing method of the present invention.

[0038] Figure 3 The diagram shows a cross-sectional structure after the hard mask opening is formed in the manufacturing method of the present invention.

[0039] Figure 4 The diagram shows a cross-sectional structure after the first sidewall is formed in the manufacturing method of the present invention.

[0040] Figure 5 The diagram shows a cross-sectional structure after the grooves are etched in the manufacturing method of the present invention.

[0041] Figure 6The diagram shown is a cross-sectional view of the insulating dielectric component and the second conductive structure formed in the manufacturing method of the present invention.

[0042] Figure 7 The diagram shown is a cross-sectional view of the PIP capacitor structure based on NORD flash memory technology of the present invention.

[0043] Figure 8 The diagram shown is a planar layout schematic of the PIP capacitor structure based on NORD flash memory technology of the present invention.

[0044] Figure 9 The diagram shows the breakdown voltage statistical distribution of the PIP capacitor structure of the present invention.

[0045] Figure 10 The diagram shows a comparison of the capacitance characteristics of the PIP capacitor structure of the present invention before and after high-voltage stress testing. Detailed Implementation

[0046] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] A PIP capacitor structure based on NORD flash memory technology, such as Figure 7 As shown, it includes:

[0048] Substrate;

[0049] The isolation structure 101 is located in the substrate;

[0050] The first conductive structure 103 is located on the isolation structure 101. The first conductive structure 103 includes two parts spaced apart, and a trench region is defined between the two parts.

[0051] Insulating dielectric assembly, located on the sidewall surface of the trench region;

[0052] The second conductive structure 109 is filled in the trench area and is isolated from the first conductive structure 103 by an insulating dielectric component;

[0053] The first conductive structure 103, the insulating dielectric component, and the second conductive structure 109 constitute a PIP capacitor structure. The first conductive structure 103 serves as the first electrode of the PIP capacitor structure, the second conductive structure 109 serves as the second electrode of the PIP capacitor structure, and the insulating dielectric component serves as the capacitor dielectric of the PIP capacitor structure.

[0054] In some embodiments, the substrate may include a bulk semiconductor substrate, which may comprise elemental semiconductors such as crystalline silicon, diamond, or germanium; compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); or alloy semiconductors such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide (GaInAsP), or combinations thereof. Alternatively, the substrate may be a semiconductor-on-insulator (SOI) structure. In SOI embodiments, the substrate includes an operating substrate, a buried oxide layer (BOX) on the operating substrate, and a semiconductor layer on the buried oxide layer. The semiconductor layer may be silicon, germanium, silicon germanium, or any of the aforementioned compound / alloy semiconductor materials. The SOI substrate may be fabricated by oxygen implantation isolation, wafer bonding, or other suitable methods. In other embodiments, the substrate may include a multilayer epitaxial structure, such as a germanium-silicon layer epitaxially grown on bulk silicon or a pure silicon layer epitaxially grown on bulk silicon. The epitaxial layer may be stressed to change properties such as carrier mobility. The substrate may also include various doping configurations depending on the design requirements (e.g., p-type substrate or n-type substrate), and the dopants may include p-type dopants (such as boron, boron difluoride) or n-type dopants (such as phosphorus, arsenic).

[0055] In some embodiments, an insulating stack 102 is further disposed below the first conductive structure 103, and the first conductive structure 103 and the insulating stack 102 together form a stepped structure; the bottom of the second conductive structure 109 extends to below the top surface of the isolation structure 101; the insulating dielectric assembly covers the sidewalls of the first conductive structure 103, the sidewalls of the insulating stack 102, and the groove surface of the isolation structure 101 formed by the extension of the second conductive structure 109.

[0056] In some embodiments, the insulating dielectric assembly is a multilayer composite structure, such as... Figure 6As shown, the structure includes: a protective sidewall 106 attached to the sidewall of the first conductive structure 103; a dielectric spacer layer 107 attached to the side of the protective sidewall 106 facing away from the first conductive structure 103; and a tunneling dielectric layer 108 located between the dielectric spacer layer 107 and the second conductive structure 109. The protective sidewall 106 can be formed using a high-temperature oxidation process to repair lattice damage caused by etching of the first conductive structure 103; the dielectric spacer layer 107 can be made of silicon nitride or silicon oxide, formed by chemical vapor deposition (CVD), serving as the primary isolation dielectric; and the tunneling dielectric layer 108 can be a silicon oxide layer formed by thermal oxidation or atomic layer deposition (ALD). This multilayer composite dielectric structure exhibits a high breakdown voltage (BV), with measured data showing that its breakdown voltage remains stable above 20 volts (V) over a long period, and no significant capacitance drift was observed after high-voltage stress testing, ensuring the reliability of the device.

[0057] In some embodiments, the capacitor cells, consisting of a first conductive structure 103, insulating dielectric components (106, 107, 108), and a second conductive structure 109, are arranged in a direction perpendicular to the substrate surface, and the capacitor cells are electrically isolated from the substrate by the bottom isolation structure 101. Figure 8 The diagram shows a schematic layout of the PIP capacitor structure. This layout is based on a large-area shallow trench isolation (Bulk STI, i.e., isolation structure 101) region on the substrate. The longitudinally extending strip structures (corresponding to the FLGT layer in the diagram, i.e., the first conductive structure 103) define the main outline of the first conductive structure 103, exhibiting a regularly parallel array of finger-like structures. The longitudinally extending first conductive structure 103 is formed within the FLGT strips; since the first conductive structure 103 comprises two spaced-apart portions, the resulting longitudinally extending trenches are filled with a second conductive structure 109 (although...). Figure 8The boundary between the first conductive structure 103 and the second conductive structure 109 is not directly filled with color within the FLGT strip. To achieve independent control and read / write of electrical signals, the first conductive structure 103 (corresponding to the control gate CG) extends laterally beyond the boundary of the aforementioned FLGT strip through the CGCT layer, and is led out by the first contact hole array (CT of CG) arranged at both ends, converging into one electrode of the capacitor. At the same time, the second conductive structure 109 (corresponding to the word line WL) located within the aforementioned FLGT strip trench is led out through the second contact hole array (CT of WL) located above the trench region, converging into the other electrode of the capacitor. This interdigitated or comb-like layout design, combined with the aforementioned deep trench vertical structure, maximizes the effective opposing sidewall area per unit chip area, thereby significantly improving the capacitance value. Combining this compact micro-pitch design with the vertical sidewall capacitor structure, the capacitance density of this device can reach approximately 1.2 femtofarads per square micrometer (fF / um²). This capacitance density is comparable to that of a conventional planar PIP capacitor (typically 0.5~2 fF / um²), meeting the high-density capacitance requirements of mixed-signal circuits. More importantly, because the bottom of the finger array rests entirely on the thicker isolation structure 101 (Bulk STI), the wide-area coupling between the lower electrode (first conductive structure 103) and the substrate is effectively severed. Furthermore, the electrode design with vertically arranged sidewalls significantly reduces parasitic capacitance, ensuring the purity of the circuit signal.

[0058] In some embodiments, the material of the first conductive structure 103 includes control gate polysilicon, and the material of the second conductive structure 109 includes word line polysilicon. Besides polysilicon, the materials of the conductive structures (103, 109) may also include amorphous silicon, doped polysilicon, metals (such as tungsten, copper, aluminum, titanium, tantalum), metal silicides (such as tungsten silicide, cobalt silicide, nickel silicide), metal nitrides (such as titanium nitride, tantalum nitride), or combinations thereof. Both the first conductive structure 103 and the second conductive structure 109 are arranged perpendicular to the substrate direction. Compared to horizontally arranged planar capacitors, this vertical architecture increases the relative area of ​​the two plates without increasing the chip footprint, thereby improving the capacitance per unit area.

[0059] In some embodiments, the isolation structure 101 is a shallow trench isolation structure. For example... Figures 2 to 7As shown, the upper region of the substrate forms the isolation structure 101. Besides shallow trench isolation (STI), the isolation structure 101 can also employ localized silicon oxide (LOCOS) or other suitable isolation techniques. For the STI structure, the filling material can include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicon glass (FSG), low-k dielectric materials, spin-on dielectric (SOD), or combinations thereof. The isolation structure 101 can include a liner layer, such as a silicon oxide liner grown by thermal oxidation. By providing a relatively thick shallow trench isolation structure 101 below the first electrode (first conductive structure 103), the direct electrical coupling path between the first electrode and the substrate can be effectively cut off, thereby significantly reducing parasitic capacitance and improving the high-frequency characteristics of the device.

[0060] In some embodiments, the insulating stack 102 comprises a silicon oxide-silicon nitride-silicon oxide stack. This insulating stack 102 (ONO) is typically used in NORD flash memory processes as a combination of a control gate coupling layer and a charge blocking layer. In capacitor structures, it not only elevates the first conductive structure 103 but also provides additional insulating protection using its multilayer dielectric properties. The insulating stack 102 can also be replaced with other forms of composite dielectric layers, such as a silicon oxide-silicon nitride-silicon oxide structure, or a stack containing high-k dielectric materials such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), etc.

[0061] A method for manufacturing a PIP capacitor structure based on NORD flash memory technology, the process flow diagram of which is shown below. Figure 1 As shown, it includes:

[0062] Step 1: Provide a substrate and form an isolation structure 101 in the substrate.

[0063] In some embodiments, such as Figure 2 As shown, a substrate is provided, and a thicker isolation structure 101 is formed on it. The steps for forming the isolation structure 101 typically include photolithography to define the active region and the isolation region, anisotropic dry etching to form deep trenches, deposition of insulating material (such as HDP oxide) to fill the vias, and chemical mechanical polishing (CMP) planarization.

[0064] Step 2: A stacked structure is formed on the isolation structure 101. The stacked structure includes an insulating layer 102 and a first conductive material layer 103 stacked sequentially from bottom to top.

[0065] In some embodiments, the stacked structure further includes a hard mask layer 104 located above the first conductive material layer 103, such as... Figure 3As shown. The insulating layer 102 can be an ONO structure, with a bottom oxide layer formed by thermal oxidation, a silicon nitride layer formed by low-pressure chemical vapor deposition (LPCVD), and a top oxide layer formed by oxidation or deposition. The first conductive material layer 103 is typically doped polycrystalline silicon. The material of the hard mask layer 104 can include silicon nitride (SiN), silicon oxynitride (SiON), or amorphous carbon (APF), and its thickness is adjusted to withstand subsequent CMP processes.

[0066] Step 3: Pattern the stacked structure to form a pattern of the first conductive structure 103 and the insulating layer 102 below it, and form trenches between the first conductive structures 103 to expose the isolation structure 101.

[0067] In some embodiments, patterning the stacked structure includes forming openings in the hard mask layer 104, such as... Figure 3 As shown; a first sidewall 105 is formed on the sidewall of the opening, as... Figure 4 As shown, the first conductive material layer 103 is etched using the first sidewall 105 as a mask to define the upper width of the trench. The first sidewall 105 is typically formed by isotropic deposition of silicon oxide or silicon nitride material, followed by an anisotropic dry etch-back process.

[0068] In some embodiments, after patterning the stacked structure, the exposed isolation structure 101 is further over-etched so that the bottom of the trench extends below the top surface of the isolation structure 101. For example... Figure 5 As shown, the bottom of the trench extends into the interior of the isolation structure 101. This over-etching step ensures complete electrical isolation between adjacent components and also increases the vertical depth of the subsequent filling of the second conductive structure 109, thereby increasing the effective capacitance area.

[0069] Step 4: Form an insulating dielectric assembly on the sidewall surface of the trench.

[0070] In some embodiments, forming an insulating dielectric assembly includes: sequentially forming a second sidewall (i.e., a protective sidewall 106) and a third sidewall (dielectric spacer layer 107) on the sidewall of the first conductive structure 103; then using this as a mask, etching the exposed isolation structure 101 to form a groove located inside the isolation structure 101; and forming a tunneling dielectric layer 108 covering the third sidewall (dielectric spacer layer 107) and the surface of the groove. Specifically, in Figure 6 As can be seen, the protective sidewall 106 and the dielectric spacer layer 107 protect the sidewalls of the first conductive structure 103 and the insulating layer 102, preventing lateral damage to the critical dielectric layer during the etching of the isolation structure 101. The tunneling dielectric layer 108 (e.g.) Figure 6(As shown) is typically a high-quality thermally oxidized layer. The protective sidewall 106, dielectric spacer layer 107, and tunneling dielectric layer 108 together serve as the main dielectric layer of the capacitor, and their quality directly determines the capacitor's withstand voltage characteristics.

[0071] Step 5: Fill the trench with a second conductive material to form a second conductive structure 109.

[0072] In some embodiments, filling the second conductive material includes: depositing polysilicon material to fill the trench and planarizing the polysilicon material by a chemical mechanical polishing process until the mask layer structure (i.e., hard mask layer 104) covering the first conductive structure 103 is exposed. Figure 6 The image shows the state after filling and planarization. At this point, the second conductive structure 109 forms a plug-like structure resembling an inverted trapezoid, tightly embedded in the trench surrounded by the first conductive structure 103. The deposition method can employ low-pressure chemical vapor deposition (LPCVD), with in-situ doping during the deposition process to reduce resistivity.

[0073] In some embodiments, a step six is ​​further included: removing the hard mask layer 104 and retaining the first sidewall 105. Subsequently, the underlying first conductive structure 103 is etched using the second conductive structure 109, the retained first sidewall 105, and the insulating dielectric components (106, 107, 108) together as a mask. This step is typically performed in a subsequent CGCT (Control Gate Contact) etching process. Figure 8 In the area covered by the CGCT layer, the control gate is not etched and is used for the subsequent formation of the contact (CT) of the first conductive structure 103; for the area not covered by the CGCT layer, a self-aligned technique is used to cut the continuous strip of polysilicon to form independent capacitor nodes, thereby achieving... Figure 7 The electrode isolation effect is shown. In this process, the retained first sidewall 105 provides additional protection for the top edge of the first conductive structure 103, ensuring the integrity of the etched morphology.

[0074] In some embodiments, the fabrication steps of the PIP capacitor structure are performed simultaneously with the fabrication steps of the NORD flash memory cell on the substrate; wherein, the first conductive structure 103 and the control gate of the NORD flash memory cell are formed simultaneously by the same first conductive material layer 103, and the second conductive structure 109 and the word line of the NORD flash memory cell are formed simultaneously by the same second conductive material layer. This integrated process means that during the fabrication of NORD Flash, only the capacitor region needs to be defined on the photolithography layout, without adding additional mask layers or additional deposition or etching equipment time. Compared to the traditional approach that requires adding a mask to fabricate a double-layer poly capacitor, this approach significantly reduces wafer manufacturing costs and simplifies the process flow.

[0075] To verify the performance advantages of the PIP capacitor structure described in this invention, the applicant conducted relevant electrical tests.

[0076] Please see Figure 9 The figure shows the statistical distribution of the breakdown voltage (BV) of the PIP capacitor structure. The horizontal axis represents the test point, and the vertical axis represents the breakdown voltage value. Because this embodiment uses composite insulating dielectric components (especially the protective sidewall 106, dielectric spacer layer 107, and high-quality tunneling dielectric layer 108) as the capacitor dielectric, excellent insulation performance is ensured. As shown in the data points, the breakdown voltage between the first conductive structure 103 and the second conductive structure 109 of this PIP capacitor structure is maintained stably above 20V for a long period, far exceeding the operating voltage of conventional analog circuits, meeting the withstand voltage requirements of high-voltage applications.

[0077] Please see Figure 10 The figure shows a comparison of the capacitance characteristics of the PIP capacitor structure before and after high-voltage stress (HV Stress) testing. To verify the long-term reliability of the device, a high-voltage stress of 15V was applied. As shown in the figure, comparing the C-V curves of the initial state (circled) and the state after applying 15V stress (squared), the two curves almost completely overlap, and no obvious capacitance drift or characteristic degradation was observed. This indicates that the device has high reliability, and the insulating dielectric component is not prone to charge trapping or dielectric damage under high field strength, ensuring stable operation over a long period of time. In summary, this invention achieves a high-density (approximately 1.2 fF / um²), low parasitic, high withstand voltage, and process-stable PIP capacitor structure by reusing the NORD Flash process without adding a photomask.

[0078] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0079] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A PIP capacitor structure based on NORD flash memory technology, characterized in that, include: Substrate; An isolation structure is located within the substrate; A first conductive structure is located on the isolation structure. The first conductive structure includes two spaced-apart portions, with a trench region defined between the two portions. An insulating dielectric assembly is located on the sidewall surface of the trench region; A second conductive structure is filled in the trench area and isolated from the first conductive structure by the insulating dielectric component; The first conductive structure, the insulating dielectric component, and the second conductive structure constitute the PIP capacitor structure; the first conductive structure serves as the first electrode of the PIP capacitor structure, the second conductive structure serves as the second electrode of the PIP capacitor structure, and the insulating dielectric component serves as the capacitor dielectric of the PIP capacitor structure.

2. The PIP capacitor structure based on NORD flash memory technology according to claim 1, characterized in that: An insulating layer is further disposed below the first conductive structure, and the first conductive structure and the insulating layer together form a stepped structure; the bottom of the second conductive structure extends to below the top surface of the isolation structure; The insulating dielectric assembly covers the sidewalls of the first conductive structure, the sidewalls of the insulating stack, and the groove surface formed by the extension of the second conductive structure in the isolation structure.

3. The PIP capacitor structure based on NORD flash memory technology according to claim 1, characterized in that: The insulating dielectric assembly is a multilayer composite structure, comprising: a protective sidewall attached to the sidewall of the first conductive structure; a dielectric spacer attached to the side of the protective sidewall opposite to the first conductive structure; and a tunneling dielectric layer located between the dielectric spacer and the second conductive structure.

4. The PIP capacitor structure based on NORD flash memory technology according to claim 1, characterized in that: The capacitor unit, which is composed of the first conductive structure, the insulating dielectric component and the second conductive structure, is arranged in a direction perpendicular to the surface of the substrate, and the capacitor unit is electrically isolated from the substrate through the isolation structure at the bottom.

5. The PIP capacitor structure based on NORD flash memory technology according to claim 1, characterized in that: The material of the first conductive structure includes control gate polysilicon, and the material of the second conductive structure includes word line polysilicon.

6. The PIP capacitor structure based on NORD flash memory technology according to claim 1, characterized in that: The isolation structure is a shallow trench isolation structure.

7. The PIP capacitor structure based on NORD flash memory technology according to claim 1, characterized in that: The insulating stack comprises a silicon oxide-silicon nitride-silicon oxide stack.

8. A method for manufacturing a PIP capacitor structure based on NORD flash memory technology, characterized in that, include: Step 1: Provide a substrate and form an isolation structure in the substrate; Step 2: Form a stacked structure on the isolation structure, the stacked structure including an insulating layer and a first conductive material layer stacked sequentially from bottom to top; Step 3: Pattern the stacked structure to form a first conductive structure and an insulating layer pattern below it, and form trenches between the first conductive structures to expose the insulating structure. Step 4: Form an insulating dielectric assembly on the sidewall surface of the trench; Step 5: Fill the trench with a second conductive material to form a second conductive structure; The first conductive structure, the insulating dielectric component, and the second conductive structure together constitute the PIP capacitor structure.

9. The manufacturing method of the PIP capacitor structure based on NORD flash memory technology according to claim 8, characterized in that: In step two, the stacked structure further includes a hard mask layer located above the first conductive material layer; In step three, the patterning process of the stacked structure includes: forming an opening in the hard mask layer; forming a first sidewall on the sidewall of the opening; and etching the first conductive material layer using the first sidewall as a mask to define the upper width of the trench.

10. The method for manufacturing a PIP capacitor structure based on NORD flash memory technology according to claim 8, characterized in that: In step three, after patterning the stacked structure, the exposed isolation structure is further etched so that the bottom of the trench extends below the top surface of the isolation structure.

11. The method for manufacturing a PIP capacitor structure based on NORD flash memory technology according to claim 8, characterized in that: In step four, forming the insulating dielectric assembly includes: sequentially forming a second sidewall and a third sidewall on the sidewall of the trench; using the third sidewall as a mask, etching the exposed isolation structure to form a groove located inside the isolation structure; and forming a tunneling dielectric layer covering the surface of the third sidewall and the groove.

12. The manufacturing method of the PIP capacitor structure based on NORD flash memory technology according to claim 8, characterized in that: In step five, filling the second conductive material includes: depositing polycrystalline silicon material to fill the trench, and planarizing the polycrystalline silicon material by a chemical mechanical polishing process until the mask layer structure covering the first conductive structure is exposed.

13. The method for manufacturing a PIP capacitor structure based on NORD flash memory technology according to claim 9, characterized in that: The method also includes step six: removing the hard mask layer, retaining the first sidewall, and using the second conductive structure, the first sidewall, and the insulating dielectric component as a mask, etching the first conductive structure to pattern the first conductive structure into independent capacitor plates.

14. The method for manufacturing a PIP capacitor structure based on NORD flash memory technology according to claim 8, characterized in that: The manufacturing steps of the PIP capacitor structure are performed synchronously with the manufacturing steps of the NORD flash memory cell on the substrate; wherein, the first conductive structure and the control gate of the NORD flash memory cell are formed simultaneously from the same first conductive material layer, and the second conductive structure and the word line of the NORD flash memory cell are formed simultaneously from the same second conductive material layer.

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