Stacked high blocking in gaas semiconductor power diodes

Abstract

A stacked high-blocking III-V semiconductor power diode and a method for manufacturing the same are disclosed. The III-V semiconductor power diode has a highly doped first semiconductor pass region, a lightly doped semiconductor drift region disposed below the first semiconductor pass region, a highly doped second semiconductor pass region disposed below the semiconductor drift region, and two interconnect layers. At least the first semiconductor pass region forms a core stack, which is surrounded laterally by a dielectric frame region. The upper or lower sides of the core stack and the dielectric frame region are closed to each other or have steps formed relative to each other. The semiconductor regions of the III-V semiconductor power diode disposed below the first semiconductor pass region are respectively included by or form carrier regions by the core stack. The carrier regions are disposed below the core stack and the frame region and are locked to a common lower material formed by the lower side of the dielectric frame region and the lower side of the core stack.

Description

[0001] This case is a divisional application of the patent application filed on March 19, 2021, with application number 202110294208.9 and invention title "Stacked High Blocking InGaAs Semiconductor Power Diode". Technical Field

[0002] This invention relates to a stacked, high-blocking InGaAs power semiconductor diode. Background Technology

[0003] A high-voltage PIN semiconductor diode made of GaAs is known from Ashkinazi's "GaAs Power Devices" (ISBN 965-7094-19-4), pages 8 and 9.

[0004] Stacked high-blocking InGaAs semiconductor power diodes and corresponding manufacturing methods are known from documents DE 10 2016 013 540 A1, DE 10 2016 013 541 A1, DE 10 2016 015 056 A1, DE 10 2017 002 935 A1 and DE 10 2017 002 936 A1.

[0005] General-purpose diodes have a breakdown voltage higher than 200V and, in addition to a low forward voltage, should have a low series resistance to reduce power loss. Furthermore, the diode should have the lowest possible leakage current, less than 1μA, in the cutoff direction.

[0006] In most cases, semiconductor devices are still protected at the wafer level through passivation layers and / or protective layers.

[0007] Corresponding methods for III-V semiconductor devices are known, for example, from VN Bessolov et al., “Passivation of GaAs in alcohol solutions of ammonium sulfide,” Semiconductor, Vol. 31, No. 11, pp. 1350-1356, ISSN 1063-7826, 1997; or from T. Tamanuki et al., “Ammonium sulfide passivation for AlGaAs / GaAs buried heterostructure laser fabrication process,” Japanese Journal of Applied Physics, Part 1, Vol. 30, No. 3, pp. 499-500, ISSN 0021-4922, 1991; or from Yi Xuan et al., “Simplified Surface Preparation for GaAs Passivation Using Atomic Layer-Deposited High- / Dielectrics,” IEEE Journal of Electronic Devices, Vol. 54, No. 8, 2007.

[0008] For separation, the channels are typically etched in the first mesa-prozess process, and then the area below the channels is cut off by sawing. The channels are usually further passivated.

[0009] It is also known that nanostructures are generated by selectively growing them on wafers covered with a structured SiO2 mask layer. Different methods are described in F. Haas et al., “Nanoimprint and selective-area MOVPE for growth of GaAs / InAs core / shell nanowires”, Nanotechnology, Vol. 24, No. 8, 085603, 2013, and in B. Kunert et al., “III / V nano ridge structures for optical applications on patterned 300 mm silicon substrate”, Applied Physics, Lett. 109, 091101, 2016. Summary of the Invention

[0010] In this context, the objective of the present invention is to describe a device that extends the prior art.

[0011] This task is accomplished by a device having features according to the invention and by a method having features according to the invention. The advantageous configuration of the invention is the preferred embodiment.

[0012] According to the subject matter of the present invention, a stacked high-blocking III-V semiconductor power diode is provided, having a highly doped first semiconductor pass region of a first conductivity type, the first semiconductor pass region having at least The dopant concentration and have a first lattice constant.

[0013] A lightly doped semiconductor drift region of a first conductivity type or a second conductivity type is disposed below the first semiconductor contact region, the semiconductor drift region having to The dopant concentration, wherein the semiconductor drift region has a first lattice constant and a layer thickness between 10 μm and 200 μm.

[0014] Below the semiconductor drift region, a highly doped second semiconductor pass region of a second conductivity type is disposed, the second semiconductor pass region having at least The dopant concentration, wherein the second semiconductor pass region has a first lattice constant or a second lattice constant.

[0015] The first metal interconnect layer is at least regionally constructed on the upper side of the first semiconductor interconnect region and is material-locked to the upper side of the first semiconductor interconnect region.

[0016] The second metal interconnect layer is at least regionally constructed below the lower side of the second semiconductor interconnect region, and is locked to, for example, the lower side of the second semiconductor interconnect region or a semiconductor layer (e.g., a substrate layer or a buffer layer) material, the semiconductor layer being disposed between the second semiconductor interconnect region and the second metal interconnect layer.

[0017] At least the first semiconductor pass region constitutes a core stack (Kernstapel). The core stack has a top side and a bottom side, as well as a side extending from the top side to the bottom side.

[0018] Furthermore, the III-V group semiconductor power diode has a dielectric frame region that surrounds the core stack along the sides and has an upper side and a lower side.

[0019] The upper side of the core stack is closed off by means of the upper side of the dielectric frame region or a first step is constructed relative to the upper side of the dielectric frame region.

[0020] The lower side of the core stack is closed off by means of the lower side of the dielectric frame region or a second step is constructed relative to the lower side of the dielectric frame region.

[0021] The semiconductor regions of the III-V group semiconductor power diodes arranged below the first semiconductor pass region are respectively included or constructed by a core stack, wherein the carrier regions are arranged below the core stack and the frame region and are locked to a common underside material formed by the underside of the dielectric frame region and the underside of the core stack.

[0022] In other words, III-V group semiconductor power diodes always have a core stack surrounded by a frame region, and the carrier region arranged below it is optional.

[0023] For example, both the drift region and the second semiconductor pass region form part of the core stack, so that the III-V semiconductor power diode either has no carrier region or has a carrier region formed by another semiconductor layer (e.g., a substrate). In an alternative implementation, for example, the drift region is formed as part of the core stack, and the III-V semiconductor power diode has a carrier region formed by at least the second semiconductor pass region.

[0024] Alternatively, the core stack may include only the first semiconductor pass region or, if necessary, additional semiconductor intermediate layers, wherein the drift region and the second semiconductor pass region are both constructed in the carrier region.

[0025] It should be noted that the metal connection layers are all capable of conducting electricity well.

[0026] Preferably, the metal interconnect layer comprises one or more metal layers, wherein the metal layers preferably include Ge and / or Au and / or Pd and / or Ag. The metal interconnect layer generates a low-ohmic electrical connection with the highly doped semiconductor interconnect region.

[0027] The larger, especially full-surface, construction of the second metal interconnect layer on the underside improves thermal coupling with the substrate and reduces the resistance of the component. At least 70% or at least 80% coverage of the underside of the second semiconductor interconnect region is referred to as a full-surface construction.

[0028] Alternatively, the second metal connection layer may be constructed as a point or a limited surface segment, or also as a finger shape.

[0029] In another alternative implementation, the III-V semiconductor power diode does not have a carrier region, and the second metal interconnect layer is constructed entirely on the underside of the III-V semiconductor power diode, i.e., the second metal interconnect layer covers the common underside formed by the underside of the core stack and the underside of the frame region.

[0030] Furthermore, it can be understood that the metal connection layer is preferably connected to the connection finger (so-called pin) by means of a bonding wire, in such a way that the semiconductor power diode is arranged on a carrier, for example, in the form of a lead frame.

[0031] It should also be noted that the terms "semiconductor layer" or "semiconductor contact layer" are preferably used synonymously with the terms "semiconductor region" or "semiconductor contact area" or "semiconductor contact zone".

[0032] It is understood that all semiconductor regions (i.e., especially the first and second semiconductor switching regions) and drift regions of the power diode are preferably constructed in layers, especially as flat layers, i.e. having flat or substantially flat upper and lower sides.

[0033] In an alternative embodiment, the first semiconductor contact region and / or the second semiconductor contact region are constructed in a trench shape. It should also be understood that the trench-shaped region preferably extends from the upper side of another flat semiconductor layer into that flat semiconductor layer.

[0034] Preferably, a trench-shaped semiconductor contact region is created in the layered drift region by introducing a dopant into the region of the drift region, wherein the region preferably extends into the drift region in a trench-like manner.

[0035] Alternatively, layered semiconductor pass regions can be created in the drift region by implanting dopants, for example, by implanting a layer of desired depth adjacent to the upper side of the drift region into a semiconductor pass region.

[0036] Preferably, all semiconductor layers of the power diode are epitaxially generated, for example, by means of MOVPE, LPE, CVD, or by implantation or diffusion. Alternatively or additionally, one or more layers in the carrier region are connected to each other by means of wafer bonding.

[0037] It is understood that the semiconductor-only region or semiconductor layer of a high-blocking III-V semiconductor diode is composed of at least a majority of III-V materials (e.g., GaAs, InGaP, InGaAs, AlGaAs, or InP).

[0038] Alternatively, high-blocking III-V semiconductor diodes may additionally include a semiconductor layer made of other semiconductor materials or an additional layer made of other non-semiconductor materials.

[0039] III-V semiconductors, especially GaAs or InGaAs, offer exceptionally high charge carrier mobility.

[0040] Furthermore, it can be understood that a semiconductor region or semiconductor layer composed of group III-V materials need to be composed primarily of group III-V materials, or, in addition to group III-V materials (i.e., materials including one or more elements from group III and / or group V), may also have impurities and / or dopants if necessary.

[0041] The corresponding situation applies to semiconductor regions or semiconductor layers composed of GaAs or InGaAs or other explicitly mentioned material combinations.

[0042] If a layer has an explicitly mentioned combination of materials, it therefore indicates that the material of the layer is essentially composed of the explicitly mentioned materials and, if necessary, other elements from Group III and / or Group V. Thus, a layer containing GaAs can be, for example, a GaAsP layer or an AlGaAs layer.

[0043] It should also be understood that high-blocking III-V semiconductor diodes can be constructed with n on p (n-auf-p) or p on n (p-auf-n). Accordingly, the first conductivity type is n and the second conductivity type is p, or vice versa.

[0044] The terms “below” and “above” or “under” and “above” are used only to describe the arrangement of the various layers and areas relative to each other and do not indicate any absolute direction.

[0045] It should be noted that the dielectric framework region is composed of a dielectric material or a material with dielectric properties. Preferably, the dielectric framework region is composed of Si. x O y (e.g., SiO2) or made of Si x N y (e.g., SiN) or made of Al x O y Or by Ta x O y Or by Ti x O y Or by Hf x O y Composition. Alternatively, the frame region has Si x O y or Si x N y Or Al x O y Or Ta x O y or Ti x O y or Hf x O yIn another embodiment, the dielectric framework region is constructed as an oxide, such as Al2O3, Ta2O5, TiO2, or HfO2, or has rare earth elements.

[0046] The dielectric framework region is preferably constructed in a layered manner with through openings (Durchgangsöffnung) to accommodate the core stack.

[0047] The resulting common layers, for example, have a flat common upper side and / or a flat common lower side. Alternatively, the core stack protrudes beyond the upper and / or lower sides of the dielectric frame region, thereby creating an ascending step at the transition from the dielectric frame region to the core stack.

[0048] In another alternative implementation, the upper side of the core stack does not extend to the upper side of the dielectric frame region, thereby creating a descending step at the transition from the upper side of the dielectric frame region to the upper side of the core stack.

[0049] The common layer thus created by the frame region and the core stack can also be arranged on the carrier region, so that the common underside (the underside of the common layer) formed by the underside of the frame and the underside of the core stack is locked to the upper material of the carrier region.

[0050] Preferably, the outer side of the frame region is closed by means of the side of the carrier region, that is, the carrier region has the following diameter: the diameter corresponds to the sum of the diameter of the core stack and twice the wall thickness of the frame region.

[0051] The frame region provides sufficient protection or passivation for the sides or pn junction, eliminating the need for additional passivation layers. This reliably suppresses leakage current and achieves high breakdown voltage and efficiency.

[0052] One advantage is that the epitaxial deposition of the III-V semiconductor layer within the dielectric framework region prevents the formation of surface states that typically form at the semiconductor surface due to oxygen contained in the air, leading to reduced breakdown voltage and decreased device efficiency. Furthermore, the pn junction remains protected within the framework region, thus reliably preventing moisture ingress. Moisture, in particular, causes higher leakage currents or lower breakdown voltages, making moisture ingress prevention especially crucial in high-blocking devices.

[0053] Furthermore, through selective growth, the frame region can be used to individually produce each power diode. This allows for the separation of the III-V group semiconductor power diodes according to the invention in a particularly simple manner using only sawing.

[0054] Additional etching prior to sawing is unnecessary. Relatively advantageous manufacturing is possible. III-V group components are generally more cost-effective to manufacture compared to SiC.

[0055] Compared to Si, III-V semiconductor power diodes can also achieve higher temperatures at the p / n junction without damaging the III-V semiconductor diode. Therefore, III-V semiconductor diodes can be used at temperatures up to 300°C, meaning they can be used even in hot ambient environments.

[0056] In one extended embodiment, the III-V group semiconductor power diode has a semiconductor interlayer of a first conductivity type between the first semiconductor on-state and the semiconductor drift region, the first conductivity type semiconductor interlayer having to The dopant concentration. It can be understood that the semiconductor intermediate layer is constructed as part of the core stack and / or as part of the carrier region.

[0057] In another embodiment, alternatively or additionally, the III-V group semiconductor power diode has a semiconductor interlayer of a second conductivity type between the second semiconductor on-state and the semiconductor drift region, the semiconductor interlayer of the second conductivity type having to The dopant concentration. It can be understood that the semiconductor intermediate layer is constructed as part of the core stack and / or as part of the carrier region.

[0058] In another embodiment, the III-V semiconductor power diode has a highly doped metamorphic buffer layer sequence, wherein the metamorphic buffer layer sequence is disposed between the semiconductor drift region and the second semiconductor pass region, having a density greater than [missing information]. The dopant concentration and layer thickness are greater than 0.5 μm and less than 20 μm, having a first conductivity type or a second conductivity type, and having a first lattice constant on the upper side toward the semiconductor drift region and a second lattice constant on the lower side toward the second semiconductor pass region, and the second semiconductor pass region having a second lattice constant.

[0059] The buffer layer sequence is, for example, part of the core stack and / or part of the carrier region.

[0060] In one extended scheme, the buffer layer sequence or a portion thereof is configured as a second semiconductor pass-through layer. That is, the buffer layer sequence not only satisfies the function of lattice constant compensation between the layers arranged above and below it, but also satisfies the function of a second semiconductor pass-through layer; or, in other words, the corresponding layer not only has the characteristics of the buffer layer sequence but also has the function of a second semiconductor pass-through layer.

[0061] In another extended scheme, the modified buffer layer sequence has at least three layers, and for example, up to twenty layers. The modified buffer layers are preferably highly n-doped or highly p-doped. The buffer layer sequence is constructed, for example, from InGaAs.

[0062] Preferably, the deteriorated buffer layer sequence has a greater than The dopant concentration and the layer thickness are greater than 0.5 μm and less than 20 μm.

[0063] In one implementation, the degraded buffer layer sequence consists of multiple In... x Ga 1-x As layers are composed of these In x Ga 1-x As has different x at each level and / or keeps the same x.

[0064] It is understood that the lattice constant changes at least once within the buffer layer. In a first embodiment, for example, the lattice constant increases layer by layer from the lowest layer of the sequence having the second lattice constant to the highest layer of the sequence having the first lattice constant.

[0065] Alternatively, starting from the bottom layer of the sequence, the lattice constant is either increased layer by layer and then decreased layer by layer, or decreased layer by layer and then increased layer by layer.

[0066] The lattice constant increases or decreases over the entire sequence in a stepwise or linear manner, or in any other form.

[0067] In another embodiment, the III-V group semiconductor power diode has a substrate layer, wherein the substrate layer is configured as part of a carrier region.

[0068] The substrate has a first lattice constant or a second lattice constant. The substrate is constructed, for example, a GaAs substrate or a Ge substrate. In one extended embodiment, the substrate forms a second semiconductor interconnect layer.

[0069] In another embodiment, the semiconductor drift region and / or the first semiconductor turn-on region and / or the second semiconductor turn-on region are composed of GaAs or InGaAs, or the semiconductor drift region and / or the first semiconductor turn-on region and / or the second semiconductor turn-on region have GaAs or InGaAs.

[0070] Preferably, the first conductivity type is p-type and the second conductivity type is n-type, or the first conductivity type is n-type and the second conductivity type is p-type.

[0071] In another embodiment, the first semiconductor contact area and / or the second semiconductor contact area are configured as a groove.

[0072] In another embodiment, the frame region is locked to the side material of the core stack.

[0073] Another subject of the present invention is a method for manufacturing a stacked, high-blocking III-V semiconductor power diode, wherein a semiconductor carrier layer is provided.

[0074] A dielectric layer is deposited on the upper side of the semiconductor carrier layer.

[0075] Next, a mask layer with at least one through-hole is fabricated on the upper side of the dielectric layer.

[0076] After the mask layer is applied, in the etching step, the dielectric layer is removed in the region of at least one through-opening in the mask layer, more precisely, down to the semiconductor carrier layer, thereby forming the dielectric framework region.

[0077] Next, remove the mask layer.

[0078] After the etching step, one or more III-V semiconductor layers are sequentially deposited on the exposed upper side of the semiconductor carrier layer, and in the metallization step, a first metal interconnect layer, at least regionally constructed, is applied on the upper side of the uppermost deposited III-V semiconductor layer and a second metal interconnect layer is applied under the lowermost deposited III-V semiconductor layer.

[0079] It is understandable that the order mentioned may not be pre-defined in terms of the chronological order of the steps in each method. Therefore, the basic temporal relationships are explicitly mentioned.

[0080] It should also be understood that this method is suitable for manufacturing III-V group semiconductor power diodes of the type described above, and the above description of III-V group semiconductor power diodes also applies accordingly to the manufacturing method according to the present invention.

[0081] It should also be understood that this manufacturing method is preferably implemented at the wafer-level, i.e., multiple III-V semiconductor power diodes are fabricated side-by-side in a matrix manner. The components are then separated by sawing in the region of the dielectric frame, and these components have sidewall passivation after separation.

[0082] Because the dielectric layer and the semiconductor carrier layer are made of different materials, i.e., different dielectric materials compared to III-V semiconductor materials, the etching steps (e.g., dry etching steps or wet chemical etching steps) can be performed with high selectivity, thereby removing little or no semiconductor carrier layer (i.e. carrier region).

[0083] Next, the recesses in the dielectric layer are at least partially or completely filled by one or more semiconductor layers, thereby constructing a core stack made of semiconductor layers surrounded by a frame region on the semiconductor carrier layer.

[0084] In one implementation, the core stack includes all the semiconductor layers of a III-V semiconductor power diode, wherein the III-V semiconductor power diode is partially exposed by removing the entire semiconductor carrier layer.

[0085] Alternatively, the core stack may consist only of a portion of the semiconductor layers of a III-V group semiconductor power diode, particularly a highly doped first semiconductor pass region and, if necessary, a drift region, wherein other layers (e.g., a second semiconductor pass region) are comprised of a semiconductor carrier layer.

[0086] In one extended embodiment, the deposited III-V semiconductor layer has a first or second conductivity type and to The semiconductor drift region with varying dopant concentrations.

[0087] Preferably, the first conductivity type, having at least The highly doped first semiconductor pass region is either generated by deposition as one of the III-V semiconductor layers after the semiconductor drift region is deposited, or generated by introducing dopant into the upper region of the semiconductor drift region.

[0088] In another extended embodiment, the semiconductor carrier layer has a substrate layer, wherein the substrate layer is not removed, partially or completely removed prior to the metallization step.

[0089] Preferably, the second conductivity type, having at least The highly doped second semiconductor junction region is formed by deposition on a substrate layer, or by introducing foreign atoms into a portion of the substrate layer, or by introducing foreign atoms into the entire substrate layer, or by providing a dopant concentration of at least A substrate layer with a dopant concentration of a certain amount is provided as part of a semiconductor carrier layer.

[0090] Alternatively, after removing the semiconductor carrier layer, a second conductivity type with at least [missing information] is generated by introducing a dopant into the lower region of the semiconductor drift region. The highly doped second semiconductor pass region with a high dopant concentration.

[0091] In another alternative implementation, after the etching step for opening the dielectric layer (i.e., creating a through-hole) and before the deposition of a III-V semiconductor layer in the semiconductor drift region, a second conductivity type with at least The highly doped second semiconductor pass region with a high dopant concentration.

[0092] In another embodiment, during the metallization step, a second metal interconnect layer is applied to the underside of the second semiconductor interconnect layer.

[0093] The provided semiconductor carrier layer preferably has a GaAs substrate, a Ge substrate, or a Si substrate.

[0094] In another embodiment, the dielectric layer has Si x O y (e.g., SiO2) or Si x Ni y Or Al x O y Or Ta x O y or Ti x O y or Hf x O y , or by Si x O y Or from Si x Ni y Or by Al x O y Or by Ta x O y Or by Ti x O y Or by Hf x O y composition.

[0095] Deposition is preferably carried out using MOVPE, LPE, or CVD.

[0096] In another extended scheme, the first semiconductor pass region is generated by implantation or diffusion. Thus, foreign atoms are introduced into other semiconductor layers (e.g., drift regions) by implantation or diffusion, and the corresponding regions of the drift regions then form or become the first semiconductor pass region. Attached Figure Description

[0097] The invention is further described below with reference to the accompanying drawings. Here, like parts are labeled with the same reference numerals. The illustrated embodiments are highly schematic, i.e., the spacing and lateral and vertical extensions are not to scale, and unless otherwise stated, they do not have any deducible geometric relationships with each other. Wherein shown: Figure 1 A cross-sectional view showing a first embodiment of a III-V group semiconductor power diode; Figure 2A top view showing a first embodiment of a III-V group semiconductor power diode; Figure 3 A cross-sectional view showing a second embodiment of a group III-V semiconductor power diode; Figure 4 A cross-sectional view showing a third embodiment of a group III-V semiconductor power diode; Figure 5 A cross-sectional view showing a fourth embodiment of a III-V group semiconductor power diode; Figure 6 A cross-sectional view showing a fifth embodiment of a group III-V semiconductor power diode; Figure 7 A cross-sectional view showing a sixth embodiment of a III-V group semiconductor power diode; Figure 8 A cross-sectional view showing a seventh embodiment of a III-V group semiconductor power diode; Figure 9 A cross-sectional view showing an eighth embodiment of a III-V group semiconductor power diode; Figure 10 A cross-sectional view showing a ninth embodiment of a III-V group semiconductor power diode; Figure 11 A cross-sectional view showing a tenth embodiment of a group III-V semiconductor power diode; Figure 12 A cross-sectional view showing an eleventh embodiment of a III-V group semiconductor power diode; Figure 13 A view showing a first embodiment of a method for manufacturing a III-V group semiconductor power diode; Figure 14 A view showing another embodiment of a method for manufacturing a III-V group semiconductor power diode; Figure 15 A view showing another embodiment of a method for manufacturing a III-V group semiconductor power diode. Detailed Implementation

[0098] For clarity, only cross-sectional views or cross-sectional views of the stacked high-blocking III-V semiconductor power diodes (HLDs) are shown in all images. The stacked layers have a top side and a bottom side.

[0099] It should be noted that all III-V semiconductor power diodes (HLDs) shown in cross-sectional view have a square, rectangular, or circular periphery in top view, or a rectangular periphery with rounded corners.

[0100] Figure 1 The image shows a stacked, high-blocking III-V semiconductor power diode, HLD.

[0101] The semiconductor power diode HLD has a highly doped first semiconductor pass region HK1 of a first conductivity type, a drift region HD1 of a first conductivity type or a second conductivity type, and a highly doped second semiconductor pass region HK2 of a second conductivity type.

[0102] The highly doped first semiconductor pass region HK1 and the drift region together constitute a core stack having an upper side, a lower side, a side extending from the upper side to the lower side, a diameter d1, and a height h1. The first semiconductor pass region HK1 and the drift region are each constructed as layers of the core stack.

[0103] The upper side of the core stack is formed by a highly doped first semiconductor pass region, and the first metal pass layer M1 is locked to the upper material.

[0104] The sides of the core stack are surrounded by a dielectric frame region DR, wherein the upper side of the dielectric frame region DR is closed by the upper side of the core stack, i.e., a flat common surface is constructed.

[0105] The lower side of the dielectric frame region DR and the lower side of the core stack are similarly enclosed to each other, or similarly constructed with a flat common lower surface. The dielectric frame region DR also has a height h1.

[0106] In addition, the dielectric frame region DR has a width b1, which is the wall thickness surrounding the core stack.

[0107] The second semiconductor access area HK2 It is constructed in layers of diameter or edge length and is locked to the common underside material of the core stack and the frame region DR.

[0108] The second metal interconnect layer M2 covers the lower side of the second semiconductor interconnect area HK2.

[0109] It can be understood that a semiconductor power diode (HLD) can be constructed not only with n above p (n über p) (i.e., n as the first conductivity type and p as the second conductivity type), but also with p above n (p über n) (i.e., p as the first conductivity type and n as the second conductivity type).

[0110] The semiconductor drift region HD1 has a first or second conductivity, i.e., it is weakly n-doped or weakly p-doped. Accordingly, the pn junction of the semiconductor power diode is either constructed between the second semiconductor on-state region and the drift region, or between the first semiconductor on-state region and the drift region.

[0111] It is understood that the terms “on top of,” “above,” “below,” and “under” are used only for the arrangement of the various areas and layers relative to each other and do not indicate any absolute direction.

[0112] exist Figure 2 The image shows Figure 1 Top view of a III-V group semiconductor power diode.

[0113] The dielectric frame region DR and the layers below it (i.e., the second semiconductor pass region HK2 and the second metal connection pass layer M2) each have square perimeters of the same size.

[0114] Conversely, the core stack (i.e., the drift region HD1 and the first semiconductor pass region HK1) has a circular outer perimeter. The first metal interconnect layer also has a circular outer perimeter, wherein the diameter of the first metal interconnect layer M1 is smaller than the diameter of the first semiconductor pass region.

[0115] The circular periphery of the core stack can be easily manufactured and is particularly advantageous in terms of electrical properties. Conversely, in the case of separation by sawing, the square or rectangular periphery of the entire component can be manufactured particularly easily.

[0116] In embodiments not shown, other shapes of the periphery of the core stack and / or the entire component are also possible or advantageous, such as the periphery of a polygon (e.g., an octagon) of the core stack or the entire component.

[0117] In other embodiments not shown, the first metal connection layer also preferably has other peripheral shapes, such as polygons.

[0118] exist Figure 3 Another embodiment is shown in the image. Only the following description relates to... Figure 1 The differences between the images.

[0119] The III-V group semiconductor power diode HLD has a first intermediate layer ZW1, which is disposed as part of the core stack between the first semiconductor on region HK1 and the semiconductor drift region HD1.

[0120] exist Figure 4 Another embodiment is shown in the image. Only the following description relates to... Figure 1 The differences between the images.

[0121] The III-V group semiconductor power diode HLD has a second intermediate layer ZW2 disposed between the second semiconductor on-state region HK2 and the semiconductor drift region HD1, and is locked to the common underside material of the core stack and the dielectric frame region DR.

[0122] exist Figure 5 Another embodiment is shown in the image. Only the following description relates to... Figure 4 The differences between the images.

[0123] Alternatively, the second intermediate layer ZW2 is constructed as part of the core stack, and in particular as the bottommost layer of the core stack.

[0124] exist Figure 6 Another embodiment is shown in the image. Only the following description relates to... Figure 1 The differences between the images.

[0125] The second semiconductor pass region is also constructed as part of the core stack, that is, as the bottom layer of the core stack. The second metal connection pass layer M2 is locked to the common underside material formed by the underside of the core stack and the underside of the dielectric edge region.

[0126] exist Figure 7 Another embodiment is shown in the image. Only the following description relates to... Figure 1 The differences between the images.

[0127] Prior to separation, multiple III-V group semiconductor power diodes (HLDs) are connected via a common dielectric frame region DR. Furthermore, in the illustrated embodiment, the semiconductor power diodes (HLDs) are also connected via a common second semiconductor pass region HK2 and a common second metal interconnect pass layer.

[0128] It is understood that other implementations can also be co-fabricated on the wafer and have a corresponding common structure. It is particularly advantageous, in addition to the frame region DR, to fabricate all layers disposed beneath the frame region DR and the core stack as a common layer. Preferably, separation is achieved through a single sawing step.

[0129] exist Figure 8 Another embodiment is shown in the image. Only the following description relates to... Figure 1 The differences between the images.

[0130] III-V group semiconductor power diodes (HLDs) have a buffer layer sequence P, wherein the buffer layer sequence P is arranged below the dielectric frame region DR and the core stack and above the second semiconductor pass region HK2.

[0131] The core stack has a first step S1 that rises toward the dielectric frame region DR on the upper side and a second step S2 that descends toward the lower side of the dielectric frame region DR. These steps are formed, for example, by etching processes during manufacturing.

[0132] The second metal connection layer M2 is constructed in a finger-like shape, that is, it has multiple finger-like segments that extend in parallel, for example, and these segments are preferably connected to each other by another laterally extending segment.

[0133] exist Figure 9 Another embodiment is shown in the image. Only the following description relates to... Figure 8 The differences between the images.

[0134] Alternatively, the buffer layer sequence P is constructed as part of the core stack. The buffer layer sequence, for example, has three layers (shown as dashed lines) with different lattice constants.

[0135] The core stack has a first step that descends toward the upper side of the dielectric frame region, while in the illustrated embodiment, the lower side of the dielectric frame region and the lower side of the core stack are closed to each other.

[0136] The second metal connection connects to the layered structure.

[0137] exist Figure 10 Another embodiment is shown in the image. Only the following description relates to... Figure 1 The differences between the images.

[0138] The first semiconductor pass area HK1 is constructed in a trench shape and extends from the top of the core stack into the core stack, where it extends into the semiconductor drift layer HD1.

[0139] exist Figure 11 Another embodiment is shown in the image. Only the following description relates to... Figure 1 The differences between the images.

[0140] Alternatively, the second semiconductor pass area HK2 is constructed in a trench shape and extends from the underside of the core stack into the core stack.

[0141] In one extended embodiment (not shown), two semiconductor pass regions HK1 and HK2 are configured to extend into the core stack in a groove shape.

[0142] exist Figure 12 Another embodiment is shown in the image. Only the following description relates to... Figure 1 The differences between the images.

[0143] The core stack of the high-blocking III-V semiconductor power diode HLD has a first semiconductor pass region HK1 and a first semiconductor intermediate layer ZW1. The drift region HD1, together with the second semiconductor pass region HK2 and the second metal interconnect pass layer M2, constitutes the carrier region.

[0144] exist Figure 13The image schematically illustrates a method for manufacturing a high-blocking III-V group semiconductor power diode (HLD) according to a first embodiment of the present invention.

[0145] On the substrate SUB, a highly doped second semiconductor pass layer HK2 is deposited, for example by means of MOVPE, LPE or CVD, wherein the substrate SUB and the second semiconductor pass layer HK2 together serve as a semiconductor carrier layer TR.

[0146] A dielectric layer DS, such as a SiO2 layer, is deposited on the upper side of the semiconductor carrier layer TR. Then, a mask layer MA having at least one through-hole OE is applied on the upper side of the dielectric layer DS.

[0147] During the etching step, the dielectric layer DS is removed from at least one through-hole OE region of the mask layer MA, down to the semiconductor carrier layer TR. It is understood that, if necessary, a portion of the semiconductor carrier layer TR, in this case, the second semiconductor interconnect layer HK2, may also be etched away by the etching process. The remaining portion of the dielectric layer DS after the etching step forms the dielectric framework region DR.

[0148] Remove the mask layer MA again.

[0149] A semiconductor drift layer HD1 is deposited on the exposed upper side of the semiconductor carrier layer TR (in this case, the second semiconductor interconnect layer HK2), wherein the thickness of the semiconductor drift layer HD1 is smaller than the height of the dielectric framework region. Figure 13 (left path) or the same ( Figure 13 (The right path) or larger (not shown).

[0150] Next, a highly doped first semiconductor interconnect layer HK1 is deposited on the upper side of the semiconductor drift layer HD1. Figure 13 (left path), or by introducing dopant into the region of the semiconductor drift layer HD1 adjacent to the upper side of the semiconductor drift layer HD1 to generate a highly doped first semiconductor pass layer HK1 ( Figure 13 (the right path).

[0151] Next, the substrate layer SUB is removed.

[0152] In the metallization step, a first metal interconnect layer M1, which is at least regionally constructed, is applied to the upper side of the first semiconductor interconnect layer HK1, and a second metal interconnect layer M2 is applied to the lower side of the second semiconductor interconnect layer HK2.

[0153] exist Figure 14 The image schematically illustrates another embodiment of the method for manufacturing a high-blocking III-V group semiconductor power diode (HLD) according to the present invention. Only the following description is related to... Figure 13 The differences between the images.

[0154] The provided substrate is transformed into a highly doped semiconductor pass-through layer HK2 by introducing dopants, and is used as a semiconductor carrier layer TR.

[0155] Accordingly, the method step of removing the substrate is omitted, wherein, in one extension scheme, the substrate layer is thinned.

[0156] exist Figure 15 The image schematically illustrates another embodiment of the invention of a method for manufacturing a high-blocking III-V group semiconductor power diode (HLD).

[0157] The substrate layer SUB serves as the carrier layer TR. After the masking and etching processes, the second semiconductor interconnect layer HK2, the drift region HD1, and the first semiconductor interconnect layer HK1 are sequentially grown on the exposed surface area of ​​the carrier layer TR (i.e., the substrate SUB).

[0158] Next, the carrier layer TR (i.e., the substrate layer SUB) is removed, and the first and second metal interconnect layers are applied. Figure 15 (left path).

[0159] Alternatively, the substrate SUB is not removed or is only partially removed (thinned), and a second metal interconnect layer M2 is applied to the underside of the substrate SUB. Figure 15 (the right path).

Claims

1. A stacked high-blocking III-V semiconductor power diode (HLD), said high-blocking III-V semiconductor power diode comprising: A semiconductor carrier layer (TR) is formed of layered, highly doped second-conductivity-type group III-V semiconductor pass regions (HK2), wherein the second semiconductor pass regions (HK2) have at least dopant concentration; A layered dielectric framework region (DR) is disposed on the upper side of the second semiconductor contact region (HK2). The dielectric framework region (DR) has a through opening extending from the upper side of the dielectric framework region (DR) to the lower side of the dielectric framework region (DR). The through opening is formed by etching and has an inner wall. At least one outer side of the dielectric framework region (DR) is formed by sawing in the region of the dielectric framework region (DR). A core stack, arranged within a constructed through opening, wherein the core stack comprises: The low-doped III-V semiconductor drift region (HD1) has to Dopant concentrations and layer thicknesses ranging from 10 μm to 200 μm, and A layered, highly doped first III-V semiconductor pass region (HK1) of a first conductivity type, the first III-V semiconductor pass region (HK1) being disposed above the semiconductor drift region (HD1) and having at least The dopant concentration, wherein the semiconductor drift region (HD1) has a first conductivity type or a second conductivity type, wherein the first conductivity type and the second conductivity type are opposite to each other; Wherein, the semiconductor drift region (HD1) and the first semiconductor contact region (HK1) are selectively epitaxially grown in the through opening after the through opening is generated; The core stack has a side that extends from the bottom of the core stack to the top of the core stack. In this configuration, the side of the core stack is constructed within a pre-constructed through opening during the selective epitaxial growth, the side of the core stack is surrounded by the inner wall of the through opening, and the side of the core stack is locked to the inner wall material. A first metal interconnect layer (M1) is disposed on the upper side of the first III-V semiconductor interconnect region (HK1), and a second metal interconnect layer (M2) is disposed on the lower side of the second III-V semiconductor interconnect region (HK2).

2. The high-blocking III-V group semiconductor power diode (HLD) according to claim 1, characterized in that, The dielectric framework region (DR) is made of Si x O y Or from Si x N y Or by Al x O y Or by Ta x O y Or by Ti x O y Or by Hf x O y Composition, or having Si x O y or Si x N y Or Al x O y Or Ta x O y or Ti x O y or Hf x O y .

3. The high-blocking III-V group semiconductor power diode (HLD) according to claim 1 or 2, characterized in that, The III-V group semiconductor power diode (HLD) has a semiconductor interlayer (ZW1) of the first conductivity type between the first semiconductor on-state region (HK1) and the semiconductor drift region (HD1), and the semiconductor interlayer of the first conductivity type has to The dopant concentration.

4. The high-blocking III-V group semiconductor power diode (HLD) according to any one of the preceding claims, characterized in that, The III-V group semiconductor power diode (HLD) has a semiconductor interlayer (ZW2) of the second conductivity type between the second semiconductor pass region (HK2) and the semiconductor drift region (HD1), the semiconductor interlayer having to The dopant concentration.

5. The high-blocking III-V group semiconductor power diode (HLD) according to any one of the preceding claims, characterized in that, The III-V group semiconductor power diode (HLD) has a highly doped modified buffer layer sequence (P), wherein the modified buffer layer sequence (P) is disposed between the semiconductor drift region (HD1) and the second semiconductor pass region (HK2), and the modified buffer layer sequence (P) has a greater than The dopant concentration and layer thickness are greater than 0.5 μm and less than 20 μm. The modified buffer layer sequence (P) has the first conductivity type or the second conductivity type. The modified buffer layer sequence (P) has the first lattice constant on the upper side toward the semiconductor drift region (HD1) and the second lattice constant on the lower side toward the second semiconductor pass region (HK2). The second semiconductor pass region (HK2) has the second lattice constant.

6. The high-blocking III-V group semiconductor power diode (HLD) according to claim 4, characterized in that, The buffer layer sequence (P) is part of the core stack and / or part of the carrier region.

7. The high-blocking III-V group semiconductor power diode (HLD) according to any one of the preceding claims, characterized in that, The group III-V semiconductor power diode (HLD) has a substrate layer (SUB) wherein the substrate layer (SUB) is configured as part of the carrier region.

8. The high-blocking III-V group semiconductor power diode (HLD) according to any one of the preceding claims, characterized in that, The semiconductor drift region (HD1) and / or the first semiconductor on-state region (HK1) and / or the second semiconductor on-state region (HK2) are composed of GaAs or InGaAs, or the semiconductor drift region (HD1) and / or the first semiconductor on-state region (HK1) and / or the second semiconductor on-state region (HK2) have GaAs or InGaAs.

9. The high-blocking III-V group semiconductor power diode (HLD) according to any one of the preceding claims, characterized in that, The first conductivity type is p-type and the second conductivity type is n-type, or the first conductivity type is n-type and the second conductivity type is p-type.

10. The high-blocking III-V group semiconductor power diode (HLD) according to any one of the preceding claims, characterized in that, The upper side of the core stack is closed by means of the upper side of the dielectric frame region (DR), or a first step (S1) is constructed relative to the upper side of the dielectric frame region.

11. The high-blocking III-V group semiconductor power diode (HLD) according to any one of the preceding claims, characterized in that, The lower side of the core stack is closed by means of the lower side of the dielectric frame region (DR), or the lower side of the core stack is constructed with a second step (S2) relative to the lower side of the dielectric frame region (DR).

12. A method for fabricating a plurality of stacked high-blocking III-V semiconductor power diodes (HLDs) on a wafer-level substrate, the method comprising the following steps: A common semiconductor carrier layer (TR) is provided, wherein the semiconductor carrier layer (TR) includes at least one layered, highly doped second group III-V semiconductor pass region (HK2) of a second conductivity type, wherein the second semiconductor pass region (HK2) has at least dopant concentration; A dielectric layer (DS) is deposited on the upper side of the second semiconductor pass region (HK2); A mask layer (MA) is applied on the upper side of a dielectric SiO2 layer (DS), the mask layer (MA) having a plurality of mask openings (OE) spaced apart from each other. The dielectric layer (DS) is removed by etching in the region of the mask opening (OE) up to the upper side of the second semiconductor contact area (HK2), so that the second semiconductor contact area (HK2) is exposed in the region of the mask opening (OE), and a common layered dielectric framework region (DR) is formed in the remaining portion of the SiO2 layer (DS) of the dielectric after etching. The dielectric framework region (DR) has a plurality of through openings, wherein each through opening extends from the upper side of the dielectric framework region (DR) to the lower side of the dielectric framework region (DR) and has an inner wall. Remove the mask layer (MA); After creating the through-opening, a lightly doped III-V semiconductor drift region (HD1) is selectively epitaxially grown on the exposed upper side of the second semiconductor on-state (HK2) within each through-opening, wherein the semiconductor drift region (HD1) has a first conductivity type or a second conductivity type, and has to The dopant concentration is high and the layer thickness ranges from 10 μm to 200 μm. Next, a layered, highly doped first III-V semiconductor pass region (HK1) of the first conductivity type is selectively epitaxially grown on the upper side of the semiconductor drift region (HD1) within the corresponding through-hole, wherein the first semiconductor pass region (HK1) has at least The dopant concentration, wherein the first conductivity type and the second conductivity type are opposite to each other; The semiconductor drift region (HD1) and the first semiconductor on-state region (HK1) form a core stack in each through-hole as follows: the core stack has a side extending from the lower side of the core stack to the upper side of the core stack. In this process, the sides of the core stack are constructed within a previously constructed through opening during the selective epitaxial growth, the sides of the core stack are applied to the inner wall of the through opening, the sides of the core stack are surrounded by the inner wall, and the sides of the core stack are locked to the inner wall material. The corresponding first metal interconnect layer (M1) is applied on the upper side of the corresponding first III-V semiconductor interconnect region (HK1); The corresponding second metal interconnect layer (M2) is applied to the underside of the corresponding second III-V semiconductor interconnect region (HK2); The III-V semiconductor diodes are separated by sawing in a common layer beneath a common dielectric frame region (DR) between the through openings and through the common layer, the common layer comprising a second III-V semiconductor pass region (HK2) and a second metal interconnect pass layer (M2), wherein the sawing produces at least one outer surface of each III-V semiconductor diode in the remaining dielectric frame region (DR) after separation.

13. The manufacturing method according to claim 12, wherein, First, a second III-V semiconductor pass region (HK2) is provided on the substrate (SUB). During the selective epitaxial growth of the dielectric framework region (DR) and the core stack, the substrate (SUB) and the second III-V semiconductor pass region (HK2) jointly form the semiconductor carrier layer (TR). The substrate (SUB) is completely removed before the second metal interconnect pass layer (M2) is applied.

14. The manufacturing method according to claim 12, wherein, A second III-V semiconductor pass region (HK2) is provided on the substrate (SUB). During the selective epitaxial growth of the dielectric framework region (DR) and the core stack, the substrate (SUB) and the second III-V semiconductor pass region (HK2) jointly form the semiconductor carrier layer (TR). The substrate (SUB) is not removed or is only partially removed before the second metal interconnect pass layer (M2) is applied, and the second metal interconnect pass layer (M2) is applied on the underside of the substrate (SUB).

15. The manufacturing method according to any one of claims 12 to 14, wherein, Selective epitaxial growth of the semiconductor drift region (HD1) and the first III-V semiconductor on-state region (HK1) is achieved by means of metal-organic compound vapor phase epitaxy or by means of liquid phase epitaxy.

16. The manufacturing method according to any one of claims 12 to 15, wherein, The first conductivity type is p-type and the second conductivity type is n-type.

17. The manufacturing method according to any one of claims 12 to 15, wherein, The first conductivity type is n-type and the second conductivity type is p-type.

18. The manufacturing method according to any one of claims 12 to 17, wherein, The remaining dielectric framework region (DR) after separation at the corresponding III-V semiconductor diode forms the sidewall passivation portion of the core stack.

19. The manufacturing method according to claim 13 or 14, wherein, The substrate layer (SUB) is a GaAs substrate, a Ge substrate, or a Si substrate.

20. The manufacturing method according to any one of claims 12 to 19, wherein, After the selective epitaxial growth of the core stack and before the separation, no etching step is performed to construct the sides of the core stack.

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